Display panel and display device

Abstract

The application discloses a display panel and a display device. A pixel circuit layer includes a plurality of pixel circuits and an initialization signal line configured to transmit an initialization signal to the pixel circuits. A light emitting device layer includes a plurality of light emitting diodes, and one light emitting diode is connected to one pixel circuit. In the display panel viewed from a top perspective, the display panel includes a plurality of pixel circuit units. In the pixel circuit units, at least two pixel circuits are arranged in rows along a first direction. In the pixel circuit units, in a second direction intersecting the first direction, one initialization signal line is disposed between two adjacent rows of pixel circuits, and one initialization signal line is connected to the two rows of pixel circuits. The application saves the layout space of the initialization signal line by using one initialization signal line for the two adjacent rows of pixel circuits in the pixel circuit units, thereby facilitating the realization of high resolution.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, OLED panels typically employ a Real RGB (real pixel) design to improve display quality. However, traditional Real RGB designs usually use a one-pixel structure corresponding to a set of signal traces, which requires a large layout area and makes it difficult to achieve high resolution. Summary of the Invention

[0003] This application provides a display panel and display device to achieve high resolution.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Substrate; A pixel circuit layer is disposed on the substrate and includes a plurality of pixel circuits and an initialization signal line, the initialization signal line being configured to transmit an initialization signal to the pixel circuit; A light-emitting device layer is disposed on the side of the pixel circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting diodes, and one light-emitting diode is correspondingly connected to one pixel circuit. In the display panel viewed from above, the display panel includes a plurality of pixel circuit units, wherein at least two of the pixel circuits are arranged in a row along a first direction; In the pixel circuit unit, in the second direction intersecting the first direction, an initialization signal line is disposed between two adjacent rows of pixel circuits, and the initialization signal line connects both rows of pixel circuits simultaneously.

[0005] Optionally, in some embodiments of this application, the pixel circuit layer includes a reference voltage line configured to provide a reference voltage to the pixel circuit, and the reference voltage line and the initialization signal line are disposed on different layers; In the pixel circuit unit, in the second direction, a reference voltage line is disposed between two adjacent rows of pixel circuits, and the reference voltage line connects both rows of pixel circuits simultaneously.

[0006] Optionally, in some embodiments of this application, in the display panel viewed from above, the initialization signal line and the reference voltage line both extend along the first direction, and the initialization signal line and the reference voltage line at least partially overlap.

[0007] Optionally, in some embodiments of this application, the pixel circuit layer includes a first control line and a second control line disposed in different layers, the first control line being configured to control the initialization signal input to the pixel circuit, and the second control line being configured to control the reference voltage input to the pixel circuit; In the display panel viewed from above, both the first control line and the second control line extend along the first direction, and the first control line and the second control line are at least partially overlapping.

[0008] Optionally, in some embodiments of this application, the pixel circuit layer includes a power line configured to provide a positive power supply voltage to the pixel circuit, wherein, in the second direction, the power line is disposed between two adjacent pixel circuit units; In two adjacent pixel circuit units, a power line simultaneously connects a row of pixel circuits in one pixel circuit unit that is close to the power line and a row of pixel circuits in another pixel circuit unit that is close to the power line.

[0009] Optionally, in some embodiments of this application, the pixel circuit layer includes data lines configured to transmit data signals to the pixel circuits, the data lines being disposed on a different layer from the initialization signal lines, and in the pixel circuit unit, at least two of the pixel circuits are arranged in a column along the second direction; In the pixel circuit unit, one data line is connected to a column of pixel circuits, and in one column of at least two columns of pixel circuits, at least two different pixel circuits are connected to light-emitting diodes of different colors.

[0010] Optionally, in some embodiments of this application, the pixel circuit includes a first transistor, a storage capacitor, and a second transistor. The first transistor is a driving transistor. The gate of the first transistor and the first plate of the storage capacitor are connected to a first node. The first terminal of the first transistor is connected to a power supply line. The second terminal of the first transistor, the second plate of the storage capacitor, the second terminal of the second transistor, and the light-emitting diode are connected to a second node. The first terminal of the second transistor is connected to the initialization signal line, and the gate of the second transistor is connected to a first control line. In the second direction, the first active portion of the first transistor is connected to the second active portion of the second transistor to form a first active unit; in two adjacent rows of pixel circuits of the pixel circuit unit, in the second direction, the first active units of one row of pixel circuits and the first active units of the other row of pixel circuits are arranged opposite to each other.

[0011] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits of the pixel circuit unit, the second active part of one row of pixel circuits and the second active part of the other row of pixel circuits are connected by a first connecting part. In the second direction, the first connecting part is disposed between two adjacent second active parts, and the initialization signal line is connected to the first connecting part.

[0012] Optionally, in some embodiments of this application, in two adjacent columns of pixel circuits of the pixel circuit unit, in the first direction, the first active units of one column of pixel circuits and the first active units of another column of pixel circuits are arranged opposite to each other. The first connection portion simultaneously connects to two rows of pixel circuits and four adjacent second active portions in two columns of pixel circuits, and the initialization signal line is connected to the central region of the first connection portion.

[0013] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits of the pixel circuit unit, the first active unit of one row of pixel circuits and the first active unit of the other row of pixel circuits are mirrored; in two adjacent columns of pixel circuits of the pixel circuit unit, the first active unit of one column of pixel circuits and the first active unit of the other column of pixel circuits are mirrored.

[0014] Optionally, in some embodiments of this application, the pixel circuit includes a third transistor and a fourth transistor, the gate of the third transistor is connected to a second control line, the first terminal of the third transistor is connected to a reference voltage line, the second terminals of the third transistor and the second terminals of the fourth transistor are connected to the first node, the gate of the fourth transistor is connected to the third control line, and the first terminal of the fourth transistor is connected to a data line. In the second direction, the third active portion of the third transistor is connected to the fourth active portion of the fourth transistor to form a second active unit; in two adjacent rows of pixel circuits of the pixel circuit unit, in the second direction, the second active units of one row of pixel circuits and the second active units of the other row of pixel circuits are arranged opposite to each other.

[0015] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits of the pixel circuit unit, the third active portion of one row of pixel circuits and the third active portion of the other row of pixel circuits are connected by a second connecting portion. In the second direction, the second connecting portion is disposed between two adjacent third active portions, and the reference voltage line is connected to the second connecting portion.

[0016] Optionally, in some embodiments of this application, in the pixel circuit unit, in the first direction, the second active units of one column of pixel circuits and the second active units of the other column of pixel circuits are arranged opposite to each other; The second connection portion simultaneously connects the four adjacent third active portions in the two rows of pixel circuits and the two columns of pixel circuits, and the reference voltage line is connected to the central region of the second connection portion.

[0017] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits in the pixel circuit unit, the second active units of one row of pixel circuits and the second active units of the other row of pixel circuits are mirrored; in the pixel circuit unit, in two adjacent columns of pixel circuits, the second active units of one column of pixel circuits and the second active units of the other column of pixel circuits are mirrored.

[0018] Optionally, in some embodiments of this application, the first connecting portion and the second connecting portion are alternately spaced apart in the first direction.

[0019] Optionally, in some embodiments of this application, the first active part and the second active part are arranged on the same layer, the third active part and the fourth active part are arranged on the same layer, and the first active unit and the second active unit are arranged on different layers. In the pixel circuit, the first active unit and the second active unit are partially overlapped.

[0020] Optionally, in some embodiments of this application, the pixel circuit layer includes a third connection portion disposed on the same layer as the first active unit, the power line and the third connection portion both extend along the first direction, and one of the third connection portions simultaneously connects to the first active portions of two adjacent rows of the pixel circuit; In the display panel viewed from above, the third connection portion and the power line are at least partially overlapped, and the power line is connected to the third connection portion through multiple vias.

[0021] Optionally, in some embodiments of this application, the first active unit further includes a first extension extending along the first direction, the first extension connecting the connection between the first active part and the second active part, and the second plate of the storage capacitor being electrically connected to the first extension. In the display panel viewed from above, the first extension and the first active portion at least partially overlap in the second direction.

[0022] Optionally, in some embodiments of this application, the first active unit and the second plate of the storage capacitor are both disposed on different layers from the second node, the second node connects the second plate of the storage capacitor and the first extension, and the second node also connects the connection between the first active part and the second active part.

[0023] Optionally, in some embodiments of this application, the first node and the second node are disposed on the same layer, the first node and the storage capacitor are disposed on different layers, the first node is connected to the first plate of the storage capacitor, and the second active unit is disposed on a different layer from the first node; the second active unit includes a second extension, and the second extension is connected to the junction of the third active part and the fourth active part; In the display panel viewed from above, in the first direction, the second extension overlaps with the fourth active portion; in the second direction, the second extension overlaps with the third active portion; in the thickness direction of the display panel, the second extension and the first node at least partially overlap; and the second extension is connected to the first node.

[0024] Optionally, in some embodiments of this application, the second active unit includes a third extension, which is connected to the side of the fourth active unit away from the third active unit in the second direction. The data line is disposed on a different layer from both the second active unit and the power line, and the data line is electrically connected to the third extension. In the display panel viewed from above, the third extension is at least partially overlapped with the power cord.

[0025] Optionally, in some embodiments of this application, the pixel circuit layer includes a first active layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a first interlayer dielectric layer, a third conductive layer, a second interlayer dielectric layer, a second active layer, a third insulating layer, a fourth conductive layer, a third interlayer dielectric layer, a fifth conductive layer, a first planarization layer, a sixth conductive layer, and a second planarization layer stacked sequentially. The first active unit is formed on the first active layer, the first control line and the first electrode are formed on the first conductive layer, the second electrode is formed on the second conductive layer, and the power line, the initialization signal line, the first node and the second node are formed on the third conductive layer. The second active unit is formed on the second active layer, the second control line and the third control line are formed on the fourth conductive layer, the reference voltage line is formed on the fifth conductive layer, and the data line is formed on the sixth conductive layer.

[0026] Optionally, in some embodiments of this application, in any row of the pixel circuit unit, two pixel circuits drive LEDs of different colors. In two adjacent columns of pixel circuits, two pixel circuits in one column drive LEDs of different colors, and two pixel circuits in the other column drive LEDs of the same color.

[0027] According to a second aspect of this application, a display device is provided, which includes a display panel as described in any of the above embodiments.

[0028] In the display panel and display device of this application embodiment, the pixel circuit layer includes a plurality of pixel circuits and an initialization signal line, wherein the initialization signal line is configured to transmit an initialization signal to the pixel circuit. The light-emitting device layer includes a plurality of light-emitting diodes, and each light-emitting diode is correspondingly connected to one of the pixel circuits. In the display panel viewed from a top angle, the display panel includes a plurality of pixel circuit units, wherein at least two pixel circuits are arranged in a row along a first direction. In the pixel circuit unit, in a second direction intersecting the first direction, an initialization signal line is disposed between two adjacent rows of pixel circuits, and the initialization signal line simultaneously connects two rows of pixel circuits.

[0029] It is understood that the embodiments of this application save layout space for the initialization signal line by setting two adjacent rows of pixel circuits in the pixel circuit unit to share the same initialization signal line, thereby facilitating the achievement of high resolution.

[0030] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0032] Figure 1 This is a schematic diagram of the overall structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 An enlarged schematic diagram of section M in the middle; Figure 3yes Figure 1 Another enlarged schematic diagram of part M in the middle; Figure 4 This is an equivalent circuit diagram of the pixel circuit in the display panel provided in the exemplary embodiments of this disclosure; Figure 5 This is a cross-sectional structural diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is a top view of the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 7 This is a top view of the first active layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 8 This is a top view of the first active layer and the first conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 9 This is a top view of the first active layer, the first conductive layer, and the second conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure. Figure 10 This is a top view of the first active layer, first conductive layer, second conductive layer and third conductive layer in the pixel circuit unit provided in the exemplary embodiment of this disclosure; Figure 11 This is a top view of the second active layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 12 This is a top view of the fourth conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 13 This is a top view of the third conductive layer, the second active layer, and the fourth conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure. Figure 14 This is a top view of the fifth conductive layer in a pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 15 This is a top view of the sixth conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 16 This is a top view of the second active layer to the sixth conductive layer in the pixel circuit unit provided in an exemplary embodiment of this disclosure; Figure 17 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0033] Explanation of reference numerals in the attached figures: First direction F1; Second direction F2; Display panel 100; Display area AA; Non-display area NA; Pixel unit U1; Light-emitting diode E0; First light-emitting diode R1; Second light-emitting diode G1; Third light-emitting diode B1; Pixel circuit unit U2; Pixel circuit U20; First transistor T1; Second transistor T2; Storage capacitor Cst; Third transistor T3; Fourth transistor T4; First electrode c1; Second electrode c2; First node Q; Second node A; Power line VD; Initialization signal line Vi; Reference voltage line Vr; Data line Da; First control line IN; Second control line Re; Third control line Gn; Substrate 101; Pixel circuit layer 102; Light-emitting device layer 103; First active layer 02a; First insulating layer 021; First conductive layer 02b; Second insulating layer 022; Second conductive layer 02c; First interlayer Dielectric layer 023; Third conductive layer 02d; Second interlayer dielectric layer 024; Second active layer 02e; Third insulating layer 025; Fourth conductive layer 02f; Third interlayer dielectric layer 026; Fifth conductive layer 02g; First planarization layer 027; Sixth conductive layer 02h; Second planarization layer 028; Buffer layer 029; Light-shielding metal layer 02j; Fourth interlayer dielectric layer 0210; Pixel electrode 031; Intermediate layer 032; Opposite electrode 033; Pixel definition layer 034; First active unit Y1; First active portion Y11; Second active portion Y12; First connecting portion Y13; Third connecting portion Y14; Via k1; First extension portion Y15; Second active unit Y2; Third active portion Y21; Fourth active portion Y22; Second connecting portion Y23; Second extension portion Y24; Third extension portion Y25; Adapter portion Z1; Display device 1000. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0035] Please refer to Figures 1 to 3 , Figure 1 This is a schematic diagram of the overall structure of the display panel 100 provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 An enlarged schematic diagram of section M in the middle; Figure 3 yes Figure 1 Another enlarged schematic diagram of part M in the middle.

[0036] exist Figure 1In the plan view, the first direction F1 can be a direction parallel to one side of the display panel 100, and for example, it can be the horizontal direction of the display panel 100. The second direction F2 can be a direction parallel to the other side of the display panel 100 in the plan view, and it can be the vertical direction of the display panel 100.

[0037] The display panel 100 may have a rectangular or square shape in a plan view, but the implementation is not limited to this. In some embodiments, the display panel 100 may have a rectangular shape with vertical corners or rounded corners in a plan view. The display panel 100 may include two short sides arranged in a first direction F1 and two long sides arranged in a second direction F2 in a plan view.

[0038] The display panel 100 may include a display area AA and a non-display area NA. In a plan view, the shape of the display area AA may correspond to the shape of the display panel 100. For example, if the display panel 100 has a rectangular shape in a plan view, the display area AA may also have a rectangular shape.

[0039] The non-display area NA can be arranged around the display area AA.

[0040] Optionally, in some embodiments of this application, the display panel 100 includes a plurality of pixel units U1, which are arranged in a matrix along a first direction F1 and a second direction F2, but are not limited thereto.

[0041] Pixel unit U1 includes multiple light-emitting diodes E0. For example, pixel unit U1 includes a first light-emitting diode R1, a second light-emitting diode G1, and a third light-emitting diode B1 that emit light of different colors. In the first direction F1, the first light-emitting diode R1 and the second light-emitting diode G1 are arranged side by side in one row, and the third light-emitting diode B1 and the second light-emitting diode G1 are arranged side by side in another row. In the second direction F2, the first light-emitting diode R1 and the third light-emitting diode B1 are arranged side by side in one column, and the two second light-emitting diodes G1 are arranged side by side in another column.

[0042] In this LED array, one of the first LED R1, the second LED G1, and the third LED B1 emits red light, another emits green light, and the last emits blue light. The following explanation uses the example of the first LED R1 emitting red light, the second LED G1 emitting green light, and the third LED B1 emitting blue light, but it is not limited to this.

[0043] exist Figure 2 In this configuration, the arrangement of LEDs E0 within all pixel units U1 is identical. However, it is not limited to this; for example, ... Figure 3As shown, in the same pixel row, the arrangement of light-emitting diodes E0 in two adjacent pixel units U1 is different. For example, in one pixel unit U1, the first light-emitting diode R1 is above the second light-emitting diode G1; in another pixel unit U1, the first light-emitting diode R1 is below the second light-emitting diode G1.

[0044] It is understandable that, compared to the design of real pixels, the embodiments of this application form pixel units U1 through sub-pixel rendering (SPR) design, so as to save the number of physical sub-pixels while achieving the effect of complete pixels, thereby facilitating the realization of high resolution of display panel 100.

[0045] Optionally, in some embodiments of this application, the display panel 100 further includes a plurality of pixel circuit units U2, each pixel circuit unit U2 driving a pixel unit U1. Each pixel circuit unit U2 includes a plurality of pixel circuits U20, each pixel circuit U20 driving a light-emitting diode E0.

[0046] Optionally, in some embodiments of this application, a pixel circuit U20 is correspondingly disposed on the area of ​​a light-emitting diode E0, but this is not limited to. For example, in some embodiments, in the connected pixel circuit U20 and light-emitting diode E0, the pixel circuit U20 may be disposed outside the area of ​​the light-emitting diode E0.

[0047] Optionally, in some embodiments of this application, in any row of pixel circuits U20, two pixel circuits U20 drive LEDs E0 of different colors. In two adjacent columns of pixel circuits U20, two pixel circuits U20 in one column drive LEDs E0 of different colors, and two pixel circuits U20 in the other column drive LEDs E0 of the same color.

[0048] For example, in pixel circuit unit U2, in each row of pixel circuits U20, one pixel circuit U20 drives the first light-emitting diode R1, and another pixel circuit U20 drives the third light-emitting diode B1. In two adjacent columns of pixel circuits U20, the two pixel circuits U20 in the first column drive the first light-emitting diode R1 and the third light-emitting diode B1 respectively, and the two pixel circuits U20 in the second column drive the second light-emitting diode G1 respectively.

[0049] Please refer to Figure 4 , Figure 4 This is an equivalent circuit diagram of the pixel circuit U20 in the display panel 100 of this application embodiment.

[0050] It should be noted that the display panel 100 in this embodiment of the application uses... Figure 4 The illustration uses the pixel circuit U20 as an example, but is not limited to this.

[0051] exist Figure 4 In the pixel circuit U20, there are a first transistor T1, a second transistor T2, a storage capacitor Cst, a third transistor T3, and a fourth transistor T4.

[0052] The first transistor T1 is a driving transistor. The gate of the first transistor T1 and the first plate c1 of the storage capacitor Cst are connected to the first node Q. The first terminal of the first transistor T1 is connected to the power supply line VD. The second terminal of the first transistor T1, the second plate c2 of the storage capacitor Cst, the second terminal of the second transistor T2, and the light-emitting diode E0 are connected to the second node A. The first terminal of the second transistor T2 is connected to the initialization signal line Vi, and the gate of the second transistor T2 is connected to the first control line IN.

[0053] The gate of the third transistor T3 is connected to the second control line Re, and the first terminal of the third transistor T3 is connected to the reference voltage line Vr. The second terminals of the third transistor T3 and the fourth transistor T4 are connected to the first node Q. The gate of the fourth transistor T4 is connected to the third control line Gn, and the first terminal of the fourth transistor T4 is connected to the data line Da.

[0054] In this transistor configuration, the first transistor T1 can be a drive transistor that outputs a drive current corresponding to the data signal, and the second transistor T2, the third transistor T3, and the fourth transistor T4 can be switching transistors that transmit signals. The first terminal of each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be either a source or a drain, and the second terminal of each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be a different terminal from the first terminal. For example, if the first terminal is a drain, the second terminal can be a source.

[0055] In one embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be a P-channel metal-oxide-semiconductor field-effect transistor (P-channel MOSFET) (PMOS), and the other transistors of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be an N-channel MOSFET (NMOS). For example, the first transistor T1 and the second transistor T2 may be PMOS, and the third transistor T3 and the fourth transistor T4 may be NMOS. In another embodiment, the third transistor T3 and the fourth transistor T4 may be PMOS, and the first transistor T1 and the second transistor T2 may be NMOS. In yet another embodiment, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may all be NMOS or all be PMOS. The following description focuses on embodiments where the first transistor T1 and the second transistor T2 are PMOS comprising silicon semiconductor and the third transistor T3 and the fourth transistor T4 are NMOS comprising oxide semiconductor.

[0056] At least one of transistors T1, T2, T3, and T4 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of transistors T1, T2, T3, and T4 may be a transistor having an oxide semiconductor layer. For example, the first transistor T1 and the second transistor T2 may include semiconductor layers made of polycrystalline silicon with high reliability, and the third transistor T3 and the fourth transistor T4 may include oxide semiconductor layers with high carrier mobility and low leakage current.

[0057] Please refer to Figure 5 , Figure 5 This is a cross-sectional structural diagram of the display panel 100 provided in the embodiments of this application.

[0058] Optionally, in some embodiments of this application, the display panel 100 includes a substrate 101, a pixel circuit layer 102, and a light-emitting device layer 103.

[0059] The pixel circuit layer 102 is disposed on the substrate 101 and includes a plurality of pixel circuits U20 and an initialization signal line Vi. The initialization signal line Vi is configured to transmit an initialization signal to the pixel circuits U20.

[0060] The light-emitting device layer 103 is disposed on the side of the pixel circuit layer 102 away from the substrate 101. The light-emitting device layer 103 includes a plurality of light-emitting diodes E0, and each light-emitting diode E0 is connected to a pixel circuit U20.

[0061] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a first active layer 02a, a first insulating layer 021, a first conductive layer 02b, a second insulating layer 022, a second conductive layer 02c, a first interlayer dielectric layer 023, a third conductive layer 02d, a second interlayer dielectric layer 024, a second active layer 02e, a third insulating layer 025, a fourth conductive layer 02f, a third interlayer dielectric layer 026, a fifth conductive layer 02g, a first planarization layer 027, a sixth conductive layer 02h, and a second planarization layer 028, stacked sequentially.

[0062] Optionally, in some embodiments of this application, the pixel circuit layer 102 further includes a buffer layer 029, a light-shielding metal layer 02j, and a fourth interlayer dielectric layer 0210.

[0063] A buffer layer 029 is disposed between the substrate 101 and the first active layer 02a. A light-shielding metal layer 02j is disposed on the side of the second interlayer dielectric layer 024 away from the substrate 101, and a fourth interlayer dielectric layer 0210 covers the light-shielding metal layer 02j. A second active layer 02e is disposed on the side of the fourth interlayer dielectric layer 0210 away from the substrate 101.

[0064] Among them, the light-shielding metal layer 02j is configured to block the second active layer 02e.

[0065] Optionally, in some embodiments, a first passivation layer is further disposed between the first planarization layer 027 and the fifth conductive layer 02g, and the first passivation layer covers the fifth conductive layer 02g. A second passivation layer is disposed between the second planarization layer 028 and the sixth conductive layer 02h, and the second passivation layer covers the sixth conductive layer 02h.

[0066] It should be noted that the structure of the pixel circuit layer 102 is not limited to that shown below. Figure 5 The architecture shown.

[0067] Optionally, in some embodiments of this application, a first control line IN and a first electrode c1 are formed on a first conductive layer 02b. The first electrode c1 is multiplexed as the gate of a first transistor T1. A second electrode c2 is formed on a second conductive layer 02c. A power supply line VD, an initialization signal line Vi, a first node Q, and a second node A are formed on a third conductive layer 02d.

[0068] The second control line Re and the third control line Gn are formed on the fourth conductive layer 02f. The reference voltage line Vr is formed on the fifth conductive layer 02g. The data line Da is formed on the sixth conductive layer 02h.

[0069] Optionally, the material of the first active layer 02a includes silicon semiconductors, such as amorphous silicon or polycrystalline silicon. The material of the second active layer 02e includes metal oxide semiconductors, such as indium gallium tin oxide, indium gallium zinc oxide, etc.

[0070] Optionally, in some embodiments of this application, the first conductive layer 02b to the sixth conductive layer 02h can be metal layers. Each of the first conductive layer 02b to the sixth conductive layer 02h may include aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten, and / or copper or combinations thereof, and may include a single layer or multiple layers containing the above materials. In an embodiment, each of the first conductive layer 02b to the sixth conductive layer 02h may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0071] Optionally, the buffer layer 029, the first insulating layer 021, the second insulating layer 022, the first interlayer dielectric layer 023, the second interlayer dielectric layer 024, the third insulating layer 025, the third interlayer dielectric layer 026, and the fourth interlayer dielectric layer 0210 may each be formed by stacking multiple inorganic layers in an alternating manner. For example, the buffer layer 029, the first insulating layer 021, the second insulating layer 022, the first interlayer dielectric layer 023, the second interlayer dielectric layer 024, the third insulating layer 025, the third interlayer dielectric layer 026, and the fourth interlayer dielectric layer 0210 may each be a bilayer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternating stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the buffer layer 029, the first insulating layer 021, the second insulating layer 022, the first interlayer dielectric layer 023, the second interlayer dielectric layer 024, the third insulating layer 025, the third interlayer dielectric layer 026, and the fourth interlayer dielectric layer 0210 may each be formed as a single inorganic layer containing the above-mentioned insulating material.

[0072] The materials of the first planarization layer 027 and the second planarization layer 028 can each be organic transparent film layers, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc.

[0073] Optionally, the light-emitting diode E0 may include a pixel electrode 031, an intermediate layer 032, and a counter electrode 033 on the pixel circuit layer 102.

[0074] The light-emitting device layer 103 includes a pixel definition layer 034, which has an opening, and an intermediate layer 032 is disposed within the opening.

[0075] Intermediate layer 032 may include an emission layer. In some embodiments, intermediate layer 032 may also include an emission layer and a functional layer. The functional layer may include a hole transport layer, a hole injection layer, an electron transport layer, and / or an electron injection layer. In some other embodiments, intermediate layer 032 may include a first stack including an emission layer and a functional layer, a second stack including an emission layer and a functional layer, and a charge generation layer located between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The emission efficiency of the tandem light-emitting diode E0 with the emission layer can be further improved by the negative charge generation layer and the positive charge generation layer.

[0076] Optionally, in some embodiments of this application, please refer to Figure 6 and Figure 10 In the display panel 100 viewed from above, the display panel 100 includes a plurality of pixel circuit units U2. In the pixel circuit unit U2, at least two pixel circuits U20 are arranged in a row along a first direction F1.

[0077] In the pixel circuit unit U2, an initialization signal line Vi is set between two adjacent rows of pixel circuits U20 on the second direction F2 that intersects with the first direction F1, and the initialization signal line Vi is connected to both rows of pixel circuits U20 at the same time.

[0078] It is understood that the display panel 100 in this application embodiment saves layout space for the initialization signal line Vi by setting two adjacent rows of pixel circuits U20 in the pixel circuit unit U2 to share the same initialization signal line Vi, thereby facilitating the achievement of high resolution.

[0079] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a reference voltage line Vr configured to provide a reference voltage to the pixel circuit U20, and the reference voltage line Vr and the initialization signal line Vi are set in different layers.

[0080] In the pixel circuit unit U2, on the second direction F2, a reference voltage line Vr is set between two adjacent rows of pixel circuits U20, and the reference voltage line Vr is connected to both rows of pixel circuits U20 at the same time.

[0081] It is understood that the display panel 100 in this application embodiment saves the layout space of the initialization signal line Vi by setting two adjacent rows of pixel circuits U20 in the pixel circuit unit U2 to share a reference voltage line Vr, thereby facilitating the achievement of high resolution.

[0082] Optionally, in some embodiments of this application, in the display panel 100 viewed from above, the initialization signal line Vi and the reference voltage line Vr both extend along the first direction F1, and the initialization signal line Vi and the reference voltage line Vr at least partially overlap.

[0083] It is understandable that overlapping the initialization signal line Vi and the reference voltage line Vr in the thickness direction, which are set up in different layers, can save planar wiring area and facilitate the achievement of high resolution. Secondly, since the initialization signal line Vi and the reference voltage line Vr are each connected to a constant voltage signal, there will be no sudden signal jumps. Therefore, overlapping the two can reduce the impact between them caused by jumps.

[0084] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a first control line IN and a second control line Re disposed on different layers. The first control line IN is configured to control the initialization signal input to the pixel circuit U20. The second control line Re is configured to control the reference voltage input to the pixel circuit U20.

[0085] In the display panel 100 viewed from above, the first control line IN and the second control line Re both extend along the first direction F1, and the first control line IN and the second control line Re are at least partially overlapped.

[0086] It is understandable that overlapping the first control line IN and the second control line Re in the thickness direction when they are set in different layers can save planar wiring area and facilitate the achievement of high resolution.

[0087] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a power line VD configured to provide a positive power supply voltage to the pixel circuit U20. In the second direction F2, the power line VD is disposed between two adjacent pixel circuit units U2.

[0088] In two adjacent pixel circuit units U2, a power line VD connects a row of pixel circuits U20 in one pixel circuit unit U2 that is close to the power line VD and a row of pixel circuits U20 in the other pixel circuit unit U2 that is close to the power line VD.

[0089] It is understandable that adjacent rows of pixel circuits U20 between different pixel circuit units U2 share a single power line VD, which facilitates the achievement of high resolution.

[0090] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a data line Da configured to transmit data signals to the pixel circuit U20. The data line Da and the initialization signal line Vi are disposed on different layers. In the pixel circuit unit U2, at least two pixel circuits U20 are arranged in a row along the second direction F2.

[0091] In pixel circuit unit U2, a data line Da is connected to a column of pixel circuits U20 at the same time, and in one column of at least two different pixel circuits U20, at least two different pixel circuits U20 are connected to light-emitting diodes E0 of different colors.

[0092] It is understandable that the pixel circuit U20, which drives LEDs E0 of different emission colors, shares a single data line Da. Compared to one data line Da driving a column of LEDs E0 of the same emission color, this saves one data line Da and facilitates the achievement of high resolution.

[0093] Optionally, in some embodiments of this application, in pixel circuit unit U2, a data line Da is simultaneously connected to a column of pixel circuits U20, and in another column of at least two columns of pixel circuits U20, all pixel circuits U20 are connected to light-emitting diodes E0 of the same color.

[0094] Please refer to Figures 7 to 10 Optionally, in some embodiments of this application, in the second direction F2, the first active portion Y11 of the first transistor T1 is connected to the second active portion Y12 of the second transistor T2 to form a first active unit Y1. In two adjacent rows of pixel circuits U20 of pixel circuit unit U2, in the second direction F2, the first active unit Y1 of one row of pixel circuit U20 and the first active unit Y1 of the other row of pixel circuit U20 are arranged opposite to each other.

[0095] Optionally, the first active unit Y1 is formed in the first active layer 02a.

[0096] It is understood that in the embodiments of this application, the first active units Y1 in two adjacent rows of the pixel circuit unit U2 are arranged opposite each other, so that the arrangement of the first transistor T1 and the second transistor T2 tends to be regular and periodic, thereby saving space and achieving high resolution.

[0097] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits U20 of pixel circuit unit U2, the second active portion Y12 of one row of pixel circuits U20 and the second active portion Y12 of the other row of pixel circuits U20 are connected by a first connecting portion Y13. In the second direction F2, the first connecting portion Y13 is disposed between two adjacent second active portions Y12, and the initialization signal line Vi is connected to the first connecting portion Y13.

[0098] It is understandable that, based on the relative arrangement of the two rows of first active units Y1, the first connecting part Y13 is connected between the two rows of first active units Y1, thereby realizing the simultaneous connection of the first active units Y1 of the two rows of pixel circuits U20 in the same column using an initialization signal line Vi.

[0099] Optionally, the first connecting part Y13 and the first active unit Y1 are connected on the same layer.

[0100] Optionally, in two adjacent rows of pixel circuits U20 of pixel circuit unit U2, the first active unit Y1 of one row of pixel circuit U20 and the first active unit Y1 of the other row of pixel circuit U20 are mirrored in the second direction F2 to improve the regularity and periodicity of the arrangement of the first transistor T1 and the second transistor T2, thereby saving space and facilitating the realization of high resolution.

[0101] Optionally, in some embodiments of this application, in two adjacent columns of pixel circuits U20 of pixel circuit unit U2, the first active unit Y1 of one column of pixel circuit U20 and the first active unit Y1 of the other column of pixel circuit U20 are arranged opposite to each other in the first direction F1.

[0102] A first connecting part Y13 simultaneously connects to four adjacent second active parts Y12 in two rows of pixel circuits U20 and two columns of pixel circuits U20, and the initialization signal line Vi is connected to the central region of the first connecting part Y13.

[0103] It is understandable that in the pixel circuit unit U2, the first active units Y1 of the two upper pixel circuits U20 and the first active units Y1 of the two lower pixel circuits U20 are arranged opposite each other, and the first active units Y1 of the two left pixel circuits U20 and the first active units Y1 of the two right pixel circuits U20 are arranged opposite each other. The first active units Y1 of the four pixel circuits U20 are all connected to the first connecting part Y13 located in the middle of the four. Based on this, by using the initialization signal line Vi to connect to the first connecting part Y13, the initialization signal line Vi can be connected to the four first active units Y1 of the two rows of pixel circuits U20 at the same time.

[0104] Secondly, the initialization signal line Vi is connected to the central region of the first connection part Y13 to improve the synchronization of the initialization signal to the four first active units Y1.

[0105] Optionally, in some embodiments of this application, in two adjacent columns of pixel circuits U20 of pixel circuit unit U2, the first active unit Y1 of one column of pixel circuit U20 and the first active unit Y1 of the other column of pixel circuit U20 are mirrored in the first direction F1, so as to improve the regularity and periodicity of the arrangement of the first transistor T1 and the second transistor T2, thereby saving space and facilitating the realization of high resolution.

[0106] Optionally, in some embodiments of this application, the pixel circuit layer 102 includes a third connection portion Y14 disposed on the same layer as the first active unit Y1. Both the power line VD and the third connection portion Y14 extend along the first direction F1. One third connection portion Y14 simultaneously connects to the first active portions Y11 of two adjacent rows of pixel circuits U20.

[0107] In the display panel 100 viewed from above, the third connection part Y14 is arranged to overlap with the power line VD at least partially, and the power line VD is connected to the third connection part Y14 through a plurality of vias k1.

[0108] It is understood that in this embodiment, the third connecting part Y14 connects the first active parts Y11 of two rows of pixel circuits U20 of different pixel circuit units U2, so that the power line VD is connected to the third connecting part Y14. This allows the power line VD to connect to the first active parts Y11 of two adjacent rows, so that the two adjacent rows of pixel circuits U20 can share a single power line VD. Secondly, the power line VD is connected to the third connecting part Y14 through multiple vias k1, so that the power line VD and the third connecting part Y14 are connected in parallel, thereby reducing impedance. In addition, the power line VD and the third connecting part Y14, which are arranged on different layers, are at least partially overlapped to save wiring space and facilitate high resolution.

[0109] Optionally, in some embodiments of this application, the first active unit Y1 further includes a first extension Y15 extending along a first direction F1, the first extension Y15 connecting the connection between the first active unit Y11 and the second active unit Y12. The second plate c2 of the storage capacitor Cst is electrically connected to the first extension Y15.

[0110] In the display panel 100 viewed from above, in the second direction F2, the first extension Y15 and the first active portion Y11 at least partially overlap.

[0111] It is understandable that the first extension Y15 is provided to connect the second plate c2 of the storage capacitor Cst. Furthermore, in the second direction F2, the first extension Y15 and the first active part Y11 at least partially overlap, making full use of the available area, saving layout space, and facilitating the achievement of high resolution.

[0112] Optionally, in some embodiments of this application, the second electrode plate c2 of the first active unit Y1 and the storage capacitor Cst are both disposed on a different layer from the second node A. The second node A connects the second electrode plate c2 of the storage capacitor Cst and the first extension Y15, and the second node A also connects the junction between the first active part Y11 and the second active part Y12.

[0113] Understandably, the second node A overlaps with both a portion of the second active part Y12 and the first extension Y15 in the thickness direction to save wiring space and facilitate high resolution. Furthermore, the second node A connects the first extension Y15, the first active part Y11, and the second active part Y12 to achieve a parallel connection between the second node A and the first active unit Y1, thus reducing trace impedance.

[0114] Optionally, in some embodiments of this application, a portion of the first control line IN is multiplexed as the gate g2 of the second transistor T2.

[0115] In the second direction F2, the gate g2 of the second transistor T2 protrudes beyond the main body line of the first control line IN, increasing the length of the gate g2 of the second transistor T2. Since the channel of the second transistor T2 overlaps with the gate g2 of the second transistor T2, the channel length of the second transistor T2 is increased, thereby reducing the risk of leakage current of the second transistor T2.

[0116] Please refer to Figures 11 to 16 Optionally, in some embodiments of this application, in the second direction F2, the third active portion Y21 of the third transistor T3 is connected to the fourth active portion Y22 of the fourth transistor T4 to form a second active unit Y2. In two adjacent rows of pixel circuits U20 of pixel circuit unit U2, in the second direction F2, the second active unit Y2 of one row of pixel circuit U20 and the second active unit Y2 of the other row of pixel circuit U20 are arranged opposite to each other.

[0117] Optionally, the second active unit Y2 is formed in the second active layer O2e.

[0118] It is understood that in the embodiments of this application, the second active units Y2 in two adjacent rows of the pixel circuit unit U2 are arranged opposite each other, so that the arrangement of the third transistor T3 and the fourth transistor T4 tends to be regular and periodic, thereby saving space and achieving high resolution.

[0119] Optionally, in two adjacent rows of pixel circuits U20 of pixel circuit unit U2, the second active unit Y2 of one row of pixel circuit U20 and the second active unit Y2 of the other row of pixel circuit U20 are mirrored to improve the regularity and periodicity of the third transistor T3 and the fourth transistor T4, thereby saving space and facilitating the achievement of high resolution.

[0120] Optionally, in some embodiments of this application, the first active part Y11 and the second active part Y12 are arranged on the same layer. The third active part Y21 and the fourth active part Y22 are arranged on the same layer, and the first active unit Y1 and the second active unit Y2 are arranged on different layers.

[0121] Please combine Figure 6 In the pixel circuit U20, the first active unit Y1 and the second active unit Y2 are partially overlapped.

[0122] It is understandable that the first active unit Y1 and the second active unit Y2, which are set in different layers, are partially overlapped in order to save the planar layout area of ​​the transistors and facilitate the achievement of high resolution.

[0123] Optionally, in some embodiments of this application, in two adjacent rows of pixel circuits U20 of pixel circuit unit U2, the third active portion Y21 of one row of pixel circuits U20 and the third active portion Y21 of the other row of pixel circuits U20 are connected by a second connecting portion Y23. In the second direction F2, the second connecting portion Y23 is disposed between two adjacent third active portions Y21. A reference voltage line Vr is connected to the second connecting portion Y23.

[0124] It is understandable that, based on the relative arrangement of the two rows of second active units Y2, the second connecting part Y23 is connected between the two rows of second active units Y2, thereby realizing the use of a reference voltage line Vr to simultaneously connect the second active units Y2 of the two rows of pixel circuits U20 in the same column.

[0125] Optionally, the second connecting part Y23 and the second active unit Y2 are connected on the same layer.

[0126] Optionally, in some embodiments of this application, in the pixel circuit unit U2, in the first direction F1, the second active unit Y2 of one column of pixel circuit U20 and the second active unit Y2 of the other column of pixel circuit U20 are arranged opposite to each other.

[0127] A second connection part Y23 simultaneously connects to four adjacent third active parts Y21 in two rows of pixel circuits U20 and two columns of pixel circuits U20, and a reference voltage line Vr is connected to the central region of the second connection part Y23.

[0128] It is understandable that in two adjacent columns of pixel circuits U20 with different pixel circuit units U2, the second active units Y2 of the upper two pixel circuits U20 and the second active units Y2 of the lower two pixel circuits U20 are arranged opposite each other, and the second active units Y2 of the left two pixel circuits U20 and the second active units Y2 of the right two pixel circuits U20 are arranged opposite each other. The second active units Y2 of the four pixel circuits U20 are all connected to the second connecting part Y23 located in the middle of the four. Based on this, by using the reference voltage line Vr to connect the second connecting part Y23, the reference voltage line Vr can be connected to the four second active units Y2 of the two rows of pixel circuits U20 at the same time.

[0129] Secondly, the reference voltage line Vr is connected to the central region of the second connection part Y23 to improve the synchronization of the initialization signal to the four second active units Y2.

[0130] Optionally, in some embodiments of this application, in the pixel circuit unit U2, in the first direction F1, the second active unit Y2 of one column of pixel circuit U20 and the second active unit Y2 of the other column of pixel circuit U20 are mirrored, and the regularity and periodicity of the third transistor T3 and the fourth transistor T4 are achieved, thereby saving space and facilitating the realization of high resolution.

[0131] Optionally, please combine Figure 6 In some embodiments of this application, in the first direction F1, the first connecting portion Y13 and the second connecting portion Y23 are alternately spaced.

[0132] It is understandable that the first connecting part Y13 and the second connecting part Y23 are arranged alternately at intervals in the first direction F1 to make full use of the layout space, thereby achieving high resolution and reducing the risk of mutual coupling between the two.

[0133] Optionally, in some embodiments of this application, the first node Q and the second node A are disposed on the same layer, and the first node Q and the storage capacitor Cst are disposed on different layers. The first node Q is connected to the first plate c1 of the storage capacitor Cst, and the second active unit Y2 is disposed on a different layer from the first node Q. The second active unit Y2 includes a second extension Y24, which connects to the junction of the third active part Y21 and the fourth active part Y22.

[0134] In the display panel 100 viewed from above, in the first direction F1, the second extension Y24 overlaps with the fourth active portion Y22. In the second direction F2, the second extension Y24 overlaps with the third active portion Y21. In the thickness direction of the display panel 100, the second extension Y24 and the first node Q at least partially overlap, and the second extension Y24 is connected to the first node Q.

[0135] It is understood that the embodiments of this application provide a second extension Y24 to connect the third transistor T3 and the fourth transistor T4 to the first node Q. Simultaneously, the second extension Y24 overlaps with the third active portion Y21 in both the first direction F1 and the second direction F2, maximizing space utilization and facilitating high resolution. Furthermore, in the thickness direction of the display panel 100, the second extension Y24 at least partially overlaps with the first node Q, saving layout area and further facilitating high resolution.

[0136] Optionally, in some embodiments of this application, the second active unit Y2 includes a third extension Y25. In the second direction F2, the third extension Y25 connects to the side of the fourth active unit Y22 away from the third active unit Y21. The data line Da is disposed on a different layer from both the second active unit Y2 and the power line VD, and is electrically connected to the third extension Y25.

[0137] In the display panel 100 viewed from above, the third extension Y25 is arranged to at least partially overlap with the power line VD.

[0138] It is understood that the embodiments of this application provide a third extension Y25 to achieve an electrical connection with the data line Da, and at least a partial overlap between the third extension Y25 and the power line VD is adopted to save layout area and facilitate the achievement of high resolution.

[0139] Optionally, in some embodiments of this application, the pixel circuit layer 102 further includes a transition portion Z1 disposed on the same layer as the reference voltage line Vr. In the thickness direction of the display panel 100, the transition portion Z1 is disposed between the third extension Y25 and the data line Da, and the data line Da is connected to the third extension Y25 through the transition portion Z1.

[0140] Optionally, in some embodiments of this application, a portion of the second control line Re is multiplexed as the gate of the third transistor T3, and a portion of the third control line Gn is multiplexed as the gate of the fourth transistor T4.

[0141] In the second direction F2, the gate g3 of the third transistor T3 protrudes beyond the main body line of the second control line Re, increasing the length of the gate g3 of the third transistor T3. Since the channel of the third transistor T3 overlaps with the gate g3 of the third transistor T3, the channel length of the third transistor T3 is increased, thereby reducing the risk of leakage current of the third transistor T3.

[0142] In the second direction F2, the gate g4 of the fourth transistor T4 protrudes beyond the body line of the third control line Gn, increasing the length of the gate g4 of the fourth transistor T4. Based on the overlap between the channel of the fourth transistor T4 and the gate g4 of the fourth transistor T4, the channel length of the fourth transistor T4 is increased, reducing the risk of leakage current of the fourth transistor T4.

[0143] Please refer to Figure 17 , Figure 17 This is a schematic diagram of the structure of a display device 1000 provided in an exemplary embodiment of this disclosure. According to a second aspect of this application, a display device 1000 is provided, which includes a display panel 100 as described in any of the above embodiments.

[0144] It should be noted that the structure of the display panel 100 of the display device 1000 provided in this application embodiment is the same as the structure of the display panel 100 provided in the above embodiments. For details, please refer to... Figures 1 to 16 Therefore, the relevant explanations will not be repeated here.

[0145] Display device 1000 can be at least one of the following: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, television, mobile medical device, camera, game console, digital camera, car navigation system, in-vehicle display screen, electronic billboard, ATM, or wearable device, VR device, AR device.

[0146] In the display device 1000 of this application embodiment, the pixel circuit layer 102 includes a plurality of pixel circuits U20 and an initialization signal line Vi, which is configured to transmit an initialization signal to the pixel circuits U20. The light-emitting device layer 103 includes a plurality of light-emitting diodes E0, and each light-emitting diode E0 is connected to a pixel circuit U20. In the display panel 100 viewed from above, the display panel 100 includes a plurality of pixel circuit units U2, in which at least two pixel circuits U20 are arranged in a row along a first direction F1. In the pixel circuit unit U2, on a second direction F2 intersecting the first direction F1, an initialization signal line Vi is disposed between two adjacent rows of pixel circuits U20, and the initialization signal line Vi connects to two rows of pixel circuits U20 simultaneously.

[0147] It is understood that, in this embodiment of the application, by setting two adjacent rows of pixel circuits U20 in pixel circuit unit U2 to share the same initialization signal line Vi, the layout space of the initialization signal line Vi is saved, which facilitates the achievement of high resolution.

[0148] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0149] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0150] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0151] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A pixel circuit layer is disposed on the substrate and includes a plurality of pixel circuits and an initialization signal line, the initialization signal line being configured to transmit an initialization signal to the pixel circuit; A light-emitting device layer is disposed on the side of the pixel circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting diodes, and the light-emitting diodes are correspondingly connected to the pixel circuit. In the display panel viewed from above, the display panel includes a plurality of pixel circuit units, wherein at least two of the pixel circuits are arranged in a row along a first direction; In the pixel circuit unit, in the second direction intersecting the first direction, an initialization signal line is disposed between two adjacent rows of pixel circuits, and the initialization signal line connects both rows of pixel circuits simultaneously.

2. The display panel according to claim 1, characterized in that, The pixel circuit layer includes a reference voltage line configured to provide a reference voltage to the pixel circuit, and the reference voltage line and the initialization signal line are disposed on different layers. In the pixel circuit unit, in the second direction, a reference voltage line is disposed between two adjacent rows of pixel circuits, and the reference voltage line connects both rows of pixel circuits simultaneously.

3. The display panel according to claim 2, characterized in that, In the display panel viewed from above, both the initialization signal line and the reference voltage line extend along the first direction, and the initialization signal line and the reference voltage line at least partially overlap.

4. The display panel according to claim 2, characterized in that, The pixel circuit layer includes a first control line and a second control line disposed in different layers. The first control line is configured to control the input of the initialization signal to the pixel circuit, and the second control line is configured to control the input of the reference voltage to the pixel circuit. In the display panel viewed from above, both the first control line and the second control line extend along the first direction, and the first control line and the second control line are at least partially overlapping.

5. The display panel according to claim 1, characterized in that, The pixel circuit layer includes power lines configured to provide a positive power supply voltage to the pixel circuit, and in the second direction, the power lines are disposed between two adjacent pixel circuit units; In two adjacent pixel circuit units, a power line simultaneously connects a row of pixel circuits in one pixel circuit unit that is close to the power line and a row of pixel circuits in another pixel circuit unit that is close to the power line.

6. The display panel according to claim 1, characterized in that, The pixel circuit layer includes data lines configured to transmit data signals to the pixel circuits, the data lines being disposed on a different layer from the initialization signal lines, and in the pixel circuit unit, at least two of the pixel circuits are arranged in a column along the second direction; In the pixel circuit unit, one data line is connected to a column of pixel circuits, and in one column of at least two columns of pixel circuits, at least two different pixel circuits are connected to light-emitting diodes of different colors.

7. The display panel according to any one of claims 1-6, characterized in that, The pixel circuit includes a first transistor, a storage capacitor, and a second transistor. The first transistor is a driving transistor. The gate of the first transistor and the first plate of the storage capacitor are connected to a first node. The first terminal of the first transistor is connected to a power line. The second terminal of the first transistor, the second plate of the storage capacitor, the second terminal of the second transistor, and the light-emitting diode are connected to a second node. The first terminal of the second transistor is connected to the initialization signal line. The gate of the second transistor is connected to a first control line. In the second direction, the first active portion of the first transistor is connected to the second active portion of the second transistor to form a first active unit; in two adjacent rows of pixel circuits of the pixel circuit unit, in the second direction, the first active units of one row of pixel circuits and the first active units of the other row of pixel circuits are arranged opposite to each other.

8. The display panel according to claim 7, characterized in that, In two adjacent rows of pixel circuits of the pixel circuit unit, the second active part of one row of pixel circuits and the second active part of the other row of pixel circuits are connected by a first connecting part. In the second direction, the first connecting part is disposed between two adjacent second active parts, and the initialization signal line is connected to the first connecting part.

9. The display panel according to claim 8, characterized in that, In two adjacent columns of pixel circuits of the pixel circuit unit, in the first direction, the first active units of one column of pixel circuits and the first active units of the other column of pixel circuits are arranged opposite to each other. The first connection portion simultaneously connects to two rows of pixel circuits and four adjacent second active portions in two columns of pixel circuits, and the initialization signal line is connected to the central region of the first connection portion.

10. The display panel according to claim 9, characterized in that, In two adjacent rows of pixel circuits in the pixel circuit unit, the first active unit of the pixel circuit in one row and the first active unit of the pixel circuit in the other row are mirror images of each other; in two adjacent columns of pixel circuits in the pixel circuit unit, the first active unit of the pixel circuit in one column and the first active unit of the pixel circuit in the other column are mirror images of each other.

11. The display panel according to claim 8, characterized in that, The pixel circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to a second control line, the first terminal of the third transistor is connected to a reference voltage line, the second terminals of the third transistor and the second terminals of the fourth transistor are connected to the first node, the gate of the fourth transistor is connected to the third control line, and the first terminal of the fourth transistor is connected to a data line. In the second direction, the third active portion of the third transistor is connected to the fourth active portion of the fourth transistor to form a second active unit; in two adjacent rows of pixel circuits of the pixel circuit unit, in the second direction, the second active units of one row of pixel circuits and the second active units of the other row of pixel circuits are arranged opposite to each other.

12. The display panel according to claim 11, characterized in that, In two adjacent rows of pixel circuits of the pixel circuit unit, the third active part of one row of pixel circuits and the third active part of the other row of pixel circuits are connected by a second connection part. In the second direction, the second connection part is disposed between two adjacent third active parts, and the reference voltage line is connected to the second connection part.

13. The display panel according to claim 12, characterized in that, In the pixel circuit unit, in the first direction, the second active units of one column of pixel circuits and the second active units of the other column of pixel circuits in two adjacent columns of pixel circuits are arranged opposite to each other; The second connection portion simultaneously connects the four adjacent third active portions in the two rows of pixel circuits and the two columns of pixel circuits, and the reference voltage line is connected to the central region of the second connection portion.

14. The display panel according to claim 13, characterized in that, In two adjacent rows of pixel circuits in the pixel circuit unit, the second active units of one row of pixel circuits and the second active units of the other row of pixel circuits are mirror images of each other; in the pixel circuit unit, the second active units of one column of pixel circuits and the second active units of the other column of pixel circuits in two adjacent columns of pixel circuits are mirror images of each other.

15. The display panel according to claim 13, characterized in that, In the first direction, the first connecting portion and the second connecting portion are alternately spaced.

16. The display panel according to claim 11, characterized in that, The first active part and the second active part are arranged on the same layer, the third active part and the fourth active part are arranged on the same layer, and the first active unit and the second active unit are arranged on different layers. In the pixel circuit, the first active unit and the second active unit are partially overlapped.

17. The display panel according to claim 16, characterized in that, The pixel circuit layer includes a third connection portion disposed on the same layer as the first active unit. The power line and the third connection portion both extend along the first direction. One of the third connection portions simultaneously connects to the first active portions of two adjacent rows of the pixel circuit. In the display panel viewed from above, the third connection portion and the power line are at least partially overlapped, and the power line is connected to the third connection portion through a plurality of vias.

18. The display panel according to claim 17, characterized in that, The first active unit further includes a first extension extending along the first direction, the first extension connecting the connection between the first active part and the second active part, and the second plate of the storage capacitor being electrically connected to the first extension. In the display panel viewed from above, the first extension and the first active portion at least partially overlap in the second direction.

19. The display panel according to claim 18, characterized in that, The first active unit and the second plate of the storage capacitor are both disposed on a different layer from the second node. The second node connects the second plate of the storage capacitor and the first extension, and the second node also connects the connection between the first active part and the second active part.

20. The display panel according to claim 19, characterized in that, The first node and the second node are arranged on the same layer, and the first node and the storage capacitor are arranged on different layers. The first node is connected to the first plate of the storage capacitor. The second active unit is arranged on a different layer from the first node. The second active unit includes a second extension, which is connected to the junction of the third active unit and the fourth active unit. In the display panel viewed from above, in the first direction, the second extension overlaps with the fourth active portion; in the second direction, the second extension overlaps with the third active portion; in the thickness direction of the display panel, the second extension and the first node at least partially overlap; and the second extension is connected to the first node.

21. The display panel according to claim 20, characterized in that, The second active unit includes a third extension. In the second direction, the third extension is connected to the side of the fourth active unit away from the third active unit. The data line is disposed on a different layer from both the second active unit and the power line. The data line is electrically connected to the third extension. In the display panel viewed from above, the third extension is at least partially overlapped with the power cord.

22. The display panel according to claim 11, characterized in that, The pixel circuit layer includes a first active layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a first interlayer dielectric layer, a third conductive layer, a second interlayer dielectric layer, a second active layer, a third insulating layer, a fourth conductive layer, a third interlayer dielectric layer, a fifth conductive layer, a first planarization layer, a sixth conductive layer, and a second planarization layer, stacked sequentially. The first active unit is formed on the first active layer, the first control line and the first electrode are formed on the first conductive layer, the second electrode is formed on the second conductive layer, and the power line, the initialization signal line, the first node and the second node are formed on the third conductive layer. The second active unit is formed on the second active layer, the second control line and the third control line are formed on the fourth conductive layer, the reference voltage line is formed on the fifth conductive layer, and the data line is formed on the sixth conductive layer.

23. The display panel according to any one of claims 1-6, characterized in that, In the pixel circuit unit, in any row of pixel circuits, two pixel circuits drive LEDs of different colors. In two adjacent columns of pixel circuits, two pixel circuits in one column drive LEDs of different colors, and two pixel circuits in the other column drive LEDs of the same color.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-23.

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