Chip package structure and chip package method

Abstract

The chip packaging structure and the chip packaging method provided by the application relate to the technical field of semiconductor packaging. The chip packaging structure comprises inner pins, a first chip, a rewiring layer and solder balls. One side of the inner pins is provided with first pins, and the other side is provided with second pins. The first chip is arranged on one side of the inner pins, and the first chip is electrically connected with the first pins. The rewiring layer is arranged on the side of the inner pins away from the first chip, and the rewiring layer is electrically connected with the second pins. The solder balls are electrically connected with the rewiring layer. The redistribution of the second pins can be realized, the number of input ends and output ends on the back of the inner pins can be increased, and the high-integration packaging is suitable.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Technology

[0002] Existing dual flat no-leads package (DFN) and quad flat no-leads package (QFN) structures have a small number of pins and a dispersed structure, making it difficult to meet the requirements of high power and high integration. How to improve the integration of the package and improve the layout of the package structure is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0003] The purpose of this invention is to provide a chip packaging structure and chip packaging method that can increase the number of pins at the input and output ends of the packaging structure, improve the pin layout at the input and output ends, and improve the integration density.

[0004] In a first aspect, the present invention provides a chip packaging structure, comprising: An inner pin has a first pin on one side and a second pin on the other side; a first groove is formed between adjacent inner pins; The first chip is disposed on one side of the inner pins and overlaps at least two of the inner pins. The first chip covers the opening of the first groove so that the first groove forms a cavity structure. The first chip is electrically connected to the first pins. A redistribution layer is provided on the side of the inner pin away from the first chip, and the redistribution layer is electrically connected to the second pin; Solder ball, which is electrically connected to the redistribution layer.

[0005] In an optional implementation, the first pin is located on the periphery of the first chip, and there is a gap between the first pin and the first chip; the first chip and the first pin are connected by a first wire bonding.

[0006] In an optional embodiment, a molding compound is further included, which is disposed on one side of the inner pin and covers the first chip, the first pin, and the first bonding wire; the molding compound fills the gap between the first pin and the first chip, retaining the cavity structure.

[0007] In an optional implementation, a heat sink is provided between adjacent second pins.

[0008] In an optional embodiment, the cavity structure is provided with a first heat dissipation fin.

[0009] In an optional embodiment, the inner pin is provided with a third groove, which divides the inner pin into a first portion and a second portion that are isolated from each other. The first pin includes a first connection portion and a second connection portion that are isolated from each other. The first connection portion is disposed in the first portion, and the second connection portion is disposed in the second portion. The first connecting portion and / or the second connecting portion are electrically connected to the first chip.

[0010] In an optional embodiment, a second heat dissipation fin is provided in the third groove, and the second heat dissipation fin is spaced apart from the first portion and the second portion respectively.

[0011] In an optional embodiment, a second chip is further stacked on the first chip, the first chip and the first connection portion are electrically connected, the second chip and the second connection portion are electrically connected, and the first chip and the second chip are electrically connected.

[0012] In an optional embodiment, one side of the inner pin is electroplated with metal to form a first pin, and the other side of the inner pin is formed with a plurality of conductive pillars using a subtractive process, the plurality of conductive pillars serving as a second pin; A dielectric layer covers the conductive pillar, and a redistribution layer electrically connected to the conductive pillar is formed within the dielectric layer.

[0013] In an optional embodiment, a heat dissipation block is provided within the dielectric layer.

[0014] In an optional embodiment, the second pin located at the edge of the inner pin has a stepped structure; the stepped structure is exposed from the edge of the dielectric layer.

[0015] In an optional implementation, a second bonding wire is provided between adjacent second pins, and the height of the second bonding wire is higher than the height of the second pin.

[0016] In an optional embodiment, the edge of the second pin forms a misalignment with the edge of the inner pin, and one end of the second bonding wire is connected to the misalignment.

[0017] Secondly, the present invention provides a chip packaging method, comprising: A conductive substrate is provided as an inner pin; a first groove is formed between adjacent inner pins; A first pin is formed on one side of the conductive substrate using an additive method, and a conductive post is formed on the other side using a subtractive method as a second pin. A first chip is mounted on the side having the first pin; the first chip is disposed on one side of the inner pin, the first chip overlaps on at least two of the inner pins, the first chip covers the opening of the first groove so that the first groove forms a cavity structure; the first chip is electrically connected to the first pin. A dielectric layer is formed on one side of the second pin; A redistribution layer connected to the second pin is formed in the dielectric layer; Solder balls that are electrically connected to the redistribution layer are formed on the surface of the dielectric layer.

[0018] In an optional embodiment, the first pin includes a first connection portion and a second connection portion that are independent of each other; the step of forming the first pin on one side of the conductive substrate using an additive method includes: A third, spaced groove is formed on the conductive substrate; A first connecting portion and a second connecting portion are formed on both sides of the third groove, respectively; The step of mounting the first chip on the side having the first pin includes: mounting a stacked first chip and a second chip; wherein the first connecting portion is electrically connected to the first chip, the second connecting portion is electrically connected to the second chip, and the first chip and the second chip are electrically connected. The step of forming conductive pillars as second pins on the other side using a subtractive method includes: etching the conductive substrate to form a plurality of spaced conductive pillars, forming an etching groove between adjacent conductive pillars, and the etching groove communicating with the third groove.

[0019] In an optional embodiment, in the step of etching the conductive substrate to form a plurality of spaced conductive pillars: An edge groove is formed by etching a first depth at the edge of the conductive substrate. The depth of the edge groove is less than the height of the conductive post, so that the conductive post at the edge forms a stepped structure.

[0020] In an optional implementation, prior to the step of forming a dielectric layer on one side of the second pin, the method further includes: A second wire is formed between adjacent conductive posts.

[0021] In an optional implementation, after the step of mounting the first chip on the side having the first pin, the method further includes: A plastic encapsulation is formed to cover the first chip.

[0022] The chip packaging structure and chip packaging method provided in this invention have the following advantages: One side of the inner pins has a first pin for wire bonding to the chip. The inner pins support the chip, and the chip is mounted on adjacent inner pins, creating a cavity structure between the first grooves of adjacent inner pins for heat dissipation. The second pin on the other side of the inner pins is used to lead out the redistribution layer. The redistribution layer allows for the redistribution of the second pins and the design of new solder balls, which helps increase the number of input and output terminals, improves the layout of input and output terminals, facilitates the functional design and layout of the package structure, and increases integration density. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a first type of chip packaging structure provided in an embodiment of the present invention; Figure 2 A top view schematic diagram of a chip packaging structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a second structure of the chip packaging structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a third chip packaging structure provided in an embodiment of the present invention; Figure 5 A schematic diagram of the distribution structure of heat sink and solder balls in a chip packaging structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a fourth chip packaging structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the fifth structure of the chip packaging structure provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of the sixth structure of the chip packaging structure provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the seventh structure of the chip packaging structure provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the eighth structure of the chip packaging structure provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the ninth structure of the chip packaging structure provided in the embodiments of the present invention; Figure 12 This is one of the first process diagrams of the chip packaging method provided in the embodiments of the present invention; Figure 13 This is a second schematic diagram of the first process of the chip packaging method provided in the embodiments of the present invention; Figure 14 This is a schematic diagram of a second process of the chip packaging method provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of a third process in the chip packaging method provided in an embodiment of the present invention; Figure 16 This is one of the fourth process diagrams of the chip packaging method provided in the embodiments of the present invention; Figure 17 This is the second schematic diagram of the fourth process of the chip packaging method provided in the embodiments of the present invention; Figure 18 This is a schematic diagram of the fifth process of the chip packaging method provided in the embodiments of the present invention.

[0025] Icons: 110-Inner pin; 101-Conductive substrate; 111-Second groove; 112-Base island; 113-First groove; 114-Third groove; 115-Etching groove; 116-Edge groove; 117-Cavity; 120-First pin; 121-First connection; 122-Second connection; 130-Second pin; 131-Heat sink; 132-Step structure; 133-Second wire bonding; 134-Misalignment; 140-First chip; 141-First wire bonding; 142-Molded package; 151-Redistribution layer; 152-Solder ball; 153-Dielectric layer; 154-Under-ball pad; 160-Second chip; 135-First heat sink fin; 123-Second heat sink fin; 102-First section; 103-Second section. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0031] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] The chip packaging structure proposed in this invention is beneficial for increasing the number of input and output terminals, improving the layout of input and output terminals, facilitating the functional design and layout of the packaging structure, and improving integration.

[0034] Please combine Figure 1 and Figure 2The chip package structure includes inner pins 110, a first chip 140, a redistribution layer 151, and solder balls 152. One side of the inner pins 110 has a first pin 120, and the other side has a second pin 130. A first groove 113 is formed between adjacent inner pins 110. The first chip 140 is located on the side of the inner pins 110 with the first pin 120, and the first chip 140 is electrically connected to the first pin 120. The first chip 140 and the first pin 120 can be connected by a first wire bonding 141, or they can be soldered; no specific limitation is made here. The number and type of the first chips 140 are not limited. The first chip 140 overlaps at least two inner pins 110, and the first chip 140 covers the opening of the first groove 113, so that the first groove 113 forms a cavity 117 structure. The inner pin 110 supports the first chip 140, placing the first chip 140 and the first pin 120 on the same plane. This facilitates the connection of the first wire bonding 141, reduces the height of the wire arc of the first wire bonding 141, and prevents the wire arc of the first wire bonding 141 from being bent or broken by the molding process. The redistribution layer 151 is located on the side of the inner pin 110 away from the first chip 140, and is electrically connected to the second pin 130. The solder ball 152 is electrically connected to the redistribution layer 151. The redistribution layer 151 redistributes the second pin 130, which helps to increase the number of input and output terminals, improves the layout of input and output terminals, facilitates the functional design and layout of the package structure, and improves integration.

[0035] Optional, please refer to Figure 3 A base island 112 is formed between the inner pins 110. The first chip 140 is mounted on the base island 112. A second groove 111 is formed between the base island 112 and the inner pins 110. The second groove 111 is located between the first chip 140 and the first pin 120. The first chip 140 and the first pin 120 are connected by a first bonding wire 141. One end of the first bonding wire 141 is soldered to the first chip 140, and the other end crosses the second groove 111 and is soldered to the first pin 120.

[0036] It should be noted that the base island 112 and the first pin 120 are independent of each other. Multiple independent second pins 130 are respectively provided on the back side of the base island 112 (the surface away from the first chip 140) and the back side of the first pin 120, and adjacent second pins 130 are separated by an insulating material. The insulating material can be insulating adhesive or dielectric layer 153, etc. In some embodiments, the second pins 130 form a wiring layer, and solder balls 152 are provided on the side of the second pins 130 away from the first pin 120, serving as input and output terminals. In some embodiments, a redistribution layer 151 is provided on the side of the second pins 130 away from the first chip 140, and the redistribution layer 151 is connected to the solder balls 152. No specific limitations are made here.

[0037] Optionally, the chip packaging structure also includes a molding compound 142, which is disposed on one side of the inner pin 110 and covers the first chip 140, the first pin 120, and the first bonding wire 141; the molding compound 142 serves to protect and reinforce the structure. It can be understood that the first pin 120 is located on the periphery of the first chip 140, and there is a gap between the first pin 120 and the first chip 140. The depth of this gap is the height of the first chip 140. The molding compound 142 fills this gap and retains the cavity 117 structure, meaning the first groove 113 is not filled by the molding compound 142.

[0038] It is worth noting that if a structure with a base island 112 is adopted, the gap depth between the first pin 120 and the first chip 140 is the sum of the depth of the second groove 111 and the height of the first chip 140. The deeper the gap, the higher the flow rate of the molding process, and the greater the risk of mold flow impact on the first wire bonding 141.

[0039] Optional, please refer to Figure 1 The edge of the first chip 140 overlaps the periphery of at least two first grooves 113, meaning the first grooves 113 are located at the bottom of the first chip 140. This structure employs a base-island-less design, which improves heat dissipation performance. In this structure, the inner pins 110 provide support for the first chip, and the gap depth between the first pins 120 and the first chip 140 is smaller, which helps to reduce the arc height of the first bonding wire 141 and reduces the risk of the arc of the first bonding wire 141 being bent by the molding flow. The molding body 142 avoids the first grooves 113, so that the first grooves 113 form a cavity 117. That is, the bottom of the first chip 140 is a cavity 117 structure, which is used for heat dissipation, improving heat dissipation performance.

[0040] The back of the first pin 120 has a plurality of spaced second pins 130, and a dielectric layer 153 is provided between the plurality of second pins 130. The second pins 130 are connected to a redistribution layer 151, and solder balls 152 are electrically connected to the redistribution layer 151.

[0041] Optional, please refer to Figure 4 and Figure 5 A heat sink 131 is provided between adjacent second pins 130 to improve heat dissipation performance.

[0042] Please combine Figure 6 Optionally, a first heat dissipation fin 135 is provided inside the cavity 117, which can dissipate heat from the first chip 140 in a timely manner, thereby improving heat dissipation performance. The first heat dissipation fin 135 can be formed by retaining part of the material in the first groove 113 during etching, and the forming process is simple, so no specific limitation is made here.

[0043] Optional, please refer to Figure 7The inner pin 110 has a third groove 114, which divides the inner pin 110 into a first portion 102 and a second portion 103 that are isolated from each other. The first pin 120 includes a first connection portion 121 and a second connection portion 122 that are isolated from each other. The first connection portion 121 is located in the first portion 102, and the second connection portion 122 is located in the second portion 103. The arrangement of the first connection portion 121 and the second connection portion 122 provides a larger number of pins, which is suitable for high-density integrated packaging and can integrate more chips. The first connection portion 121 and / or the second connection portion 122 are electrically connected to the first chip 140.

[0044] Optionally, the chip packaging structure further includes a second chip 160 stacked on the first chip 140. The first chip 140 is electrically connected to the first connection portion 121, and the second chip 160 is electrically connected to the second connection portion 122. In this embodiment, the first chip 140 and the second chip 160 are both upright chips. The first chip 140 and the first connection portion 121 are connected by wire bonding, and the second chip 160 and the second connection portion 122 are connected by wire bonding. Optionally, the first chip 140 and the second chip 160 are connected by wire bonding. The stacked arrangement of the first chip 140 and the second chip 160 results in a compact structure and higher integration. Of course, in other embodiments, the first chip 140 and the second chip 160 can also be flip-chips; this is not specifically limited here. In this embodiment, the chip is connected to the first pin 120 using a wire bonding structure, which provides stronger current overload capability and is suitable for high-computing-power packaging structures.

[0045] Optional, please refer to Figure 8 The third groove 114 is provided with a second heat dissipation fin 123, which is spaced apart from the first section 102 and the second section 103. The second heat dissipation fin 123 serves to conduct heat and does not have an electrical connection function, thereby improving the heat dissipation effect between the first section 102 and the second section 103, and between the first connecting part 121 and the second connecting part 122.

[0046] The second heat dissipation fin 123 can retain part of the material in the third groove 114 as the second heat dissipation fin 123 when the third groove 114 is etched. The forming process is simple and will not be specifically limited here.

[0047] Optionally, the main body of the inner pin 110 is a conductive substrate 101, such as copper. Metal is electroplated on one side of the conductive substrate 101 to form the first pin 120, and conductive pillars are formed on the other side of the conductive substrate 101 using a subtractive process to serve as the second pin 130. Alternatively, an etching process can be used to etch the side of the conductive substrate 101 away from the first pin 120, removing excess material and retaining multiple copper pillar structures as conductive pillars, which then serve as the second pin 130. These multiple conductive pillar structures can also be viewed as a patterned wiring layer formed by etching.

[0048] Optionally, dielectric layer 153 covers conductive pillars, and a redistribution layer 151 electrically connected to the conductive pillars is formed within dielectric layer 153. Redistribution layer 151 redistributes the second pin 130.

[0049] Optionally, a heat sink 131 is provided within the dielectric layer 153. It can be understood that the heat sink 131 may be a portion of the conductive substrate 101 retained after etching. This portion of the conductive substrate 101 does not serve as an electrical connection terminal but rather as a heat dissipation device. The heat sink 131 is located at the bottom of the first chip 140, promptly dissipating the heat generated at the first chip 140 and preventing excessive heat accumulation at the first chip 140.

[0050] Optional, please refer to Figure 9 The second pin 130, located at the edge of the inner pin 110, has a stepped structure 132; the stepped structure 132 protrudes from the edge of the dielectric layer 153. The stepped structure 132 can improve current overload capacity, enhance heat dissipation, and improve the bonding strength between the second pin 130 and the dielectric layer 153. When the solder ball 152 is soldered to other modules such as the substrate, solder side-crawling occurs, meaning solder overflows to the stepped structure 132. The exposed stepped structure 132 is made of metallic material, resulting in a stronger bond between the stepped structure 132 and the solder, making the soldering more reliable. Furthermore, the contact between the dielectric layer 153 and the solder can absorb soldering stress, further improving soldering quality and connection reliability.

[0051] Please combine Figure 10 Optionally, a second bonding wire 133 is provided between adjacent second pins 130, and the height of the second bonding wire 133 is higher than the height of the second pins 130. The setting of the second bonding wire 133 is beneficial to improve the current overload capacity and play an overload protection role; it is beneficial to guide static electricity to the dielectric layer 153 for release; in addition, it also improves the heat dissipation capacity and the bonding force between the dielectric layer 153 and the conductive substrate 101.

[0052] Optionally, the cross-sectional area of ​​the second pin 130 is smaller than that of the inner pin 110, and the edge of the second pin 130 forms a misalignment portion 134 with the edge of the inner pin 110. One end of the second bonding wire 133 is connected to the misalignment portion 134. This arrangement results in a more compact structure and facilitates the conduction of static electricity from the first pin 120 to the dielectric layer 153. The number and distribution of the second bonding wires 133 are not limited.

[0053] It should be noted that if the second bonding wire 133 is grounded, it can provide electromagnetic shielding between the redistribution layers 151 or between the second pins 130. In this embodiment, the solder ball 152 connected to the stepped structure 132 serves as the grounding terminal.

[0054] The aforementioned features, such as base island 112, baseless island, stepped structure 132, heat sink 131, first heat sink fin 135, second heat sink fin 123, and second wiring 133, can be combined with each other without conflict. Please refer to the following: Figure 11 With the base island 112, the first chip 140 is mounted on the base island 112, and the conductive pillars at the edge form a stepped structure 132. Part of the stepped structure 132 is exposed from the dielectric layer 153, and a second bonding wire 133 is designed between the conductive pillars.

[0055] This invention also provides a chip packaging method, comprising: A conductive substrate 101 is provided; the conductive substrate 101 may include a film of copper or a copper alloy, or a film of other metals or metal alloys. The conductive substrate 101 serves as the main structure of the inner pin 110.

[0056] A first pin 120 is formed on one side of the conductive substrate 101 using an additive manufacturing process, and a conductive post is formed on the other side using a subtractive manufacturing process to serve as a second pin 130. The steps for forming the first pin 120 generally include: Please combine Figure 12 Taking a baseless island structure as an example, a first groove 113 with spacing is formed on the conductive substrate 101. When the first chip 140 is mounted, the first chip 140 overlaps the edge of the first groove 113. The first pin 120 and the first chip 140 are connected by the first bonding wire 141, and a molding compound 142 is formed. The molding compound 142 does not fill the first groove 113, retaining the cavity 117 structure formed by the first groove 113.

[0057] Please combine Figure 13 Optionally, a second pin 130 is formed on the side of the conductive substrate 101 away from the first chip 140. Using an etching process, an etch mask with a patterned layer is used to cover the surface of the conductive substrate 101 away from the first chip 140. Excess conductive substrate 101 is removed using exposure and development to form a patterned wiring layer, i.e., the second pin 130. Further residue is removed using a chemical cleaning agent.

[0058] A dielectric layer 153 is formed on one side of the second pin 130. Optionally, the dielectric layer 153 is formed on the side of the conductive substrate 101 having the second pin 130 using a coating process or a lamination process. The material of the dielectric layer 153 can be epoxy resin, polyimide, ABF film, or molding compound, etc.

[0059] A redistribution layer 151 connected to the second pin 130 is formed in the dielectric layer 153 to redistribute the second pin 130; then solder balls 152 electrically connected to the redistribution layer 151 are formed on the surface of the dielectric layer 153.

[0060] Optionally, metal can be selectively pre-plated in the pad area of ​​the redistribution layer 151 as under-ball pads 154. The plating metal includes, but is not limited to, any one or more of nickel, palladium, gold, tin, lead, and silver. Lead-free solder, electroless tin plating of nickel, silver plating, or gold plating can also be used. The number of plating metal layers can be one or more, which is not specifically limited here.

[0061] Optionally, a ball-mounting process is used to form solder balls 152 on the under-ball pad 154. The materials of the solder balls 152 include, but are not limited to, at least one or more of tin, copper, silver, bismuth, indium, zinc, and antimony. Finally, a dicing process is used to separate them into individual products. Please refer to... Figure 14 Taking the base island 112 structure as an example, a second groove 111 is formed on one side of the conductive substrate 101 using chemical etching, stamping, or cutting methods. The second groove 111 separates the base island 112 and the inner pin 110. Metal is selectively pre-plated into the inner pin 110 area using an electroplating process to form a first pin 120. The electroplating material can be one or more of nickel, palladium, gold, and silver. The first pin 120 serves as a wire bonding pad. A first chip 140 is mounted onto the base island 112, and the first chip 140 and the first pin 120 are electrically connected by a first wire bonding 141 to form a molding compound 142. The remaining steps are the same as... Figure 13 The process steps are similar, so they will not be repeated here.

[0062] Optional, such as Figure 15 As shown, in the step of forming the patterned wiring layer, a portion of the conductive substrate 101 can be retained as a heat sink 131. The heat sink 131 is independent of the patterned wiring layer and is located at the bottom of the first chip 140, serving a heat dissipation function. It can be understood that the heat sink 131 and the second pin 130 are spaced apart to form a trench, improving the fluidity of the dielectric layer 153, enhancing the bonding between the dielectric layer 153 and the conductive substrate 101, and improving heat dissipation performance. The heat sink 131 does not need to be connected to the redistribution layer 151 and has no electrical connection function.

[0063] Optional, such as Figure 16 and Figure 17 As shown, the first pin 120 includes a first connecting portion 121 and a second connecting portion 122 that are independent of each other; the step of forming the first pin 120 on one side of the conductive substrate 101 using an additive manufacturing method includes: The step of forming the first groove 113 also includes forming a spaced third groove 114 on the conductive substrate 101; A first connecting portion 121 and a second connecting portion 122 are formed on both sides of the third groove 114; that is, the third groove 114 divides the inner pin 110 into a first portion 102 and a second portion 103, and the first portion 102 and the second portion 103 are electroplated with metal to form the first connecting portion 121 and the second connecting portion 122. The first connecting portion 121 and the second connecting portion 122 are separated from each other by the third groove 114.

[0064] The step of mounting the first chip 140 on the side having the first pin 120 includes: mounting the stacked first chip 140 and second chip 160; wherein the first chip 140 is mounted first, and then the second chip 160 is mounted on the first chip 140. Optionally, the first connection portion 121 and the first chip 140 are electrically connected by wire bonding, the second connection portion 122 and the second chip 160 are electrically connected by wire bonding, and the first chip 140 and the second chip 160 are electrically connected by wire bonding. Afterwards, a molding compound 142 is formed, which encapsulates the first chip 140, the second chip 160, and all the wire bonding structures.

[0065] Optionally, the step of forming conductive pillars as the second pin 130 on the other side using a subtractive process includes: etching the conductive substrate 101 to form multiple spaced conductive pillars, forming etching grooves 115 between adjacent conductive pillars, and the etching grooves 115 communicating with the third groove 114. This completely separates the first connection portion 121 and the second connection portion 122, avoiding circuit bridging. Optionally, the height of the conductive pillars after etching is approximately 100µm to 300µm. The sum of the depth of the etching groove 115 and the depth of the third groove 114 is the thickness of the conductive substrate 101.

[0066] Optional, please refer to Figure 18 In the step of etching conductive substrate 101 to form multiple spaced conductive pillars: An edge groove 116 is formed by etching a first depth at the edge of the conductive substrate 101. The depth of the edge groove 116 is less than the height of the conductive pillar. Multiple conductive pillars are then etched. The depth of the etching groove 115 is deeper than the depth of the edge groove 116, so that the conductive pillars at the edge form a stepped structure 132, which is beneficial to improve the bonding between the dielectric layer 153 and the conductive pillars and improve the overcurrent protection capability.

[0067] Optionally, prior to the step of forming the dielectric layer 153 on one side of the second pin 130, the method further includes: A second bonding wire 133 is formed between adjacent conductive posts. In this embodiment, a misalignment portion 134 is formed between the edge of the first pin 120 and the edge of the second pin 130. One end of the second bonding wire 133 is connected to the misalignment portion 134, and the other end is connected between adjacent conductive posts.

[0068] After forming the second bonding wire 133, a dielectric layer 153 is coated, covering the second bonding wire 133 and multiple conductive posts. Optionally, a redistribution layer 151 electrically connected to the conductive posts is formed within the dielectric layer 153 to redistribute the second pins 130. Finally, solder balls 152 electrically connected to the redistribution layer 151 are formed, and the products are cut and separated into individual products, such as... Figure 10 As shown.

[0069] In summary, the chip packaging structure and chip packaging method provided by the embodiments of the present invention have the following beneficial effects, including: The first pin 120 on one side of the inner pin 110 is used for chip mounting, and the second pin 130 on the other side is used to lead out the redistribution layer 151. The redistribution layer 151 redistributes the second pin 130, and new solder balls 152 are designed, which helps to increase the number of input and output terminals, improve the layout of input and output terminals, facilitate the functional design and layout of the package structure, and improve integration. A cavity 117 structure is formed at the bottom of the first chip 140 to improve heat dissipation. Dividing the first pin 120 into a first connection portion 121 and a second connection portion 122 improves integration and increases the number of input and output terminals in the package structure. Forming a second bonding wire 133 helps to improve overcurrent protection, guide electrostatic discharge, and improve heat dissipation and bonding strength.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: An inner pin has a first pin on one side and a second pin on the other side; a first groove is formed between adjacent inner pins; The first chip is disposed on one side of the inner pins and overlaps at least two of the inner pins. The first chip covers the opening of the first groove so that the first groove forms a cavity structure. The first chip is electrically connected to the first pins. A dielectric layer is disposed on the side of the inner pin away from the first pin and covers the second pin; A redistribution layer is provided on the side of the inner pin away from the first chip, and the redistribution layer is electrically connected to the second pin; the dielectric layer covers the redistribution layer; The edge of the second pin, located at the edge of the inner pin, is exposed from the dielectric layer; A molding compound is disposed on the side of the inner pin away from the second pin and covers the first chip and the first pin. The molding compound does not fill the first groove. The dielectric layer, the first chip, and the inner pin together form a cavity structure. Solder ball, which is electrically connected to the redistribution layer.

2. The chip packaging structure according to claim 1, characterized in that, The first pin is located on the periphery of the first chip, and there is a gap between the first pin and the first chip; the first chip and the first pin are connected by a first wire bonding.

3. The chip packaging structure according to claim 2, characterized in that, The molding compound covers the first bonding wire; the molding compound fills the gap between the first pin and the first chip, and retains the cavity structure.

4. The chip packaging structure according to claim 1, characterized in that, A heat sink is provided between adjacent second pins.

5. The chip packaging structure according to claim 1, characterized in that, The cavity structure is provided with a first heat dissipation fin.

6. The chip packaging structure according to claim 1, characterized in that, The inner pin is provided with a third groove, which divides the inner pin into a first part and a second part that are isolated from each other. The first pin includes a first connection part and a second connection part that are isolated from each other. The first connection part is located in the first part, and the second connection part is located in the second part. The first connecting portion and / or the second connecting portion are electrically connected to the first chip.

7. The chip packaging structure according to claim 6, characterized in that, The third groove is provided with a second heat dissipation fin, which is spaced apart from the first part and the second part respectively.

8. The chip packaging structure according to claim 6, characterized in that, It also includes a second chip stacked on the first chip, the first chip being electrically connected to the first connection portion, the second chip being electrically connected to the second connection portion, and the first chip and the second chip being electrically connected.

9. The chip packaging structure according to claim 1, characterized in that, One side of the inner pin is electroplated with metal to form a first pin, and the other side of the inner pin is formed with multiple conductive pillars using a subtractive process, with the multiple conductive pillars serving as a second pin. A dielectric layer covers the conductive pillar, and a redistribution layer electrically connected to the conductive pillar is formed within the dielectric layer.

10. The chip packaging structure according to claim 9, characterized in that, The dielectric layer contains heat dissipation blocks.

11. The chip packaging structure according to claim 9, characterized in that, The second pin, located at the edge of the inner pin, has a stepped structure; the stepped structure is exposed from the edge of the dielectric layer.

12. The chip packaging structure according to claim 1, characterized in that, A second bonding wire is provided between adjacent second pins, and the height of the second bonding wire is higher than the height of the second pin.

13. The chip packaging structure according to claim 12, characterized in that, The edge of the second pin and the edge of the inner pin form a misalignment portion, and one end of the second bonding wire is connected to the misalignment portion.

14. A chip packaging method, characterized in that, include: A conductive substrate is provided as an inner pin; a first groove is formed between adjacent inner pins; A first pin is formed on one side of the conductive substrate using an additive method, and a conductive post is formed on the other side using a subtractive method as a second pin. A first chip is mounted on the side having the first pin; the first chip is disposed on one side of the inner pin, the first chip overlaps on at least two of the inner pins, the first chip covers the opening of the first groove so that the first groove forms a cavity structure; the first chip is electrically connected to the first pin. A dielectric layer is formed on one side of the second pin; The dielectric layer covers the second pin; the dielectric layer, the first chip, and the inner pin together form a cavity structure. The edge of the second pin, located at the edge of the inner pin, is exposed from the dielectric layer; A redistribution layer connected to the second pin is formed in the dielectric layer; The molding compound is located on the side of the inner pin away from the second pin and covers the first chip and the first pin. The molding compound does not fill the cavity structure. Solder balls that are electrically connected to the redistribution layer are formed on the surface of the dielectric layer.

15. The chip packaging method according to claim 14, characterized in that, The first pin includes a first connection portion and a second connection portion that are independent of each other; the step of forming the first pin on one side of the conductive substrate using an additive method includes: A third, spaced groove is formed on the conductive substrate; A first connecting portion and a second connecting portion are formed on both sides of the third groove, respectively; The step of mounting the first chip on the side having the first pin includes: mounting a stacked first chip and a second chip; wherein the first connecting portion is electrically connected to the first chip, the second connecting portion is electrically connected to the second chip, and the first chip and the second chip are electrically connected. The step of forming conductive pillars as second pins on the other side using a subtractive method includes: etching the conductive substrate to form a plurality of spaced conductive pillars, forming an etching groove between adjacent conductive pillars, and the etching groove communicating with the third groove.

16. The chip packaging method according to claim 15, characterized in that, In the step of etching the conductive substrate to form a plurality of spaced conductive pillars: An edge groove is formed by etching a first depth at the edge of the conductive substrate. The depth of the edge groove is less than the height of the conductive post, so that the conductive post at the edge forms a stepped structure.

17. The chip packaging method according to claim 15, characterized in that, Prior to the step of forming a dielectric layer on one side of the second pin, the method further includes: A second wire is formed between adjacent conductive posts.

18. The chip packaging method according to any one of claims 14-17, characterized in that, After the step of mounting the first chip on the side having the first pin, the method further includes: The encapsulation is formed to cover the first chip.

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