Manufacturing method of double-sided heat dissipation packaging structure and packaging structure

Abstract

The application relates to the field of advanced packaging technology of integrated circuits, and particularly relates to a manufacturing method of a double-side heat dissipation packaging structure and the packaging structure, which comprises the following steps: mounting a chip to a heat dissipation substrate and cutting a plastic package to obtain an inner-embedded unit; embedding the inner-embedded unit into a receiving cavity in a packaging substrate by flip-chip mounting; embedding the inner-embedded unit in a plastic package; slotting and metalizing to form a heat dissipation copper block adhered to the bottom surface of the heat dissipation substrate; drilling and metalizing to form an interconnection through hole; forming a heat dissipation layer and a redistribution layer on the surface of the plastic package layer; manufacturing a solder resist layer and cutting and separating to obtain the double-side heat dissipation packaging structure. The method is compatible with a board-level packaging process, is suitable for planar and vertical structure chips, and can greatly improve the heat dissipation efficiency of power devices without increasing the size of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology for integrated circuits, and specifically to a method for manufacturing a double-sided heat dissipation packaging structure.

[0002] The new energy vehicle and industrial robot industries are experiencing explosive growth, leading to increasingly widespread and in-depth applications of power devices in automotive and industrial control fields. For power devices, high heat dissipation translates to lower junction-to-case thermal resistance, resulting in lower junction temperatures for the same power output, thus extending lifespan and enhancing performance. Therefore, double-sided cooling (DSC) packaging structures represent a significant development trend in power device packaging.

[0003] Power metal-oxide-semiconductor (MOS) devices are divided into conventional vertical MOS structures and planar MOS structures (such as enhancement-mode gallium nitride, E-GaN). Existing packaging methods include traditional leadframe structures, such as... Figure 1 As shown, a double-sided heat dissipation structure cannot be achieved; the copper clip bonding process, such as... Figure 2 As shown, a double-sided heat dissipation structure can be achieved, but its double-sided welding process is difficult, and excessive local stress is hard to eliminate. Furthermore, for planar MOS structures (such as E-GaN), such as... Figure 3 As shown, its source-drain-gate are coplanar, and the active surface is divided into electrodes between the source and drain phases. There is a large voltage difference between the source and drain, which requires strict insulation, making the soldering difficult and the failure risk high. The Copper Clip process cannot encapsulate it into a double-sided heat dissipation structure well.

[0004] Existing packaging solutions with double-sided heat dissipation structures are technically challenging and applicable to a limited range of power devices. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the first aspect of this invention provides a method for manufacturing a double-sided heat dissipation packaging structure. This method utilizes molding and redistribution layer manufacturing processes to achieve a double-sided heat dissipation packaging structure for power chips. The specific technical solution is as follows: A method for manufacturing a double-sided heat dissipation packaging structure includes the following steps: S10 Manufacturing embedded unit: Obtain heat dissipation substrate, mount chip to the top surface of heat dissipation substrate, press first molding layer on the top surface of heat dissipation substrate and above chip, cut to obtain embedded unit, the thermal conductivity of heat dissipation substrate is not less than 100W / (m·K), and the thickness of heat dissipation substrate is 250μm to 1500μm. S20 Embedded Unit Mounting: Obtain the packaging substrate, open a through groove on the packaging substrate to form a receiving cavity, apply temporary bonding adhesive to the bottom surface of the packaging substrate, flip-mount the embedded unit into the receiving cavity, and bond the first molding layer to the temporary bonding adhesive. S30 Molding: The top surface of the encapsulation substrate and the embedded unit are encapsulated to form a second molding layer. After removing the temporary bonding adhesive, a combined molding body is obtained. A third molding layer is pressed onto the bottom surface of the combined molding body. S40 manufactures heat dissipation copper blocks and interconnect vias: slots are cut and metallized in the second molding layer to form heat dissipation copper blocks that fit against the bottom surface of the heat dissipation substrate; holes are drilled and metallized in the third molding layer to form interconnect vias that connect to the chip. S40 forms a heat dissipation layer on the surface of the second molding layer and a redistribution layer on the surface of the third molding layer; the redistribution layer is used for electrical connection and heat dissipation. The S60 is fabricated with a solder mask layer and then cut and separated to obtain a double-sided heat dissipation package structure.

[0006] The heat dissipation substrate can be selected from pure copper substrate, direct plated copper ceramic substrate (DPC), direct bonded copper ceramic substrate (DBC), active metal brazing ceramic substrate (AMB), aluminum silicon carbide substrate, graphene / carbon nanotube composite substrate, and other substrate materials with high heat dissipation capacity.

[0007] High-performance chips have a smaller area and higher power, so their heat flux density during operation is much greater than that of ordinary chips. The thermal conductivity of the heat dissipation substrate is not less than 100W / (m·K), which enables it to dissipate the heat of the chip more quickly. The thickness of the heat dissipation substrate is set to 250μm to 1500μm, which can better meet the thermal conductivity requirements of the chip and the pressure resistance requirements of the packaging structure.

[0008] The mounted chips can be a single chip or multiple chips used to form functional circuits such as half-bridge circuits, dual-core parallel circuits, dual-core series circuits, and full-bridge circuits; chip categories include vertical structure chips and planar structure chips. When mounting chips, peripheral components can be mounted together to facilitate circuit connection and functional expansion. Peripheral components may include passive components, structural copper blocks, etc.

[0009] The molding process can employ compression molding technology. The heat dissipation substrate with the chip already mounted is loaded into a mold, and a sheet of epoxy molding compound (EMC) is placed over the front of the chip. The mold is closed while vacuum degassing is activated. After the mold is fully closed, a specific pressure is applied, and the molding compound melts and flows to fill the gaps and evenly cover the chip and substrate surfaces. The process is maintained at temperature and pressure for a period of time. After the molding compound has cured, it is removed and transferred to an oven. Depending on the characteristics of the molding compound, post-curing is performed at a certain temperature to form a molecular cross-linked structure, eliminate internal stress, and improve mechanical strength.

[0010] Molding the chip during the manufacturing process of embedded cells protects it and avoids the following losses: When the chip is exposed, it is subjected to pressure from the mold during molding and embedding into the packaging substrate. This pressure is transmitted to the fragile chip wafer through the incompletely melted molding compound, potentially leading to chipping or even breakage. Furthermore, after molding, the outer surface of the embedded cell is a flat first molding layer, and the back is a flat surface of the heat dissipation substrate. This flat structure on both sides facilitates the pick-up, transfer, and placement of the chip by mounting equipment, improving placement yield.

[0011] The packaging substrate is generally a copper-clad laminate, but it can also be an organic substrate such as a fiberglass reinforced epoxy resin substrate (FR-4), an aramid substrate, or a BT resin substrate.

[0012] Through pattern etching and laser grooving, through slots are cut into the package substrate at the designed positions to serve as cavities for accommodating embedded cells. To facilitate temporary fixation of the embedded cells, temporary bonding adhesive is applied to the bottom of the cavity with the adhesive side facing the cavity. The embedded cells are then placed upside down (chip side down) into the cavity using a mounting device, and the first molding layer is bonded and fixed to the temporary bonding adhesive.

[0013] After the embedded unit is encapsulated, the position of the embedded unit in the cavity is fixed by the second encapsulation layer formed by the cured encapsulant. At this time, the temporary bonding adhesive can be removed by photolysis, pyrolysis or physical removal according to the characteristics of the temporary bonding adhesive to obtain the encapsulated body.

[0014] In the second molding layer, a laser is used to create a large blind trench, exposing the back side of the embedded unit. The back side is generally made of copper, so the blind trench can be metallized by direct copper plating to form a copper block that is eutectic bonded to the copper on the back side as a heat dissipation copper block. In the third molding layer, a laser is used to drill blind holes to the chip pads. Through processes such as sputtering, copper plating, and electroplating, the blind holes are metallized to form columnar interconnect vias. One end is connected to the electrode pads of the chip or peripheral components, and the other end is used to connect to the redistribution layer to achieve signal conduction.

[0015] A heat dissipation layer is formed on the surface of the second molding layer using semi-additive and subtractive redistribution processes to balance the redistribution layer stack. A redistribution layer connected to interconnect vias is formed on the surface of the third molding layer. The redistribution layer is used for both fan-out of electrode signals and heat dissipation of the power chip.

[0016] After fabricating the solder mask layer and cutting it apart, a double-sided heat dissipation package structure is obtained. At this point, the redistribution layer in the package structure serves as the heat dissipation structure on the chip pad side, while the heat dissipation substrate, heat dissipation copper block, and heat dissipation layer together constitute the heat dissipation structure on the back of the chip.

[0017] Furthermore, the steps for forming the redistribution layer are as follows: A conductive and thermally conductive layer is deposited and patterned on the third molding layer, the conductive and thermally conductive layer having multiple mutually insulated heat dissipation copper regions; And, when the total number of rewiring layers is greater than 1, perform the following steps: S401 laminates a dielectric layer onto the most recently formed conductive and thermally conductive layer, forming interconnect vias in the dielectric layer; S402 deposits and patterns a conductive and thermally conductive layer on the dielectric layer; Repeat steps S401 to 402 until the required total number of redistribution layers is reached; the sum of the areas of the heat dissipation copper regions in any conductive and thermally conductive layer shall account for no less than 90% of the total area of ​​the conductive and thermally conductive layer.

[0018] When the circuit is relatively simple or the product thickness requirements are strict, the redistribution layer can be set to 1 layer, that is, a conductive and thermally conductive layer can be directly deposited and patterned on the second molding layer. When the circuit is more complex, in order to avoid signal interference between circuits and facilitate external connection, the redistribution layer can be set to 2 or more layers. The required number of redistribution layers can be achieved by repeatedly laminating dielectric layers, forming vias, and patterning conductive and thermally conductive layers.

[0019] The heat dissipation copper area is used for both connecting other circuits and heat dissipation. Setting it to a large area ratio (not less than 90%) greatly increases the cross-sectional area of ​​the heat conduction path without increasing the package structure size, significantly reduces thermal resistance, and greatly improves the heat dissipation efficiency of power devices.

[0020] Furthermore, interconnect vias form a thermally conductive array in the corresponding dielectric layer for electrical connection and heat dissipation of the heat-dissipating copper area.

[0021] The thermal via array can efficiently conduct heat from the chip pads and heat dissipation copper area in the package structure to the outermost heat dissipation copper area, and so on, until it reaches the outermost layer, thereby further improving heat dissipation efficiency.

[0022] Furthermore, the thickness of the packaging substrate is less than the thickness of the embedded unit.

[0023] Typically, chip thickness is 80μm-200μm, passive component thickness is 100μm-350μm, heat dissipation substrate thickness is approximately 500-1500μm, and embedded unit thickness can reach 700-2000μm. In this case, if a packaging substrate with a thickness greater than that of the embedded unit is used, the aspect ratio of the gap that the molding compound needs to fill during molding increases sharply, making it difficult for the molding compound to fully fill the gap. It is necessary to increase the size of the cavity or select a molding compound with higher fluidity to meet the molding requirements. On the one hand, these two solutions will increase the size of the packaging structure, and the molding compound with higher fluidity is more expensive, resulting in a significant increase in cost. On the other hand, changes in the fluidity of the molding compound will lead to the deterioration of other parameters such as the coefficient of thermal expansion, and ultimately affect the reliability of the packaging structure.

[0024] By setting the thickness of the packaging substrate to be less than the thickness of the embedded unit, since the chip in the embedded unit is embedded and protected by the first molding compound layer, even if the embedded unit protrudes from the cavity during the lamination of the second molding compound layer, the pressure applied to the embedded unit is absorbed by the first molding compound layer, significantly reducing the risk of chip damage. At the same time, the aspect ratio of the gap to be filled in the cavity is reduced, necessitating better flowability of the molding compound and avoiding increased cost and risk in the packaging structure.

[0025] Furthermore, the thickness h of the packaging substrate core Determine according to the following steps: A. The flow coefficient L of the molding compound used when laminating the second molding layer fl ; B. Obtain the total height H and remaining slot width Ld of the combined molding compound based on the design. The thickness h of the C-package substrate core Satisfy the following formula: ; .

[0026] Use the steps described above to determine the thickness h of the packaging substrate. core The principle is as follows: During the manufacturing of the second molding layer, the total height H of the assembled molding body is equal to the thickness h of the packaging substrate. core The thickness h of the sheet molding compound EMC The sum of (Formula 1) To ensure that the molding compound completely fills the gap between the embedded unit and the receiving cavity, the flow volume V of the molding compound needs to be guaranteed. fl Not less than the volume V of the gap to be filled cav The volume of adhesive flow V fl Calculate using the following formula (Formula 2) in It is the flow coefficient of the molding compound, which is the ratio of the flow distance of the molding compound to its thickness, and can be obtained through testing; Thickness is The flow distance of the molding compound; C is the perimeter of the cavity, obtained according to the design; Volume V of the gap to be filled cav Calculate using the following formula: (Formula 3) Where L d The remaining slot width, i.e., the distance from the edge of the embedded unit to the nearest receiving cavity sidewall, can be obtained according to the design; Based on the flow volume V fl Not less than the volume V of the gap to be filled cav Combining formulas 2 and 3, we can obtain (Formula 4) Substituting into Formula 1, we can calculate... ; In the compression molding process of sheet molding compound, the thickness is generally no more than 500μm, depending on the coating process range. Combining with Formula 1, we can obtain .

[0027] Furthermore, the flow coefficient L fl The following methods were used for determination: A1. Take a sheet of molding compound with a thickness of h and cut it to obtain a square sample with a side length of a; A2. Laminate the square sample onto the copper-clad laminate to form an adhesive layer; A3. Measure the length L1 and width L2 of the laminated layer; according to the formula... Calculate the flow length L of the press-fit layer; A4. Repeat steps A1-A3 to obtain multiple flow lengths L, calculate the average value L0, and then apply the formula... Calculate the flow coefficient L fl .

[0028] This invention provides a method for determining the flow coefficient of sheet molding compound, by introducing the flow coefficient L fl This method transforms the flow behavior into quantitative parameters. It can accurately define the encapsulation process window and effectively prevent insufficient adhesive.

[0029] Furthermore, the pressing of the first molding layer includes the following steps: The bottom surface of the heat dissipation substrate in the embedded unit is fixed to the stainless steel plate to form an assembly. The assembly is placed on the oven table with the embedded unit at the bottom and the stainless steel plate at the top. The stainless steel plate is pressed by its own weight and baked and cured in a nitrogen atmosphere.

[0030] Since the molding process of chips and peripheral components is single-sided molding, there is a risk of warping due to chemical shrinkage during curing. Stainless steel plates are rigid and have a low coefficient of thermal expansion. Their supporting role and the application of gravity can release curing stress.

[0031] Furthermore, the thickness of the stainless steel plate shall not be less than 10mm.

[0032] The stainless steel plate needs to have sufficient rigidity and appropriate quality. The present invention sets the thickness of the stainless steel plate to not less than 10mm, which can provide better support and pressure.

[0033] Furthermore, the heat dissipation substrate is a ceramic substrate, which is formed by sequentially laminating an upper copper layer, a ceramic core layer, and a lower copper layer. Before mounting the chip, the upper copper layer is etched to form mounting islands, which also serve as chip mounting markers.

[0034] Using a ceramic substrate as the heat dissipation substrate offers advantages such as excellent thermal conductivity and natural insulation properties. It allows for direct connection to external heat dissipation structures, improving heat dissipation efficiency and extending the lifespan and performance of power devices. Etching the upper copper layer to form mounting islands increases the creepage distance between the upper and lower copper layers. Furthermore, the islands' outlines serve as independent mounting markers for each chip, increasing chip mounting yield.

[0035] A second aspect of the present invention provides a double-sided heat dissipation packaging structure, which is manufactured using any of the aforementioned manufacturing methods.

[0036] In summary, this invention discloses a method for manufacturing a double-sided heat dissipation packaging structure. Using the above-described solution, the beneficial effects of this invention are as follows: 1. A method for manufacturing a double-sided heat dissipation packaging structure compatible with board-level packaging technology is provided. It is not only applicable to conventional vertical structure MOS, but also well applicable to planar structure MOS, avoiding the problems of high difficulty and high failure risk of existing copper sheet clip bonding and soldering.

[0037] 2. The redistribution layer is set as multiple insulated heat-dissipating copper areas, which are used for both electrical connection and heat dissipation. The sum of the areas of the heat-dissipating copper areas is set to account for more than 90%. While ensuring the interconnection of electrical signals, the cross-sectional area of ​​the heat conduction path is greatly increased, the thermal resistance is significantly reduced, and the heat dissipation efficiency of power devices is greatly improved without increasing the package structure size.

[0038] 3. By pre-molding and embedding the chip to form an embedded unit, the chip is protected by the molded package. When mounting and embedding the package substrate, a receiving cavity with a height smaller than that of the embedded unit can be selected. On the one hand, this reduces the aspect ratio of the gap between the embedded unit and the receiving cavity, which facilitates good filling of the molding compound during molding and reduces voids in the molding layer. On the other hand, it can prevent the chip from breaking during lamination.

[0039] 4. Calculate the thickness range of the receiving cavity based on the design thickness of the molding compound, the remaining groove width, and the flow distance of the molding compound. This will help guide the selection of production processes and reduce costs.

[0040] 5. Using a ceramic substrate as a heat dissipation substrate, the ceramic core layer has good thermal conductivity and natural insulation properties, and can be directly connected to an external heat dissipation structure to improve heat dissipation efficiency and enhance the lifespan and performance of power devices. Attached Figure Description

[0041] Figure 1 It is a lead frame packaging structure based on existing technology; Figure 2 It is a packaging structure based on existing copper sheet clip bonding technology; Figure 3 This is a diagram showing the electrode distribution of a planar chip structure. Figures 4-13 This is a schematic diagram of the manufacturing process of a double-sided heat dissipation packaging structure according to Embodiment 1; Figures 14-21 This is a schematic diagram of the manufacturing process of a double-sided heat dissipation packaging structure according to Embodiment 2; Figure 22 This is a schematic diagram of the packaging structure obtained by a method for manufacturing a double-sided heat dissipation packaging structure according to Embodiment 3; Figure 23 yes Figure 22 Enlarged view of point A in the middle; Figure 24 This is a schematic diagram of the method for determining the flow coefficient of the molding compound in Example 3; Figures 25-27 This is a schematic diagram of the manufacturing process of a double-sided heat dissipation packaging structure according to Embodiment 4.

[0042] In the picture:

[0043] 1-Embedded unit; 11-Heat dissipation substrate; 113-Upper copper layer; 114-Ceramic core layer; 115-Lower copper layer; 116-Mounting island; 12-First molding compound layer; 2-Chip; 3-Packaging substrate; 30-Combined molding compound; 31-Receiving cavity; 32-Second molding compound layer; 321-Heat dissipation copper block; 33-Third molding compound layer; 4-Temporary bonding adhesive; 5-Reconnection layer; 51-Conductive and thermally conductive layer; 511-Heat dissipation copper area; 52-Dielectric layer; 6-Heat dissipation layer; 7-Interconnect via; 71-Temperature conductive hole array; 8-Stainless steel plate; 9-Pyrolytic adhesive. Detailed Implementation

[0044] The following description, in conjunction with the accompanying drawings, further illustrates an encapsulation structure, its over-temperature protection method, and its manufacturing method according to the present invention.

[0045] Example 1 Figures 4-13 The figure shown is a method for manufacturing a double-sided heat dissipation packaging structure according to an embodiment of the present invention, including the following steps: S10 Manufacturing embedded unit 1: Obtain heat dissipation substrate 11, attach chip 2 to the top surface of heat dissipation substrate 11, press the first molding layer 12 on the top surface of heat dissipation substrate 11 and above chip 2, cut to obtain embedded unit 1, the thermal conductivity of heat dissipation substrate 11 is not less than 100W / (m·K), and the thickness of heat dissipation substrate 11 is 250μm to 1500μm. like Figure 4 As shown, the substrate in this embodiment is a pure copper substrate with a thermal conductivity of approximately 400 W / (m·K). Figure 5 As shown, the mounted chip 2 includes a planar chip and a vertical chip. The source, drain, and gate pads of the planar chip are all located on the front side of the chip; the source and gate pads of the vertical chip are located on the front side of the chip, and the drain pad is located on the back side of the chip; all chips 2 are back-side soldered to the top surface of the heat sink substrate 11. To facilitate the extraction of signals from the back side of the vertical chip, this embodiment also includes a structural copper block mounted on the top surface of the heat sink substrate 11. Figure 6 As shown, a first molding compound 12 is laminated on the top surface of the heat dissipation substrate 11 and above the chip 2 and the structural copper block, and the embedded unit 1 is obtained by cutting. S20 Surface Mount Embedded Unit 1: (e.g.) Figures 7-9 As shown, a packaging substrate 3 is obtained, a through groove is formed on the packaging substrate 3 to form a receiving cavity 31, a temporary bonding adhesive 4 is attached to the bottom surface of the packaging substrate 3, the embedded unit 1 is flipped into the receiving cavity 31, and the first molding layer 12 is bonded to the temporary bonding adhesive 4. S30 plastic sealing: such as Figures 10-11As shown, the top surface of the embedded unit 1 and the encapsulation substrate 3 is encapsulated to form a second encapsulation layer 32, and the encapsulation material fills the gap between the embedded unit 1 and the receiving cavity 31; after removing the temporary bonding adhesive 4, the combined encapsulation body 30 is obtained, and a third encapsulation layer 33 is pressed onto the bottom surface of the combined encapsulation body 30. S40 manufactures heat sinks and interconnect vias: such as Figure 12 As shown, a groove is made and metallized in the second molding layer 32 to form a heat dissipation copper block 321 that is attached to the bottom surface of the heat dissipation substrate 11. Holes are drilled and metallized in the third molding layer 33 to form interconnection vias 7 that communicate with the chip 2 and peripheral components. S40 Figure 13 As shown, a heat dissipation layer 6 is formed on the surface of the second molding layer 32, and a redistribution layer 5 is formed on the surface of the third molding layer 33; the redistribution layer 5 is used for electrical connection and heat dissipation.

[0046] The redistribution layer 5 is formed by depositing and patterning a conductive and thermally conductive layer 51 on the second molding layer 32. The conductive and thermally conductive layer 51 has multiple mutually insulated heat dissipation copper regions 511. The heat dissipation layer 6 and the heat dissipation copper block 321 are electroplated in the same process.

[0047] The S60 is fabricated with a solder mask layer and then cut and separated to obtain a double-sided heat dissipation package structure.

[0048] Example 2 Figures 14-20 The diagram shows a method for manufacturing a double-sided heat dissipation packaging structure according to Embodiment 2 of the present invention, which differs from Embodiment 1 in that: like Figures 14-15 As shown, in this embodiment, the heat dissipation substrate 11 is a ceramic substrate with a total thermal conductivity of about 200 W / (m·K). It is formed by sequentially laminating an upper copper layer 113, a ceramic core layer 114, and a lower copper layer 115. Before mounting the chip 2, the upper copper layer 113 is etched to form mounting islands 116, which also serve as chip mounting markers.

[0049] Figure 16 The image shown is a panel layout diagram of the entire chip assembly in this embodiment.

[0050] Figure 17 The diagram shown is a top view after the interconnecting vias 7 are formed in the third molding layer 33.

[0051] In this embodiment, the redistribution layer 5 has a total of 2 layers and is manufactured by performing the following steps: like Figure 18 As shown, a conductive and thermally conductive layer 51 is deposited and patterned on the third molding layer 33. The conductive and thermally conductive layer 51 has multiple mutually insulated heat dissipation copper regions 511. S401 Figure 19As shown, a dielectric layer 52 is laminated onto the most recently formed conductive and thermally conductive layer 51, and interconnecting vias 7 are formed in the dielectric layer 52; in some embodiments, the interconnecting vias 7 form a thermally conductive hole array 71 in the corresponding dielectric layer 52 for electrical connection and heat dissipation of the heat dissipation copper region 511.

[0052] .S402 Figure 20 As shown, a conductive and thermally conductive layer 51 is deposited and patterned on the dielectric layer 52.

[0053] like Figure 21 As shown, when the number of redistribution layers 5 is 2, a redistribution layer manufacturing process is used to manufacture 2 heat dissipation layers 6 on the surface of the second molding layer 32 to achieve stacking balance.

[0054] In some embodiments, to facilitate electrical connection, the number of redistribution layers 5 can be set to 2 or more. In this case, steps S401 to 402 can be repeated until the required total number of redistribution layers 5 is reached. Correspondingly, a heat dissipation layer 6 with the same number of layers is manufactured on the surface of the second molding layer 32 to achieve stacking balance.

[0055] The sum of the areas of the heat dissipation copper regions 511 in any conductive and heat-conducting layer 51 shall account for no less than 90% of the total area of ​​the conductive and heat-conducting layer 51.

[0056] Example 3

[0057] Figure 22 , Figure 23 The diagram shown is a schematic of a package structure obtained by a method for manufacturing a double-sided heat dissipation package structure according to Embodiment 3 of the present invention. The difference from Embodiment 1 is that: The thickness h of the packaging substrate 3 core It is less than the thickness h1 of the embedded unit 1.

[0058] The thickness h of the packaging substrate 3 core The scope is determined according to the following steps: A. The flow coefficient L of the molding compound used when obtaining the second molding layer 32 during lamination. fl ; B. Obtain the total height H of the combined molding compound 30 and the remaining slot width Ld according to the design; The thickness h of the C-package substrate 3 core Satisfy the following formula: ; .

[0059] The remaining slot width L d The horizontal distance between the edge of embedded unit 1 and the nearest receiving cavity sidewall; flow coefficient L flThis refers to the coefficient relating the distance the molding compound flows and diffuses after melting under the specified pressing parameters to the thickness of the molding compound.

[0060] like Figure 24 As shown, the flow coefficient L is determined using the following method in this embodiment. fl : A1. Take a sheet of molding compound with a thickness of h and cut it to obtain a square sample with a side length of a; A2. The square sample is laminated onto a copper-clad laminate to form a laminate layer with a thickness of h. A3. Measure the length L1 and width L2 of the laminated layer; according to the formula... Calculate the flow length L of the press-fit layer; A4. Repeat steps A1-A3 to obtain multiple flow lengths L, calculate the average value L0, and then apply the formula... Calculate the flow coefficient L fl .

[0061] A preferred implementation is shown below: Three sheets of molding compound with dimensions of 408*510mm and a thickness of 100μm were taken and uniformly sampled using the 9-point method. Square samples with a side length of 20mm were cut from the molding compound, resulting in a total of 27 samples. The sample was placed on a copper-clad laminate and then placed in a vacuum laminator for a two-step lamination process. The lamination thickness was h, and the lamination parameters were as follows: Step 1: Pressure 8.0 kg / cm 2 Temperature 75℃, pressing time 60s, vacuum degree 2.0hpa, vacuum time 60s; Step 2: Pressure 3.0 kg / cm2, temperature 60℃, pressing time 10s.

[0062] After lamination, the copper-clad laminate is removed, and the length L1 and width L2 of the laminated layer formed for each sample are measured. Calculate the flow length L of the press-fit layer; Repeat steps A1-A3 until the flow length L of all 27 samples is obtained. The average value L0 = 1.0 mm can be calculated, and the flow coefficient L can be calculated. fl It is 10.

[0063] Taking the following design parameters as an example: the height H of the combined molding compound 30 is 1mm, and the remaining groove width L d It is 0.2mm, and the calculation yields... ; .

[0064] Considering the packaging substrate specifications and molding compound costs, a 0.8mm thick packaging substrate can be selected for embedded packaging of an embedded unit 1 with a thickness of approximately 1mm.

[0065] Example 4

[0066] Figures 25-27 The diagram shows a method for manufacturing a double-sided heat dissipation packaging structure according to Embodiment 4 of the present invention, which differs from Embodiment 1 in that: The pressing of the first molding layer 12 includes the following steps: The bottom surface of the heat dissipation substrate 11 is fixed to the stainless steel plate 8 to form an assembly. The assembly is placed on the oven table with the chip 2 at the bottom and the stainless steel plate 8 at the top. The stainless steel plate 8 is pressed by its own weight and baked and cured in a nitrogen atmosphere before the stainless steel plate 8 is removed.

[0067] The thickness of the stainless steel plate shall not be less than 10mm.

[0068] In this embodiment, the pyrolytic adhesive 9 is used for temporary fixation. The pyrolytic adhesive 9 has a debonding temperature higher than the curing temperature, so it can maintain its adhesiveness during curing. After curing, the stainless steel plate 8 can be removed by debonding on the heating platform.

[0069] In some implementations, temporary fixation can also be achieved using photodegradable bonding adhesives, pressure-sensitive adhesives, and other bonding materials.

[0070] Example 5 A double-sided heat dissipation packaging structure is manufactured using any of the manufacturing methods described in Embodiments 1 to 4 above.

Claims

1. A method for manufacturing a double-sided heat dissipation packaging structure, characterized in that, Includes the following steps: S10 Manufacturing embedded unit (1): Obtain heat dissipation substrate (11), attach chip (2) to the top surface of heat dissipation substrate (11), press the first plastic sealing layer (12) on the top surface of heat dissipation substrate (11) and chip (2), cut to obtain embedded unit (1), the thermal conductivity of heat dissipation substrate (11) is not less than 100W / (m·K), and the thickness of heat dissipation substrate (11) is 250μm to 1500μm; S20 Mounting Embedded Unit (1): Obtain the encapsulation substrate (3), open a through groove on the encapsulation substrate (3) to form a receiving cavity (31), attach temporary bonding adhesive (4) to the bottom surface of the encapsulation substrate (3), flip the embedded unit (1) into the receiving cavity (31), and bond the first plastic encapsulation layer (12) to the temporary bonding adhesive (4). S30 Molding: The top surface of the encapsulation substrate (3) and the embedded unit (1) are encapsulated to form a second molding layer (32). After removing the temporary bonding adhesive (4), a combined molding body (30) is obtained. A third molding layer (33) is pressed onto the bottom surface of the combined molding body (30). S40 Manufacturing heat dissipation copper block and interconnect via: Grooving and metallizing the second molding layer (32) to form a heat dissipation copper block (321) that is attached to the bottom surface of the heat dissipation substrate (11); drilling and metallizing the third molding layer (33) to form an interconnect via (7) that communicates with the chip (2). S50 forms a heat dissipation layer (6) on the surface of the second molding layer (32) and a redistribution layer (5) on the surface of the third molding layer (33); the redistribution layer (5) is used for electrical connection and heat dissipation; The S60 is fabricated with a solder mask layer and then cut and separated to obtain a double-sided heat dissipation package structure.

2. The manufacturing method as described in claim 1, characterized in that, The step of forming the redistribution layer (5) is as follows: A conductive and thermally conductive layer (51) is deposited and patterned on the third molding layer (33), the conductive and thermally conductive layer (51) having a plurality of mutually insulated heat dissipation copper regions (511). And, when the total number of redistribution layers (5) is greater than 1, the following steps are performed: S401 laminates a dielectric layer (52) onto the most recently formed conductive and thermally conductive layer (51), and forms interconnecting vias (7) in the dielectric layer (52). S402 deposits and patterns a conductive and thermally conductive layer (51) on the dielectric layer (52); Repeat steps S401 to S402 until the total number of redistribution layers (5) required is reached; The sum of the areas of the heat dissipation copper regions (511) in any conductive and heat-conducting layer (51) shall account for no less than 90% of the total area of ​​the conductive and heat-conducting layer (51).

3. The manufacturing method as described in claim 2, characterized in that, The interconnecting vias (7) form a thermally conductive hole array (71) in the corresponding dielectric layer (52) for electrical connection and heat dissipation of the heat dissipation copper area (511).

4. The manufacturing method as described in claim 1, characterized in that, The thickness of the encapsulation substrate (3) is less than the thickness of the embedded unit (1).

5. The manufacturing method as described in claim 4, characterized in that, The thickness h of the packaging substrate (3) core Determine according to the following steps: The flow coefficient L of the molding compound used when A obtains the second molding layer (32) is... fl ; B obtains the total height H of the combined molding compound (30) and the remaining slot width L according to the design. d ; The thickness h of the packaging substrate (3) mentioned in C core Satisfy the following formula: ； 。 6. The manufacturing method as described in claim 5, characterized in that, The flow coefficient L fl The following methods were used for determination: A1. Take a sheet of molding compound with a thickness of h and cut it to obtain a square sample with a side length of a; A2. The square sample is laminated onto a copper-clad laminate to form a laminate layer with a thickness of h. A3. Measure the length L1 and width L2 of the laminated layer; according to the formula... Calculate the flow length L of the press-fit layer; A4. Repeat steps A1-A3 to obtain multiple flow lengths L, calculate the average value L0, and then apply the formula... Calculate the flow coefficient L fl .

7. The manufacturing method as described in claim 1, characterized in that, The pressing of the first molding layer (12) includes the following steps: The bottom surface of the heat dissipation substrate (11) is fixed to the stainless steel plate (8) to form an assembly. The assembly is placed on the oven table with the chip (2) at the bottom and the stainless steel plate (8) at the top. The stainless steel plate (8) is pressed by its own weight and baked and cured in a nitrogen atmosphere before the stainless steel plate (8) is removed.

8. The manufacturing method as described in claim 7, characterized in that, The thickness of the stainless steel plate (8) is not less than 10 mm.

9. The manufacturing method as described in claim 1, characterized in that, The heat dissipation substrate (11) is a ceramic substrate. The ceramic substrate is formed by sequentially laminating an upper copper layer (113), a ceramic core layer (114), and a lower copper layer (115). Before mounting the chip (2) and peripheral components, the upper copper layer (113) is etched to form a mounting island (116). The mounting island (116) also serves as a chip mounting identifier.

10. A double-sided heat dissipation packaging structure, characterized in that, The double-sided heat dissipation packaging structure is manufactured using the manufacturing method described in any one of claims 1 to 9.

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