Capacitive sensing circuit, system and apparatus thereof
Patent Information
- Application Number
- CN202480036484.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2026-08-28
Smart Images
Figure CN122663552A_ABST
Abstract
Description
Background Technology
[0001] This disclosure relates to capacitive sensing circuits, systems, and devices thereof.
[0002] Capacitive sensing, especially capacitive touch sensing, is a technique that utilizes the change in capacitance that occurs when an object (such as a human finger or stylus) approaches a capacitor. The presence of a finger or stylus increases capacitance by introducing a material with a relatively high dielectric constant (such as the human body or stylus) and providing a conductive surface that forms an additional capacitance in parallel with the existing capacitor.
[0003] Summary of the Invention In one aspect, a capacitance sensing circuit includes: a current mirror circuit configured to receive two input current signals respectively associated with two corresponding capacitance values and output two mirrored current signals; a current differential summing circuit configured to receive the two mirrored current signals from the current mirror circuit and output a current differential signal and a current summing signal; a transconductance circuit including a transconductance device, wherein the transconductance circuit is configured to receive the current summing signal and output a feedback current; and a clamping circuit configured to receive the feedback current and minimize the difference between two voltages at two corresponding nodes of the current mirror circuit.
[0004] In some embodiments, the current mirror circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are connected via a first common source node, and the third transistor and the fourth transistor are connected via a second common source node.
[0005] In some embodiments, the first transistor and the second transistor are configured to receive the two input current signals associated with the two corresponding capacitance values, and the third transistor and the fourth transistor are configured to output the two mirrored current signals.
[0006] In some embodiments, the first gate of the first transistor is connected to the fourth gate of the fourth transistor, and the second gate of the second transistor is connected to the third gate of the third transistor.
[0007] In some embodiments, the current differential signal is configured as an output current.
[0008] In some embodiments, the current summation signal is configured to provide an output voltage via an output resistor.
[0009] In some embodiments, the transconductance device includes a negative input terminal and a positive input terminal, wherein the negative input terminal is configured to receive the current differential signal and the positive input terminal is grounded.
[0010] In some embodiments, the clamping circuit includes a bias current source, an operational amplifier, and a fifth transistor, wherein the positive input of the operational amplifier is configured to receive the feedback current, the negative input of the operational amplifier is connected to the source terminal of the fifth transistor, and the output of the operational amplifier is configured to be connected to the gate terminal of the fifth transistor.
[0011] In some embodiments, the clamping circuit is configured to be connected to an input voltage provided to the current mirror circuit via the bias current source and the fifth transistor.
[0012] In some embodiments, the current mirror circuit is configured to receive the two input current signals associated with the two corresponding capacitance values of the touch panel circuit.
[0013] In another aspect, a touch panel device includes: a touch panel circuit including a capacitor array; a drive circuit coupled to the touch panel circuit and configured to drive a transmitting voltage to the capacitor array; a sensing control circuit coupled to the touch panel circuit and configured to receive a received voltage from the capacitor array; a capacitance sensing circuit coupled to the sensing control circuit and configured to detect the capacitance of the capacitor array; a microcontroller unit configured to perform operation of the touch panel device; and a memory configured to store data from the capacitance sensing circuit or the microcontroller unit, wherein the capacitor... The capacitive sensing circuit includes: a current mirror circuit configured to receive two input current signals associated with two corresponding capacitance values and output two mirrored current signals; a current differential summing circuit configured to receive the two mirrored current signals from the current mirror circuit and output a current differential signal and a current summing signal; a transconductance circuit including a transconductance device, wherein the transconductance circuit is configured to receive the current summing signal and output a feedback current; and a clamping circuit configured to receive the feedback current and minimize the difference between the two voltages at two corresponding nodes of the current mirror circuit.
[0014] In some embodiments, the current mirror circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are connected via a first common source node, and the third transistor and the fourth transistor are connected via a second common source node.
[0015] In some embodiments, the first transistor and the second transistor are configured to receive the two input current signals associated with the two corresponding capacitance values, and the third transistor and the fourth transistor are configured to output the two mirrored current signals.
[0016] In some embodiments, the first gate of the first transistor is connected to the fourth gate of the fourth transistor, and the second gate of the second transistor is connected to the third gate of the third transistor.
[0017] In some embodiments, the current differential signal is configured as an output current.
[0018] In some embodiments, the current summation signal is configured to provide an output voltage via an output resistor.
[0019] In some embodiments, the transconductance device includes a negative input terminal and a positive input terminal, the negative input terminal being configured to receive the current differential signal, and the positive input terminal being grounded.
[0020] In some embodiments, the clamping circuit includes a bias current source, an operational amplifier, and a fifth transistor, wherein the positive input of the operational amplifier is configured to receive the feedback current, the negative input of the operational amplifier is connected to the source terminal of the fifth transistor, and the output of the operational amplifier is configured to be connected to the gate terminal of the fifth transistor.
[0021] In some embodiments, the clamping circuit is configured to be connected to an input voltage provided to the current mirror circuit via the bias current source and the fifth transistor.
[0022] In some embodiments, the current mirror circuit is configured to receive the two input current signals associated with the two corresponding capacitance values of the touch panel circuit.
[0023] In another aspect, a method for controlling a capacitance sensing circuit includes: receiving two input current signals associated with two corresponding capacitance values and outputting two mirrored current signals; receiving the two mirrored current signals and outputting a current difference signal and a current summation signal; receiving the current summation signal and outputting a feedback current; and receiving the feedback current and minimizing the difference between two voltages at two corresponding nodes of the current mirror circuit.
[0024] In some embodiments, the circuit for capacitance sensing includes the current mirror circuit, the current differential summation circuit, the transconductance circuit, and the clamping circuit. The current mirror circuit, coupled to the touch panel circuit, receives the two input current signals associated with the two corresponding capacitance values and outputs the two mirrored current signals. The two corresponding capacitance values are received by two corresponding transparent electrodes in the touch panel circuit.
[0025] In some embodiments, the current differential signal and the current summation signal are received by the two mirrored current signals and output by the current differential summation circuit.
[0026] In some embodiments, receiving the current summation signal and outputting the feedback current are performed by the transconductance circuit.
[0027] In some embodiments, the clamping circuit performs the function of receiving the feedback current and minimizing the difference between the two voltages of the two corresponding nodes.
[0028] Brief description of the attached figures The accompanying drawings, which are incorporated herein by reference as part of the specification, are used to illustrate various aspects of this disclosure and, together with the specification, further explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.
[0029] Figure 1 A schematic diagram of a touch device according to some aspects of this disclosure is shown.
[0030] Figure 2 A schematic diagram of a capacitance sensing circuit according to some aspects of this disclosure is shown.
[0031] Figure 3 A schematic diagram of a capacitive sensing system according to some aspects of this disclosure is shown.
[0032] Figure 4 A flowchart of a method for controlling a capacitive sensing circuit according to some aspects of this disclosure is shown.
[0033] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation
[0034] While specific structures and arrangements are discussed below, it should be understood that they are for illustrative purposes only. Therefore, other structures and arrangements may be adopted without departing from the scope of this disclosure. Furthermore, this disclosure can be applied to a variety of other application scenarios. The functional and structural features described can be combined, adjusted, and modified in ways not explicitly shown in the accompanying drawings, provided that such combinations, adjustments, and modifications fall within the scope of this disclosure.
[0035] Generally, the meaning of a term can be understood, at least in part, from its context. For example, the term "one or more," as used herein, can be used, at least in part, depending on the context, to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, the terms "an," "a," or "described" can also be understood, depending on the context, to indicate either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to indicate an exclusive set of factors, but may allow for additional factors not explicitly described, also depending at least in part on the context.
[0036] It should be readily understood that, in this disclosure, the meanings of “coupled to” and “connected to” should be interpreted in the broadest possible sense, such that “coupled to” can mean not only “directly coupled to” something, but also include cases where “coupled to” something is achieved through an intermediate feature or component therebetween.
[0037] Capacitive touch sensing has wide-ranging applications, including many consumer electronics products such as touch panel buttons on home appliances and touch screens on mobile phones, making it closely related to people's daily lives. Traditional capacitive touch sensing technology is based on a capacitor-to-voltage converter or capacitor-to-voltage conversion circuit, which converts capacitance changes into electrical signals, such as voltage signals. However, one problem with capacitor-to-voltage converters is that the measurement of capacitance values may suffer from non-linear distortion, meaning the output signal may not be an accurate reproduction of the original input signal waveform. This non-linear distortion may require additional compensation circuitry, control logic, or algorithms to correct for these signal distortions. Furthermore, another problem with capacitor-to-voltage converters is their susceptibility to interference from externally coupled voltages. This reduces the sensitivity of the touchscreen or touch panel buttons, resulting in a poorer user experience. Additionally, the sampling and integration circuits in capacitor-to-voltage converters consume a considerable amount of space.
[0038] To address one or more of the aforementioned problems, this disclosure introduces a solution that incorporates a current-type capacitance detection circuit. Firstly, by utilizing current to detect or sense capacitance changes, detection accuracy can be improved. Specifically, since current-type capacitance detection minimizes nonlinear distortion, the sensitivity and quality of touch panel products can be effectively improved, thereby enhancing the overall user experience.
[0039] Furthermore, by employing current-mode capacitance sensing instead of a capacitance-to-voltage converter, additional capacitors, such as MIM (metal-insulator-metal) capacitors or MOM (metal-oxide-metal) capacitors, are eliminated. These MIM or MOM capacitors are the primary source of area footprint in capacitance sensing circuits. By reducing additional MIM or MOM capacitors, the cost of the capacitance sensing circuit can also be minimized.
[0040] Furthermore, in a capacitor-to-voltage converter, the voltage signal may need to be multiplied by an additional operational amplifier before being accumulated in the integrator. However, a current-type capacitor detection circuit only requires an integrator, thus reducing the need for additional operational amplifiers. Therefore, it is also possible to minimize area footprint and cost.
[0041] In particular, according to some embodiments of this disclosure, the current mirror circuit can be configured as a current source for transmitting current signals received from the touch panel circuit and providing a constant current to the current differential summing circuit.
[0042] Furthermore, the current output from the current mirror circuit can be adjusted by a feedback circuit (e.g., a negative feedback loop) coupled to the current mirror circuit to suppress interference signals and reduce noise, thereby improving detection sensitivity. Additionally, multiplying the current signal can be easily achieved by adjusting the current mirror circuit, and the current mirror circuit has a relatively small footprint compared to other signal amplifiers.
[0043] Furthermore, according to some embodiments of this disclosure, the clamping circuit can provide overvoltage protection, shutting off the power supply or clamping the output when the voltage exceeds a preset level. Simultaneously, the clamping circuit can reduce the channel length modulation effect by making the two voltages at two corresponding nodes in the current mirror circuit almost identical, thereby minimizing the current difference between the two corresponding nodes, for example, to less than 1%, further improving the sensitivity of the capacitance detection circuit.
[0044] Finally, the combination of the current differential summation circuit and the transconductance circuit can reduce nonlinearity problems and sensitivity to parasitic sensing capacitance, which is undesirable.
[0045] Figure 1 A schematic diagram of a touch device 100 according to some aspects of this disclosure is shown. For example... Figure 1 As shown, the touch device 100 includes a touch panel 101. The touch panel 101 may include a first transparent electrode 1011 extending along the x-direction and a second transparent electrode 1013 extending along the y-direction and intersecting the first transparent electrode 1011 in a plan view. When a user touches the touch panel 101, a capacitance signal at that coordinate or position is received through the first transparent electrode 1011 and the second transparent electrode 1013. In some embodiments, a protective cover (not shown) may be formed on the first transparent electrode 1011 and the second transparent electrode 1013 and configured as a contact interface for user touch. Furthermore, a substrate (e.g., a glass substrate) may be formed below the first transparent electrode 1011 and the second transparent electrode 1013 and configured as a support substrate for the first transparent electrode 1011 and the second transparent electrode 1013. Further, in some embodiments, a display is formed below the substrate. The display includes a liquid crystal display or a light-emitting diode display. The liquid crystal display includes a thin-film transistor liquid crystal display. The light-emitting diode display includes LED backlight display, organic light-emitting diode display, active matrix organic light-emitting diode display, quantum dot light-emitting diode display, Mini LED display or Micro-LED display.
[0046] The touch device 100 may further include a driving circuit 111 coupled to the touch panel 101, and a sensing control circuit 113 coupled to the touch panel 101. The driving circuit 111 may include a transmitter Tx and is configured to apply a transmitting voltage to a capacitor array beneath the electrodes of the touch panel 101 (e.g., the first transparent electrode 1011 and the second transparent electrode 1013). The capacitor array may include multiple capacitors located beneath the corresponding electrodes, thereby enabling the detection of the user's touch point position. The sensing control circuit 113 may include a receiver Rx and is configured to receive a received voltage from the electrodes of the touch panel 101 (e.g., the first transparent electrode 1011 and the second transparent electrode 1013) via the capacitor array. Specifically, by applying a voltage to the capacitor array to form a uniform electrostatic field, this electrostatic field can be measured by the sensing control circuit 113. When a conductive object (e.g., a user's finger) touches the touch panel 101, it distorts the electrostatic field of the electrodes near the touch point, thereby allowing the measurement of capacitance changes.
[0047] The touch device 100 may further include a control system 103 coupled to the driving circuit 111 and the sensing control circuit 113, and configured to receive instructions and perform operations of the touch device 100, including controlling the driving circuit 111 and the sensing control circuit 113. In some embodiments, the function of controlling the driving circuit 111 and the sensing control circuit 113 is part of the control system 103. The control system 103 may include a readout circuit 117, a microcontroller unit 119, and a memory 123. The readout circuit 117 may include a capacitive sensing circuit according to some embodiments of the present disclosure. The readout circuit 117 is configured to read data (e.g., capacitance value or capacitance value expressed as a current value) from the touch panel 101 via the sensing control circuit 113. The capacitive sensing circuit will be further described later. In some embodiments, the readout circuit 117 may further include an integrator coupled to the capacitive sensing circuit and an analog-to-digital converter coupled to the integrator. The microcontroller unit 119 is configured to perform operations, including signal processing, on the digital signals from the analog-to-digital converter using algorithms disposed in a field-programmable gate array, control logic, or other related integrated circuits. The signal processing may include noise filtering, position determination, feature extraction, or other signal processing techniques. The memory 123 is configured to store data from the readout circuit 117 or the microcontroller unit 119. In some embodiments, the memory 123 includes volatile memory such as static random access memory or dynamic random access memory, or non-volatile memory such as ferroelectric random access memory, resistive random access memory, phase-change random access memory, or flash memory.
[0048] Figure 2 A schematic diagram of a capacitance sensing circuit 200 according to some aspects of this disclosure is shown. The capacitance sensing circuit 200 may include a current mirror circuit 201 configured to receive two capacitance values C1 and C2 from two corresponding transparent electrodes 1011 and 1013 of the touch panel 101. The current mirror circuit 201 may include a first transistor 2011, a second transistor 2013, a third transistor 2031, and a fourth transistor 2033. In some embodiments, each of the first transistor 2011, the second transistor 2013, the third transistor 2031, and the fourth transistor 2033 may be a P-channel metal-oxide-semiconductor transistor or an N-channel metal-oxide-semiconductor transistor. A first terminal (e.g., drain terminal) and a second terminal (e.g., gate terminal) of the first transistor 2011 are connected to each other and also connected to a second terminal (e.g., gate terminal) of the fourth transistor 2033. Therefore, the first input current I1 flowing through the third terminal (e.g., the source terminal) of the first transistor 2011 can be mirrored as a first mirror current I11 flowing through the first terminal (e.g., the drain terminal) of the fourth transistor 2033. The ratio between the first input current I1 and the first mirror current I11 (e.g., the multiplication factor of the current signal) can be determined by adjusting the parameter ratio (e.g., the width-to-length ratio W / L) of the first transistor 2011 and the fourth transistor 2033. Similarly, the first terminal (e.g., the drain terminal) and the second terminal (e.g., the gate terminal) of the second transistor 2013 are connected to each other and are also connected to the second terminal (e.g., the gate terminal) of the third transistor 2031. Therefore, the second input current I2 flowing through the third terminal (e.g., the source terminal) of the second transistor 2013 can be mirrored as a second mirror current I21 flowing through the first terminal (e.g., the drain terminal) of the third transistor 2031. The ratio between the second input current I2 and the second mirror current I21 (e.g., the multiplication factor of the current signal) can be determined by adjusting the parameter ratio (e.g., the width-to-length ratio W / L) of the second transistor 2013 and the third transistor 2031. In some embodiments, the first switch 217 may be coupled to the third terminal (e.g., the source terminal) of the first transistor 2011 and configured to control the first input current I1 and the second input current I2 to be zero or to a receive capacitance signal expressed in current form.
[0049] The capacitance sensing circuit 200 may further include a current differential summing circuit 205 coupled to the current mirror circuit 201 and configured to receive two mirrored currents (e.g., I21 and I11). The current differential summing circuit 205 may include a first output terminal 2051 that generates the summed current and a second output terminal 2053 that generates the differential current. The differential current is considered as the output current Iout. The summed current is further transmitted to the transconductance circuit to form a feedback loop. Accordingly, the summed current is transmitted via a third switch 221 to a first input terminal 2071 (e.g., a negative input terminal) of the transconductance device 207. When the third switch 221 is closed, the summed current is transmitted to the transconductance device 207, and the feedback current Ic output from the output terminal of the transconductance device 207 can be determined. Conversely, when the third switch 221 is open, the summing current is transmitted via the output resistor Rout 225 and subtracted from the reference current Iref (e.g., provided by the reference current source 227) to determine the output voltage Vout (e.g., measured via output node 235), wherein the reference current Iref can be determined using the feedback current Ic received from the output of the transconductance device 207 when the third switch 221 is closed. In this way, the summing current I11+I21 can remain constant without being affected by parasitic capacitance in the circuit. Therefore, the design of this disclosure has low sensitivity to parasitic capacitance. In some embodiments, the second switch 219 may be coupled to the first output 2051 of the current differential summing circuit 205 and configured to control whether the summing current I11+I21 is zero. The output voltage Vout at the input of the transconductance device 207 is sampled through the holding capacitor Csh 229. The second input 2073 of the transconductance device 207 (e.g., the positive input) is grounded. The feedback current Ic is further transmitted to clamping circuit 209. Clamping circuit 209 may include input voltage line 215 configured to apply input voltage Vcc. Clamping circuit 209 may also include bias current source 213 configured to apply bias current Ib to current mirror circuit 201. In some embodiments, the bias current Ib is applied from input voltage line 215 to first node A 231, where the third terminal (e.g., source terminal) of the first transistor 2011 is interconnected with the third terminal (e.g., source terminal) of the second transistor 2013. The feedback current Ic is transmitted to first node A 231. First node A 231 is a common source node for the first transistor 2011 and the second transistor 2013, and second node B 233 is a common source node for the third transistor 2031 and the fourth transistor 2033.
[0050] The clamping circuit 209 may include an operational amplifier 211 and a fifth transistor 223. A first node A 231 is connected to a first input terminal 2111 (e.g., positive input terminal) of the operational amplifier 211, and a second node B 233 is connected to a second input terminal 2113 (e.g., negative input terminal) of the operational amplifier 211. The second node B 233 is a node where the third terminal (e.g., source terminal) of the third transistor 2031 and the third terminal (e.g., source terminal) of the fourth transistor 2033 are interconnected. The output terminal of the operational amplifier 211 is connected to the second terminal (e.g., gate terminal) of the fifth transistor 223. An input voltage line 215 is connected to the first terminal (e.g., drain terminal) of the fifth transistor 223 and applies the input voltage Vcc to the first terminal of the fifth transistor 223. The third terminal (e.g., source terminal) of the fifth transistor 223 is connected to the second node B 233 and the second input terminal 2113 (e.g., negative input terminal) of the operational amplifier 211. Therefore, the clamping circuit 209 is configured to make Va = Vb, thereby reducing the current difference between the two common source nodes, the first node A 231 and the second node B 233, to less than 1%. This minimizes the channel length modulation effect. Furthermore, the clamping circuit 209 is also configured to provide overvoltage protection and prevent high current from damaging the capacitors or transistors in the capacitance sensing circuit 200. In some embodiments, the fifth transistor 223 may be an NMOS transistor.
[0051] Figure 3 A schematic diagram of a capacitance sensing system 300 according to some aspects of this disclosure is shown. The capacitance sensing system 300 may include a current mirror circuit 301 (e.g., corresponding to...). Figure 2 The current mirror circuit 301 in the system can measure at least two capacitance values in the form of current values. The capacitance sensing system 300 may also include a current differential summation circuit 305 (e.g., corresponding to...). Figure 2 The current differential summing circuit 305 in the current mirror circuit 301 can be used to mirror at least two currents into two output currents, and the two output currents can be transmitted to the current differential summing circuit 305. The capacitance sensing system 300 may also include a transconductance circuit 307 configured to receive the output voltage Vout and provide a feedback current Ic to form a feedback loop to compensate for and reduce noise or sudden pulses. The capacitance sensing system 300 may also include a clamping circuit 309 (e.g., corresponding to the current differential summing circuit 205 in the current mirror circuit 301). Figure 2The clamping circuit 209 is configured to make the two voltages on the two corresponding nodes in the current mirror circuit nearly identical, thereby minimizing the current difference between the two corresponding common source nodes, for example, to less than 1%. The feedback current Ic is transmitted to the clamping circuit 309, in which a feedback loop including an operational amplifier is configured to form negative feedback, making the two voltages on the two corresponding common source nodes in the current mirror circuit nearly identical, for example, minimizing the current difference between the two corresponding common source nodes to less than 1%. In this way, the sensitivity of the capacitive sensing system 300 can be improved, thereby enhancing the user experience.
[0052] Figure 4 A control circuit for capacitive sensing (e.g.) is shown according to some aspects of this disclosure. Figure 2 The flowchart of method 400 (capacitive sensing circuit 200 in the circuit) is shown. It should be understood that the operations shown in method 400 are not exhaustive, and other operations may be performed before, after, or in between any of the operations shown.
[0053] Reference Figure 4 The method 400 begins with operation 402, in which two input current signals associated with two corresponding capacitance values are received, and two mirrored current signals are output. For example, the current mirror circuit 201 can receive the input current signals associated with the two corresponding capacitance values (e.g., from...). Figure 2 The two input current signals (e.g., the two corresponding capacitance values C1 and C2 of the two transparent electrodes 1011 and 1013 in the middle) are associated with the two input current signals (e.g., Figure 2 The first input current I1 and the second input current I2 in the system. The two input current signals are mirrored into two mirrored current signals (e.g., the first input current I1 and the second input current I2 in the system). Figure 2 The first mirror current I11 and the second mirror current I21 in the circuit), and transmit the two mirror current signals to the current differential summing circuit (e.g. Figure 2 The current differential summation circuit 205 in the middle.
[0054] The method 400 continues until... Figure 4 The illustrated operation 404 involves receiving the two mirrored current signals and outputting a current differential signal and a current summation signal. For example, the two mirrored current signals (e.g.) Figure 2 The first mirror current I11 and the second mirror current I21 in the current differential summation circuit (e.g.) are obtained by the current differential summation circuit (e.g.) Figure 2 The current differential summing circuit 205 in the middle receives the signal, and then the current differential summing circuit outputs a current differential signal (e.g., Figure 2 The current differential signal (2053) and the current summation signal (e.g.) Figure 2The current summation signal 2051 in the middle. The current differential signal is then used as the output current (e.g., Figure 2 The output current 237 is output. The current summation signal is then transmitted and passed through the output resistor (e.g., ...). Figure 2 The output resistor Rout 225 is used for transmission.
[0055] The method 400 continues until... Figure 4 In the illustrated operation 406, the current summation signal is further transmitted and received by a transconductance device, which then outputs a feedback current. For example, the current summation signal is transmitted and received by the transconductance device (e.g., ... Figure 2 The transconducting device 207 in the middle receives the current, and then the transconducting device outputs a feedback current to the current mirror circuit (e.g., Figure 2 The feedback current Ic in the current mirror circuit. In some embodiments, before the feedback current is transmitted to the current mirror circuit, the clamping circuit is configured to minimize the difference between the two voltages of the two corresponding nodes of the current mirror circuit.
[0056] The method 400 continues until... Figure 4 The illustrated operation 408 involves the feedback current being received by the clamping circuit, which sets the difference between the two voltages at two corresponding nodes of the current mirror circuit to a minimum. For example, the feedback current Ic is received by the clamping circuit (e.g., Figure 2 The clamping circuit 209 in the current mirror circuit (e.g., current mirror circuit 201) receives the signal and sets the voltage difference between the two corresponding nodes (e.g., first common source node A 231 and second common source node B 233) of the current mirror circuit (e.g., current mirror circuit 201) to a minimum. This minimizes the channel length modulation effect, effectively improving the sensitivity and quality of the touch panel device and further enhancing the overall user experience.
[0057] The foregoing description of the specific embodiments can be readily modified and / or adjusted for various applications. Therefore, such modifications and adjustments made based on the teachings and guidance provided herein should fall within the equivalent scope and meaning of the disclosed embodiments.
[0058] The scope of protection of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only by the following claims and their equivalents.
Claims
1. A circuit for capacitive sensing, comprising: A current mirror circuit is configured to receive two input current signals associated with two corresponding capacitance values and output two mirrored current signals. A current differential summing circuit is configured to receive the two mirrored current signals from the current mirror circuit and output a current differential signal and a current summing signal. A transconducting circuit, comprising a transconducting device, wherein the transconducting circuit is configured to receive the current summation signal and output a feedback current; as well as A clamping circuit is configured to receive the feedback current and minimize the difference between the two voltages at the two corresponding nodes of the current mirror circuit.
2. The circuit as described in claim 1, wherein, The current mirror circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are connected via a first common source node, and the third transistor and the fourth transistor are connected via a second common source node.
3. The circuit as described in claim 2, wherein, The first transistor and the second transistor are configured to receive the two input current signals associated with the two corresponding capacitance values, and the third transistor and the fourth transistor are configured to output the two mirrored current signals.
4. The circuit as described in claim 2, wherein, The first gate of the first transistor is connected to the fourth gate of the fourth transistor, and the second gate of the second transistor is connected to the third gate of the third transistor.
5. The circuit as described in claim 1, wherein, The current differential signal is configured as the output current.
6. The circuit as claimed in claim 1, wherein, The current summation signal is configured to provide an output voltage via an output resistor.
7. The circuit as claimed in claim 1, wherein, The transconductance device includes a negative input terminal and a positive input terminal, wherein the negative input terminal is configured to receive the current differential signal, and the positive input terminal is grounded.
8. The circuit as claimed in claim 1, wherein, The clamping circuit includes a bias current source, an operational amplifier, and a fifth transistor, wherein the positive input terminal of the operational amplifier is configured to receive the feedback current, the negative input terminal of the operational amplifier is connected to the source terminal of the fifth transistor, and the output terminal of the operational amplifier is configured to be connected to the gate terminal of the fifth transistor.
9. The circuit as claimed in claim 8, wherein, The clamping circuit is configured to be connected to an input voltage, which is provided to the current mirror circuit via the bias current source and the fifth transistor.
10. The circuit as claimed in claim 1, wherein, The current mirror circuit is configured to receive the two input current signals associated with the two corresponding capacitance values of the touch panel circuit.
11. A touch panel device, comprising: Touch panel circuitry, which includes a capacitor array; A drive circuit coupled to the touch panel circuitry and configured to drive an emission voltage to the capacitor array; A sensing control circuit coupled to the touch panel circuitry and configured to receive a received voltage from the capacitor array; A capacitance sensing circuit coupled to the sensing control circuit and configured to detect the capacitance of the capacitor array. A microcontroller unit configured to perform operations of the touch panel device; as well as A memory configured to store data from the capacitive sensing circuit or the microcontroller unit. The capacitance sensing circuit includes: A current mirror circuit is configured to receive two input current signals associated with two corresponding capacitance values and output two mirrored current signals. A current differential summing circuit is configured to receive the two mirrored current signals from the current mirror circuit and output a current differential signal and a current summing signal. A transconducting circuit, comprising a transconducting device, wherein the transconducting circuit is configured to receive the current summation signal and output a feedback current; and A clamping circuit is configured to receive the feedback current and minimize the difference between the two voltages at the two corresponding nodes of the current mirror circuit.
12. The touch panel device as claimed in claim 11, wherein, The current mirror circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are connected via a first common source node, and the third transistor and the fourth transistor are connected via a second common source node.
13. The touch panel device as claimed in claim 12, wherein, The first transistor and the second transistor are configured to receive the two input current signals associated with the two corresponding capacitance values, and the third transistor and the fourth transistor are configured to output the two mirrored current signals.
14. The touch panel device as claimed in claim 12, wherein, The first gate of the first transistor is connected to the fourth gate of the fourth transistor, and the second gate of the second transistor is connected to the third gate of the third transistor.
15. The touch panel device as claimed in claim 11, wherein, The current differential signal is configured as the output current.
16. The touch panel device as claimed in claim 11, wherein, The current summation signal is configured to provide an output voltage via an output resistor.
17. The touch panel device as claimed in claim 11, wherein, The transconductance device includes a negative input terminal and a positive input terminal, wherein the negative input terminal is configured to receive the current differential signal, and the positive input terminal is grounded.
18. The touch panel device as claimed in claim 11, wherein, The clamping circuit includes a bias current source, an operational amplifier, and a fifth transistor, wherein the positive input terminal of the operational amplifier is configured to receive the feedback current, the negative input terminal of the operational amplifier is connected to the source terminal of the fifth transistor, and the output terminal of the operational amplifier is configured to be connected to the gate terminal of the fifth transistor.
19. The touch panel device as claimed in claim 18, wherein, The clamping circuit is configured to be connected to an input voltage, which is provided to the current mirror circuit via the bias current source and the fifth transistor.
20. The touch panel device as claimed in claim 11, wherein, The current mirror circuit is configured to receive the two input current signals associated with the two corresponding capacitance values of the touch panel circuit.
21. A method for controlling a capacitance sensing circuit, comprising: It receives two input current signals associated with two corresponding capacitance values and outputs two mirror current signals. Receive the two mirrored current signals and output a current differential signal and a current summation signal; Receive the current summation signal and output the feedback current; as well as The feedback current is received and the difference between the two voltages at the two corresponding nodes of the current mirror circuit is minimized.
22. The method of claim 21, wherein, The circuit for capacitance sensing includes: the current mirror circuit, the current differential summation circuit, the transconductance circuit, and the clamping circuit, wherein receiving the two input current signals associated with the two corresponding capacitance values and outputting the two mirrored current signals is performed by the current mirror circuit coupled to the touch panel circuit, wherein the two corresponding capacitance values are received by two corresponding transparent electrodes in the touch panel circuit.
23. The method of claim 22, wherein, The current differential signal and the current summation signal are received by the two mirrored current signals and output by the current differential summation circuit.
24. The method of claim 22, wherein, The receiving of the current summation signal and the output of the feedback current are executed by the transconductance circuit.
25. The method of claim 22, wherein, The clamping circuit performs the function of receiving the feedback current and minimizing the difference between the two voltages of the two corresponding nodes.