An airborne embedded triple-system satellite navigation receiving device

Abstract

An airborne embedded three-system satellite navigation receiving device, the satellite navigation receiving device receives navigation satellite signals through a first receiving, and through branching, amplification, filtering, mixing and through an A / D analog-to-digital converter to complete analog-to-digital conversion to send to FPGA and DSP for digital signal processing. The DSP realizes a system control unit, a navigation processing unit, and a channel processing unit. A feeder protection device is used for external antenna short circuit protection, and a lightning protection device is used for overvoltage protection against lightning strikes in an airborne environment. The FPGA realizes a three-navigation signal capture tracking unit, a key destruction unit, and an external interface unit. A FLASH is used to save ephemeris, DSP and FPGA programs. A PRM military code generation chip provides BD second-generation system military code streams and completes Q branch text decryption, and an IC card chip completes text decryption. A key destruction interpreter judges the PRM and IC card key destruction level command to drive the key destruction unit to work to realize safe key destruction of the PRM and IC card.

Description

Technical Field

[0001] This invention belongs to the field of positioning, navigation and control technology, and specifically relates to an airborne embedded three-system satellite navigation receiving device applied in a satellite navigation receiver. Background Technology

[0002] Satellite navigation technology boasts advantages such as all-weather, all-time availability, and high positioning accuracy, leading to its increasing use in airborne applications on transport aircraft, fighter jets, and civil airliners. These airborne applications include special environments such as lightning strike protection and aircraft power supply switching, and place high demands on the security of confidential devices such as the BD2 military code generator PRM and BD2 decryption IC card. Existing satellite navigation receivers are not designed for these special airborne environments and cannot meet the requirements of airborne applications. Furthermore, most of them adopt a single-unit design, resulting in a large size and weight, which is not suitable for the requirements of small size and light weight in airborne applications. Therefore, it is necessary to design a satellite navigation receiver specifically for airborne application environments. Summary of the Invention

[0003] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide an airborne embedded three-system satellite navigation receiver. This device realizes the design for special airborne application environments such as lightning protection, PRM and IC card security key destruction, time retention, and power supply protection. The airborne embedded three-system satellite navigation receiver adopts a single-board design to reduce the size and weight of the satellite navigation device. It has navigation and positioning capabilities for three frequencies of GPS, GLONASS, and BDII-B3 systems. The FPGA design has large resources, which greatly improves the performance of the navigation receiver.

[0004] The technical solution of this invention is: an airborne embedded three-system satellite navigation receiver, comprising a splitter, a lightning protection device, a power supply protection device, a first frequency synthesizer, a second frequency synthesizer, a third frequency synthesizer, a first amplifier, a second amplifier, a third amplifier, a first filter, a second filter, a third filter, a first mixer, a second mixer, a third mixer, a first analog-to-digital converter, a second analog-to-digital converter, a third analog-to-digital converter, a DSP, an FPGA, a crystal oscillator, a fourth amplifier, a clock divider, a FLASH memory, a watchdog timer, a voltage converter, a BD second-generation military code generator PRM, a BD second-generation decryption IC card, a key destruction reader, a real-time clock, an interface circuit, and a first electrical connector and a second electrical connector;

[0005] The first electrical connector inputs the analog radio frequency navigation satellite signal received from the outside to the splitter; at the same time, it provides +5V power to the external antenna.

[0006] The power supply protector receives +5V power and outputs it to the first connector;

[0007] A lightning protection device is connected in parallel to the output of the first connector to provide lightning protection for the navigation receiver.

[0008] The splitter receives the analog radio frequency navigation satellite signal output from the first electrical connector, divides it into three paths according to power, and sends them to the first amplifier, the second amplifier, and the third amplifier respectively.

[0009] The first amplifier receives the first satellite signal from the splitter, amplifies it, and sends it to the first filter.

[0010] The second amplifier receives the second satellite signal from the splitter, amplifies it, and then sends it to the second filter.

[0011] The third amplifier receives the third satellite signal from the splitter, amplifies it, and then sends it to the third filter.

[0012] The first filter receives the first satellite signal from the amplifier, performs bandpass filtering, and then sends it to the first mixer.

[0013] The second filter receives the second satellite signal from the amplifier, performs bandpass filtering, and then sends it to the second mixer.

[0014] The third filter receives the third satellite signal from the amplifier, performs bandpass filtering, and then sends it to the third mixer.

[0015] The first mixer simultaneously receives the satellite signal from the first filter and the frequency synthesizer A, performs mixing and down-conversion processing, and outputs the signal to the first A / D analog-to-digital converter.

[0016] The second mixer simultaneously receives the satellite signal from the second filter and the frequency synthesizer B, performs mixing and down-conversion processing, and outputs the signal to the second A / D analog-to-digital converter.

[0017] The third mixer simultaneously receives the satellite signal and frequency synthesizer C from the third filter, performs mixing and down-conversion processing, and outputs the signal to the third A / D analog-to-digital converter.

[0018] The first A / D analog-to-digital converter converts the analog intermediate frequency satellite signal from the first mixer into a digital signal p(n) and outputs it to the FPGA;

[0019] The second A / D converter converts the analog intermediate frequency satellite signal from the second mixer into a digital signal q(n) and outputs it to the FPGA;

[0020] The third A / D converter converts the analog intermediate frequency satellite signal from the third mixer into a digital signal x(n) and outputs it to the FPGA;

[0021] The FPGA includes a capture and tracking unit, an interface unit, and a key destruction unit. Upon power-up, the capture and tracking unit reads the real-time clock information and sequentially performs code capture and tracking on the received digital signals p(n), q(n), and x(n), using a carrier-locked loop to achieve carrier capture and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation. It then saves the three sets of raw observation data, including satellite position information, satellite velocity information, pseudorange, pseudorange rate, satellite almanac, satellite ephemeris, and time information. The capture and tracking unit sends the time information and the Q-branch message from the satellite ephemeris to the BD2 military code generator PRM, while simultaneously receiving the BD2 system military code stream and its conversion from the PRM. The Q branch message is replaced; the key destruction unit reads the key destruction protocol instructions of the interface circuit in real time through the interface unit, and at the same time reads the key destruction level instructions of the key destruction judge. When at least two of the three received key destruction protocol instructions are correct and the key destruction level instructions are valid, the key destruction unit performs key destruction operation on the BD2 military code generation chip PRM and the BD2 decryption IC card; at the same time, the key destruction unit reads back the data of the BD2 military code generation chip PRM and the BD2 decryption IC card to confirm the key destruction result. If the key destruction is not completed, it continues to perform key destruction operation on the BD2 military code generation chip PRM and the BD2 decryption IC card until the key destruction is completed, and sends the key destruction completion information to the interface circuit; the interface unit performs timing conversion on the received DSP output information and outputs it to the second electrical connector through the interface circuit;

[0022] The DSP, acting as the main processor, includes a system control unit, a navigation processing unit, and a channel processing unit. The channel processing unit controls the FPGA's acquisition and tracking, outputting acquisition and tracking status information to the system control unit. Simultaneously, it reads three sets of raw observation data from the FPGA and sends them to the navigation processing unit. The navigation processing unit performs positioning calculations on the three sets of raw observation data to obtain the receiver's position information, receiver velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs this information to the system control unit. The system control unit outputs the receiver's position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information to the FPGA, and stores the satellite almanac, receiver position information, and time information in FLASH memory. Upon power-up, it initializes the first frequency synthesizer, second frequency synthesizer, third frequency synthesizer, first mixer, second mixer, third mixer, DSP, FPGA, real-time clock, and interface circuits.

[0023] The crystal oscillator generates a low-jitter system clock and sends it to the fourth amplifier;

[0024] The fourth amplifier receives the clock generated by the crystal oscillator and sends the amplified clock to the first frequency synthesizer, the second frequency synthesizer, the third frequency synthesizer, and the clock divider;

[0025] The clock divider receives clock A, which is amplified by the fourth amplifier. After frequency conversion and shaping, clock B is generated and sent to the FPGA, DSP, first A / D converter, second A / D converter and third A / D converter respectively.

[0026] The first frequency synthesizer receives the clock A amplified and processed by the fourth amplifier, and generates frequency synthesizer A through frequency conversion, which is then sent to the first mixer.

[0027] The second frequency synthesizer receives the clock A, which is amplified and processed by the fourth amplifier. After frequency conversion, the clock synthesizer B is generated and sent to the second mixer.

[0028] The clock A, which is received by the third frequency synthesizer and amplified by the fourth amplifier, is converted into frequency synthesizer C and sent to the third mixer.

[0029] The FLASH memory stores the DSP program and the FPGA program, and also saves the satellite almanac, position information and time information stored in the DSP.

[0030] The watchdog monitors the DSP's operating status and provides a reset function for the DSP to prevent DSP crashes due to sudden reasons.

[0031] The BD2 military code generator PRM provides the FPGA with the BD2 system military code stream and the converted Q-branch message. If the BD2 system Q-branch message is encrypted, the Q-branch message is first decrypted by the BD2 decryption IC card and then sent to the PRM for Q-branch message conversion. The converted Q-branch message is then output to the FPGA.

[0032] The real-time clock provides time information when the navigation receiver is powered on;

[0033] The interface circuit receives the key destruction protocol instruction from the second electrical connector and outputs it to the FPGA. At the same time, it obtains the receiver location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac and time information from the FPGA and sends them to the second electrical connector.

[0034] The key destruction reader receives the key destruction level command from the second electrical connector and outputs it to the FPGA;

[0035] The second electrical connector outputs the key destruction level command sent by the external host computer to the key destruction reader, outputs the key destruction protocol command sent by the external host computer to the interface circuit, sends the +5V power output by the host computer to the voltage conversion regulator, and sends the receiver location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac and time information output by the interface circuit to the external host computer.

[0036] The voltage conversion regulator converts the +5V voltage into the operating voltage of each component.

[0037] The voltage converter is model LTC3614.

[0038] The lightning protection chip model is SMDJ5.0A.

[0039] The power supply protector chip is model MAX893.

[0040] The real-time clock consists of a DS1390U timing chip, an MC-306-32.768K crystal, and a 400uF capacitor.

[0041] The key destruction reader uses an optocoupler HCPL-6631.

[0042] The system control unit includes an initialization module, a FLASH data read / write module, a channel allocation module, and an external interface module;

[0043] The initialization module initializes the hardware and software in the receiving device.

[0044] The FLASH data read / write module writes the received satellite almanac, current position information, and time information to the FLASH memory; when the navigation receiver is reset or powered on again, it outputs the saved satellite almanac, current position information, and time information to the DSP.

[0045] The channel allocation module allocates satellites to the satellite processing channels;

[0046] The external interface module outputs the receiver's location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac, and time information to the FPGA.

[0047] The navigation processing unit includes a navigation calculation module, a RAIM monitoring module, a message processing module, and a satellite forecasting module;

[0048] The message processing module uses satellite navigation messages from raw observations obtained from the FPGA to demodulate satellite ephemeris and satellite almanac;

[0049] The satellite forecasting module forecasts satellite position, velocity, clock difference, and time information based on satellite ephemeris and almanac.

[0050] The navigation solution module uses satellite position, satellite velocity, clock error, pseudorange, pseudorange change rate, time information, and ionospheric and tropospheric correction information to establish a navigation solution matrix equation, and obtains the navigation information of the receiving device through least squares iterative calculation.

[0051] The RAIM monitoring module detects and removes faulty stars.

[0052] The channel processing unit is completed by the channel processing module and driven by the interrupt handler. It outputs raw observation data to the navigation processing unit, outputs the tracking status information generated by the FPGA to the system control unit, reads the raw observation data from the FPGA and processes the digital signal, and completes code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition and message demodulation.

[0053] The FLASH storage space is divided into L segments, which are used to store DSP and FPGA programs. The segmented address space is controlled by the DSP's general-purpose I / O; L is a positive integer.

[0054] Compared with the prior art, the present invention has the following advantages:

[0055] (1) The navigation receiving device of the present invention uses three frequency synthesizers, amplifiers, filters, mixers and A / D converters to realize three-channel reception. The three receiving channels use the same type of devices and have a compatible package design. After appropriate adjustment of the filter, the channels can be interchanged.

[0056] (2) The navigation receiver of the present invention can simultaneously receive signals from three systems and three frequencies of GPS-L1, GLONASS-G1 and BDII-B3, thereby achieving navigation constellation redundancy and improving the availability and reliability of the device.

[0057] (3) The navigation receiving device of the present invention can simultaneously receive BDII-B3 military code and civilian code signals.

[0058] (4) The navigation receiving device of the present invention uses a medium filter, which has good phase consistency and high out-of-band suppression, thus improving the receiving device's ability to resist external interference.

[0059] (5) The navigation receiving device of the present invention uses only one radio frequency input port of the first connector to realize the reception of satellite signals of three systems and three frequencies, which reduces the installation complexity.

[0060] (6) The navigation receiver of the present invention adopts an integrated OEM board design for radio frequency channel and baseband channel, which improves hardware density, reduces volume and weight, and realizes miniaturization of the receiver and reduces airborne load.

[0061] (7) The FLASH storage space of the navigation receiving device of the present invention is divided into L segments, and the DSP and FPGA programs are stored in segments, making the programs clearer. The segmented address space is controlled by the DSP general IO, which increases the static memory capacity.

[0062] (8) The lightning protection device of the navigation receiver of the present invention uses a transient suppression diode SMDJ5.0A connected to ground through the RF input port signal line to achieve lightning protection. It has a simple structure and good lightning protection effect.

[0063] (9) The power supply protector of the navigation receiver of the present invention adopts the radio frequency input port connected in parallel with the MAX893 current limiting switch, the external antenna short circuit protection receiver, the output current of the current limiting switch is controllable, and it can self-recover after the external short circuit disappears.

[0064] (10) The satellite navigation receiver of the present invention has a modular design for the DSP. The DSP includes a system control unit, a navigation processing unit and a channel processing unit. The three units work together to achieve the characteristics of tracking a large number of satellites, fast positioning speed, multiple positioning modes and high positioning accuracy. It can also perform hardware fault detection with a high detection rate.

[0065] (11) The power chip model used in the satellite navigation receiver of the present invention is only LTC3614, which unifies the power chip model, reduces the types of components, and improves the reliability of the device.

[0066] (12) The baseband processing device of the present invention also adopts a low jitter clock scheme. The temperature compensated crystal oscillator CFPT-9007-10MHz is used as the system clock reference. The amplifier AD8041 generates a low jitter system 10MHz clock A, which is amplified to provide a reference clock for three frequency synthesizers ADF4360. Another part is converted by the clock divider ICS525 to provide clock B for DSP, FPGA and three A / D analog-to-digital converters. This realizes the design of the system clock from the same source and improves the EMC performance of the whole machine.

[0067] (13) The real-time clock of the navigation receiver of the present invention uses a timing chip DS1390U, a crystal MC-306-32.768K and a 400uF capacitor. It can keep time for more than 20 minutes after the navigation receiver is powered off, and the time can be increased by increasing the capacitance value.

[0068] (14) The navigation receiver key destroyer of the present invention uses an optocoupler HCPL-6631 to convert the external key destroying hard command into the internal level signal of the receiver, thereby isolating the external key destroying hard command from the receiver and protecting the receiver from external influences.

[0069] (15) The interface circuit of the navigation receiver of the present invention implements an optically coupled isolated RS422 interface, adopts an RS422 serial port core, uses MAX422 to drive the transmitting end, and uses HCPL-6631 to receive the receiving end, so as to realize the safety protection between the device and the external device. Attached Figure Description

[0070] Figure 1 This is a schematic diagram of the composition and structure of the satellite navigation receiver device of the present invention;

[0071] Figure 2 This is a functional block diagram of the DSP in the satellite navigation receiver of the present invention;

[0072] Figure 3 The flowchart of the internal implementation of the DSP in the satellite navigation receiver of this invention. Detailed Implementation

[0073] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0074] like Figure 1 The diagram shows the structural composition of the satellite navigation receiver of the present invention. As can be seen from the diagram, the navigation receiver includes a splitter, a lightning protection device, a power supply protection device, a first frequency synthesizer, a second frequency synthesizer, a third frequency synthesizer, a first amplifier, a second amplifier, a third amplifier, a first filter, a second filter, a third filter, a first mixer, a second mixer, a third mixer, a first analog-to-digital converter, a second analog-to-digital converter, a third analog-to-digital converter, a DSP, an FPGA, a crystal oscillator, a fourth amplifier, a clock divider, a FLASH memory, a watchdog timer, a voltage converter, a BD second-generation military code generator PRM, a BD second-generation decryption IC card, a key destruction reader, a real-time clock, an interface circuit, and a first electrical connector and a second electrical connector.

[0075] The CFPT-9007-10MHz crystal oscillator generates a low-jitter system clock, which is amplified twice by the fourth amplifier AD8041AR to produce a 10MHz clock A. One path is sent to the clock divider ICS525R-02I to generate a 62MHz system clock B for the DSP, FPGA, and three A / D converters. The clock divider ICS525R-02I can adjust the output frequency to change the operating frequency of the receiving device. The other paths are sent to the first frequency synthesizer ADF4360-7BCPZ to generate a 1268MHz frequency synthesizer A, to the second frequency synthesizer ADF4360-7BCPZ to generate a 1603MHz frequency synthesizer B, and to the third frequency synthesizer ADF4360-7BCPZ to generate a 1575MHz frequency synthesizer C.

[0076] The first electrical connector, model SMB-KWHD3, receives navigation satellite signals from three frequencies: BDII-B3 (1268MHz), GLONASS-G1 (1603MHz), and GPS-L1 (1575MHz). These signals are then split into three channels by a splitter (model SCA-4-20) and sent to three amplifiers (models BGA427, BGA427, and BGA427 respectively). A transient suppression diode (SMDJ5.0A) is connected in parallel to ground on the RF input signal line of the first electrical connector to provide lightning protection for the navigation receiver. Simultaneously, a MAX893 output +5V power supply is connected in parallel, with the output current limited to 280mA, to provide short-circuit current limiting protection for the external antenna.

[0077] The first amplifier, BGA427, amplifies BDII-B3 by 20dB and sends it to the first filter, MF2A1268F020KCA, for filtering and suppressing out-of-band noise by 30dB. Then, it is sent to the first mixer, AD8347ARU, where it is mixed and down-converted to zero intermediate frequency (IF) with a 1268MHz frequency synthesizer A from the first frequency synthesizer. The signal is then converted to a digital signal p(n) by the first A / D converter, AD9288BST-80, at a 62MHz clock B, and output to the FPGA. The second amplifier, BGA427, amplifies GLONASS-G1 by 20dB and sends it to the second filter, MF3A1603S12DCA, for filtering and suppressing out-of-band noise by 30dB before being sent to the second mixer, AD8347. The ARU and the 1603MHz frequency synthesizer B from the second frequency synthesizer complete the mixing and downconversion to zero intermediate frequency. The signal is then converted into a digital signal q(n) by the second A / D converter AD9288BST-80 with a 62MHz clock B and output to the FPGA. The third amplifier BGA427 amplifies the GPS-L1 signal by 20dB and sends it to the third filter AE1575C88 to filter and suppress out-of-band noise by 30dB before sending it to the third mixer AD8347. The ARU and the 1575MHz frequency synthesizer C from the third frequency synthesizer complete the mixing and downconversion to zero intermediate frequency. The signal is then converted into a digital signal ×(n) by the third A / D converter AD9288BST-80 with a 62MHz clock B and output to the FPGA.

[0078] The FPGA, model EP3C120F484, receives the digital signal p(n) output from the first A / D converter, the digital signal q(n) output from the second A / D converter, and the digital signal x(n) output from the third A / D converter. Next, the FPGA sequentially performs code acquisition and tracking, carrier acquisition and tracking using a carrier-locked loop, bit synchronization, frame synchronization, data acquisition, and message demodulation on signals p(n), q(n), and x(n), respectively, and saves the processed raw observation data. Simultaneously, the FPGA receives DSP output information, performs timing conversion, and outputs it to the second electrical connector through an interface circuit. It also reads the key destruction soft command from the second connector through the interface circuit. Finally, the FPGA receives the key destruction hard command output from the key destruction reader HCPL-6631 and the key destruction soft command from the interface circuit to jointly determine the secure destruction of the PRM and IC card. The FPGA sends the generated code stream extraction time and the received Q-branch message to the BD2 military code generator PRM, and simultaneously receives the BD2 system military code stream and the converted Q-branch message output by the BD2 military code generator PRM. When the FPGA powers on, it initializes the real-time clock and reads the real-time clock information upon power-on for rapid acquisition of satellite signals. The gatekeeper real-time clock consists of a timing chip DS1390U, a crystal MC-306-32.768K, and a 400uF capacitor. It can keep time for more than 20 minutes after the navigation receiver is powered off, and the timekeeping time can be increased by increasing the capacitance value.

[0079] The specific working process of an FPGA is as follows:

[0080] (1) Code capture

[0081] The main search is conducted within two uncertain ranges: the code phase of the satellite pseudocode and the carrier Doppler. The system detects whether the signal energy exceeds the detection threshold. Once a signal is detected, the system locks on and enters the tracking state.

[0082] (2) Code tracking

[0083] A code delay-locked loop is used to track satellite pseudocodes, and pseudorange observations are obtained by measuring the phase difference between the local pseudocode and the input pseudocode.

[0084] (3) Carrier acquisition

[0085] After the code acquisition system acquires the pseudo code and carrier component, the local carrier has not yet accurately tracked the carrier component of the satellite signal, resulting in a large Doppler frequency error, generally above several hundred hertz. In order to accurately acquire the carrier Doppler, AFC (Automatic Frequency Locking) and COSTAS combined loop processing are used, which not only reduces the frequency locking time but also reduces the phase locking time.

[0086] (4) Carrier tracking

[0087] The carrier Doppler error is already very small after being processed by the carrier acquisition module. To obtain higher accuracy, it then enters the carrier tracking module, which uses a narrowband digital phase-locked loop (DPLL).

[0088] (5) Bit synchronization

[0089] The initial phase of the satellite pseudocode is synchronized with the data conversion point. Taking GPS as an example, the bit synchronization process is to correctly determine which of the 20 C / A code initial phases coincides with a data bit at 50Hz. The energy of each of the 20 C / A code initial phases is determined by integrating and summing them, and the maximum energy is found to achieve bit synchronization.

[0090] (6) Frame synchronization

[0091] A sequence word with a distinctive identifier is identified from the satellite's navigation data stream to achieve subframe synchronization. Taking GPS as an example, this identifier is located in the first 8 bits of the telemetry word in the message subframe and is repeated every 6 seconds.

[0092] (7) Data Acquisition

[0093] This module reads pseudorange and pseudorange change rate information and outputs it to the navigation processing module.

[0094] (8) Message demodulation

[0095] The satellite signal data is demodulated and transmitted to the navigation processing module for processing parameters such as ephemeris and almanac.

[0096] The FPGA used in this invention employs an EP3C120F484, which provides loop design resources for 4 PLLs, 120,000 logic units, and 288 18-bit multipliers.

[0097] like Figure 2 The diagram shown is a functional block diagram of the DSP in the baseband processing device of this invention. This invention uses the DSP chip TMS32C6414EZLZA6E3 as the main program processor. The DSP includes a system control unit, a navigation processing unit, and a channel processing unit. The DSP operates at 372MHz, a six-fold multiplier of the 62MHz clock output from the second crystal oscillator. The 372MHz frequency can be adjusted by changing the clock divider settings.

[0098] The system control unit is the management center of the baseband processing device. It is responsible for the organic coordination and mutual invocation of various subtasks, connecting the various dispersed modules to jointly complete the system's various tasks. The system control unit outputs receiver position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, stores the satellite almanac, position information, and time information in the FLASH memory, and initializes the first, second, and third frequency synthesizers, the first mixer, the second mixer, the third mixer, the DSP, the FPGA, the real-time clock, and the interfaces after power-on. Furthermore, it receives control information from an external host computer via the FPGA. The system control unit consists of the following functional modules: initialization module, FLASH data read / write module, channel allocation module, and external interface module.

[0099] The initialization module includes the initialization of both hardware and software, enabling them to begin working together. Hardware initialization includes enabling hardware interrupt timers, toggling the watchdog timer, initializing the FPGA, and initializing the three frequency synthesizers, three mixers, the real-time clock, and the interfaces. Software initialization includes initializing global variables, the time system, the positioning mode and state, and the navigation model.

[0100] The FLASH data read / write module is responsible for writing the received satellite almanac, current positioning information, and time into the FLASH memory. When the baseband processing device resets or powers on again, it uses the saved, more accurate time, position information, and satellite almanac to predict satellites, thereby accelerating the baseband processing device's satellite search and acquisition and shortening the user terminal's initial positioning time. It also includes upgrade functions for the DSP and FPGA programs.

[0101] The channel allocation module allocates satellites to parallel satellite tracking channels. This module performs the following functions: pre-setting satellite channels and setting the search frequency until a satellite is tracked; re-acquiring a satellite after it has lost lock; resetting idle channels to acquire satellites; and forcibly dropping certain satellites.

[0102] The external interface module outputs position information, velocity information, pseudorange, pseudorange rate, and time information to the FPGA, and receives control information from the host computer sent by the FPGA.

[0103] The navigation processing unit calculates receiver position, velocity, pseudorange, pseudorange rate, satellite ephemeris, and time information from the raw observation data, and outputs these information to the system control unit. The navigation processing unit consists of the following functional modules: message processing module, satellite prediction module, navigation calculation module, and RAIM monitoring module.

[0104] The main function of the message processing module is to demodulate information such as ephemeris and almanac from the original satellite navigation messages obtained from the FPGA for navigation calculations, and to save the almanac data to FLASH.

[0105] The satellite prediction module's functions include almanac prediction and ephemeris calculation. For navigation satellites, the message consists of two parts: ephemeris and almanac. Ephemeris contains precise satellite clock and orbital information, used for positioning calculations. Almanac is a collection of reduced-precision ephemeris data from all satellites, primarily used for satellite acquisition. Almanac prediction uses satellite ephemeris parameters to predict the satellite's position, velocity, elevation, azimuth, and Doppler parameters at a specific time, used for satellite acquisition. Ephemeris calculation uses satellite ephemeris parameters to calculate the satellite's position, velocity, time delay, clock error, and other information at a specific time, used for navigation calculations.

[0106] The navigation solution module is the main task of the DSP. It uses the satellite prediction module to obtain information such as the satellite's position, velocity, clock error, ionospheric and tropospheric corrections, pseudorange, and pseudorange change rate at the positioning time. It then establishes navigation solution equations and matrices and iteratively calculates navigation information such as the user's position, velocity, and time using the least squares method.

[0107] The RAIM monitoring module primarily detects faulty satellites and identifies which satellite is faulty. It employs the least squares method, using pseudorange residual vectors as the monitoring quantity to detect and determine the presence of faulty satellites. Its key features are: it's based on the assumption of a single satellite malfunctioning; that is, at the same sampling time, when one satellite malfunctions, there's a way to determine which satellite is faulty; however, when more than one satellite malfunctions simultaneously, it only provides the information that a faulty satellite is present, without specifying which satellites are faulty. The algorithm only performs detection and judgment based on current measurement data, independent of historical data. The RAIM algorithm operates conditionally: at least five satellites are required for error detection, and six or more satellites are needed to remove one faulty satellite.

[0108] The channel processing unit is driven by an interrupt handler, and its functions are implemented by the channel processing module. The channel processing module controls the FPGA to perform code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation. It outputs pseudorange, pseudorange change rate, and raw message data to the navigation processing unit and outputs tracking status information to the system control unit. The module reads raw observation data from the FPGA for digital signal processing, including the highest priority task at 1kHz (carrier lock decision and carrier tracking); the second-highest priority task at 10Hz (measurement data reading module); and the lowest priority task at 1kHz (switching task), which performs code acquisition, code tracking, carrier lockout decision, carrier acquisition decision, bit synchronization, and data demodulation.

[0109] like Figure 3 The diagram shows the DSP implementation flowchart of the navigation receiver device of this invention. The software of this invention is embedded and runs in the DSP, coordinating with the hardware to receive and process radio frequency navigation satellite signals. After running, it first executes an initialization module, and then cycles through the message processing module, satellite prediction module, navigation calculation module, RAIM monitoring module, FLASH data read / write module, channel allocation module, external interface module, and channel processing module. Each of these modules is called in the main program module, performing different processing for different needs and times. The internal time period control of the program uses the count value of the 100ms period sampling time generated by the FPGA. The receiver device continuously sends the current position, pseudorange, pseudorange rate, velocity, and time information to the host computer through the interface circuit.

[0110] The FLASH uses the 64Mbits storage space of SST39VF6401B-70-4I-EKE, which is divided into 4 segments of 16Mbits each. The segmented address space is controlled by the DSP general-purpose I / O. The segments store the DSP and FPGA programs, and also save the satellite almanac, location information and time information stored by the DSP.

[0111] The watchdog timer, model MAX706MJA, monitors program execution and provides a reset function for the DSP to prevent program crashes due to unforeseen circumstances.

[0112] The BD2 military code generator PRM provides the FPGA with the BD2 system military code stream and the converted Q-branch message. If the BD2 system Q-branch message is encrypted, the BD2 decryption IC card first receives the Q-branch message output from the second FPGA for decryption processing. The specific process is as follows:

[0113] After obtaining the valid BeiDou week number from the message, the BD2 military code generator PRM performs code stream extraction and message conversion upon successful transmission of the timing parameter command. The FPGA sends the precise code stream extraction time to the BD2 military code generator PRM to extract the code stream for Q-branch acquisition and tracking. If the Q-branch message is unencrypted, it is sent to the BD2 military code generator PRM for message conversion to obtain the Q-branch message parameters. If the Q-branch message is encrypted, it is sent to the BD2 decryption IC card for decryption processing, and then back to the BD2 military code generator PRM for message conversion to obtain the Q-branch message parameters. The BD2 decryption IC card performs message decryption, first using the BeiDou week and week second for self-testing. Upon successful self-testing, the encrypted Q-branch message is sent for decryption processing; if the Q-branch message is unencrypted, the BD2 decryption IC card does not require processing. Both the second-generation military code generator (PRM) and the IC card require marking before use. Marking is completed by connecting to an external dedicated marking device via an RS422 serial port. The receiving device communicates with the host computer via an RS422 serial port.

[0114] The interface circuit receives control information and key destruction protocol commands from the second electrical connector and outputs them to the FPGA. Simultaneously, it receives receiver position information, speed information, pseudorange, pseudorange rate, and time information from the FPGA and sends them to the second electrical connector. In this embodiment, the interface circuit includes an optocoupler-isolated RS422 interface circuit. The RS422 serial port is implemented using an RS422 serial port core plus a MAX422 transmitter driver chip and an HCPL-6631 optocoupler receiver, achieving a transmission rate of 115.2 Kbits / s and providing secure protection between the interface and external devices.

[0115] The second electrical connector is a J14A type rectangular electrical connector, which outputs control information and key destruction protocol commands sent by the external host computer to the interface circuit, and sends the receiver position information, speed information, pseudorange, pseudorange rate, and time information output by the interface circuit to the external host computer. The rectangular electrical connector communicates with the host computer, obtains +5V power from the host computer, and supplies power to the voltage converter and power supply protector. The communication port uses an RS422 serial port to send positioning results to the host computer; simultaneously, the communication port is used for FPGA and DSP program upgrades; and the communication port uses an RS422 serial port to complete PRM chip and IC card refilling.

[0116] Only one type of power supply chip, the LTC3614IUDD, is used to provide the necessary voltages for all components of the satellite navigation receiver. Upon power-up, a +5V primary bus power supply is obtained via the second electrical connector. Five voltage converters (one type and five in total) generate the required secondary power supplies of +1.2V, +1.4V, +1.8V, +2.5V, and +3.3V to power the various devices. Simultaneously, the +5V voltage serves as a feed power supply to the external antenna via the MAX893L feed protector.

[0117] Testing has confirmed that this invention implements an airborne embedded three-system satellite navigation receiver. The three receiving channels utilize similar components and have compatible packaging designs. Channel interchangeability is possible with appropriate filter adjustments. It can simultaneously receive GPS-L1 civilian code, GLONASS-G1 civilian code, BDII-B3 military code, and civilian code signals, achieving navigation constellation redundancy. A single RF input port reduces installation complexity; a dielectric filter ensures good phase consistency and high out-of-band rejection; an integrated OEM board design for the RF and baseband channels reduces airborne load; segmented FLASH storage of DSP and FPGA programs provides clearer programming; and a transient suppression diode SMDJ5.0A is used for lightning protection, offering simple structure and good lightning protection. A MAX893L current-limiting switch protects against external antenna short circuits and self-recovers after the external short circuit disappears. Only one power supply chip, the LTC3614, is used, and the device employs a common-source clock, improving EMC performance. The real-time clock can maintain its time for over 20 minutes after a power outage, and this time can be further increased by adding capacitor value. The key destruction reader uses an optocoupler HCPL-6631 to isolate external key destruction hardware commands and the receiving device. The interface uses a MAX422 and an optocoupler HCPL-6631 to implement an optically isolated RS422 interface. The navigation receiver was ultimately implemented on a 150mm × 120mm OEM circuit board.

[0118] Of course, any equivalent transformations or substitutions made to the components, positional relationships, and connection methods of the present invention without changing their functions also fall within the protection scope of the present invention.

[0119] The technologies not disclosed in this invention specification are known in the art.

Claims

1. An airborne embedded three-system satellite navigation receiver, characterized in that: Includes a splitter, lightning protection device, power supply protection device, first frequency synthesizer, second frequency synthesizer, third frequency synthesizer, first amplifier, second amplifier, third amplifier, first filter, second filter, third filter, first mixer, second mixer, third mixer, first analog-to-digital converter, second analog-to-digital converter, third analog-to-digital converter, DSP, FPGA, crystal oscillator, fourth amplifier, clock divider, FLASH, watchdog timer, voltage converter, BD second generation military code generator PRM, BD second generation decryption IC card, key destruction reader, real-time clock, interface circuit, and first electrical connector and second electrical connector; The first electrical connector inputs the analog radio frequency navigation satellite signal received from the outside to the splitter; at the same time, it provides +5V power to the external antenna. The power supply protector receives +5V power and outputs it to the first electrical connector. A lightning protection device is connected in parallel to the output of the first electrical connector to provide lightning protection for the navigation receiver. The splitter receives the analog radio frequency navigation satellite signal output from the first electrical connector, divides it into three paths according to power, and sends them to the first amplifier, the second amplifier, and the third amplifier respectively. The first amplifier receives the first satellite signal from the splitter, amplifies it, and sends it to the first filter. The second amplifier receives the second satellite signal from the splitter, amplifies it, and then sends it to the second filter. The third amplifier receives the third satellite signal from the splitter, amplifies it, and then sends it to the third filter. The first filter receives the first satellite signal from the first amplifier, performs bandpass filtering, and then sends it to the first mixer. The second filter receives the second satellite signal from the second amplifier, performs bandpass filtering, and then sends it to the second mixer. The third filter receives the third satellite signal from the third amplifier, performs bandpass filtering, and then sends it to the third mixer. The first mixer simultaneously receives the satellite signal from the first filter and frequency synthesizer A, performs mixing and down-conversion processing, and outputs the signal to the first analog-to-digital converter. The second mixer simultaneously receives the satellite signal from the second filter and the frequency synthesizer B, performs mixing and down-conversion processing, and outputs the signal to the second analog-to-digital converter. The third mixer simultaneously receives the satellite signal and frequency synthesizer C from the third filter, performs mixing and down-conversion processing, and outputs the signal to the third analog-to-digital converter. The first analog-to-digital converter converts the analog intermediate frequency satellite signal from the first mixer into a digital signal p(n) and outputs it to the FPGA; The second analog-to-digital converter converts the analog intermediate frequency satellite signal from the second mixer into a digital signal q(n) and outputs it to the FPGA; The third analog-to-digital converter converts the analog intermediate frequency satellite signal from the third mixer into a digital signal x(n) and outputs it to the FPGA; The FPGA includes a capture and tracking unit, an interface unit, and a key destruction unit. Upon power-up, the capture and tracking unit reads the real-time clock information and sequentially performs code capture and tracking on the received digital signals p(n), q(n), and x(n), using a carrier-locked loop to achieve carrier capture and tracking, bit synchronization, frame synchronization, data acquisition, and message demodulation. It then saves the three sets of raw observation data, including satellite position information, satellite velocity information, pseudorange, pseudorange rate, satellite almanac, satellite ephemeris, and time information. The capture and tracking unit sends the time information and the Q-branch message from the satellite ephemeris to the BD2 military code generator PRM, while simultaneously receiving the BD2 system military code stream and its conversion from the PRM. The Q branch message is replaced; the key destruction unit reads the key destruction protocol instruction of the interface circuit in real time through the interface unit, and at the same time reads the key destruction level instruction of the key destruction judge. When at least two of the three received key destruction protocol instructions are correct and the key destruction level instruction is valid, the key destruction unit performs key destruction operation on the BD second-generation military code generator PRM and the BD second-generation decryption IC card; at the same time, the key destruction unit reads back the data of the BD second-generation military code generator PRM and the BD second-generation decryption IC card to confirm the key destruction result. If the key destruction is not completed, it continues to perform key destruction operation on the BD second-generation military code generator PRM and the BD second-generation decryption IC card until the key destruction is completed, and sends the key destruction completion information to the interface circuit; the interface unit performs timing conversion on the received DSP output information and outputs it to the second electrical connector through the interface circuit. The DSP, acting as the main processor, includes a system control unit, a navigation processing unit, and a channel processing unit. The channel processing unit controls the FPGA's acquisition and tracking, outputting acquisition and tracking status information to the system control unit. Simultaneously, it reads three sets of raw observation data from the FPGA and sends them to the navigation processing unit. The navigation processing unit performs positioning calculations on the three sets of raw observation data to obtain the receiver's position information, receiver velocity information, pseudorange, pseudorange rate, satellite almanac, and time information, and outputs this information to the system control unit. The system control unit outputs the receiver's position information, velocity information, pseudorange, pseudorange rate, satellite almanac, and time information to the FPGA, and stores the satellite almanac, receiver position information, and time information in FLASH memory. Upon power-up, it initializes the first frequency synthesizer, second frequency synthesizer, third frequency synthesizer, first mixer, second mixer, third mixer, DSP, FPGA, real-time clock, and interface circuitry. The crystal oscillator generates a low-jitter system clock and sends it to the fourth amplifier; The fourth amplifier receives the clock generated by the crystal oscillator and sends the amplified clock to the first frequency synthesizer, the second frequency synthesizer, the third frequency synthesizer, and the clock divider; The clock divider receives clock A, which is amplified by the fourth amplifier. After frequency conversion and shaping, clock B is generated and sent to the FPGA, DSP, first analog-to-digital converter, second analog-to-digital converter, and third analog-to-digital converter respectively. The first frequency synthesizer receives the clock A amplified and processed by the fourth amplifier, and generates frequency synthesizer A through frequency conversion, which is then sent to the first mixer. The second frequency synthesizer receives the clock A, which is amplified and processed by the fourth amplifier, and generates frequency synthesizer B through frequency conversion, which is then sent to the second mixer. The third frequency synthesizer receives the clock A, which is amplified and processed by the fourth amplifier. After frequency conversion, the frequency synthesizer C is generated and sent to the third mixer. The FLASH memory stores the DSP program and the FPGA program, and also saves the satellite almanac, receiver location information and time information stored in the DSP. The watchdog monitors the DSP's operating status and provides a reset function for the DSP to prevent DSP crashes due to sudden reasons. The BD2 military code generator PRM provides the FPGA with the BD2 system military code stream and the converted Q-branch message. If the BD2 system Q-branch message is encrypted, the Q-branch message is first decrypted by the BD2 decryption IC card and then sent to the PRM for Q-branch message conversion. The converted Q-branch message is then output to the FPGA. The real-time clock provides time information when the navigation receiver is powered on; The interface circuit receives the key destruction protocol instruction from the second electrical connector and outputs it to the FPGA. At the same time, it obtains the receiver location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac and time information from the FPGA and sends them to the second electrical connector. The key destruction reader receives the key destruction level command from the second electrical connector and outputs it to the FPGA; The second electrical connector outputs the key destruction level command sent by the external host computer to the key destruction reader, outputs the key destruction protocol command sent by the external host computer to the interface circuit, sends the +5V power output by the host computer to the voltage conversion regulator, and sends the receiver location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac and time information output by the interface circuit to the external host computer. The voltage conversion regulator converts the +5V voltage into the operating voltage of each component.

2. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The voltage converter is model LTC3614.

3. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The lightning protection chip model is SMDJ5.0A.

4. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The power supply protector chip is model MAX893.

5. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The real-time clock consists of a DS1390U timing chip, an MC-306-32.768K crystal, and a 400uF capacitor.

6. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The key destruction reader uses an optocoupler HCPL-6631.

7. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The system control unit includes an initialization module, a FLASH data read / write module, a channel allocation module, and an external interface module; The initialization module initializes the hardware and software in the receiving device. The FLASH data read / write module writes the received satellite almanac, as well as the current location and time information of the receiving device, into the FLASH memory. When the navigation receiver is reset or powered on again, it will output the saved satellite almanac as well as the current receiver position and time information to the DSP. The channel allocation module allocates satellites to the satellite processing channels; The external interface module outputs the receiver's location information, receiver speed information, pseudorange, pseudorange rate, satellite almanac, and time information to the FPGA.

8. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The navigation processing unit includes a navigation calculation module, a RAIM monitoring module, a message processing module, and a satellite forecasting module; The message processing module uses satellite navigation messages from the raw observation data obtained from the FPGA to demodulate satellite ephemeris and satellite almanac; The satellite forecasting module forecasts satellite position, velocity, clock difference, and time information based on satellite ephemeris and almanac. The navigation solution module uses satellite position, satellite velocity, clock error, pseudorange, pseudorange rate, time information, and ionospheric and tropospheric correction information to establish a navigation solution matrix equation, and obtains the navigation information of the receiving device through least squares iterative calculation. The RAIM monitoring module detects and removes faulty stars.

9. The airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The channel processing unit is completed by the channel processing module and driven by the interrupt handler. It outputs raw observation data to the navigation processing unit, outputs the tracking status information generated by the FPGA to the system control unit, reads the raw observation data from the FPGA and processes the digital signal, and completes code acquisition and tracking, carrier acquisition and tracking, bit synchronization, frame synchronization, data acquisition and message demodulation.

10. An airborne embedded three-system satellite navigation receiver according to claim 1, characterized in that: The FLASH storage space is divided into L segments, which are used to store DSP and FPGA programs. The segmented address space is controlled by the DSP's general-purpose I / O; L is a positive integer.

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