FPGA configuration file loading system and working mode quick switching method

Abstract

An FPGA configuration file loading system and a working mode quick switching method thereof, which adopts high-efficiency software control technology, high-speed bus technology, DDR data buffering technology and high-speed parallel loading technology, breaks through the speed bottleneck limitation of traditional FPGA loading mode, quickly selects and switches among multiple working modes according to task requirements, and completes working mode switching within 0.2S at the fastest, so that the device meets the demand of "one machine with multiple uses" and maximally realizes software processing of the system.

Description

Technical Field

[0001] This invention relates to an FPGA configuration file loading system and a method for rapid switching of working modes, which enables the device to meet the requirement of "one machine for multiple uses" and maximizes the software processing of the system. Background Technology

[0002] In the field of aerospace telemetry, tracking, and command (TT&C) communication, to improve design flexibility and compatibility with various TT&C systems and operating modes, the logic functions of FPGAs must be able to switch in real time. However, traditional FPGA loading methods are limited by factors such as the read / write speed of dedicated FPGA configuration chips, data transmission bit width, and configuration clock frequency, making it difficult to achieve fast real-time switching. Therefore, a better method is needed to overcome the speed bottleneck of traditional FPGA loading methods, enabling rapid selection and switching between multiple operating modes according to mission requirements, allowing the equipment to meet the "one machine, multiple uses" requirement, and maximizing the software-based processing of the system. Since data transmission involves many links and related technologies, and requires overcoming many difficulties not encountered in low-speed transmission, this is a challenging task. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide an FPGA configuration file loading system and a method for rapid switching of working modes. By combining high-efficiency software control technology of host computer, high-speed bus technology, DDR data buffer technology and high-speed parallel loading technology, it breaks through the speed bottleneck limitation of traditional FPGA loading methods. According to the task requirements, it can quickly select and switch between multiple working modes, so that the device can meet the needs of "one machine for multiple uses" and maximize the software processing of the system.

[0004] The technical solution of this invention:

[0005] An FPGA configuration file loading system includes: a host computer module, an FPGA, a high-speed bus, a storage interface control module, a loading control module, a DDR controller, and a DDR memory;

[0006] The host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus. The storage interface control module stores the configuration file in the DDR memory by controlling the DDR controller. The storage interface control module also sends the control commands to the loading control module. The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control commands, thereby loading the FPGA's operating mode.

[0007] A method for rapidly switching FPGA operating modes in the system described in claim 1, comprising the following steps:

[0008] (1) The host computer module sets up the driver buffer according to the driver chain memory pool management method, and stores the configuration file and control instructions in the driver buffer;

[0009] (2) The host computer module sends the configuration file and control instructions in the drive buffer to the storage interface control module through the high-speed bus;

[0010] (3) The storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module;

[0011] (4) The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control instructions, thereby loading the FPGA working mode;

[0012] (5) The host computer module sends control commands and updated configuration files to the storage interface control module via a high-speed bus;

[0013] (6) The storage interface control module stores the updated configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module.

[0014] (7) The loading control module loads the updated configuration file in the DDR memory into the FPGA according to the received control instructions, and causes the FPGA to switch working modes.

[0015] In step (1), the host computer module sets the driver buffer according to the driver's chained memory pool management method, specifically as follows:

[0016] (3.1) A non-paged memory unit of length A is preset for the driver, which is requested by the application through the driver interface during initialization. A is greater than the length of each DMA transfer.

[0017] (3.2) After receiving a request, the driver requests a non-paged memory block of size A from the operating system in a loop until the size required by the application is reached;

[0018] (3.3) Put the starting address of each memory block that has been allocated into a list. If not enough memory has been allocated, save the list of addresses of the allocated memory blocks.

[0019] (3.4) Set the starting address of the first memory block as the write address for the first DMA transfer;

[0020] (3.5) If there is a DMA transfer request for memory, first read the length to be transferred, and then check whether the boundary of the memory block is crossed based on the DMA write address. If it is not crossed, return the write address directly. If it will cross the boundary, use the initial address of the next memory block as the write address and return it to the DMA transfer.

[0021] (3.6) If an application requests memory, first check if the memory has already been requested. If the request has been completed, return the memory address list directly, and let the application control the read and write operations. If the request has not been completed, repeat steps 3.1-3.3, and then return the memory address list.

[0022] In step (2), the host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus, specifically as follows:

[0023] (4.1) The host computer module sends a DMA start command to the high-speed bus;

[0024] (4.2) After receiving the DMA start command, the high-speed bus receives the data sent by the host computer module and then saves the received data into the bus FIFO;

[0025] (4.3) When the amount of readable data in the bus FIFO exceeds the preset value, the DMA transfer amount is set to 0, the host computer module stops sending data to the high-speed bus, and the storage interface control module reads data from the bus FIFO.

[0026] (4.4) Monitor the amount of readable data in the bus FIFO. If the amount of readable data is less than the preset value, the DMA transfer amount is set to the preset value, and the host computer module continues to perform DMA transfer.

[0027] (4.5) Repeat steps (4.2) to (4.4) until the configuration file and control commands in the host computer are sent.

[0028] In step (3), the storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, specifically as follows:

[0029] (5.1) Time-division multiplexing of DDR allows read and write operations to compete for bandwidth;

[0030] (5.2) Perform a two-level cache on the input data, that is, first save the data to a block of RAM, and after the preset amount is stored, then save the data to DDR;

[0031] (5.3) A prefetch strategy is adopted for the read data. That is, when there is no data to read, a prefetch address is first set, and the DDR controller controls the DDR to read data from the prefetch address and store it into the dual-port RAM during the idle period.

[0032] In step (4), the loading control module loads the configuration file from the DDR memory into the FPGA according to the received control instructions, specifically as follows:

[0033] (6.1) The loading control module sets the configuration file size, configuration clock rate and configuration data bus width according to the FPGA type. When it receives the FPGA loading instruction, the loading control module first sends a start configuration signal to the FPGA.

[0034] (6.2) After receiving the status signal from the FPGA, wait for a preset time according to the FPGA type and then start sending the configuration file data;

[0035] (6.3) Continuously send configuration file data until all data has been sent. After receiving the configuration success signal from the FPGA, the entire configuration process is complete.

[0036] The advantages of this invention compared to the prior art are:

[0037] (1) Compared with the traditional working mode switching method, the present invention can achieve higher data transmission speed and logic update speed;

[0038] (2) Compared with traditional working mode switching methods, the present invention is more flexible and gives users more freedom. Attached Figure Description

[0039] Figure 1 A schematic diagram of the overall system framework of this invention;

[0040] Figure 2 A schematic diagram of the overall workflow of this invention;

[0041] Figure 3 This is a schematic diagram of the transmission control process of the present invention;

[0042] Figure 4 This is a schematic diagram of the working mode switching process of the present invention;

[0043] Figure 5 This is a schematic diagram of the host driver chained memory pool structure of the present invention;

[0044] Figure 6 This is a schematic diagram of the chained memory management process of the host driver of the present invention; Detailed Implementation

[0045] This invention relates to an FPGA (Field Programmable Gate Array) configuration file loading system and a method for rapid switching of operating modes. The system's structure is as follows: Figure 1As shown, the system includes: a host computer module, an FPGA, a high-speed bus, a storage interface control module, a loading control module, a DDR controller, and a DDR memory;

[0046] The host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus. The storage interface control module stores the configuration file in the DDR memory by controlling the DDR controller. The storage interface control module also sends the control commands to the loading control module. The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control commands, thereby loading the FPGA's operating mode.

[0047] Figure 2 The overall workflow of a method for quickly switching operating modes in an FPGA configuration file loading system is illustrated below.

[0048] (1) The host computer module sets up the driver buffer according to the driver chain memory pool management method, and stores the configuration file and control instructions in the driver buffer;

[0049] Figure 3 This invention explains the optimization of memory usage by the host driver. In high-speed transmission drivers, memory copying is very time-consuming. The optimization aims to ensure that data is transferred using the same buffer for both DMA (Direct Memory Access) transfers and application copying, thus minimizing time consumption and improving transmission efficiency. Considering that the driver's DMA transfer requires contiguous non-paged memory, which the application cannot request from the operating system, it must request memory from the driver and then share the memory pointer with the application. Because of the operating system's memory management mechanism, non-paged memory is very precious in the driver, and large blocks of contiguous non-paged memory are difficult to allocate. To overcome these difficulties, this invention adopts a memory management model of multiple small memory blocks forming a chained memory pool, managed uniformly by a chained memory management module, allocating cache space for them during DMA transfers and application requests.

[0050] Figure 4This describes the chained memory management process in the driver. The management program is responsible for requesting, allocating, and releasing memory. When the application starts, it needs to request memory from the management program through the driver interface and set the block size. The management program requests memory block by block according to the requested block size. If the request fails, it only uses the successfully requested portion and notifies the application of the result. After the memory request is completed, the management program checks in real time whether there is a DMA memory request or an application memory request. If there is a DMA memory request, it allocates a contiguous block of memory from the memory pool according to the read / write address and returns it to the DMA. If there is an application memory request, it returns a list of valid addresses to the application, which controls the initial address of the relevant read / write operations. The chained memory uses a cyclical approach, operating on the first block of memory only after the last block is used up, thus maximizing the data transfer speed.

[0051] In summary, the host computer module sets up the driver buffer according to the driver's chained memory pool management method, specifically as follows:

[0052] (1.1) A non-paged memory unit of length A is preset for the driver, which is requested by the application through the driver interface during initialization. A is greater than the length of each DMA transfer.

[0053] (1.2) After receiving a request, the driver requests a non-paged memory block of size A from the operating system in a loop until the size required by the application is reached;

[0054] (1.3) Put the starting address of each memory block that has been allocated into a list. If not enough memory has been allocated, save the list of addresses of the allocated memory blocks.

[0055] (1.4) Set the starting address of the first memory block as the write address for the first DMA transfer;

[0056] (1.5) If there is a DMA transfer request for memory, first read the length to be transferred, and then check whether the boundary of the memory block is crossed based on the DMA write address. If it is not crossed, return the write address directly. If it will cross the boundary, use the initial address of the next memory block as the write address and return it to the DMA transfer.

[0057] (1.6) If an application requests memory, first check if the memory has been requested. If the request has been completed, return the memory address list directly, and let the application control the read and write operations. If the request has not been completed, repeat steps 1.1-1.3, and then return the memory address list.

[0058] (2) The host computer module sends the configuration file and control instructions in the drive buffer to the storage interface control module through the high-speed bus;

[0059] Figure 5 This describes the optimized transmission control program flow (only the data transmission control from the host to the main control unit is described here). The entire transmission process is implemented by the high-speed bus module. In the diagram, S0: Idle, S1: Start DMA transmission and receive data, S2: Transmission in progress, local transmission is enabled, and the DMA transmission amount is set to a preset value, S3: Waiting, controlling the local transmission and DMA transmission amounts based on the amount of readable and writable data, and S4: DMA ends.

[0060] The host computer module sends a DMA start command to the high-speed bus. Upon receiving the command, the high-speed bus receives the data from the host computer module and saves it to the bus FIFO (a first-in, first-out storage structure). When the amount of readable data in the FIFO exceeds a preset value, the DMA transfer threshold is set to 0, the host computer module pauses data transmission to the high-speed bus, and the storage interface control module reads data from the FIFO. When the amount of readable data in the FIFO is less than the preset value, the DMA transfer threshold is set to the preset value, and the host computer module continues DMA transmission. This process repeats until the configuration file and control commands from the host computer are completely sent.

[0061] In summary, the host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus, specifically as follows:

[0062] (2.1) The host computer module sends a DMA start command to the high-speed bus;

[0063] (2.2) After receiving the DMA start command, the high-speed bus receives the data sent by the host computer module and then saves the received data into the bus FIFO;

[0064] (2.3) When the amount of readable data in the bus FIFO exceeds the preset value, the DMA transfer amount is set to 0, the host computer module stops sending data to the high-speed bus, and the storage interface control module reads data from the bus FIFO.

[0065] (2.4) Monitor the amount of readable data in the bus FIFO. If the amount of readable data is less than the preset value, the DMA transfer amount is set to the preset value, and the host computer module continues to perform DMA transfer.

[0066] (2.5) Repeat steps (2.2) to (2.4) until the configuration file and control commands in the host computer are sent.

[0067] (3) The storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module;

[0068] The storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, specifically as follows:

[0069] (3.1) Time-division multiplexing of DDR allows read and write operations to compete for bandwidth;

[0070] (3.2) Perform a two-level cache on the input data, that is, first save the data to a block of RAM, and after the preset amount is stored, save the data to DDR;

[0071] (3.3) A prefetch strategy is adopted for the read data. That is, when there is no data to read, a prefetch address is first set, and the DDR controller controls the DDR to read data from the prefetch address and store it into the dual-port RAM during the idle period.

[0072] (4) The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control instructions, thereby loading the FPGA working mode;

[0073] (5) The host computer module sends control commands and updated configuration files to the storage interface control module via a high-speed bus;

[0074] (6) The storage interface control module stores the updated configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module.

[0075] (7) The loading control module loads the updated configuration file in the DDR memory into the FPGA according to the received control instructions, and causes the FPGA to switch working modes.

[0076] Figure 6 The optimized process of the working mode switching method is explained. The entire switching process is implemented by the loading control module. In the figure, S0: Idle, S1: Start the working mode switching process and send a start configuration signal to the controlled end, S2: Send configuration data, the controlled end receives the data and performs configuration operations, S3: Configuration process error, report the error status code, wait for the next configuration operation, S4: Data transmission ends and the working mode switching is completed.

[0077] The loading control module sets operating parameters such as configuration file size, configuration clock rate, and configuration data bus width according to the FPGA type. Upon receiving a working mode switching command, the loading control module first sends a start configuration signal to the FPGA. After receiving the status signal from the FPGA, it waits for a period of time according to the FPGA type before sending configuration file data. It continuously sends configuration file data until all data is sent. After receiving a configuration success signal from the FPGA, the entire configuration process is marked as complete, and the working mode switching is successful. Throughout the entire working mode switching process, the loading control module reports the amount of configured data and the configuration status in real time.

[0078] In summary, the loading control module in steps 4 and 7 loads the configuration file from the DDR memory into the FPGA according to the received control instructions, specifically as follows:

[0079] (6.1) The loading control module sets the configuration file size, configuration clock rate and configuration data bus width according to the FPGA type. When it receives the FPGA loading instruction, the loading control module first sends a start configuration signal to the FPGA.

[0080] (6.2) After receiving the status signal from the FPGA, wait for a preset time according to the FPGA type and then start sending the configuration file data;

[0081] (6.3) Continuously send configuration file data until all data has been sent. After receiving a configuration success signal from the FPGA, the entire configuration process is complete. In step 7, a new configuration file was loaded, thus completing the working mode switch.

[0082] The method of this invention has been applied in some engineering projects. After adopting the method of this invention, the speed and flexibility of system operating mode switching have been improved. Table 1 illustrates a comparison of some key performance aspects between the method of this invention and the traditional method. During testing, the traditional method was tested using its highest configuration rate on an FPGA implementation of operating mode switching.

[0083] Table 1 illustrates the performance improvement of the system's operating mode after implementing the optimization program:

[0084] Table 1. Performance test results of system working mode switching

[0085] Application Mode configuration file Configuration frequency <![CDATA[ Bit width ]]> Mode switching time traditional methods 12MB 40MHz 1 bit 3s High-speed switching mode 12MB 80MHz 32bit 0.2s

[0086] This invention is implemented within Altera's FPGA, breaking through the speed bottleneck of traditional FPGA loading methods. It can significantly reduce the time for switching between working modes, and has good practicality and application value. It can provide a feasible solution for users who need to quickly select and switch between multiple working modes to meet the "one machine, multiple uses" requirement of the device.

Claims

1. An FPGA configuration file loading system, characterized in that... include: Host computer module, FPGA, high-speed bus, storage interface control module, loading control module, DDR controller and DDR memory; The host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus. The storage interface control module stores the configuration file in the DDR memory by controlling the DDR controller. The storage interface control module also sends the control commands to the loading control module. The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control commands, thereby loading the FPGA's operating mode.

2. A method for rapidly switching FPGA operating modes in the system of claim 1, characterized in that... The steps are as follows: (1) The host computer module sets up the driver buffer according to the driver chain memory pool management method, and stores the configuration file and control instructions in the driver buffer; (2) The host computer module sends the configuration file and control instructions in the drive buffer to the storage interface control module through the high-speed bus; (3) The storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module; (4) The loading control module loads the configuration file in the DDR memory into the FPGA according to the received control instructions, thereby loading the FPGA working mode; (5) The host computer module sends control commands and updated configuration files to the storage interface control module via a high-speed bus; (6) The storage interface control module stores the updated configuration file into the DDR memory by controlling the DDR controller, and the storage interface control module also sends the control command to the loading control module. (7) The loading control module loads the updated configuration file in the DDR memory into the FPGA according to the received control instructions, and causes the FPGA to switch working modes.

3. The method for fast switching of FPGA operating modes according to claim 2, characterized in that: In step (1), the host computer module sets the driver buffer according to the driver's chained memory pool management method, specifically as follows: (3.1) A non-paged memory unit of length A is preset for the driver, which is requested by the application through the driver interface during initialization. A is greater than the length of each DMA transfer. (3.2) After receiving a request, the driver requests a non-paged memory block of size A from the operating system in a loop until the size required by the application is reached; (3.3) Put the starting address of each memory block that has been allocated into a list. If not enough memory has been allocated, save the list of addresses of the allocated memory blocks. (3.4) Set the starting address of the first memory block as the write address for the first DMA transfer; (3.5) If there is a DMA transfer request for memory, first read the length to be transferred, and then check whether it will cross the boundary of the memory block according to the DMA write address. If it will not cross the boundary, return the write address directly. If it will cross the boundary, use the starting address of the next memory block as the write address and return it to the DMA transfer. (3.6) If an application requests memory, first check if memory has been requested. If the request has been completed, return the list of memory block addresses directly, and let the application control the read and write operations. If the request has not been completed, repeat (3.1)-(3.3) and then return the list of memory block addresses.

4. The method for fast switching of FPGA operating modes according to claim 2, characterized in that: In step (2), the host computer module sends the configuration file and control commands to the storage interface control module via a high-speed bus, specifically as follows: (4.1) The host computer module sends a DMA start command to the high-speed bus; (4.2) After receiving the DMA start command, the high-speed bus receives the data sent by the host computer module and then saves the received data into the bus FIFO; (4.3) When the amount of readable data in the bus FIFO exceeds the preset value, the DMA transfer amount is set to 0, the host computer module stops sending data to the high-speed bus, and the storage interface control module reads data from the bus FIFO. (4.4) Monitor the amount of readable data in the bus FIFO. If the amount of readable data is less than the preset value, the DMA transfer amount is set to the preset value, and the host computer module continues to perform DMA transfer. (4.5) Repeat steps (4.2) to (4.4) until the configuration file and control instructions in the host computer module are sent.

5. The method for fast switching of FPGA operating modes according to claim 2, characterized in that: In step (3), the storage interface control module stores the configuration file into the DDR memory by controlling the DDR controller, specifically as follows: (5.1) Time-division multiplexing of DDR memory, with read and write operations competing for bandwidth; (5.2) Perform a two-level cache for the input data, that is, first save the data to a block of RAM, and after the preset amount is stored, then store the data into DDR memory; (5.3) A prefetch strategy is adopted for the read data. That is, when there is no data to read, a prefetch address is first set, and the DDR controller controls the DDR memory to read data from the prefetch address and store it into the dual-port RAM during the idle period.

6. The method for fast switching of FPGA operating modes according to claim 2, characterized in that: In step (4), the loading control module loads the configuration file from the DDR memory into the FPGA according to the received control instructions, specifically as follows: (6.1) The loading control module sets the configuration file size, configuration clock rate and configuration data bus width according to the FPGA type. When it receives the FPGA loading instruction, the loading control module first sends a start configuration signal to the FPGA. (6.2) After receiving the status signal from the FPGA, wait for a preset time according to the FPGA type and then start sending the configuration file data; (6.3) Continuously send configuration file data until all data has been sent. After receiving the configuration success signal from the FPGA, the entire configuration process is complete.

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