A 12-256 way dynamically configurable lead switching electrocardio detection circuit

Abstract

The application discloses a 12-256-way dynamically configurable lead switching electrocardio detection circuit, which is a complete 12-256-way dynamically configurable lead switching solution. The 256 electrodes are combined in any difference mode through a lead dynamic configuration controller and a lead switching matrix unit, so that the hardware scale and wiring complexity are greatly reduced while the configuration flexibility is ensured. Through multi-channel parallel acquisition and time slot scheduling, the time slot switching clock frequency is greatly reduced while the sampling time of each lead is highly synchronized, so that the performance requirement of analog devices is relaxed. Through timing optimization and parameter adaptive adjustment, the consistency of signal quality in different lead modes is ensured. The application can expand the physiological signal acquisition modules of electromyography, electroencephalogram, respiration, body temperature and the like on the basis of the existing electrocardio acquisition channel, and realize the synchronous acquisition and analysis of multi-modal signals through the same lead switching matrix unit and lead dynamic configuration controller.

Description

Technical Field

[0001] This invention belongs to the fields of biomedical signal processing, integrated circuit design and clinical electrophysiological monitoring technology, and specifically relates to a 12-256 channel dynamically configurable lead switching electrocardiogram detection circuit. Background Technology

[0002] Electrocardiography (ECG), as one of the most basic and widely used examination methods in the clinical diagnosis of cardiovascular diseases, has always received widespread attention from the medical and engineering communities regarding its technological development. Routine ECG monitoring typically uses a standard 12-lead system, sufficient for most clinical diagnoses. By recording the potential changes of cardiac electrical activity at different locations on the body surface, it provides important evidence for the diagnosis of arrhythmias, myocardial ischemia, and other diseases. However, in the localization of complex arrhythmias, body surface potential mapping (BSPM), and electrophysiological studies, the spatial resolution of 12 leads is often insufficient to accurately characterize the subtle spatial distribution features of cardiac electrical activity. It is generally believed in the field that high-lead ECG acquisition with 128 or more leads using a time-division multiplexing architecture inevitably sacrifices sampling synchronization and signal-to-noise ratio. Therefore, mainstream industry solutions all adopt a fully parallel channel architecture, without in-depth research on optimizing the synchronization of time-division multiplexing. Therefore, high-lead body surface potential mapping (BSPM) technology with 12 to 256 electrodes has become a research focus.

[0003] Existing high-lead systems mostly employ a rigid mapping mode with one electrode and one channel. This architecture faces a severe contradiction between hardware redundancy and energy consumption: even in monitoring tasks requiring only a few leads, the entire hardware link continues to operate, resulting in high system power consumption and severely limiting its portability and long-term continuous monitoring applications. Furthermore, due to the lack of a flexible resource allocation mechanism, existing devices cannot dynamically adjust sampling weights based on patient size or lesion location, making truly personalized and accurate modeling difficult. At the hardware expansion level, when the channel size increases significantly, traditional switching schemes easily introduce distributed capacitance and impedance mismatch. The resulting charge injection effect often induces severe baseline drift and power frequency interference, compromising the physical consistency and numerical stability required for forward modeling.

[0004] Therefore, developing a lead switching system that supports 12-256 dynamically configurable channels, adaptive lead resource allocation, and maintains a high signal-to-noise ratio is of vital importance for improving the physiological realism of forward ECG modeling, reducing modeling costs, and optimizing individualized diagnosis and treatment outcomes. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a 12-256 channel dynamically configurable lead-switching ECG detection circuit. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a 12-256 channel dynamically configurable lead-switching ECG detection circuit, which includes: An electrode interface array comprising 256 electrodes; the electrode interface array is used to receive multiple leads from the human body through the 256 electrodes. The lead dynamic configuration controller is used to parse the lead mode, number of leads, and reference electrode number from the built-in lead configuration table according to the lead configuration update instruction. Within a fixed frame period, the multiple leads determined according to the lead mode and number of leads are divided into multiple time slots. In each time slot, the switching matrix address counter is triggered by the time slot switching clock to read the corresponding gating address. Based on the gating address, the gating control signal required by the lead switching matrix unit of the corresponding time slot is generated, and the gating control signal required by the multi-channel acquisition unit of the corresponding time slot is generated based on the parsed reference electrode number. The lead switching matrix unit is used to select the control signals required by the lead switching matrix unit based on the corresponding time slot. The first-level electrode grouping selection layer groups the 256 electrodes in the electrode interface array, and the second-level channel input selection layer connects any specified group to the positive and negative input terminals of any sampling channel in the subsequent stage. The positive and negative input terminals of the sampling channel are configured with independent analog multiplexers to form differential input paths, so as to realize the dynamic configuration of 12 to 256 leads. The multi-channel parallel signal acquisition unit amplifies and filters the differential signal generated according to the differential input path based on the reference voltage in each sampling channel. Under the control of the ADC synchronous clock, all sampling channels perform analog-to-digital conversion on the amplified and filtered differential signal, and buffer the differential signal after analog-to-digital conversion in the data buffer area of ​​the lead dynamic configuration controller. The reference voltage is generated by the reference terminal generation network according to the gating control signal required by the multi-channel acquisition unit in the corresponding time slot. A stable waiting period is inserted before the analog-to-digital conversion. The data packet and communication unit is used to send the differential signals in the data buffer of the lead dynamic configuration controller to the host computer, and to send the lead configuration update command issued by the host computer to the lead dynamic configuration controller.

[0006] The beneficial effects of this invention are: This invention proposes a 12-256 channel dynamically configurable lead-switching ECG detection circuit. Addressing the core issues of existing high-lead ECG detection systems, such as rigid architecture, severe hardware redundancy, inconsistent signal quality, and high wiring complexity, this invention offers a complete 12-256 channel dynamically configurable lead switching solution. Specifically, it achieves arbitrary differential combinations of 256 electrodes through a lead dynamic configuration controller and lead switching matrix unit, significantly reducing hardware scale and wiring complexity while maintaining configuration flexibility. Through multi-channel parallel acquisition and time-slot scheduling, it significantly reduces the time-slot switching clock frequency while ensuring high synchronization of sampling times across leads, relaxing performance requirements for analog devices. Timing optimization and adaptive parameter adjustment ensure consistent signal quality across different lead modes. As can be seen, this invention, without changing the hardware circuitry, flexibly configures the acquisition channels into various working modes such as 12-lead, 24-lead, 32-lead, 64-lead, 128-lead, and 256-lead through software instructions, achieving on-demand allocation of channel resources. While ensuring high spatial resolution acquisition, it optimizes the system's energy efficiency and solves the signal consistency problem during large-scale electrode array switching. Based on existing ECG acquisition channels, this invention can expand to include other physiological signal acquisition modules such as EMG, EEG, respiration, and body temperature, achieving synchronous acquisition and analysis of multimodal signals through the same lead switching matrix unit and lead dynamic configuration controller.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a 12-256 channel dynamically configurable lead switching ECG detection circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the dynamic configuration and acquisition operation of the lead dynamic configuration controller in the lead switching ECG detection circuit provided in this embodiment of the invention; Figure 3 This is a schematic diagram of the lead switching matrix unit in the lead switching ECG detection circuit provided in this embodiment of the invention; Figure 4 This is a schematic diagram of the structure of the multi-channel parallel signal acquisition unit in the lead-switching ECG detection circuit provided in this embodiment of the invention. Detailed Implementation

[0009] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0010] Please see Figure 1 This invention provides a 12-256 channel dynamically configurable lead-switching ECG detection circuit, which includes: An electrode interface array comprising 256 electrodes; the electrode interface array is used to receive multiple leads from the human body through the 256 electrodes. The lead dynamic configuration controller is used to parse the lead mode, number of leads, and reference electrode number from the built-in lead configuration table according to the lead configuration update instruction. Within a fixed frame period, the multiple leads determined according to the lead mode and number of leads are divided into multiple time slots. In each time slot, the switching matrix address counter is triggered by the time slot switching clock to read the corresponding gating address. Based on the gating address, the gating control signal required by the lead switching matrix unit of the corresponding time slot is generated, and the gating control signal required by the multi-channel acquisition unit of the corresponding time slot is generated based on the parsed reference electrode number. The lead switching matrix unit is used to select the control signals required by the lead switching matrix unit based on the corresponding time slot. The first-level electrode grouping selection layer groups the 256 electrodes in the electrode interface array, and the second-level channel input selection layer connects any specified group to the positive and negative input terminals of any sampling channel in the subsequent stage. The positive and negative input terminals of the sampling channel are configured with independent analog multiplexers to form differential input paths, so as to realize the dynamic configuration of 12 to 256 leads. The multi-channel parallel signal acquisition unit amplifies and filters the differential signal generated according to the differential input path based on the reference voltage in each sampling channel. Under the control of the ADC synchronous clock, all sampling channels perform analog-to-digital conversion on the amplified and filtered differential signal, and buffer the differential signal after analog-to-digital conversion in the data buffer area of ​​the lead dynamic configuration controller. The reference voltage is generated by the reference terminal generation network according to the gating control signal required by the multi-channel acquisition unit in the corresponding time slot. A stable waiting period is inserted before the analog-to-digital conversion. The data packet and communication unit is used to send the differential signals in the data buffer of the lead dynamic configuration controller to the host computer, and to send the lead configuration update command issued by the host computer to the lead dynamic configuration controller.

[0011] The lead dynamic configuration controller in this embodiment of the invention is further used to selectively reduce or increase the time slot switching clock frequency according to the parsed lead mode and lead number; wherein, when the lead number is less than or equal to 12, the time slot switching clock frequency is reduced to increase the stabilization time between adjacent lead switching; when the lead number is greater than or equal to 256, the time slot switching clock frequency is increased to increase the driving capability of the discharge switch and shorten the pre-charging time.

[0012] The lead dynamic configuration controller of this invention is further configured to, upon receiving a new lead configuration update instruction from the host computer, parse a new lead configuration table from the new instruction and store it in a spare RAM. After all leads in the current frame have been acquired, the switching matrix address counter is cleared, and the new lead configuration table in the spare RAM is switched to the lead configuration table used for the next frame's lead acquisition, so that the next frame's leads can continue to perform time-division synchronous acquisition according to the new lead configuration table. It can be seen that the lead dynamic configuration controller of this invention uses dual RAM partitioning internally, and under normal circumstances, it uses the primary RAM to avoid configuration errors and data misalignment caused by new lead configuration update instructions in half-frames.

[0013] Next, each part of the lead-switching ECG detection circuit proposed in this invention will be described in detail.

[0014] The electrode interface array of this invention provides up to 256 input terminals for electrodes, each of which has built-in electrostatic protection and filtering circuitry.

[0015] Furthermore, in this embodiment of the invention, the lead dynamic configuration controller is internally configured with an online-updable lead configuration table. The depth of this table is equal to the maximum supported lead number Lmax, for example, Lmax = 256. During each mode switch, the host computer writes the current lead number M (12 ≤ M ≤ 256) and M sets of lead definitions into this table via a communication interface. Each lead definition includes: positive electrode number, negative electrode number, reference electrode number, and reference network configuration word. The reference network configuration word is used to configure the internal switching, gain, and filtering parameters of the reference-end generation network.

[0016] The specific dynamic configuration and data acquisition work of the lead dynamic configuration controller is as follows: Figure 2 As shown, specifically: Initialization Phase. After the system powers on, the lead dynamic configuration controller loads the default lead configuration (e.g., standard 12 leads, 10 electrodes, 12 lead vectors). If dynamic switching is required, the host computer sends a lead configuration update command and a new lead definition table. After receiving complete data, the lead dynamic configuration controller first pauses the current acquisition, saves the new lead definition table in the spare RAM, and generates a reset pulse to clear the switching matrix address counter.

[0017] Frame acquisition enabled. The lead dynamic configuration controller initiates a frame acquisition with a fixed frame period Tf, triggering the acquisition cycle. Tf corresponds to the refresh rate of the output leads, typically set to the required sampling rate for the ECG signal (e.g., 1kHz). Within one frame acquisition, the lead dynamic configuration controller needs to complete the acquisition of M leads in a time-division multiplexing manner. To this end, the lead dynamic configuration controller generates a high-frequency switching clock with a frequency of M×fs, where fs is the required ADC sampling rate for each lead (e.g., 1kHz per lead, M=256, the time slot switching clock frequency is 256kHz).

[0018] Lead switching and acquisition loop. Within each frame, M leads need to be acquired, using a parallel operation of K channels. The lead dynamic configuration controller divides the M leads into M / K time slots. Each time slot simultaneously assigns the positive and negative electrode addresses and gain settings corresponding to the K leads to the K channels. Within each time slot, the switching matrix address counter is triggered by the time slot switching clock, causing the switching matrix address counter to count sequentially from 0 to M-1. For the current count value i: based on the i-th record in the lead configuration table, the positive electrode number is decoded into the gating address of the first and second stage positive input MUX, and the negative electrode number is simultaneously decoded into the gating address of the second stage negative input MUX. The gating control signal required by the lead switching matrix unit is generated based on the gating address. If the reference electrode number configuration in the i-th record changes relative to the previous record, the configuration word of the reference generation network is updated synchronously. After the switch address is updated, a programmable stable waiting period (typically 5μs~10μs) is inserted. During this period, the fast discharge switch closes and then opens, ensuring that the input of the instrumentation amplifier in the subsequent multi-channel parallel signal acquisition unit is fully established and will not interfere with subsequent ADC sampling. After the waiting period ends, the lead dynamic configuration controller outputs the ADC synchronization clock. After the ADC completes the conversion, the analog-to-digital conversion result is stored in the buffer of the corresponding lead number. Finally, as the switching matrix address counter increments, the process moves to the next lead, repeating the above process until i=M-1. Here, both the time slot switching clock and the ADC synchronization clock are generated by frequency division of a fixed frame period, ensuring that the timing of the entire system is consistent and there is no asynchronous drift. After the stable waiting period within each time slot ends, the ADC synchronization clock is output, which is consistent with the time slot switching clock but not aligned with the edge of the time slot switching clock, lagging behind by a stable waiting period. The time slot switching clock and the ADC synchronization clock have the same frequency.

[0019] Frame data processing and output. Once a frame is acquired, the lead dynamic configuration controller adds a frame header (including lead mode identifier, lead number M, timestamp, etc.) to the buffer containing M leads and sends it to the host computer via a high-speed serial interface. After transmission, the acquisition of the next frame begins immediately.

[0020] Dynamic mode switching. During system operation, if a new lead configuration update command is received, the lead dynamic configuration controller will seamlessly switch to the new lead configuration table after the current frame acquisition is completed, and perform switching acquisition according to the updated M value and lead configuration table from the next frame onwards. Since the switching only changes the lead configuration table and M value, the hardware analog channels do not require any physical modifications, thus achieving seamless dynamic configuration between 12 and 256 channels.

[0021] To achieve optimal signal quality across different lead numbers, the lead dynamic configuration controller in this embodiment incorporates adaptive adjustment logic: when M is small (e.g., 12 leads), the time slot switching clock frequency is automatically reduced, increasing the stabilization time between adjacent lead switching and further reducing switching transient interference; simultaneously, some idle acquisition channels can be used in parallel with working channels to improve common-mode rejection. When M is large (e.g., 256 leads), the time slot switching clock frequency is correspondingly increased. To ensure rapid amplifier stabilization after switching, the lead dynamic configuration controller increases the driving capability of the fast discharge switch and shortens the pre-charge time, while slightly increasing the instrumentation amplifier bandwidth. A programmable gain amplifier is used to adjust the overall gain, ensuring signal stabilization within a short time.

[0022] The lead dynamic configuration controller of this invention can be implemented using an FPGA to achieve dynamic lead configuration and timing control, or it can be implemented using a high-performance ARM Cortex-M7 / M4 series MCU, to suit cost-sensitive applications with ≤128 leads; for ultra-large-scale lead systems (>256 channels), it can be replaced by a Zynq series FPGA+ARM heterogeneous processor.

[0023] Furthermore, to support dynamic configuration of leads from 12 to 256, while avoiding overly complex design, the lead switching matrix unit of this invention adopts a two-level selection and channel parallel structure, specifically: The embodiments of the present invention provide a first type of lead switching matrix unit structure as follows: Figure 3 As shown, the first-level electrode grouping selection layer in this lead switching matrix unit includes 32 8-to-1 analog multiplexers to group the 256 electrodes into 32 groups, resulting in 32 groups of output signals. It can be seen that this embodiment divides the 256 electrode inputs into 32 groups of 8, with each group connected to one 8-to-1 analog multiplexer, using a total of 32 8-to-1 MUXs. This design compresses the original 256 parallel wirings into 32, significantly reducing spatial crosstalk and wiring complexity in large-scale electrode arrays. This stage can be viewed as dividing the electrode space into 32 independent regions.

[0024] In the second-level channel input selection layer, if there are K acquisition channels, each acquisition channel has an independent 32-to-1 analog multiplexer at both its positive and negative input terminals. Each of the 32 input ports of this 32-to-1 multiplexer is connected to one of the 32 groups of output signals; where K is either 8 or 16. Therefore, for K acquisition channels, each acquisition channel has an independent 32-to-1 analog multiplexer at both its positive and negative input terminals. The 32 input ports of this 32-to-1 multiplexer are connected to the 32 groups of output signals from the first level. The positive MUX uses one group, and the negative MUX uses another group of 32 signals with the same structure. These two groups are completely independently controlled, allowing the differential input of any channel to be freely selected from 256 electrodes, and the positive and negative electrodes can come from different groups.

[0025] In this way, through two-stage selection, the differential input of each acquisition channel can arbitrarily select positive and negative electrodes from 256 electrodes, and the electrodes selected for the positive and negative ends can come from different groups. The overall size of the lead switching matrix unit is: 32 electrodes for 8-to-1 selection in the first stage, and 2K electrodes for 32-to-1 selection in the second stage. When K=8, the total number of analog switches is moderate, ensuring low complexity and high reliability.

[0026] Similarly, this embodiment of the invention provides a second lead switching matrix unit structure. The first-level electrode grouping selection layer of the lead switching matrix unit includes 16 16-to-1 analog multiplexers to group 256 electrodes into 16 groups, obtaining 16 group output signals. The second-level channel input selection layer, if there are K acquisition channels, each acquisition channel has an independent 16-to-1 analog multiplexer at both its positive and negative input terminals. The 16 input ports of this 16-to-1 analog multiplexer are all connected to the 16 group output signals; where K is either 8 or 16. Compared to the first lead switching matrix unit structure, the second lead switching matrix unit structure reduces the total number of analog switches while maintaining the same configuration capability, but slightly increases parasitic capacitance.

[0027] When K=8, the system only requires 32 8-to-1 MUX chips and 16 32-to-1 MUX chips, keeping the total number of analog switches within a reasonable range. This achieves full-range lead configuration capability while avoiding the parasitic parameter deterioration problem caused by a large-scale switch matrix.

[0028] Furthermore, in this embodiment of the invention, the multi-channel parallel signal acquisition unit acquires signals synchronously through K sampling channels, where K is either 8 or 16; each sampling channel is as follows: Figure 4 As shown, it includes an instrumentation amplifier, a programmable gain amplifier, an anti-aliasing low-pass filter, and an analog-to-digital converter connected in sequence; wherein, An instrumentation amplifier is used to amplify the differential signal for the first time based on a reference voltage; a programmable gain amplifier is used to amplify the differential signal a second time based on a preset gain coefficient; an anti-aliasing low-pass filter is used to filter the differential signal amplified a second time using an active fourth-order Butterworth low-pass filter; and an analog-to-digital converter (ADC) is used to convert the filtered differential signal to digital. To ensure time-division synchronous acquisition, the ADC of each sampling channel performs analog-to-digital conversion synchronously under the control of the ADC synchronization clock. More specifically: The instrumentation amplifier in this embodiment of the invention employs a high-precision instrumentation amplifier (such as AD8422), with a fixed gain of 10x and a common-mode rejection ratio exceeding 100dB. Its differential input receives the ECG signal after discharge and pre-charge processing, outputs a single-ended voltage to analog ground, and uses Vref as the output reference. The instrumentation amplifier output contains a differential ECG signal amplified 10x, superimposed with the reference voltage Vref. In the multi-channel parallel signal acquisition unit, the reference terminal generation network generates the reference voltage Vref according to the gating control signal required by the multi-channel acquisition unit. This includes selecting a corresponding electrode from 256 electrodes based on the reference terminal electrode number as the reference terminal, and using the common-mode reference level generated by this reference terminal as the reference voltage Vref. The reference generation network is a dedicated analog circuit that provides a dynamically configurable reference voltage Vref for the instrumentation amplifier of each acquisition channel. Its core function is to arbitrarily select a specified electrode from 256 electrodes as the reference terminal, extract and generate a stable common-mode reference level, which serves as the voltage reference for the differential output of the instrumentation amplifier, ensuring accurate amplification of the differential ECG signal and maintaining a high common-mode rejection ratio (CMRR>100dB). By dynamically switching the reference electrode, the system can match the optimal reference terminal to the common-mode interference characteristics of different leads, solving the problem of decreased common-mode rejection capability in high-lead modes with traditional fixed reference terminals.

[0029] In this embodiment of the invention, the programmable gain amplifier (PGA) follows the instrumentation amplifier. The gain is set in real-time by the lead dynamic configuration controller based on the ECG signal amplitude. Selectable gains are 1, 2, 5, 10, 20, 50, and 100 times, allowing the total gain to be selected within the range of 10 to 1000 times. The PGA consists of a low-noise operational amplifier paired with a feedback resistor network that uses analog switching. Gain switching is completed within the stable waiting period of lead switching, avoiding the introduction of switching spikes. For high-lead-count modes such as surface potential mapping, where the ECG signal amplitude varies significantly between adjacent electrodes, the lead dynamic configuration controller can independently set the gain for different leads (gain labels are stored in the lead mapping table), thereby preventing amplifier saturation.

[0030] The anti-aliasing low-pass filter in this embodiment of the invention is an active fourth-order Butterworth low-pass filter with selectable cutoff frequencies of 150Hz and 500Hz (for conventional ECG and high-frequency ECG analysis, respectively). The cutoff frequency is changed by switching the capacitor value using an analog switch, and the switching is also performed by the lead dynamic configuration controller during non-acquisition periods. The filtered signal is sent to the ADC pre-stage drive buffer.

[0031] In this embodiment of the invention, the analog-to-digital converter (ADC) is equipped with a single 24-bit Σ-Δ ADC (such as the internal ADC of the ADS1298 or a separate device), supporting output data rates of 1kSPS and 2kSPS. Under the unified timing of the lead dynamic configuration controller, all acquisition channels' ADCs synchronously start conversion. After conversion, each ADC uploads the 24-bit analog-to-digital conversion result to the lead dynamic configuration controller via the SPI interface. The ADC integrates a programmable digital filter to suppress 50 / 60Hz power frequency interference.

[0032] In this embodiment of the invention, the gain switching of the programmable gain amplifier (PGA) and the cutoff frequency switching of the anti-aliasing low-pass filter in the multi-channel parallel signal acquisition unit are both completed within a stable waiting period. Specifically, the gain switching (1-100 times) of the programmable gain amplifier (PGA) and the cutoff frequency switching (150Hz / 500Hz) of the anti-aliasing filter are both completed within the stable waiting period, avoiding the introduction of interference during signal acquisition. To address the issue of large amplitude differences between adjacent electrode signals in high-lead mode, the gain can be set independently for each lead, and the parameters are stored in the lead configuration table and automatically loaded.

[0033] In this embodiment of the invention, a bleeder switch is designed between the lead switching matrix unit and the multi-channel parallel signal acquisition unit. During the stabilization waiting period, the bleeder switch is closed; outside the stabilization waiting period, it is open. Specifically, before each acquisition, a programmable stabilization waiting period of 5μs to 10μs is inserted, while simultaneously controlling the fast bleeder switch to close first and then open, rapidly discharging residual charge on the parasitic capacitance, ensuring sufficient establishment at the instrumentation amplifier input, and effectively eliminating baseline drift and switching spikes.

[0034] In this embodiment of the invention, the lead dynamic configuration controller triggers the acquisition cycle with a fixed frame period Tf (e.g., 1ms, corresponding to a 1kHz frame rate). Within one frame, M leads need to be acquired, employing a parallel operation mode with K channels. The lead dynamic configuration controller divides the M leads into M / K time slots. Within a time slot, after switching stabilizes, K-channel ADC conversion is synchronously initiated. The conversion results are cached in the cache address corresponding to the lead number, where lead number = time slot number × total number of sampling channels + sampling channel number. If the number of sampling channels in the last time slot exceeds M, the data from the extra channels is automatically discarded, ensuring accurate correspondence between data and leads. This parallel mode reduces the maximum number of leads (256) to only 32 time slots when K=8, lowering the time slot switching clock frequency to 32kHz, significantly relaxing the requirements for the stabilization time of analog switches and amplifiers, while ensuring high consistency in the sampling times of each lead.

[0035] Through the circuit design and time-division switching strategy described above, this invention achieves dynamic configuration of 12-256 ECG leads using only K physical acquisition channels, significantly simplifying the hardware scale while maintaining time consistency and flexibility between the signals of each lead.

[0036] Furthermore, in this embodiment of the invention, the data packet assembly and communication unit sequentially packages the time-division acquired lead data and sends it to the host computer via a high-speed serial interface. The physical interface can be a USB 2.0 controller (such as CY7C68013A) or an Ethernet controller (such as W5500), which integrates a MAC / PHY. The lead dynamic configuration controller sends the assembled data packets to the communication chip via a parallel bus or SPI. For the USB interface, the firmware maps the raw data port to batch endpoints, allowing the host computer to directly read the streaming data via a driver; for the Ethernet interface, the data is encapsulated as UDP packets with a fixed destination port, allowing the host computer to listen to the corresponding port. The communication interface also supports downlink commands: the host computer sends commands such as lead configuration update, start / stop acquisition, and calibration request via control endpoints or TCP / UDP command ports, which are parsed by the communication engine and sent to the lead dynamic configuration controller for execution, achieving bidirectional interaction. To support higher data bandwidth, the physical interface of the data packet assembly and communication unit can also be USB 3.0; for portable devices, Bluetooth 5.0 / BLE or Wi-Fi 6 can be used instead for wireless data transmission.

[0037] It should be noted that the embodiments of the present invention have been described in detail with a maximum number of supported leads of 256 as an example. In order to meet the requirements of higher precision body surface potential mapping, the maximum number of supported leads can be expanded from 256 to 512, the number of first-stage electrode group MUXs can be expanded from 32 to 64, and the second-stage 32-to-1 MUX can be upgraded to a 64-to-1 MUX.

[0038] Traditional high-lead systems typically employ a rigid mapping mode of one electrode per channel, with the number of leads and electrode connections fixed at the factory. This prevents flexible switching between standard 12-lead monitoring and 256-lead surface potential mapping based on clinical needs. Different lead numbers require different device models, severely limiting the applicable scenarios. This invention, through a two-level MUX and a channel-parallel scalable architecture, achieves arbitrary differential combinations of 256 electrodes using only 8 or 16 physical acquisition channels. It supports dynamic configurations of standard lead numbers (12, 24, 32, 64, 128, 256) and any custom lead numbers. Based on an online-updateable lead configuration table, the host computer can issue new lead definitions at any time during system operation. The dynamic lead configuration controller automatically switches to the new mode after the current frame acquisition is completed. The entire process requires no hardware circuit modifications, and there is no data loss or acquisition interruption. In clinical applications, the same device can simultaneously meet various needs, such as routine outpatient 12-lead rapid screening, cardiology 24-lead arrhythmia localization, and research institution 256-lead body surface potential mapping, significantly improving equipment utilization and clinical diagnostic and treatment efficiency.

[0039] Traditional 256-lead systems require 256 complete signal acquisition links (including instrumentation amplifiers, PGAs, filters, ADCs, etc.). Even in routine monitoring tasks requiring only 12 leads, all hardware links continue to operate, resulting in system power consumption of several watts or even tens of watts, making portability and long-term continuous monitoring impossible. Simultaneously, the large amount of idle hardware resources leads to significant cost waste. This invention employs time-division multiplexing technology, allocating the acquisition tasks of 256 leads to K physical channels (K=8 or 16) for parallel completion. When K=8, the hardware scale is only 1 / 32 of the traditional solution, with the total number of analog switches controlled at 48 (32 8-to-1 switches or 16 32-to-1 switches), significantly reducing system cost and size. System power consumption is proportional to the number of currently operating leads: in 12-lead mode, only two time slots are needed to complete one frame of acquisition, with a time slot switching clock frequency of only 2kHz. The system remains in a low-power state most of the time, reducing overall power consumption to less than 5% of the traditional solution. The low power consumption feature allows the device to be battery powered, supporting portable wearable devices and long-term continuous monitoring for more than 72 hours, expanding the application of high-lead ECG technology in home health management and telemedicine.

[0040] Traditional time-division multiplexing schemes require switching using a high-frequency clock of 256kHz. The sampling time difference between each lead is approximately 4μs, and for a 256-lead system, the sampling time difference between the first and last leads is approximately 1ms. This leads to temporal phase distortion of the ECG signal, severely affecting the accuracy of surface potential mapping and forward ECG modeling. This invention employs a multi-channel parallel acquisition and time-slot scheduling mechanism. When K=8, only 32 time slots are needed to complete the acquisition of 256 leads, reducing the time-slot switching clock frequency to 32kHz. Within each time slot, K channels are sampled synchronously. The ADCs of all channels are initiated by a unified ADC synchronization clock issued by the lead dynamic configuration controller. The sampling times of the K leads within the same time slot are completely consistent, and the sampling time interval between different time slots is only 31.25μs, far less than the ECG signal's variation period. The maximum deviation of the sampling time of each lead is <5μs, ensuring the temporal consistency of the ECG signal and providing a reliable data foundation for high-precision surface potential mapping and three-dimensional reconstruction of cardiac electrical activity.

[0041] In summary, the 12-256 channel dynamically configurable lead-switching ECG detection circuit proposed in this invention addresses the core problems of existing high-lead ECG detection systems, such as rigid architecture, severe hardware redundancy, inconsistent signal quality, and high wiring complexity. It offers a complete 12-256 channel dynamically configurable lead switching solution. Specifically, it achieves arbitrary differential combinations of 256 electrodes through a lead dynamic configuration controller and lead switching matrix unit, significantly reducing hardware scale and wiring complexity while maintaining configuration flexibility. Through multi-channel parallel acquisition and time slot scheduling, it significantly reduces the time slot switching clock frequency while ensuring high synchronization of sampling times for each lead, relaxing the performance requirements for analog devices. Timing optimization and adaptive parameter adjustment ensure consistent signal quality across different lead modes. As can be seen, this invention, without changing the hardware circuitry, flexibly configures the acquisition channels into various working modes such as 12-lead, 24-lead, 32-lead, 64-lead, 128-lead, and 256-lead through software instructions, achieving on-demand allocation of channel resources. While ensuring high spatial resolution acquisition, it optimizes the system's energy efficiency and solves the signal consistency problem during large-scale electrode array switching. Based on existing ECG acquisition channels, this invention can expand to include other physiological signal acquisition modules such as EMG, EEG, respiration, and body temperature, achieving synchronous acquisition and analysis of multimodal signals through the same lead switching matrix unit and lead dynamic configuration controller.

[0042] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A 12-256 channel dynamically configurable lead-switching ECG detection circuit, characterized in that, The lead-switching ECG detection circuit includes: An electrode interface array comprising 256 electrodes; the electrode interface array is used to receive multiple leads from the human body through the 256 electrodes. The lead dynamic configuration controller is used to parse the lead mode, number of leads, and reference electrode number from the built-in lead configuration table according to the lead configuration update instruction. Within a fixed frame period, the multiple leads determined according to the lead mode and number of leads are divided into multiple time slots. In each time slot, the switching matrix address counter is triggered by the time slot switching clock to read the corresponding gating address. Based on the gating address, the gating control signal required by the lead switching matrix unit of the corresponding time slot is generated, and the gating control signal required by the multi-channel acquisition unit of the corresponding time slot is generated based on the parsed reference electrode number. The lead switching matrix unit is used to select the control signals required by the lead switching matrix unit based on the corresponding time slot. The first-level electrode grouping selection layer groups the 256 electrodes in the electrode interface array, and the second-level channel input selection layer connects any specified group to the positive and negative input terminals of any sampling channel in the subsequent stage. The positive and negative input terminals of the sampling channel are configured with independent analog multiplexers to form differential input paths, so as to realize the dynamic configuration of 12 to 256 leads. The multi-channel parallel signal acquisition unit amplifies and filters the differential signal generated according to the differential input path based on the reference voltage in each sampling channel. Under the control of the ADC synchronous clock, all sampling channels perform analog-to-digital conversion on the amplified and filtered differential signal, and buffer the differential signal after analog-to-digital conversion in the data buffer area of ​​the lead dynamic configuration controller. The reference voltage is generated by the reference terminal generation network according to the gating control signal required by the multi-channel acquisition unit in the corresponding time slot. A stable waiting period is inserted before the analog-to-digital conversion. The data packet and communication unit is used to send the differential signals in the data buffer of the lead dynamic configuration controller to the host computer, and to send the lead configuration update command issued by the host computer to the lead dynamic configuration controller.

2. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, The lead dynamic configuration controller is also used to selectively reduce or increase the time slot switching clock frequency based on the resolved lead mode and number of leads; wherein, when the number of leads is less than or equal to 12, the time slot switching clock frequency is reduced to increase the settling time between adjacent lead switching; when the number of leads is greater than or equal to 256, the time slot switching clock frequency is increased to increase the driving capability of the discharge switch and shorten the pre-charging time.

3. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, The lead dynamic configuration controller is also used to parse the new lead configuration table from the new lead configuration update instruction issued by the host computer, store the new lead configuration table in the spare RAM, clear the switching matrix address counter after all leads in the current frame have been acquired, and switch the new lead configuration table in the spare RAM to the lead configuration table used for the next frame of lead acquisition, so that the next frame of leads can continue to perform time-division synchronous acquisition according to the new lead configuration table.

4. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, The first-level electrode grouping selection layer in the lead switching matrix unit includes 32 8-to-1 analog multiplexers to group 256 electrodes into 32 groups, resulting in 32 groups of output signals. In the second-level channel input selection layer, if there are K acquisition channels, each acquisition channel has an independent 32-to-1 analog multiplexer set at its positive and negative input terminals. The 32 input ports of the 32-to-1 analog multiplexer are connected to 32 groups of output signals; where K is 8 or 16.

5. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, The first-level electrode grouping selection layer in the lead switching matrix unit includes 16 16-to-1 analog multiplexers to group 256 electrodes into 16 groups, resulting in 16 groups of output signals. In the second-level channel input selection layer, if there are K acquisition channels, each acquisition channel has an independent 16-to-1 analog multiplexer set at its positive and negative input terminals. The 16 input ports of the 16-to-1 analog multiplexer are connected to 16 groups of output signals; where K is either 8 or 16.

6. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, The multi-channel parallel signal acquisition unit simultaneously acquires K sampling channels, where K can be 8 or 16. Each sampling channel includes, in sequence, an instrumentation amplifier, a programmable gain amplifier, an anti-aliasing low-pass filter, and an analog-to-digital converter. An instrumentation amplifier is used to perform the first amplification of a differential signal based on a reference voltage. A programmable gain amplifier is used to perform a second amplification of the differential signal after the first amplification according to a preset gain coefficient. Anti-aliasing low-pass filter is used to filter the differential signal after the second amplification by employing an active fourth-order Butterworth low-pass filter. An analog-to-digital converter is used to perform analog-to-digital conversion on filtered differential signals. To ensure time-division synchronous acquisition, the analog-to-digital converters of each sampling channel perform analog-to-digital conversion processing synchronously under the control of the ADC synchronization clock.

7. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 6, characterized in that, In the multi-channel parallel signal acquisition unit, the gain switching of the programmable gain amplifier and the cutoff frequency switching of the anti-aliasing low-pass filter are both completed within a stable waiting period.

8. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 6, characterized in that, In the multi-channel parallel acquisition unit, after all sampling channels have completed analog-to-digital conversion, the differential signal after analog-to-digital conversion is buffered in the buffer address corresponding to the lead number. When the number of sampling channels exceeds the number of leads, the remaining sampling channels are discarded. Lead number = time slot number × total number of sampling channels + sampling channel number.

9. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, In the multi-channel parallel signal acquisition unit, the reference terminal generation network generates a reference voltage based on the gating control signal required by the multi-channel acquisition unit, including: Select the corresponding electrode from 256 electrodes according to the reference terminal electrode number, and use the common-mode reference level generated by the reference terminal as the reference voltage.

10. The 12-256 channel dynamically configurable lead-switching ECG detection circuit according to claim 1, characterized in that, A bleeder switch is designed between the lead switching matrix unit and the multi-channel signal parallel acquisition unit. The bleeder switch is closed during the stable waiting period and open outside the stable waiting period.

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