A device control method, control system, electronic device, and storage medium

Abstract

This application discloses a device control method, control system, electronic device, and storage medium. The method includes: allocating carrier frequency pairs to multiple focal points, generating distinct difference frequencies between corresponding carrier frequency pairs as frequency domain labels, and constraining the intermodulation products generated between each carrier frequency pair to deviate from the frequency domain labels based on preset constraints; coherently outputting multiple drive signals based on the same master clock according to the allocated carrier frequency pairs; acquiring the response electrical signals of the corresponding drive signals under synchronous drive of the master clock; performing frequency separation demodulation on the response electrical signals using the frequency domain labels to extract the separated response data corresponding to each focal point; and generating and issuing adjustment commands corresponding to each focal point based on the difference between the separated response data and a preset target value. This application can eliminate in-band non-target interference focal points in non-target regions, separate the responses of each focal point from the mixed response electrical signals, construct a multi-target independent closed-loop mechanism, and improve the selectivity and control accuracy of neural modulation devices.

Description

Technical Field

[0001] This application belongs to the field of signal frequency division multiplexing and processing technology of brain-computer interface and digital diagnostic and treatment equipment, specifically relating to a device control method, control system, electronic device and storage medium. Background Technology

[0002] Temporal coherent electrical stimulation (TCS) is a non-invasive, multifocal electrical stimulation control technique. Its core principle lies in applying high-frequency carrier signals to the target region via multiple pairs of electrodes. Utilizing the physical property of brain tissue as a volume conductor, multiple high-frequency carriers undergo electric field superposition and interference in the deep region, generating a low-frequency interference electric field carrying the envelope frequency. Because the scalp and superficial tissues are penetrated by high-frequency signals and do not exhibit a low-frequency response to high frequencies, this technique enables spatially selective modulation of deep regions.

[0003] Currently, in multifocal time-domain coherent electrical stimulation, existing methods employ empirically fixed small frequency offsets or ensure that each focus uses the same envelope frequency. As the number of target focuses increases, the overlap region of the whole-brain electric field grows exponentially. Second-order or higher-order intermodulation products generated at the overlap point by any two non-target carriers easily fall into the effective envelope band, inducing a large number of in-band non-target interference focuses in non-target regions, resulting in stray false stimulation. When acquiring response electrical signals, because each focus uses the same difference frequency, the envelope-following responses of different focuses alias in the frequency domain. The control system cannot independently extract the response amplitude of the specific focus from the mixed EEG signals, severing the link for independent evaluation and closed-loop feedback by focus, thus limiting the practical application and control accuracy of multi-target neuromodulation devices. Summary of the Invention

[0004] This application solves the problems of false stimulation in non-target areas and the inability to independently close the loop feedback due to the aliasing of response signals from different focal points in the prior art, and provides a device control method, control system, electronic device and storage medium.

[0005] This application provides a device control method for a multifocal time-domain coherent electrical stimulation system, comprising:

[0006] Carrier frequency pairs are assigned to multiple focal points respectively, so that the carrier frequency pairs corresponding to each focal point form different difference frequencies as frequency domain labels, and the intermodulation products generated between each carrier frequency pair are constrained to deviate from the frequency domain labels based on preset constraints.

[0007] Based on the assigned carrier frequency pair, multiple drive signals are coherently output using the same master clock.

[0008] Under the synchronous drive of the master clock, the response electrical signal of the corresponding drive signal is acquired.

[0009] Frequency domain labels are used to perform frequency separation demodulation on the response electrical signal, and the separated response data corresponding to each focal point are extracted.

[0010] Based on the difference between the separated response data and the preset target value, adjustment commands corresponding to each focus are generated and issued.

[0011] Optionally, carrier frequency pairs are assigned to multiple focal points, including: obtaining the frequency band requirement range of multiple focal points; configuring different envelope frequencies as frequency domain labels for each focal point; and solving to generate reference carrier frequencies corresponding to each focal point, such that the frequency difference between reference carrier frequencies belonging to the same focal point is equal to the corresponding envelope frequency.

[0012] Optionally, the intermodulation products generated between each carrier frequency pair are constrained to deviate from the frequency domain label based on preset constraints, including: determining the second-order difference frequency between any two non-co-focal reference carrier frequencies; constructing frequency avoidance conditions, setting the second-order difference frequency to exceed the preset effective envelope frequency band, and the second-order difference frequency not equal to any frequency domain label.

[0013] Optionally, the process of generating the reference carrier frequency for each focus includes: constructing a frequency planning model containing an objective function and multidimensional boundary conditions, including the extreme value of the device output frequency, the upper and lower limits of the effective envelope bandwidth, the minimum safe interval between each frequency domain label, and frequency avoidance conditions; using an online parameter optimization algorithm to iteratively search the frequency planning model, and determining whether the current candidate frequency pair combination satisfies the multidimensional boundary conditions in each iteration; in response to the existence of a candidate frequency pair combination that satisfies the multidimensional boundary conditions, outputting the candidate frequency pair combination that makes the objective function reach an extreme value as the reference carrier frequency, and sending the reference carrier frequency as the working frequency parameter to the hardware generator for configuration.

[0014] Optionally, based on the assigned carrier frequency pair, multiple drive signals are coherently output based on the same master clock, including: receiving the master clock signal from the system bus; performing phase synchronization based on the master clock signal through a multi-channel generator and generating multiple radio frequency waveforms with corresponding carrier frequency pairs; performing power amplification on the multiple radio frequency waveforms and outputting them as drive signals to the corresponding external channels.

[0015] Optionally, under the synchronous drive of the master clock, the response electrical signal corresponding to the drive signal is acquired, including: transmitting the master clock signal to the EEG acquisition module using a distribution network; locking the internal sampling clock with the master clock signal using a phase-locked loop circuit in the EEG acquisition module; and performing analog-to-digital conversion on the amplified original electrical signal to obtain the response electrical signal under the trigger of the locked internal sampling clock.

[0016] Optionally, the frequency domain label is used to perform frequency separation demodulation on the response electrical signal to extract the separation response data corresponding to each focal point, including: generating a local reference signal with the same frequency as the corresponding frequency domain label for each focal point; performing calculations on the response electrical signal and the local reference signal to extract the corresponding frequency band components and use them as separation response data.

[0017] Optionally, the response electrical signal and the local reference signal are processed to extract the corresponding frequency band components and use them as the separated response data, including: multiplying the response electrical signal with two mutually orthogonal local reference signals respectively; performing low-pass filtering on the two multiplied signals respectively to obtain an in-phase baseband signal and a quadrature baseband signal; calculating the magnitude of the in-phase baseband signal and the quadrature baseband signal to obtain envelope following response amplitude data, and using the envelope following response amplitude data as the separated response data.

[0018] Optionally, before mixing and multiplying the response electrical signal with two mutually orthogonal local reference signals, the method further includes: performing wideband bandpass filtering on the response electrical signal, the passband of which covers the frequency domain labels corresponding to all focal points; downsampling the response electrical signal after wideband bandpass filtering; establishing multiple sets of orthogonal operation channels with the same number of focal points; inputting the downsampled response electrical signal into each set of orthogonal operation channels in parallel; configuring a direct digital frequency synthesizer with the corresponding frequency domain label frequency as a signal source in each set of orthogonal operation channels; and outputting multiple sets of separated response data corresponding to different focal points in parallel through the multiple sets of orthogonal operation channels.

[0019] Optionally, based on the difference between the separation response data and the preset target value, adjustment commands corresponding to each focus are generated and issued, including: calculating the error of the separation response data of each focus deviating from the corresponding preset target value; using the controller algorithm to calculate the gain of the error and generate adjustment commands containing intensity adjustment information; and mapping and sending the adjustment commands to the control channel corresponding to the focus.

[0020] Optionally, the gain calculation of the error is performed using the controller algorithm to generate an adjustment instruction containing intensity adjustment information, including: performing proportional-integral-derivative operations or state-space matrix operations on the error to output independent control parameters; performing amplitude limiting processing on the independent control parameters to constrain them within a safe output threshold range; generating an adjustment instruction based on the amplitude-limited independent control parameters and refreshing the output amplitude register of the multi-channel generator.

[0021] This application also provides a control system for a multifocal time-domain coherent electrical stimulation system, including a data processing module, a drive output module, a synchronous acquisition module, and a separation closed-loop module. The data processing module is configured to allocate carrier frequency pairs to multiple focal points, such that the carrier frequency pairs corresponding to each focal point form distinct difference frequencies as frequency domain labels, and constrain the intermodulation products generated between each carrier frequency pair to deviate from the frequency domain labels based on preset constraints. The drive output module is configured to coherently output multiple drive signals based on the allocated carrier frequency pairs and the same master clock. The synchronous acquisition module is configured to acquire the response electrical signals of the corresponding drive signals under synchronous drive of the same master clock. The separation closed-loop module is configured to perform frequency separation demodulation on the response electrical signals using the frequency domain labels, extract the separation response data corresponding to each focal point, and generate adjustment commands corresponding to each focal point based on the difference between the separation response data and a preset target value, and send them to the drive output module.

[0022] Optionally, the synchronous acquisition module includes a distribution network, a phase-locked loop (PLL) circuit, and an analog-to-digital converter (ADC). The distribution network is connected to the bus structure of the system motherboard and is configured to receive a reference signal from the same master clock. The PLL circuit is configured to lock onto and generate an internal sampling clock based on the reference signal. The ADC is configured to convert the EEG signals input from the front-end hardware and output a response electrical signal when triggered by the internal sampling clock.

[0023] This application also provides an electronic device, including a memory and a processor. The memory is used to store a computer program. The processor is used to execute the computer program to implement the device control method described above.

[0024] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the above-described device control methods.

[0025] This application isolates the difference frequencies of each focus into distinct frequency domain labels, eliminating in-band non-target interference focuses at the source through spurious-free frequency constraints. Simultaneously, this application establishes an integrated hardware architecture for acquisition and stimulation (referred to as the "integrated acquisition and stimulation architecture") based on a single master clock synchronization, enabling the drive output and signal acquisition to share the same time base reference, reducing the impact of stimulation artifacts on the acquisition of the response electrical signal. The integrated acquisition and stimulation architecture, established with a single master clock synchronization, improves the synchronization of the response electrical signal acquisition. By utilizing differentiated frequency domain labels to separate the true response amplitude of each focus from the mixed signal, a multi-focus parallel independent closed-loop control mechanism is constructed, improving the spatial selectivity, security, and control accuracy of signal modulation in complex devices. Attached Figure Description

[0026] Figure 1This is a schematic diagram of the overall structure of the electronic device provided in the embodiments of this application.

[0027] Figure 2 This is a flowchart of the device control method provided in the embodiments of this application.

[0028] Figure 3 This is a block diagram of the control system logic structure provided in the embodiments of this application.

[0029] Figure 4 This is a schematic diagram of the spurious-free frequency planning spectrum comparison plane provided in the embodiments of this application.

[0030] Figure 5 This is a schematic diagram of the carrier clustering layout plan provided in the embodiments of this application.

[0031] Figure 6 This is a schematic diagram of the spectral comparison plane based on the separability of the focus label provided in the embodiments of this application.

[0032] Figure 7 This is a schematic diagram of the demodulation and closed-loop effect provided in the embodiments of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Example 1

[0035] This embodiment focuses on describing the device control method applied to a multifocal time-domain coherent electrical stimulation system and its underlying hardware interaction execution process.

[0036] Describe the hardware platform on which this method is executed. For example... Figure 1As shown, the electronic device provided in this application embodiment includes a low-level hardware base for executing control logic and signal interaction. This electronic device includes, but is not limited to, a processor 101, a memory 102, a multi-channel generator 103, and a synchronous acquisition module 104. The electronic device is also supplemented with a power supply module 105 for end-to-end power supply and a communication interface 106 for receiving instructions from the host computer and implementing bus data flow. The communication interface 106 can be a hardware module such as a universal serial bus interface, a network interface, or a high-speed interconnect bus. The above components are electrically connected and communicate with each other through a parallel or serial high-speed bus network within the system. The multi-channel generator 103, as a hardware generator, is configured with multiple sets of direct digital frequency synthesizers and integrates a programmable operational amplifier network to generate and output high-frequency waveforms to the corresponding channels; the synchronous acquisition module 104 includes an EEG front-end amplification link and an analog-to-digital converter array to acquire feedback electrical response signals in real time; the processor 101 undertakes the task of overall instruction coordination.

[0037] like Figure 2 As shown, based on the aforementioned hardware base, this application embodiment provides a device control method, the output of which is device control parameters or electrical signal separation data, without directly forming a disease diagnosis conclusion or treatment plan, specifically including the following control steps:

[0038] Step S201: Assign carrier frequency pairs to multiple focal points respectively, so that the carrier frequency pairs corresponding to each focal point form different difference frequencies as frequency domain labels, and constrain the intermodulation products generated between each carrier frequency pair to deviate from the frequency domain labels based on preset constraints.

[0039] To manage the frequencies of multiple control focal points and avoid crosstalk, processor 101 acquires multi-focal configuration parameters. Based on the physical location and target response characteristics of each focal point, a specific envelope frequency is configured for the k-th focal point. This envelope frequency is defined as a unique characteristic identifier of that focal point in the frequency domain, i.e., a frequency domain label, and is denoted as the target difference frequency variable. The system requires that the envelope frequencies of all focal points be distinct and not harmonic to each other.

[0040] After obtaining the frequency domain labels for each focus, the system solves for and generates the reference carrier frequency pairs corresponding to each focus. Let f be the pair of high-frequency carrier frequencies assigned to the k-th focus. k1 with f k2 In order for the carrier pairs to interfere at their spatial physical overlap to form corresponding envelope frequencies, processor 101 follows the following frequency difference relationship logic:

[0041]

[0042] Among them, f k2f represents the higher first carrier frequency corresponding to this focal point. k1 This indicates the lower second carrier frequency corresponding to the focal point; This indicates the desired low-frequency envelope frequency to be generated by the focal point. In specific implementation scenarios, it is assumed that... For each focal point, the system acquires a preset effective envelope frequency band range B: 1-100Hz, and selects distinct values ​​from this range as the difference frequency labels for each focal point. These 8 tags are configured at 5, 9, 13, 17, 23, 29, 37, and 43 Hz.

[0043] Processor 101 performs intervention calculations based on preset constraints. It extracts the reference carrier frequencies of any two non-co-focal points and calculates the second-order difference frequency generated by their spatial interference. The system constructs frequency avoidance conditions, limiting the second-order difference frequency to outside the effective envelope frequency band B, thereby ensuring that parasitic low-frequency products generated by any non-co-focal intermodulation do not fall within the 1-100Hz range. The frequency avoidance conditions also stipulate that this second-order difference frequency is not equal to any pre-assigned frequency domain label. Through constraint logic, the system eliminates in-band non-target interference focal points, ensuring the frequency band purity of all frequency domain labels.

[0044] Processor 101 constructs a frequency planning model that includes an objective function and multi-dimensional boundary conditions. The multi-dimensional boundary conditions include the extreme frequencies that the device can output, the upper and lower limits of the effective envelope bandwidth, the minimum safe interval between each frequency domain label, and frequency avoidance conditions. The system uses an online parameter optimization algorithm for iterative search. During iteration, the system evaluates each generated candidate frequency pair combination using the following objective function:

[0045]

[0046] Where cost represents the overall penalty cost of this frequency combination scheme; n2 represents the number of non-target second-order intermodulation products falling within the effective envelope frequency band; n4 represents the number of fourth-order intermodulation products caused by the recombination of the difference frequencies of the two carriers; and span represents the total bandwidth span of all carrier frequency distributions. The system assigns a very high multiplier factor to n2 as a hard constraint; applies a small penalty weight to n4 as a soft constraint; and minimizes the occupied total bandwidth span through span.

[0047] When a candidate solution is found that satisfies the multidimensional boundary conditions and the objective function cost converges to a minimum, the processor 101 outputs the set of frequency configurations and converts them into operating frequency parameters, which are then sent to the multi-channel generator 103 via the communication interface 106.

[0048] like Figure 4 Comparison of spurious-free frequency planning spectrum and Figure 5As shown in the schematic diagram of the carrier clustering layout plan, after adopting the optimization algorithm, the conventional control group generated 105 in-band non-target interference focal points, with a fourth-order spurious product count as high as 2160. The scheme generated in this application extends the carrier frequency band to 2000-3793Hz, reduces the number of in-band non-target interference focal points to 0, and decreases the fourth-order spurious product count to 532. By constructing and solving a band-constrained frequency planning model, redundant parasitic erroneous stimuli caused by the spatial overlap of multi-focal modulation are eliminated from the physical source, achieving signal separation.

[0049] Step S202: Based on the allocated carrier frequency pair, coherently output multiple drive signals using the same master clock.

[0050] After receiving the carrier frequency table from the processor 101, the multi-channel generator 103 initiates the high-frequency drive output process. The multi-channel generator 103 receives the same master clock signal from the system motherboard or bus via an internal clock network. Synchronized by this master clock, the direct digital frequency synthesizers configured in each channel generate phase-aligned radio frequency waveforms, the center frequencies of which correspond to the assigned carrier frequency pairs. The power amplification module inside the multi-channel generator 103 performs constant current or constant voltage power amplification on the generated radio frequency waveforms and converts them into high-energy drive signals, which are output to external channels via electrical contacts. By sharing the same master clock, it is ensured that the drive signals generated by all independent frequency channels remain coherent in phase and time reference.

[0051] Step S203: Under the synchronous drive of the master clock, the response electrical signal of the corresponding drive signal is acquired.

[0052] The synchronous acquisition module 104 captures weak electrical signals from the external target area while the device applies a drive signal. The system uses a hardware distribution network to transmit the same master clock signal to the synchronous acquisition module 104. The synchronous acquisition module 104 locks its internal sampling clock crystal with this master clock signal through a phase-locked loop circuit. Triggered by the locked internal sampling clock, the system performs high-frequency, high-precision analog-to-digital conversion on the amplified raw electrical signal to obtain a digitized response electrical signal. This characteristic, where the envelope is naturally generated by deep interference and the electrode current applied to the surface itself does not contain low-frequency components, naturally eliminates direct high-frequency stimulation artifacts in the low-frequency EEG acquisition band, a feature unique to multifocal time-domain coherent electrical stimulation systems.

[0053] Step S204: Frequency domain labeling is used to perform frequency separation demodulation on the response electrical signal to extract the separated response data corresponding to each focal point.

[0054] After acquiring the digitized response electrical signal, it is necessary to extract the state corresponding to each focus. The system establishes a hybrid model of the overall signal, and the processor establishes the following accumulation operation model:

[0055]

[0056] Where x(t) represents the global mixed response electrical signal acquired by the synchronous acquisition module 104; r k b(t) represents the effective electrical response generated in the region by the envelope detection at the k-th focus; b(t) represents the broadband random background noise independent of the effective signal; a(t) represents the residual power frequency interference signal induced by the external environment. The broadband random background noise b(t) is expressed as variance and standard deviation. The pink noise, and the form of the power frequency residual interference signal a(t) can be expressed as Fixed-frequency harmonic interference.

[0057] The system assigns a unique frequency domain label to the envelope frequency of each focal point, providing a basis for frequency division multiplexing (FDM) separation. For each focal point, the processor 101 generates an orthogonal local reference signal in the digital domain, consistent with its frequency domain label frequency. The acquired response electrical signal is then mixed and multiplied with the two orthogonal local reference signals, and the multiplication results are subjected to low-pass integral filtering to obtain the in-phase baseband signal and the quadrature baseband signal in DC state.

[0058] The core discrete accumulation algorithm of this quadrature phase-locked demodulation is shown below. The processor 101 performs the calculation through the multiply-accumulator:

[0059]

[0060]

[0061] Among them, I k Q represents the extracted in-phase baseband signal component corresponding to the k-th focal point; k This represents the extracted orthogonal baseband signal component corresponding to the k-th focal point; N represents the total number of sampling points within the integration period; t n This represents the nth discrete sampling time. This is the unique difference frequency domain label corresponding to this focal point; x(t) n ) represents the global mixed response electrical signal value input to the system at the current sampling time.

[0062] The system performs Euclidean magnitude calculations on in-phase and quadrature baseband signals to determine their absolute amplitudes.

[0063]

[0064] in, This represents the envelope following response amplitude data of the calculated physical response at that focus, and it is cached as the separate response data for that focus.

[0065] The system sets each focal point to use a distinct and non-harmonic difference frequency label. Based on the principle of trigonometric orthogonality, the mixed signal x(t) passes through the focal point labeled with a specific frequency difference label. After a long integration over a period of time, the cumulative values ​​of all other frequency components will cancel each other out and approach zero. Only the components belonging to the same frequency as the tag are retained, thus avoiding the vector amplitude aliasing phenomenon caused by using the same difference frequency. For example... Figure 6 As shown in the spectrum comparison diagram of the separability of the focus tag, this application recovered 8 clear energy peaks from the mixed background, with a demodulation recovery correlation coefficient r as high as 0.95 and the maximum demodulation recovery error controlled within 16.0%, realizing the decoupling of the multifocus response in the digital space.

[0066] Step S205: Based on the difference between the separated response data and the preset target value, generate and issue adjustment commands corresponding to each focus.

[0067] Based on the extracted separation response data, the system independently initiates closed-loop negative feedback regulation for each focal point. The processor 101 calculates the control error between the separation response data corresponding to each focal point and the preset target value of the control system, performing the following subtraction operation:

[0068]

[0069] Among them, e k A represents the current deviation error at the k-th focus; target This indicates the preset physical response target amplitude value for that focal point; It is the actual separation response data demodulated.

[0070] After acquiring the error, the system uses a controller algorithm to perform proportional, state-space matrix, or integral-differential operations on the error, outputting independent control parameters. In the preferred embodiment using pure proportional operations, processor 101 executes a limiting update control law:

[0071]

[0072] Among them, I k This indicates the register control word for the stimulation current intensity or amplitude corresponding to the focus k, which is sent to the generator channel; I represents the empirically given closed-loop proportional gain; max This represents the upper limit of the safe output strength threshold allowed by the hardware. The limiting function restricts the calculation result to between 0 and 1. max This is to prevent hardware damage caused by overdrive. Closed-loop proportional coefficient. The value is 0.6, and the closed-loop target response amplitude value A is... targetThe value is set to 0.7. The system can also employ a proportional-integral-derivative controller with an integral term or a complex multivariable state-space control law.

[0073] By generating adjustment commands and refreshing the internal output amplitude register of the multi-channel generator 103 via the bus, the system completes the signal control loop. For example... Figure 7 As shown in the bar chart of demodulation and closed-loop effect, after closed-loop communication iteration, the output response of each focus independently and smoothly converges to the preset target response line. By implementing error comparison and amplitude limiting adjustment steps, the system is endowed with the ability to control multiple targets in parallel, and the optimization of equipment status is achieved while ensuring electrical output safety.

[0074] Example 2

[0075] Combination Figure 3 The control system logic block diagram shown in this application embodiment provides an integrated control system. This control system includes at least a data processing module 301, a drive output module 302, a synchronous acquisition module 104, and a separate closed-loop module 304.

[0076] The data processing module 301 is configured to perform resource allocation. It acquires system parameters and assigns carrier frequency pairs to multiple focal points in the system, ensuring that each focal point's corresponding carrier frequency pair forms a unique difference frequency as its frequency domain label. Internally, this module includes an optimization constraint solver that, based on preset constraints, performs screening calculations across a vast frequency combination space, limiting the deviation of intermodulation products generated between each carrier frequency pair from their frequency domain labels.

[0077] The drive output module 302 and the data processing module 301 are bidirectionally connected at both the physical and logic layers. This module integrates underlying radio frequency devices. The drive output module 302 is configured to receive the optimal carrier frequency parameters from the data processing module 301, and based on the same master clock network provided by the system backplane, generate multiple strictly coherent and power-amplified drive signals and apply them to the external load.

[0078] The synchronous acquisition module 104 is connected to the data processing module 301 and the same master clock network. This module is configured to perform high-speed analog-to-digital conversion (ADC) under synchronous drive with the same master clock as a reference when receiving weak analog signals from external feedback, and to acquire the corresponding electrical signals of the drive signals. Specifically, the synchronous acquisition module 104 includes a front-end distribution network, a phase-locked loop (PLL) circuit, and multiple high-performance analog-to-digital converters (ADCs). The distribution network connects to the system motherboard's bus structure to receive the reference signal of the same master clock; the PLL circuit performs phase locking and frequency multiplication based on the reference signal to generate an internal high-frequency sampling clock; the ADCs utilize the effective trigger edge of the internal sampling clock to perform digital discrete conversion on the complex EEG signals input from the front-end hardware and output the results.

[0079] The separation closed-loop module 304 is connected to both the synchronous acquisition module 104 and the drive output module 302, forming a closed logic loop. This module is configured to take over the digitized response electrical signal, utilize various frequency domain labels to perform orthogonal separation and demodulation of the mixed signal stream in the frequency dimension, and extract the separation response data corresponding to each overlapping focal point. The separation closed-loop module 304 performs a subtraction comparison between the extracted separation response data and the system's preset control target value, and generates intensity or phase adjustment commands for the corresponding independent focal points based on the difference, which are then sent back to the drive output module 302.

[0080] The front-end EEG acquisition circuit of the synchronous acquisition module 104 of the control system includes an analog front-end conditioning unit consisting of a low-noise amplifier, an anti-aliasing filter, and a multi-stage high-pass / low-pass filter link. This conditioning unit is designed to filter out the high-frequency carrier baseband energy generated by direct stimulation, mainly retaining the effective low-frequency signal band with low-frequency physiological characteristics and difference frequency envelope.

[0081] Example 3

[0082] Before performing the core operation of mixing and multiplying the response electrical signal with two mutually orthogonal local reference signals, a series of pre-processing and parallel processing steps are added to the data processing link:

[0083] A broadband bandpass filter is used to perform broadband bandpass filtering on the response electrical signal output by the synchronous acquisition module. The lower and upper limits of the broadband bandpass filter are configured to cover the frequency bands of all focal points corresponding to the frequency domain labels, thus eliminating white noise interference outside the frequency bands.

[0084] The response electrical signal after broadband bandpass filtering undergoes multi-stage downsampling and decimation processing. By extracting the decimation coefficients, the real-time data throughput for digital communication transmission to the back-end separation module is reduced, thereby alleviating bus bandwidth consumption.

[0085] In field-programmable gate arrays (FPGAs) or high-performance digital signal processors (DSPs), the system establishes multiple highly independent parallel orthogonal operation channels with the same number of focal points as the number of focal points. The downsampled response electrical signals are synchronously fanned out and input in parallel to each group of orthogonal operation channels. Within each group of hardware logic channels, a direct digital frequency synthesizer corresponding to a specific frequency domain tag frequency is independently instantiated and configured as a local signal source.

[0086] Through the architecture design of pre-filtering, data extraction, and multi-channel parallel mapping in the underlying hardware, the system can simultaneously output multiple sets of separate response data corresponding to different focal points through parallel throughput of multiple sets of orthogonal operation channels with extremely low latency.

[0087] Example 4

[0088] This application provides an electronic device. (See again...) Figure 1 The electronic device has at least one processor 101 and a memory 102 containing a solid-state memory array mounted on its motherboard structure. The memory 102 is used to non-volatilely store computer program instruction code containing frequency planning, demodulation algorithms, and closed-loop logic. The processor 101 is configured to obtain the status of external devices by reading the system bus and to invoke the computer program stored in the memory 102. When the processor 101 executes the program, it controls the underlying components such as the multi-channel generator 103 and the synchronous acquisition module 104 connected to the bus, realizing various processes of the device control method. The processor 101 is not limited to a central processing unit; it can also be a graphics processing unit, an application-specific integrated circuit (ASIC), a programmable logic controller (PLC), or a field-programmable gate array (FPGA), or other chip combinations with computing power.

[0089] This application also provides a computer-readable storage medium, which can be a magnetic hard disk, optical disk, or flash memory chip, or any other physical object capable of carrying microinstructions. A computer program that can be interpreted and executed by a computing unit is written onto and stored thereon. When this computer program is loaded and executed by the processor of various industrial devices, it can implement the various steps of the device control method described in any of the foregoing embodiments.

[0090] This application decouples and integrates frequency domain planning and spatial interferometry. At the source side, multidimensional boundary constraints suppress uncontrollable in-band interference from non-target interference generated during cross-excitation, utilizing the non-collinear orthogonal characteristics of low-frequency difference signals. This system uses this orthogonal characteristic as the demodulation basis for reading weak responses from massive background noise, achieving closed-loop control of the equipment with unified coherent excitation at the front end, synchronous readback in phase at the mid-end, and multi-channel demodulation and closed-loop correction at the back end. This scheme balances anti-interference specificity and hardware channel isolation, providing a fundamental solution for large-scale, high-dimensional spatial electromagnetic control systems.

Claims

1. A device control method applied to a multifocal time-domain coherent electrical stimulation system, characterized in that, include: Carrier frequency pairs are assigned to multiple focal points respectively, so that the carrier frequency pairs corresponding to each focal point form different difference frequencies as frequency domain labels, and the intermodulation products generated between each carrier frequency pair are constrained to deviate from the frequency domain labels based on preset constraints. Based on the allocated carrier frequency pair, multiple drive signals are coherently output using the same master clock. Under the synchronous drive of the master clock, the response electrical signal corresponding to the drive signal is acquired; The frequency domain label is used to perform frequency separation demodulation on the response electrical signal to extract the separated response data corresponding to each focal point; Based on the difference between the separated response data and the preset target value, adjustment commands corresponding to each focus are generated and issued.

2. The method as described in claim 1, characterized in that, The method of allocating carrier frequency pairs to multiple focal points includes: Obtain the frequency band requirement range of the multiple focal points; Each focal point is assigned a different envelope frequency as its frequency domain label. The reference carrier frequencies corresponding to each focus are generated by solving the problem, such that the frequency difference between the reference carrier frequencies belonging to the same focus is equal to the corresponding envelope frequency.

3. The method as described in claim 2, characterized in that, The constraint based on preset constraints on the deviation of intermodulation products generated between each carrier frequency pair from the frequency domain label includes: Determine the second-order difference frequency between any two reference carrier frequencies that are not co-focal; Construct frequency avoidance conditions, setting the second-order difference frequency to exceed the preset effective envelope frequency band, and the second-order difference frequency not equal to any of the frequency domain labels.

4. The method as described in claim 3, characterized in that, The process of generating the reference carrier frequency corresponding to each focal point includes: A frequency planning model is constructed, which includes an objective function and multidimensional boundary conditions. The multidimensional boundary conditions include the extreme values ​​of the device output frequency, the upper and lower limits of the effective envelope frequency band, the minimum safe interval between each frequency domain label, and the frequency avoidance conditions. An online parameter optimization algorithm is used to iteratively search the frequency planning model, and in each iteration, it is determined whether the current candidate frequency pair combination satisfies the multidimensional boundary conditions. In response to the existence of candidate frequency pair combinations that satisfy the multidimensional boundary conditions, the candidate frequency pair combination that makes the objective function reach an extreme value is output as the reference carrier frequency, and the reference carrier frequency is sent to the hardware generator as the operating frequency parameter for configuration.

5. The method as described in claim 1, characterized in that, The method of coherently outputting multiple drive signals based on the same master clock according to the allocated carrier frequency pair includes: Receives the master clock signal from the system bus; A multi-channel generator performs phase synchronization based on the master clock signal and generates multiple radio frequency waveforms with corresponding carrier frequency pairs. The multiple radio frequency waveforms are amplified and output as driving signals to the corresponding external channels.

6. The method as described in claim 5, characterized in that, The step of acquiring the response electrical signal corresponding to the drive signal under the synchronous drive of the master clock includes: The master clock signal is transmitted to the EEG acquisition module using a distribution network; In the EEG acquisition module, a phase-locked loop circuit is used to lock the internal sampling clock with the master clock signal; The amplified original electrical signal is converted from analog to digital under the trigger of the locked internal sampling clock to obtain the response electrical signal.

7. The method as described in claim 1, characterized in that, The step of using the frequency domain label to perform frequency separation demodulation on the response electrical signal and extracting the separated response data corresponding to each focal point includes: For each focal point, a local reference signal with the same frequency as the corresponding frequency domain label is generated; The response electrical signal and the local reference signal are processed to extract the corresponding frequency band components and use them as the separated response data.

8. The method as described in claim 7, characterized in that, The step of performing calculations on the response electrical signal and the local reference signal to extract the corresponding frequency band components and use them as the separated response data includes: The response electrical signal is mixed and multiplied with two mutually orthogonal local reference signals respectively; The two multiplied signals are subjected to low-pass filtering to obtain in-phase baseband signal and quadrature baseband signal; The envelope follower response amplitude data is obtained by calculating the magnitude of the in-phase baseband signal and the quadrature baseband signal, and the envelope follower response amplitude data is used as the separation response data.

9. The method as described in claim 8, characterized in that, Before performing frequency mixing and multiplication of the response electrical signal with the two mutually orthogonal local reference signals, the method further includes: A wideband bandpass filter is performed on the response electrical signal, wherein the passband range of the wideband bandpass filter covers the frequency domain labels corresponding to all focal points; The response electrical signal after broadband bandpass filtering is downsampled; Multiple sets of orthogonal operation channels with the same number of focal points are established. The downsampled response electrical signal is input in parallel into each set of orthogonal operation channels. A direct digital frequency synthesizer corresponding to the frequency domain label frequency is configured as a signal source in each set of orthogonal operation channels. Multiple sets of separated response data corresponding to different focal points are output in parallel through the multiple sets of orthogonal operation channels.

10. The method as described in claim 1, characterized in that, The step of generating and issuing adjustment commands corresponding to each focus point based on the difference between the separated response data and the preset target value includes: Calculate the error of the separation response data of each focal point deviating from the corresponding preset target value; The gain of the error is calculated using a controller algorithm to generate the adjustment command containing intensity adjustment information; The adjustment command is mapped and sent to the control channel corresponding to the focus.

11. The method as described in claim 10, characterized in that, The step of using a controller algorithm to calculate the gain of the error and generating the adjustment command containing intensity adjustment information includes: Perform proportional-integral-differential operations or state-space matrix operations on the error to output independent control parameters; The independent control parameters are limited to a safe output threshold range. The adjustment command is generated based on the independent control parameters after amplitude limiting, and the output amplitude register of the multi-channel generator is refreshed.

12. A control system applied to a multifocal time-domain coherent electrical stimulation system, characterized in that, include: The data processing module is configured to allocate carrier frequency pairs to multiple focal points respectively, so that the carrier frequency pairs corresponding to each focal point form different difference frequencies as frequency domain labels, and constrain the intermodulation products generated between each carrier frequency pair to deviate from the frequency domain labels based on preset constraints. The drive output module is connected to the data processing module and is configured to coherently output multiple drive signals based on the same master clock according to the allocated carrier frequency pair. A synchronous acquisition module, connected to the data processing module and the same master clock, is configured to acquire response electrical signals corresponding to the drive signal under the synchronous drive of the same master clock. The separation closed-loop module is connected to the synchronous acquisition module and the drive output module respectively. It is configured to use the frequency domain label to perform frequency separation demodulation on the response electrical signal, extract the separation response data corresponding to each focus, and generate adjustment instructions corresponding to each focus according to the difference between the separation response data and the preset target value and send them to the drive output module.

13. The control system as described in claim 12, characterized in that, The synchronous acquisition module includes a distribution network, a phase-locked loop circuit, and an analog-to-digital converter. The bus structure of the distribution network connection system motherboard is configured to receive the reference signal of the same master clock; The phase-locked loop circuit is connected to the distribution network and is configured to lock onto and generate an internal sampling clock based on the reference signal; The analog-to-digital converter is connected to the phase-locked loop circuit and is configured to convert the EEG signal input from the front-end hardware and output the response electrical signal under the trigger of the internal sampling clock.

14. An electronic device, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to execute the computer program to implement the method as described in any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, implements the method as described in any one of claims 1 to 11.

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