A polishing slurry and polishing process for improving the edge quality of silicon wafers

Abstract

This invention relates to the field of semiconductor material manufacturing technology, and in particular to a polishing slurry for improving the edge quality of silicon wafers. By weight, it comprises the following components: composite abrasive, 25-45 parts; composite surfactant, 0.5-2.5 parts; chelating agent, 0.2-1.2 parts; oxidant, 0.1-0.5 parts; organic base pH adjuster to adjust the pH of the polishing slurry to 9.8-10.8, with the balance being deionized water.

Description

Technical Field

[0001] This invention relates to the field of semiconductor material manufacturing technology, and in particular to a polishing slurry and polishing process for improving the edge quality of silicon wafers. Background Technology

[0002] As semiconductor manufacturing processes advance to 5nm and below, epitaxial wafers are widely used in high-end logic chips and memory chips due to their excellent crystal integrity and electrical performance. However, post-epitaxy slip lines have become a key defect restricting the yield of epitaxial wafers.

[0003] The formation mechanism of slip lines after epitaxy lies in the fact that during the early processing of the silicon wafer edge (including wire cutting, grinding, edge chamfering, edge polishing, etc.), a subsurface damage layer, microcracks, and residual mechanical stress are introduced. These defects become sources of dislocation multiplication during high-temperature epitaxy (usually 1120℃~1180℃), and under the drive of thermal stress, slip lines form along the edge. <110> Crystalline slippage forms slip lines that extend from the edge to the center. Once formed, this defect cannot be repaired by subsequent processes, directly causing chip failure in the edge region.

[0004] Existing edge polishing techniques primarily focus on reducing edge roughness and particle contamination, but they fail to effectively eliminate the subsurface damage layer and edge geometric abrupt changes (Edge Roll-Off anomalies). Furthermore, traditional polishing slurries often contain alkaline residues and metal ion contamination (Na₂O₃). + Fe 3+ Cu 2+ High temperatures during epitaxy can exacerbate dislocation movement. Therefore, there is an urgent need to develop an edge polishing technique that can eliminate post-epitaxy slip lines at their source. Summary of the Invention

[0005] This invention provides a special polishing slurry and a matching edge polishing process, which aims to remove the subsurface damage layer, optimize the edge geometry, and achieve edge surface passivation through chemical-mechanical synergy, fundamentally eliminating stress sources and dislocation sources that induce slip lines after epitaxy, thereby significantly improving the edge quality of epitaxial silicon wafers and the final chip yield.

[0006] In a first aspect, the present invention provides the following technical solution: A polishing slurry for improving the edge quality of silicon wafers, comprising the following components by weight: composite abrasive, 25-45 parts; composite surfactant, 0.5-2.5 parts; chelating agent, 0.2-1.2 parts; oxidant, 0.1-0.5 parts; organic base pH adjuster to adjust the pH of the polishing slurry to 9.8-10.8, with the remainder being deionized water.

[0007] Preferably, the composite abrasive is composed of colloidal silica and surface-modified cerium oxide in a mass ratio of (2~4):1.

[0008] Preferably, the colloidal silica has an average particle size of 30-60 nm.

[0009] Preferably, the surface-modified cerium oxide has an average particle size of 15-25 nm, and the cerium oxide surface is modified with an organosilane coupling agent to improve dispersion stability and chemical affinity with the silicon substrate.

[0010] Preferably, the organic base pH adjuster is at least one of tetramethylammonium hydroxide and choline.

[0011] Preferably, the composite surfactant is a mixture of nonionic and anionic surfactants.

[0012] Preferably, the chelating agent is at least one of EDTA and HEDTA, used to complex metal ions and prevent catalytic dislocations at high temperatures.

[0013] Preferably, the oxidant is hydrogen peroxide or peracetic acid.

[0014] Secondly, the present invention provides a polishing process, comprising the following steps: Step S1: Damaged layer removal stage The edges of the silicon wafer are polished using a first polishing wheel with a Shore hardness of A85~95, with a polishing pressure of 0.20~0.30MPa, and the polishing slurry is continuously supplied during the polishing process; Step S2: Contour trimming and stress relief stage The silicon wafer edge is polished using a second polishing wheel with a Shore hardness of A65~75. The polishing pressure is reduced to 0.06~0.12 MPa, and the time is 120~180 seconds. During the polishing process, a diluted polishing slurry is continuously supplied with a concentration of 60%~80% of the concentration of the polishing slurry in step S1. Step S3: Surface passivation and metal chelation cleaning stage Continue polishing the edge of the silicon wafer using the second polishing wheel. Reduce the polishing pressure to 0.01~0.03 MPa and the time to 30~60 seconds. During the polishing process, continuously supply further diluted polishing fluid with a concentration of 20%~30% of the polishing fluid concentration in step S1.

[0015] Preferably, in step S1, the polishing slurry supply flow rate is 2.0~3.0 L / min, the polishing wheel speed is 1500~2000 rpm, the silicon wafer speed is 60~80 rpm, and the time is 90~150 seconds; In step S2, the polishing slurry supply flow rate is 1.0~1.5 L / min, the polishing wheel speed is 2200~2800 rpm, the silicon wafer speed is 100~150 rpm, and the time is 120~180 seconds; In step S3, the polishing slurry is supplied at a flow rate of 0.3~0.8 L / min, the polishing wheel rotates at a speed of 1500~2000 rpm, the silicon wafer rotates at a speed of 60~80 rpm, and the time is 30~60 seconds.

[0016] Compared with the prior art, the present invention has the following significant advantages: Complete elimination of slip lines after epitaxy: X-ray morphology test showed that silicon wafers treated with the present invention had no slip line defects within the 0-3mm range of the edge after epitaxy at 1120℃; while silicon wafers treated with traditional processes had multiple radial slip lines at the edge under the same epitaxial conditions, with a slip line density of 15-30 lines / wafer.

[0017] Reduced edge dislocation density: Optical microscopy examination after Secco etching showed that the density of dislocation corrosion pits in the edge region was reduced from 1×10⁻⁶ in traditional processes. 5 cm -2 Reduced to ≤1×10 3 cm -2 .

[0018] Optimized edge geometry: The edge roll-off value is improved from 0.15μm in the traditional process to ≤0.05μm, and the local flatness (SFQR) within 1mm of the edge is improved by more than 50%.

[0019] Ultra-low metal contamination: The total concentration of metal ions such as Na, Fe, and Cu on the polished edge surface is ≤5×10⁻⁶. 9 atoms / cm 2 (TXRF testing) meets the stringent requirements for edge cleanliness in advanced epitaxial processes.

[0020] Improved final chip yield: When epitaxial silicon wafers are applied to nodes of 28nm and below, the chip yield in the edge region (within 3mm from the edge) is increased from 82% in the traditional process to more than 94%, and the number of usable chips on the whole wafer increases by about 6% to 8%.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] Figure 1 The image shows a silicon wafer processed using the polishing slurry and polishing process of this invention, which is free of slip line defects.

[0023] Figure 2 This is a partial inspection image of a silicon wafer polished using a traditional polishing slurry, showing obvious slip line defects. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below.

[0025] This embodiment provides a polishing slurry for improving the edge quality of silicon wafers, comprising the following components by weight: A composite abrasive, 25-45 parts; composed of colloidal silica and surface-modified cerium oxide in a mass ratio of (2-4):1, wherein cerium oxide enhances the chemical etching of the damaged layer. The colloidal silica has an average particle size of 30-60 nm. The surface-modified cerium oxide has an average particle size of 15-25 nm, and the cerium oxide surface is modified with an organosilane coupling agent to improve dispersion stability and chemical affinity with the silicon substrate.

[0026] The composite surfactant, 0.5 to 2.5 parts, is composed of a mixture of nonionic (e.g., polyoxyethylene ether) and anionic (alkylbenzene sulfonate) surfactants. The mixing ratio is not strictly limited, and those skilled in the art can easily adjust the ratio according to the overall solid content and pH value of the polishing solution. Chelating agent 0.2~1.2 parts; EDTA or HEDTA is used to complex metal ions and prevent catalytic dislocations at high temperatures; Oxidizing agent, 0.1~0.5 parts; using hydrogen peroxide or peracetic acid to promote oxidation of silicon surface, achieving "chemical softening-mechanical removal"; An appropriate amount of organic base pH adjuster is used to adjust the polishing solution to pH 9.8~10.8; tetramethylammonium hydroxide (TMAH) or choline is used instead of traditional KOH / NaOH to avoid alkali metal ion residue; the remainder is deionized water.

[0027] This embodiment also provides a polishing process using the above-mentioned polishing liquid, including the following steps: Step S1: Damage layer removal stage (chemically enhanced polishing) The first polishing wheel (Shore hardness A85~95, high removal rate) is used to polish the edge of the silicon wafer. During the polishing process, the polishing fluid supply flow rate is 2.0~3.0 L / min, the polishing pressure is 0.20~0.30 MPa (high pressure to ensure effective removal of the damaged layer), the polishing wheel speed is 1500~2000 rpm, the silicon wafer speed is 60~80 rpm, and the time is 90~150 seconds. The main purpose of step S1 is to remove the subsurface damage layer (approximately 0.5~1.5 μm thick) in the chamfered area by combining the chemical etching of cerium oxide with mechanical polishing, thereby eliminating dislocation sources.

[0028] Step S2: Contour trimming and stress relief stage Switch to the second polishing wheel (Shore hardness A65~75, flexible polishing) to polish the edge of the silicon wafer. Dilute the polishing slurry to 60%~80% of the concentration of the polishing slurry (stock solution) in step S1. Polishing slurry flow rate: 1.0~1.5 L / min, polishing pressure reduced to: 0.06~0.12 MPa, polishing wheel speed: 2200~2800 rpm, silicon wafer speed: 100~150 rpm, time: 120~180 seconds; The main purpose of step S2 is to use a "low-pressure, high-speed" process to finely trim the edge geometry (controlling EdgeRoll-Off) while releasing residual stress on the surface to avoid stress concentration areas at the edges.

[0029] Step S3: Surface passivation and metal chelation cleaning stage Keep the second polishing wheel polishing the edge of the silicon wafer. Further dilute the polishing slurry (stock solution: deionized water = 1:3). Polishing slurry flow rate: 0.3~0.8 L / min. Polishing pressure is reduced to: 0.01~0.03 MPa (near-zero pressure polishing). Polishing wheel speed: 1500~2000 rpm. Silicon wafer speed: 60~80 rpm. Time: 30~60 seconds.

[0030] The main purpose of step S3 is to form a chemical passivation layer (silicon-rich layer) on the edge surface using H2O2 (oxidant), while simultaneously using a chelating agent to deeply remove adsorbed metal ions, ensuring that the concentration of metal contaminants on the edge surface is ≤5×10⁻⁶. 9 atoms / cm 2 .

[0031] Mechanism of action of this invention (specifically for post-elongated slip line): Dislocation source elimination: The root cause of slip lines after epitaxy lies in microcracks and dislocation nuclei in the subsurface damage layer at the edge. In the S1 stage, this invention uses a polishing slurry containing cerium oxide. Cerium oxide has higher chemical activity than silicon dioxide and can preferentially react with dangling bonds and strain regions in the damage layer to achieve "selective chemical etching," which completely removes the damage layer under high pressure, eliminating dislocation sources at their source.

[0032] Thermal stress relief: Abrupt edge geometry changes (such as sharp edge roll-off) can cause thermal stress to concentrate at the edges during epitaxy. The contour trimming process in stage S2 of this invention, through the combination of a flexible polishing wheel and low pressure and high speed, optimizes the edge contour into a smooth transition curvature, effectively dispersing epitaxial thermal stress.

[0033] Metal contamination control: Alkali metal ions (Na+) in traditional polishing solutions + K + At high epitaxial temperatures, metals diffuse into the silicon lattice, reducing dislocation activation energy and promoting slip line propagation. This invention uses TMAH organic base and EDTA chelating agent to reduce edge metal residue to extremely low levels, avoiding metal-induced dislocation multiplication.

[0034] Example 1 (Preferred Solution) This embodiment provides a polishing slurry for improving the edge quality of silicon wafers, by weight, comprising the following components: 35 parts of composite abrasive (in which the mass ratio of colloidal silica to surface-modified cerium oxide is 3:1, the average particle size of colloidal silica is 45 nm, and the average particle size of surface-modified cerium oxide is 20 nm); 1.5 parts of composite surfactant (composed of polyoxyethylene ether and alkylbenzene sulfonate mixed in a mass ratio of 2:1); 0.7 parts of chelating agent (using EDTA); 0.3 parts of oxidant (using hydrogen peroxide); the organic base pH adjuster is tetramethylammonium hydroxide (TMAH), adjusting the pH of the polishing slurry to 10.3; the remainder is deionized water.

[0035] The preparation method is as follows: First, the surface-modified cerium oxide is dispersed in deionized water and ultrasonically stirred for 20 minutes. Then, colloidal silica sol is added and stirred for another 30 minutes to obtain a composite abrasive dispersion. Subsequently, a composite surfactant, chelating agent and oxidant are added in sequence, and deionized water is added to 100 parts. Finally, the pH of the system is adjusted to 10.3 with TMAH to obtain the polishing solution.

[0036] The polishing slurry used in this embodiment is used to polish the edges of an 8-inch silicon wafer. Polishing process parameters: Step S1: Polish the edge of the silicon wafer using the first polishing wheel. During the polishing process, the polishing fluid supply flow rate is 2.5 L / min, the polishing pressure is 0.2 MPa, the polishing wheel speed is 1500 rpm, the silicon wafer speed is 60 rpm, and the time is 90 seconds. Step S2: Switch to the second polishing wheel to polish the edge of the silicon wafer. Dilute the polishing slurry to 60%~80% of the concentration of the polishing slurry (stock solution) in step S1. Polishing slurry flow rate: 1.5 L / min, polishing pressure reduced to: 0.12 MPa, polishing wheel speed: 2200 rpm, silicon wafer speed: 100 rpm, time: 120 seconds. Step S3: Keep the second polishing wheel polishing the edge of the silicon wafer, further dilute the polishing slurry (stock solution: deionized water = 1:3), polishing slurry flow rate: 0.8 L / min, polishing pressure reduced to: 0.03 MPa (near-zero pressure polishing), polishing wheel speed: 1500 rpm, silicon wafer speed: 60 rpm, time: 30 seconds.

[0037] Testing revealed that after polishing, the metal FE contamination at the edge of the silicon wafer was ≤5 ppb, and the surface 26nm particle count was ≤10 particles / wafer. Figure 1 As shown, there are no slip line defects, no dislocation defects, the edge damage layer is completely removed, and the surface smoothness is excellent.

[0038] Example 2 By weight, the composite abrasive consists of 45 parts (colloidal silica to surface-modified cerium oxide in a mass ratio of 4:1, with an average particle size of 60 nm for colloidal silica and 15 nm for surface-modified cerium oxide); 1.5 parts composite surfactant; 0.7 parts chelating agent; 0.3 parts oxidant; pH adjusted to 10.3 with TMAH; and the remainder being deionized water. The preparation method is the same as in Example 1.

[0039] Tested using the same polishing process, this embodiment, due to enhanced mechanical action, showed that the silicon wafer metal FE contamination after polishing was ≤8ppb, the 26nm particle count was ≤30 particles / wafer, the slip line defect level was medium (with slight slip traces), and the dislocation defect level was excellent, with no dislocation residue. This indicates that when the abrasive ratio is too high, the mechanical shear force increases, requiring gentler polishing parameters, such as reducing polishing pressure and grinding speed, to avoid slip lines.

[0040] Example 3 By weight, the composite abrasive consists of 35 parts (same proportions as in Example 1); the composite surfactant consists of 1.5 parts; the chelating agent consists of 0.7 parts; the oxidizing agent consists of 0.1 parts (peracetic acid is used); the pH is adjusted to 10.3 with TMAH; the remainder is deionized water. The preparation method is the same as in Example 1.

[0041] After testing with the same polishing process, the silicon wafer in this embodiment showed FE contamination ≤10ppb, 26nm particle count ≤15 particles / wafer, slip line defect level of good, and dislocation defect level of medium (some subsurface damage layer was not completely removed). The results indicate that when the oxidant content is too low, the chemical softening layer on the silicon surface is insufficient, requiring higher polishing intensity, a higher abrasive content in the polishing slurry, or a higher pH to completely remove dislocation defects. Considering the overall processing effect, the preferred oxidant addition amount in this invention is 0.2–0.5 parts by weight, with an overall applicable range of 0.1–0.5 parts by weight.

[0042] Example 4 By weight, the composite abrasive consists of 35 parts (same as in Example 1); the composite surfactant consists of 1.5 parts; the chelating agent consists of 0.7 parts; the oxidizing agent consists of 0.3 parts; the pH is adjusted to 9.8 with TMAH; and the remainder is deionized water. The preparation method is the same as in Example 1.

[0043] After testing with the same polishing process, the silicon wafer in this embodiment showed a metal FE contamination level of ≤15ppb, a 26nm particle count of ≤12 particles / wafer, a slip line defect level of good, and a dislocation defect level of medium. This indicates that at lower pH, the chemical etching and leveling effect of TMAH on the silicon surface decreases, and the dispersion stability of colloidal silica is slightly reduced, resulting in insufficient chemical etching efficiency. Higher polishing intensity or a higher proportion of abrasive or oxidant in the polishing slurry is required to completely remove dislocation defects. Considering the overall processing effect, the preferred pH value of the polishing slurry in this invention is 10.0~10.5, and the overall applicable range is 9.8~10.8 parts by weight.

[0044] Example 5 (Comparative Example) By weight, the composite abrasive consists of 35 parts (same as in Example 1); the composite surfactant consists of 0.5 parts; the chelating agent consists of 0.2 parts; the oxidizing agent consists of 0.3 parts; the pH is adjusted to 10.3 with TMAH; and the remainder is deionized water. The preparation method is the same as in Example 1.

[0045] After testing with the same polishing process, the silicon wafers in this embodiment showed ≥30 ppb of metal FE contamination, ≥60 particles per 26nm wafer, medium slip line defect level, and good dislocation defect level. The reasons for this are as follows: insufficient surfactant led to severe abrasive particle aggregation, resulting in numerous large particle scratches during polishing and a sharp increase in particle count; insufficient chelating agent prevented the effective complexation of Cu, Fe, and other metal ions introduced during polishing, leading to localized pitting corrosion on the silicon surface under high-temperature catalytic oxidation, thus exacerbating metal contamination. This indicates that the amounts of composite surfactant and chelating agent must be synergistically matched. When the surfactant content is low (0.5 parts), the amount of chelating agent (greater than 0.2 parts) needs to be increased to ensure system stability and cleaning effect.

[0046] To more clearly illustrate the technical effects of this invention, a comparative example is provided: The traditional polishing slurry formulation was used, which contains no surface-modified cerium oxide (only 50 parts colloidal silica), 1.5 parts composite surfactant, 0.7 parts chelating agent, and 0.3 parts oxidant, with the pH adjusted to 10.5 using KOH. Tests using the same polishing process showed that the FE contamination at the silicon wafer edge reached as high as 45 ppb, with a 26nm particle count ≥100 particles / wafer. Figure 2As shown, the slip line grade and dislocation grade are both poor. This is because the lack of chemical etching enhancement from cerium oxide results in low efficiency of damage layer removal; simultaneously, the residual sodium and potassium ions introduced by KOH lead to excessive Fe metal contamination. All indicators in the comparative examples are significantly inferior to those in Examples 1-4 of this invention, fully demonstrating the superiority of the formulation of this invention in improving the edge quality of silicon wafers.

[0047] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A polishing slurry for improving the edge quality of silicon wafers, characterized in that, By weight, it contains the following components: composite abrasive, 25-45 parts; composite surfactant, 0.5-2.5 parts; chelating agent, 0.2-1.2 parts; oxidizing agent, 0.1-0.5 parts; An organic base pH adjuster is used to adjust the polishing solution to pH 9.8-10.8, with the remainder being deionized water.

2. The polishing slurry for improving the edge quality of silicon wafers according to claim 1, characterized in that, The composite abrasive is composed of colloidal silica and surface-modified cerium oxide in a mass ratio of (2~4):

1.

3. The polishing slurry for improving the edge quality of silicon wafers according to claim 2, characterized in that, The colloidal silica has an average particle size of 30~60nm.

4. The polishing slurry for improving the edge quality of silicon wafers according to claim 2, characterized in that, The surface-modified cerium oxide has an average particle size of 15-25 nm, and the cerium oxide surface is modified with an organosilane coupling agent to improve dispersion stability and chemical affinity with the silicon substrate.

5. The polishing slurry for improving the edge quality of silicon wafers according to claim 1, characterized in that, The organic base pH adjuster is at least one of tetramethylammonium hydroxide and choline.

6. The polishing slurry for improving the edge quality of silicon wafers according to claim 1, characterized in that, The composite surfactant is composed of a mixture of nonionic and anionic surfactants.

7. The polishing slurry for improving the edge quality of silicon wafers according to claim 1, characterized in that, The chelating agent is at least one of EDTA and HEDTA, used to complex metal ions and prevent catalytic dislocations at high temperatures.

8. The polishing slurry for improving the edge quality of silicon wafers according to claim 1, characterized in that, The oxidant is hydrogen peroxide or peracetic acid.

9. A polishing process, characterized in that, Includes the following steps: Step S1: Damaged layer removal stage The edge of the silicon wafer is polished using a first polishing wheel with a Shore hardness of A85~95, with a polishing pressure of 0.20~0.30 MPa, and the polishing fluid according to any one of claims 1 to 8 is continuously supplied during the polishing process; Step S2: Contour trimming and stress relief stage The silicon wafer edge is polished using a second polishing wheel with a Shore hardness of A65~75. The polishing pressure is reduced to 0.06~0.12MPa, and the time is 120~180 seconds. During the polishing process, a diluted polishing slurry is continuously supplied with a concentration of 60%~80% of the concentration of the polishing slurry in step S1. Step S3: Surface passivation and metal chelation cleaning stage Continue polishing the edge of the silicon wafer using the second polishing wheel. Reduce the polishing pressure to 0.01~0.03 MPa and the time to 30~60 seconds. During the polishing process, continuously supply further diluted polishing fluid with a concentration of 20%~30% of the polishing fluid concentration in step S1.

10. The polishing process according to claim 9, characterized in that, In step S1, the polishing slurry supply flow rate is 2.0~3.0 L / min, the polishing wheel speed is 1500~2000 rpm, the silicon wafer speed is 60~80 rpm, and the time is 90~150 seconds; In step S2, the polishing slurry supply flow rate is 1.0~1.5 L / min, the polishing wheel speed is 2200~2800 rpm, the silicon wafer speed is 100~150 rpm, and the time is 120~180 seconds; In step S3, the polishing slurry supply flow rate is 0.3~0.8 L / min, the polishing wheel speed is 1500~2000 rpm, the silicon wafer speed is 60~80 rpm, and the time is 30~60 seconds.

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