Energy-time conversion multi-channel pet signal high integration processing method

Abstract

This invention belongs to the field of PET signal processing, and particularly relates to a highly integrated multi-channel PET signal processing method with energy-time conversion. The method includes: conditioning and converting the charge pulses of each channel of a silicon photomultiplier tube to an energy-time pulse with a pulse width proportional to the charge amount; measuring the pulse width using a multi-channel time-to-digital converter to obtain digitized energy time data; packaging the data and transmitting it to a back-end chip via a high-speed serial interface; and using the chip to perform coincidence filtering based on a time window, extracting the energy and time information of coincidence events for reconstruction. This invention converts energy information to time-domain measurement, eliminating the need for traditional peak hold and high-speed analog-to-digital conversion, significantly reducing circuit complexity and power consumption, and increasing single-board integration density. It is suitable for multi-channel PET systems.

Description

Technical Field

[0001] This invention belongs to the field of PET signal processing, and particularly relates to a highly integrated processing method for multi-channel PET signals with energy-time conversion. Background Technology

[0002] Positron emission tomography (PET) reconstructs images by detecting a pair of nearly opposite gamma photons with an energy of 511 keV generated by positron annihilation. Its spatial, energy, and temporal resolutions directly depend on the front-end electronics' ability to accurately measure the arrival time of these two photons at the detector. To achieve high-sensitivity imaging, PET systems typically require the deployment of tens of thousands of detector channels, posing a significant challenge to the integration and power consumption of the front-end electronics. Traditional solutions generally employ a "peak-hold + analog-to-digital converter" architecture, where a peak-hold circuit first captures the amplitude of the scintillation pulse to obtain energy information, and then a high-speed ADC completes the digitization. However, as the number of channels increases dramatically, the shortcomings of this architecture become increasingly prominent: each channel requires an independent peak-hold circuit and a high-speed ADC, resulting in high circuit complexity and enormous power consumption; crosstalk and clock synchronization between multiple channels are difficult to control; and the integration density of a single board is severely limited, making it difficult to overcome the bottleneck of high channel density. Although some existing technologies attempt to reduce power consumption through multiplexing or sharing the ADC, they essentially still rely on accurate sampling in the amplitude domain, failing to fundamentally resolve the contradiction between integration density and power consumption. Therefore, there is an urgent need for a multi-channel PET signal processing method that can completely abandon high-speed sampling in the amplitude domain and measure energy information directly by mapping it to the time domain, thereby achieving ultra-high integration and low power consumption on a single board. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a highly integrated multi-channel PET signal processing method based on energy-time conversion. This method conditions and converts the charge pulses of each channel of a silicon photomultiplier tube (SMT) to an energy-time pulse with a pulse width proportional to the charge amount. A multi-channel time-to-digital converter (TD-SCDMA) is used to measure the pulse width, obtaining digitized energy-time data. The data is packaged and transmitted to the back-end chip via a high-speed serial interface. The chip performs coincidence filtering based on a time window, extracting the energy and time information of coincident events for reconstruction. This invention converts energy information to time-domain measurement, eliminating the need for traditional peak hold and high-speed analog-to-digital conversion, significantly reducing circuit complexity and power consumption, and increasing single-board integration density. It is suitable for multi-channel PET systems.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A highly integrated processing method for multi-channel PET signals with energy-time conversion includes:

[0006] The configured sensor system acquires the charge pulse signals generated by each channel of the silicon photomultiplier tube in response to gamma photons arriving at the scintillation crystal. The charge pulse signals are conditioned by a front-end passive filter network and an impedance matching circuit, and the conditioned charge pulses are output.

[0007] The conditioned charge pulse is input into the charge-time converter, and the conditioned charge pulse is used to charge the internal integrating capacitor. When the voltage of the integrating capacitor reaches a preset reference threshold, the comparator is triggered to flip, generating an energy-time pulse signal whose pulse width is proportional to the total amount of input charge.

[0008] The energy-time pulse signal output from each channel is measured by a multi-channel time-to-digital converter, and the pulse width or time interval of the energy-time pulse signal is digitized using a time reference to obtain digital time data characterizing gamma photon energy information.

[0009] The digitized time data, along with the corresponding channel identifier and event timestamp, is encapsulated into a time data packet. The time data packets from multiple channels are then aggregated and transmitted to the back-end integrated circuit via a high-speed serial interface.

[0010] The back-end integrated circuit performs a matching judgment on the timestamps carried in the time data packets of different channels according to a preset standard time discrimination window, identifies two gamma photon event pairs belonging to the same annihilation event, and extracts the corresponding energy information and time information for PET image reconstruction.

[0011] Specifically, the charge pulse signal is conditioned by a front-end passive filter network and an impedance matching circuit to output a conditioned charge pulse, including:

[0012] The leading edge of the charge pulse signal is detected to obtain the rising slope value of the leading edge;

[0013] The rising slope value of the pulse leading edge is compared with a preset slope threshold, and the signal conditioning mode is determined based on the comparison result:

[0014] When the rising slope of the pulse leading edge is greater than or equal to the preset slope threshold, the pulse fidelity mode is entered.

[0015] When the rising slope of the pulse leading edge is less than the preset slope threshold, noise suppression mode is entered.

[0016] In the pulse fidelity mode, the first set of passive component parameters is selected to configure the front-end passive filter network. The first set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network higher than the equivalent bandwidth of the leading edge of the charge pulse signal, so that the amplitude attenuation of the component in the charge pulse signal whose frequency is within the equivalent bandwidth of the leading edge of the pulse is lower than the preset fidelity attenuation threshold after passing through the front-end passive filter network. In addition, the first set of passive component parameters makes the leading edge time jitter of the conditioned charge pulse less than the preset time jitter tolerance.

[0017] Specifically, the charge pulse signal is conditioned by a front-end passive filter network and an impedance matching circuit to output a conditioned charge pulse, and the method further includes:

[0018] In noise suppression mode, the second set of passive component parameters is selected to configure the front-end passive filter network. The second set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network lower than the equivalent bandwidth of the pulse leading edge, and makes the stopband start frequency of the front-end passive filter network lower than the lower limit frequency of the preset dark count noise characteristic frequency band, so that the stopband attenuation provided by the front-end passive filter network for signal components whose frequency is within the preset dark count noise characteristic frequency band is greater than the preset noise suppression threshold.

[0019] Obtain the first output impedance presented at the output terminal of the front-end passive filter network when using the first set of passive component parameters in pulse fidelity mode; or, obtain the second output impedance presented at the output terminal of the front-end passive filter network when using the second set of passive component parameters in noise suppression mode.

[0020] Based on the first or second output impedance, adjust the reactance value of the variable reactance element in the impedance matching circuit so that the input impedance of the impedance matching circuit and the output impedance presented by the front-end passive filter network in the current operating mode satisfy the conjugate matching condition that the real parts are equal and the absolute values ​​of the imaginary parts are equal but opposite in sign. This ensures that the reflection coefficient at the output of the front-end passive filter network is greater than or equal to zero and less than the preset reflection coefficient threshold, resulting in a conditioned charge pulse without pulse ringing.

[0021] Specifically, generating an energy-time pulse signal with a pulse width proportional to the total input charge includes:

[0022] Obtain the peak amplitude of the conditioned charge pulse;

[0023] The peak amplitude is compared with a preset upper limit threshold of the linear interval, and the input capacitance value of the integrating capacitor is determined based on the comparison result, specifically as follows:

[0024] When the peak amplitude is less than or equal to the upper limit threshold of the preset linear interval, the integrating capacitor is configured to a first capacitance value. The integrated capacitor connected with the first capacitance value is charged using the conditioned charge pulse. At the first moment when the integrated voltage across the integrating capacitor rises from the initial level to the preset reference threshold, the comparator is triggered to generate a first flip edge. At the second moment when the conditioned charge pulse is detected to have ended, the comparator is triggered to generate a second flip edge, thereby obtaining an energy-time pulse signal with a pulse width equal to the time interval between the first moment and the second moment.

[0025] Specifically, generating an energy-time pulse signal with a pulse width proportional to the total input charge also includes:

[0026] When the peak amplitude is greater than the upper limit threshold of the preset linear interval, the integrating capacitor is configured with a second capacitance value. The integrated capacitor connected with the second capacitance value is charged using the conditioned charge pulse. At a third moment when the integrated voltage across the integrating capacitor rises to the preset reference threshold, the comparator is triggered to generate the first flip edge. At a fourth moment when the conditioned charge pulse is detected to have ended, the comparator is triggered to generate the second flip edge, resulting in an energy-time pulse signal with a pulse width equal to the time interval between the third and fourth moments. The second capacitance value is greater than the first capacitance value, and... The second capacitor value is configured such that when the conditioned charge pulse has the maximum input charge, the peak value of the integral voltage does not exceed the upper limit of the preset integrator output swing; wherein, the second capacitor value is determined as follows: when the total input charge of the conditioned charge pulse is any measured value within the full preset dynamic range, the absolute value of the deviation between the pulse width measurement value of the energy-time pulse signal corresponding to that measured value and the ideal linear pulse width value is less than the preset pulse width nonlinearity tolerance; the ideal linear pulse width value is a linear interpolation determined by the pulse width reference value corresponding to the minimum input charge and the pulse width full-scale value corresponding to the maximum input charge.

[0027] Specifically, obtaining digital time data characterizing gamma photon energy information includes:

[0028] The energy-time pulse signals output from each channel are respectively connected to the delay chain input of the corresponding channel in the multi-channel time-to-digital converter, so that the energy-time pulse signals propagate step by step along the unit delay unit of the delay chain. The output state of each stage of the delay chain is latched by a global reference clock synchronized with the time base, so that the pulse width of the energy-time pulse signal is quantized in the delay chain to be an integer multiple of the unit delay unit of the delay chain, thereby obtaining coarse count data and fine count data corresponding to the pulse width.

[0029] For the current processing channel in each channel, obtain the fine count data of the current processing channel, extract the phase offset feature value caused by crosstalk between the current processing channel and the adjacent channel in the fine count data, and compare the phase offset feature value with a preset crosstalk tolerance threshold.

[0030] When the phase offset characteristic value is greater than the preset crosstalk tolerance threshold, crosstalk compensation correction is performed on the coarse count data or fine count data of the current processing channel to obtain corrected digitized time data, and the corrected digitized time data is output as the digitized time data.

[0031] Specifically, obtaining digital time data characterizing gamma photon energy information also includes:

[0032] When the phase offset characteristic value is less than or equal to the preset crosstalk tolerance threshold, the coarse count data and fine count data of the current processing channel are merged and directly output as the digitized time data;

[0033] The delay amount of a unit delay unit in the delay chain is determined by the period of the time reference and the number of stages in the delay chain. The delay amount of the unit delay unit is configured such that the quantization error of the digitized time data is less than a preset time quantization error tolerance in the full dynamic range of the energy-time pulse signal from the minimum pulse width to the maximum pulse width.

[0034] Specifically, the step of aggregating and transmitting the multi-channel time data packets to the back-end integrated circuit via a high-speed serial interface includes:

[0035] A high-speed serial link is configured for each group of a preset number of channels, and each high-speed serial link is connected to a serial data transmission port. The preset number is determined by the maximum integer number of links obtained by dividing the total number of board-level interconnect pins by the number of pins required for each high-speed serial link.

[0036] When any channel generates the time data packet, the time data packet of the channel is written into the channel buffer queue corresponding to the channel. The depth of the channel buffer queue is configured to be at least greater than the number of time data packets accumulated by the channel under the maximum event rate and the maximum arbitration waiting time.

[0037] According to the preset arbitration strategy, the channel that currently has the right to send is selected among multiple channel buffer queues belonging to the same high-speed serial link. The time data packet is read from the channel buffer queue of the channel, and the time data packet is encapsulated into a serial data frame containing the channel group identifier and the time data packet during reading.

[0038] Specifically, the method of aggregating and transmitting the multi-channel time data packets to the back-end integrated circuit via a high-speed serial interface further includes:

[0039] The serial data frame is sent to the back-end integrated circuit through the high-speed serial link, and an idle data code is sent within the frame interval of the serial data frame to maintain the synchronization state of the high-speed serial link.

[0040] On the receiving side of the back-end integrated circuit, the time data packet is distributed to the corresponding conformity selection channel processing unit according to the channel group identifier and the channel identifier carried in the time data packet.

[0041] Specifically, according to a preset arbitration strategy, the channel currently granted the right to transmit is selected from multiple channel buffer queues belonging to the same high-speed serial link, including:

[0042] Using the channel group identifier corresponding to the channel group as the arbitration domain, each channel is numbered within the arbitration domain to obtain the channel sequence number of each channel within the arbitration domain.

[0043] At the beginning of each arbitration cycle, starting from the next channel number of the service channel of the previous arbitration cycle, the empty / full status of the channel buffer queue of each channel is queried in the order of the channel number cyclically increasing.

[0044] When the first non-empty state of the channel buffer queue is found, the channel is determined as the channel that currently has the right to send. After the time data packet of the channel is read, the query start position is updated to the next channel number of the channel, and the query for the next arbitration cycle begins.

[0045] Specifically, after the time data packet of the channel is read, the process further includes:

[0046] When the channel buffer queues of all channels within the arbitration domain are found to be empty for K consecutive arbitration cycles, the arbitration domain is determined to have entered a link idle state. Arbitration operations for the arbitration domain are suspended, and the idle data code is continuously sent to the high-speed serial link until the channel buffer queue of any channel is detected to be non-empty. Then, the arbitration operations for the arbitration domain are resumed, and the transmission of the serial data frame is restarted.

[0047] Specifically, during reading, the time data packet is encapsulated into a serial data frame containing a channel group identifier and the time data packet, including:

[0048] After reading the time data packet, a frame start delimiter and a frame header field containing the channel group identifier are added to the beginning of the time data packet, and a cyclic redundancy check field and a frame end delimiter are added to the end of the time data packet to obtain the serial data frame.

[0049] Compared with the prior art, the beneficial effects of the present invention are:

[0050] This invention directly converts detector charge pulses into time signals with pulse width proportional to energy through charge-time conversion. A multi-channel time-to-digital converter performs high-precision pulse width measurement under a unified time reference, thus digitizing energy information without relying on high-speed analog-to-digital converters and peak-hold circuits. This significantly reduces the complexity and power consumption of single-channel analog circuits, making it possible to integrate thousands of channels on a single processing board or chip. Secondly, energy information and event timestamps are acquired synchronously in the same all-digital measurement link, fundamentally avoiding complex clock synchronization and analog crosstalk between multiple channels. Channel identifiers, timestamps, and energy-time data are encapsulated into a unified time data packet and transmitted via a high-speed serial interface, significantly reducing board-level interconnect overhead and further improving system integration density and scalability. The back-end integrated circuit only needs to perform coincidence discrimination on the timestamps according to a standard time window to directly extract the energy and time information of matching photon pairs for image reconstruction. The entire acquisition and processing process is simple and efficient, achieving low power consumption, high integration, and easy expansion of multi-channel PET front-end electronics while ensuring high-sensitivity imaging. Attached Figure Description

[0051] Figure 1 This is a flowchart of a multi-channel PET signal high-integration processing method for energy-time conversion according to the present invention;

[0052] Figure 2 This is a flowchart illustrating the process of obtaining the conditioned charge pulses according to the present invention. Detailed Implementation

[0053] Example 1

[0054] Please see Figure 1 The present invention provides an embodiment of a highly integrated processing method for multi-channel PET signals with energy-time conversion, comprising the following steps:

[0055] S1. The configured sensor system acquires the charge pulse signals generated by each channel of the silicon photomultiplier tube in response to the arrival of gamma photons on the scintillation crystal. The charge pulse signals are conditioned by a front-end passive filter network and an impedance matching circuit to suppress high-frequency noise and signal reflection, and the conditioned charge pulses are output. It should be further noted that the sensor system of this embodiment is specifically configured by those skilled in the art according to the needs of the collected data, and will not be described in detail here.

[0056] S2. The conditioned charge pulse is input into the charge-time converter, and the conditioned charge pulse is used to charge the internal integrating capacitor. When the voltage of the integrating capacitor reaches the preset reference threshold, the comparator is triggered to flip, generating an energy-time pulse signal with a pulse width proportional to the total input charge, thereby realizing the transformation of charge quantity into time quantity.

[0057] S3. The energy-time pulse signal output from each channel is measured by a multi-channel time-to-digital converter. The pulse width or time interval of the energy-time pulse signal is digitized using a high-precision time reference to obtain digital time data characterizing the energy information of gamma photons.

[0058] S4. Encapsulate the digitized time data with the corresponding channel identifier and event timestamp into a time data packet, and transmit the time data packets from multiple channels to the back-end integrated circuit through a high-speed serial interface;

[0059] S5. The back-end integrated circuit performs a matching judgment on the timestamps carried in the time data packets of different channels according to a preset standard time discrimination window, identifies two gamma photon event pairs belonging to the same annihilation event, and extracts the corresponding energy information and time information for PET image reconstruction.

[0060] In this embodiment, the core operation of this step is to use the back-end integrated circuit as a processing platform to perform matching of the event timestamps carried in the time data packets transmitted from each channel across the entire channel range. A preset standard time discrimination window is used as the judgment boundary for the same annihilation event. Two 511keV gamma photon event pairs belonging to the same positron annihilation are selected from a large number of candidate events. The energy digitization time data and precise arrival timestamps corresponding to the successfully matched events are extracted and output as the original projection data input for the PET image reconstruction algorithm. Its physical principle is based on the coincidence detection principle of positron emission tomography: two 511keV gamma photons generated by a positron annihilation fly away from the annihilation position in opposite directions. Under ideal no-scattering conditions, the time difference between the two photons arriving at the two relative channels on the detector ring surrounding the human body is determined only by the speed of light and the path difference from the annihilation position to the two detectors. Its absolute value does not exceed the maximum flight time difference corresponding to the diameter of the detector ring. Therefore, if the difference between the event timestamps recorded by two different channels falls within the preset standard time discrimination window, then these two events are physically very likely to originate from the same annihilation, forming a pair of coincidence events. Conversely, if the difference between the event timestamp recorded by one channel and the event timestamps of all other channels exceeds the discrimination window, then the event is judged as a single-photon background event and is discarded. The preset standard time discrimination window is set based on: the maximum time difference caused by the uncertainty of the positron annihilation position, the pulse arrival time jitter caused by the decay time of the scintillation crystal, the time measurement errors introduced by various front-end electronics components, and the total time broadening value after the system target coincidence time resolution is synthesized by the square root. It is determined by those skilled in the art based on the measured or simulated time performance parameters of the above-mentioned components, and is usually set to cover the total time broadening value. The interval corresponding to 3 times the standard deviation is used to ensure that the capture efficiency of true coincidence event pairs is not less than 99.7%. As a specific example, in this embodiment, the detector ring diameter is 80 cm, corresponding to a maximum path difference light speed flight time of approximately 2.7 nanoseconds; the pulse time jitter caused by the light emission decay time of the scintillation crystal LYSO of approximately 40 nanoseconds is controlled to within approximately 0.5 nanoseconds after front-end signal conditioning; the total time error introduced by each component of the front-end electronics is measured to be approximately 0.3 nanosecond root mean square value; the system target coincidence time resolution is set to 1 nanosecond; the total time broadening after the above time broadening components are synthesized by the root of square is approximately 3 nanoseconds, and ±3 times the standard deviation, i.e., ±9 nanoseconds, is taken as the preset standard time discrimination window, with a total window width of 18 nanoseconds.

[0061] Further explanation is needed; please refer to [link / reference]. Figure 2 This embodiment uses a front-end passive filter network and impedance matching circuit to perform signal conditioning on the charge pulse signal, including:

[0062] S101. Detect the leading edge of the charge pulse signal and obtain the rising slope value of the leading edge of the pulse.

[0063] In this embodiment, the charge pulse output by the silicon photomultiplier tube in response to a gamma photon event directly reflects the temporal concentration of the initial photons arriving in the scintillation pulse in terms of its rising rate. When dark counting noise is superimposed on the signal, it changes the slope characteristics of the pulse leading edge, making the originally steep signal edge more gradual. Therefore, by extracting the rising slope value of the pulse leading edge, the degree of dark counting noise contamination of the current pulse can be reliably reflected, providing a quantitative basis for subsequent adaptive selection of filtering strategies. As a specific example, in this embodiment, a differential amplifier with a bandwidth of 500MHz is used to perform real-time differentiation processing on the silicon photomultiplier tube charge pulse buffered by the preamplifier. The voltage amplitude output by the differential amplifier is proportional to the instantaneous rate of change of the input pulse, and its gain constant is calibrated to 1 millivolt per volt per second. Subsequently, a high-speed peak sample-and-hold circuit captures the maximum value of the differentiated signal during the pulse leading edge, obtaining a peak voltage value. Dividing the peak voltage value by the gain constant yields the pulse leading edge rising slope value in volts per second. Furthermore, in this embodiment, the pA-level weak current pulse output by the silicon photomultiplier tube needs to undergo a current-to-voltage linear conversion first through a low-noise transimpedance amplifier. The core parameters of this transimpedance amplifier are configured as follows: bandwidth not less than 500MHz, transimpedance gain 10kΩ, and input reference noise current not greater than 10pA / Ω. The conversion gain is calibrated to 10mV / pC. The voltage pulse, after being buffered by the transimpedance amplifier, is then input to the subsequent differential amplifier circuit to achieve accurate detection of the pulse leading edge slope.

[0064] S102. Compare the rising slope value of the pulse leading edge with a preset slope threshold, and determine the signal conditioning mode based on the comparison result:

[0065] In this embodiment, a preset slope threshold is used as a discrimination threshold to divide the rising slope value of the pulse leading edge into two intervals, corresponding to two states where the pulse is not significantly affected by dark counting noise and is significantly affected, respectively. When the slope value is higher than the threshold, the high-frequency components of the pulse leading edge are well preserved, and the system should prioritize ensuring the accurate transmission of the pulse arrival time; when the slope value is lower than the threshold, the pulse leading edge has been broadened by noise, and the system should prioritize filtering out noise to protect the accuracy of subsequent energy integration. This preset slope threshold is set by those skilled in the art based on the dark counting rate of the silicon photomultiplier tube used, the luminous decay time of the scintillation crystal, and the system's budget for time resolution. As a specific example, in this embodiment, a detector unit using an LYSO scintillation crystal coupled with a 3mm×3mm silicon photomultiplier tube is used, and the measured dark counting rate at room temperature is approximately 100kHz / mm. 2Based on the typical rise time distribution range of 1.5ns to 3ns for the pulse front, the preset slope threshold is calibrated to 1×10. 8 V / s ensures that there is sufficient discrimination margin between the leading edge slope of a normal flicker pulse and this threshold.

[0066] In this embodiment, the preset slope threshold is scientifically determined through a three-level calibration method. First, the leading edge slope distribution of the noise pulse output by the silicon photomultiplier tube under dark counting conditions is collected, and the 95th percentile of the dark counting pulse leading edge slope is taken as the noise floor threshold. Second, the leading edge slope distribution of the effective signal pulse corresponding to gamma photons from 250keV to 511keV is collected, and the 5th percentile of the effective signal pulse leading edge slope is taken as the effective signal lower limit. Finally, the preset slope threshold is set as the midpoint between the noise floor threshold and the effective signal lower limit, ensuring that the discrimination margin between the effective signal and dark counting noise is not less than 3 times the standard deviation. In this embodiment, the calibrated 1×10 8 The V / s threshold corresponds to an upper limit of the dark counting noise pulse slope of 5 × 10⁻⁶. 7 V / s, the lower limit of the effective signal pulse slope is 1.5 × 10 8 V / s, which fully meets the discrimination margin requirements.

[0067] S103. When the rising slope of the pulse leading edge is greater than or equal to the preset slope threshold, the pulse fidelity mode is entered. This step signifies that the signal conditioning link has entered a working mode prioritizing time transmission fidelity. In this mode, the subsequent front-end passive filter network will adopt parameter configurations focused on broadband transmission, aiming to maximize the retention of high-frequency timing spectral components carried by the pulse leading edge, thereby constraining the leading edge time fluctuation of the final conditioned charge pulse within the tolerance budget allocated to this stage by the system.

[0068] S104. When the rising slope of the pulse leading edge is less than the preset slope threshold, noise suppression mode is entered. This step signifies that the signal conditioning link enters a working mode prioritizing noise suppression. In this mode, the pulse leading edge is significantly broadened by dark counting noise, and its high-frequency signal-to-noise ratio is severely degraded, making it meaningless to continue pursuing leading edge fidelity. Therefore, the subsequent front-end passive filter network will adopt parameter configurations that focus on out-of-band noise attenuation, aiming to reduce the residual power of dark counting noise on the conditioned charge pulse to a level that will not cause nonlinear errors in the charge-time conversion.

[0069] S105. In the pulse fidelity mode, the first set of passive component parameters is selected to configure the front-end passive filter network. The first set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network higher than the equivalent bandwidth of the pulse leading edge of the charge pulse signal, so that the amplitude attenuation of the component in the charge pulse signal whose frequency is within the equivalent bandwidth of the pulse leading edge after passing through the front-end passive filter network is lower than the preset fidelity attenuation threshold. The first set of passive component parameters makes the leading edge time jitter of the conditioned charge pulse less than the preset time jitter tolerance.

[0070] In this embodiment, the equivalent bandwidth of the pulse leading edge refers to the frequency range occupied by the main high-frequency components of the charge pulse signal during the pulse leading edge phase. This bandwidth is estimated and determined by the reciprocal of the rise time of the pulse leading edge. Specifically, the pulse leading edge signal after differential processing by a 500MHz bandwidth differential amplifier is subjected to high-speed peak sampling and holding. The maximum value of the differential signal during the pulse leading edge is captured as the rise slope value of the pulse leading edge. Then, the rise time of the pulse leading edge is extracted according to the correspondence between the slope value and the pulse amplitude. The reciprocal of the rise time is used as the nominal value of the equivalent bandwidth of the pulse leading edge, which characterizes the direct mapping relationship of the steepness of the pulse leading edge in the frequency domain. The equivalent bandwidth of the pulse leading edge serves as a reference for setting the -3dB cutoff frequency of the front-end passive filter network in pulse fidelity mode. When the parameters of the first set of passive components configure the -3dB cutoff frequency of the filter network to a value higher than this bandwidth, the amplitude attenuation of the signal components within the equivalent bandwidth of the pulse leading edge after passing through the filter network can be controlled to be below the preset fidelity attenuation threshold of 0.5dB. Furthermore, the timing jitter of the conditioning charge pulse's leading edge can be constrained to be less than the preset timing jitter tolerance of 50ps, thereby controlling the timing jitter introduced in this step to a level compatible with the system's 1 nanosecond time resolution. As a specific example, in this embodiment, the equivalent bandwidth of the pulse leading edge is estimated to be approximately 100MHz to 150MHz using the reciprocal of the pulse leading edge rise time. The parameters of the first set of passive components configure the -3dB cutoff frequency of the front-end passive filter network to 180MHz. Under this frequency setting, the measured amplitude attenuation within the 100MHz to 150MHz band is 0.4dB, and the measured timing jitter is 35ps, meeting the system design specifications. In this embodiment, the preset fidelity attenuation threshold of 0.5dB is set based on the system's strict constraint on the amplitude error introduced by the signal conditioning stage in the energy measurement link. In pulse fidelity mode, the front-end filter network essentially acts as a low-pass filter in the signal path. If there is excessive attenuation within its passband, it will directly cause the linear relationship between the pulse width and the input charge after charge-time conversion to be compressed at the low-energy end, thereby degrading the energy resolution. In this embodiment, after determining the equivalent bandwidth of the pulse leading edge through a three-level calibration method, the cutoff frequency of the filter network is configured to a value higher than this bandwidth. By selecting passive components with high quality factors and low equivalent series resistance, the insertion loss in the passband is controlled to an extremely low level. The preset fidelity attenuation threshold is set to 0.5dB, ensuring that the amplitude error of the spectral component after the pulse leading edge passes is less than 0.5dB. The impact of this error on the energy digitization data is allocated within the acceptable margin of the system's target energy resolution, thereby ensuring the accuracy of energy information transmission.

[0071] In this embodiment, the setting is based on the step-by-step error budget allocation from the system's top-level coincidence time resolution index to each processing stage. The embodiment specifies a target coincidence time resolution of 1 nanosecond, which needs to be decomposed into multiple components, including the scintillation crystal decay time jitter and time measurement errors in various front-end electronics stages. As a crucial component of the front-end electronics, the signal conditioning stage introduces pulse front-end arrival time jitter, which directly contributes to the degradation of the final coincidence time resolution. Therefore, based on the system's error tolerance allocation requirements for each stage, a strict upper limit for time jitter is set for the signal conditioning stage, namely 50 ps. This value is selected based on the principle of not significantly increasing the total system time jitter, ensuring that the additional time error introduced by this stage accounts for a negligible proportion of the total index, thus reserving sufficient design margin for subsequent charge-time conversion and time digitization. In this embodiment, to achieve this 50 ps tolerance requirement, the -3dB cutoff frequency of the front-end passive filter network in pulse fidelity mode is configured to 180 MHz, far exceeding the upper limit frequency of the equivalent bandwidth of the pulse front. This design reduces the group delay variation of the filter network within the pulse leading-edge spectrum to an extremely low level, effectively suppressing the leading-edge arrival time jitter caused by minute changes in signal amplitude or shape. Experimental results show that, under this configuration, the leading-edge time jitter of the conditioned charge pulse is only 35 ps, lower than the preset 50 ps tolerance. This ensures that the contribution of the signal conditioning stage to the system's 1 nanosecond target time resolution is strictly constrained within the allocated budget, providing a reliable guarantee for high-precision timing across the entire link.

[0072] In this embodiment, the rise time of the pulse leading edge is uniformly defined as the time interval corresponding to the pulse amplitude rising from 10% to 90%. The equivalent bandwidth of the pulse leading edge is estimated by the formula "equivalent bandwidth ≈ 0.35 / rise time". The equivalent bandwidth corresponding to a rise time of 1.5ns is approximately 233MHz, and the equivalent bandwidth corresponding to a rise time of 3ns is approximately 117MHz. Thus, the equivalent bandwidth of the pulse leading edge in this embodiment is determined to be in the range of 100MHz to 150MHz, providing a precise benchmark reference for configuring the cutoff frequency of the front-end passive filter network.

[0073] In this embodiment, the parameters of the first group of passive components include the capacitance value of the tuning capacitor constituting the front-end passive filter network, the inductance value of the tuning inductor, the equivalent series resistance value of the tuning capacitor, the equivalent series resistance value of the tuning inductor, and the filter network quality factor determined by the tuning capacitor and the tuning inductor. The capacitance and inductance of the tuning capacitor and inductor together determine the -3dB cutoff frequency of the front-end passive filter network in pulse fidelity mode. This ensures that the cutoff frequency is higher than the equivalent bandwidth of the leading edge of the charge pulse signal, so that the amplitude attenuation of the signal component within the equivalent bandwidth of the leading edge after passing through the filter network is lower than a preset fidelity attenuation threshold. The equivalent series resistance of the tuning capacitor and inductor affects the insertion loss in the passband of the filter network, controlling the actual amplitude attenuation of the component in the charge pulse signal whose frequency is within the equivalent bandwidth of the leading edge after passing through the filter network. This attenuation is set by those skilled in the art based on the system's allocation budget for the pulse leading edge time jitter tolerance. The quality factor of the filter network is determined by the capacitance, inductance, and equivalent series resistance values ​​mentioned above. Its value affects the amplitude-frequency response shape and group delay rate of the filter network near the cutoff frequency, thereby determining the magnitude of the conditioned charge pulse leading edge time jitter. It must be ensured that this jitter is less than a preset time jitter tolerance. As a specific example, in this embodiment, the parameters of the first group of passive components are specifically set as follows: the capacitance of the first tuning capacitor is 18pF, the equivalent series resistance is less than 0.1Ω in the 100MHz to 150MHz frequency band, and the temperature coefficient is C0G; the inductance of the first tuning inductor is 47nH, it is wound with silver-plated copper wire with a wire diameter of 0.5mm in an air-core form, and the equivalent series resistance is less than 0.3Ω in the same frequency band; the measured -3dB cutoff frequency of the LC low-pass filter network composed of the above parameters is 173MHz, the quality factor is about 80, the measured insertion loss in the equivalent bandwidth of the pulse leading edge in the 100MHz to 150MHz range is 0.3dB, which is lower than the preset fidelity attenuation threshold of 0.5dB, and the resulting conditioned charge pulse leading edge time jitter is measured to be 35ps, which is less than the preset time jitter tolerance of 50ps.

[0074] In this embodiment, the steepness of the pulse leading edge is determined by the amplitude and phase integrity of the high-frequency components in its spectrum. The front-end passive filter network is essentially a low-pass filter. If its -3dB cutoff frequency is set too low, it will attenuate the high-frequency components within the equivalent bandwidth of the pulse leading edge and introduce a group delay that varies with frequency, causing the pulse leading edge arrival time to fluctuate with slight changes in signal amplitude or shape. Therefore, setting the -3dB cutoff frequency higher than the equivalent bandwidth of the pulse leading edge ensures that the frequency components within this bandwidth are essentially unaffected by attenuation and phase distortion, thereby controlling the time fluctuation introduced by this step to a level compatible with the system's time resolution. As a specific example, in this embodiment, the equivalent bandwidth of the leading edge of the charge pulse signal is estimated to be approximately 100MHz to 150MHz by the reciprocal of the rise time of the leading edge. The parameters of the first set of passive components are configured such that the -3dB cutoff frequency of the front-end passive filter network is set to 180MHz. Under this frequency setting, the measured amplitude attenuation in the 100MHz to 150MHz band is 0.4dB, which is lower than the preset fidelity attenuation threshold of 0.5dB. The resulting pulse leading edge time jitter is measured to be 35ps, which is less than the preset time jitter tolerance of 50ps.

[0075] It should be further explained that, in this embodiment, the first set of passive component parameters is selected to configure the front-end passive filter network, including:

[0076] S1051. A first low-pass filter network topology is formed by using a first tuning capacitor and a first tuning inductor. By adjusting the capacitance value of the first tuning capacitor and the inductance value of the first tuning inductor, the -3dB cutoff frequency of the first low-pass filter network topology is higher than the lower limit frequency of the equivalent bandwidth of the pulse leading edge.

[0077] In this embodiment, the -3dB cutoff frequency of the LC low-pass filter network is determined by the parameters of the resonant components. By precisely selecting tuning capacitors and tuning inductors with high Q values ​​and low temperature coefficients, the cutoff frequency can be set stably and accurately, while the parasitic effects of the components themselves are controlled within a small range, avoiding the introduction of additional uncertain frequency responses. As a specific example, in this embodiment, the lower limit frequency of the equivalent bandwidth of the pulse leading edge is measured to be 100MHz. To meet the requirement that the cutoff frequency is higher than this lower limit frequency, the capacitance value of the first tuning capacitor is selected as 18pF, and the inductance value of the first tuning inductor is selected as 47nH. The measured -3dB cutoff frequency of this parameter combination is 173MHz, leaving sufficient margin for a lower limit frequency requirement higher than 100MHz. Furthermore, a ceramic capacitor with a temperature coefficient of C0G is selected for the capacitor, and an air-core wire-wound inductor is selected to reduce the influence of distributed capacitance.

[0078] S1052. Control the equivalent series impedance of the first low-pass filter network topology within the equivalent bandwidth of the pulse leading edge, so that the amplitude attenuation of the component of the charge pulse signal whose frequency is within the equivalent bandwidth of the pulse leading edge after passing through the first low-pass filter network topology is lower than the preset fidelity attenuation threshold.

[0079] In this embodiment, the insertion loss of the low-pass filter network in the passband is mainly determined by the equivalent series resistance and dielectric loss of the components. The smaller the equivalent series impedance, the lower the power loss of the signal in the passband. By selecting inductors and capacitors with low equivalent series resistance and optimizing the printed circuit board layout to reduce parasitic resistance, the passband attenuation can be controlled to an extremely low level. As a specific example, in this embodiment, the first tuning inductor is wound with silver-plated copper wire with a wire diameter of 0.5mm. The measured equivalent series resistance is less than 0.3Ω in the equivalent bandwidth of the 100MHz to 150MHz pulse leading edge, and the equivalent series resistance of the first tuning capacitor is less than 0.1Ω in this frequency band. The insertion loss of the first low-pass filter network topology formed by the two is measured to be 0.3dB in this frequency band, which is lower than the preset fidelity attenuation threshold of 0.5dB.

[0080] S106. In noise suppression mode, the second set of passive component parameters is selected to configure the front-end passive filter network. The second set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network lower than the equivalent bandwidth of the pulse leading edge, and makes the stopband start frequency of the front-end passive filter network lower than the lower limit frequency of the preset dark count noise characteristic frequency band, so that the stopband attenuation provided by the front-end passive filter network for signal components whose frequency is within the preset dark count noise characteristic frequency band is greater than the preset noise suppression threshold.

[0081] In this embodiment, the second set of passive component parameters includes the capacitance value of the tuning capacitor constituting the front-end passive filter network, the inductance value of the tuning inductor, the equivalent series resistance value of the tuning capacitor, the equivalent series resistance value of the tuning inductor, the filter network order determined by the tuning capacitor and the tuning inductor, and the stopband attenuation slope corresponding to the order. The capacitance value of the tuning capacitor and the inductance value of the tuning inductor together determine the -3dB cutoff frequency of the front-end passive filter network in noise suppression mode. This ensures that the cutoff frequency is lower than the equivalent bandwidth of the leading edge of the charge pulse signal and that the stopband start frequency of the filter network is lower than the lower limit frequency of the preset dark count noise characteristic frequency band, thus ensuring that the preset dark count noise characteristic frequency band falls completely within the stopband region of the filter network. The equivalent series resistance values ​​of the tuning capacitor and tuning inductor affect the minimum attenuation within the stopband and must ensure that the stopband attenuation still meets the design requirements under the influence of component parasitic parameters. The order of the filter network directly determines the stopband attenuation slope. The higher the order, the faster the stopband attenuation increases with frequency, and a greater attenuation depth can be obtained with the same frequency offset. This order is determined by those skilled in the art based on the difference between the preset noise suppression threshold and the attenuation of a single-order network. As a specific example, in this embodiment, the parameters of the second group of passive components are specifically set as follows: the capacitance of the second tuning capacitor is 390pF, and it is a ceramic capacitor with a temperature coefficient of C0G; the inductance of the second tuning inductor is 680nH, and it is wound with 0.5mm diameter silver-plated copper wire in an air-core form; the measured -3dB cutoff frequency of the single-order LC low-pass filter network topology composed of the above capacitance and inductance values ​​is 9.8MHz, and the stopband start frequency is approximately 12MHz; the order of the filter network is set to third order, that is, it is composed of three cascaded single-order LC filter sections with the same parameters, and its stopband attenuation slope is approximately 60dB per decade; at the lower limit frequency of the preset dark count noise characteristic band of 40MHz, the measured stopband attenuation is 26dB, which is greater than the preset noise suppression threshold of 20dB, thus meeting the system's design requirements for dark count noise suppression. In this embodiment, the lower limit frequency of the preset dark count noise characteristic band is set based on the measured calibration results of the dark count noise spectrum characteristics of the silicon photomultiplier tube. The embodiment explicitly states that, through spectral analysis of dark noise, it was determined that the spectral energy of dark counting noise is mainly concentrated in a specific frequency band, and the lower limit frequency of this band is the starting boundary of the preset dark counting noise characteristic frequency band. Its physical significance lies in the fact that the noise pulse formed by dark carriers generated by thermal excitation and other factors under no-light conditions in a silicon photomultiplier tube does not cover an infinite bandwidth, but rather possesses a characteristic frequency band with significant energy contribution. By extracting the lower limit frequency of this characteristic frequency band, the embodiment provides a precise frequency domain coordinate reference for setting the stopband starting frequency of the front-end passive filter network in noise suppression mode.When the stopband start frequency of the filter network is configured to be lower than the lower limit frequency, it can be ensured that the entire dark count noise characteristic frequency band falls completely within the effective attenuation region of the stopband of the filter network. This achieves full-coverage suppression of the main energy components of dark count noise in the frequency domain, preventing noise from falling into the filter passband and directly interfering with the subsequent charge-time conversion integration process.

[0082] In this embodiment, the preset noise suppression threshold of 20dB is set based on the system's upper tolerance limit for the error introduced by the residual power of dark count noise in the energy measurement link. In noise suppression mode, although dark count noise is attenuated by the filtering network, the residual noise power is still superimposed on the conditioned charge pulse of the effective signal, causing random fluctuations in the pulse width after charge-time conversion, thus degrading the energy resolution. This embodiment, by setting the preset noise suppression threshold to 20dB, forces the filtering network to provide a stopband attenuation greater than this threshold for the signal components within the characteristic frequency band of dark count noise, thereby suppressing the noise interference power to less than one percent of its original level. This value is determined in conjunction with the system's target energy resolution and the minimum signal-to-noise ratio requirement for this stage. In this embodiment, since the preset noise suppression threshold requirement is high and the frequency offset between the lower limit of the dark count noise characteristic frequency band and the cutoff frequency of the filter network is less than one octave, the attenuation provided by the single-order network cannot meet the 20dB requirement. Therefore, this embodiment further sets the order of the filter network to the third order, so that the stopband attenuation slope is increased to 60dB per octave, thereby achieving an attenuation depth of more than 20dB at the required frequency offset, ensuring that the noise suppression effect meets the system design specifications, and protecting the linearity of the energy-time conversion from noise interference.

[0083] In this embodiment, under noise suppression mode, the leading edge of the signal pulse has lost its original high-frequency timing spectral components due to the superposition of dark counting noise. At this point, retaining the signal component within the equivalent bandwidth of the pulse leading edge contributes very little to improving time resolution; instead, it introduces the accompanying broadband dark counting noise into the subsequent charge-to-time converter. Therefore, by reducing the -3dB cutoff frequency of the filter network below the equivalent bandwidth of the pulse leading edge, the filter network enters the stopband region before the characteristic frequency band of the dark counting noise. The attenuation characteristics of the stopband effectively suppress the interference power within this noise frequency band, thereby protecting the integration process of the energy-to-time conversion from noise interference. As a specific example, in this embodiment, the measured upper limit frequency of the equivalent bandwidth of the pulse leading edge is 150MHz. The preset dark count noise characteristic frequency band is determined to be 5MHz to 40MHz by dark noise spectrum analysis. The parameters of the second group of passive components are configured as capacitor 390pF and inductor 680nH, so that the -3dB cutoff frequency of the front-end passive filter network is 9.8MHz and the stopband start frequency is about 12MHz, which is lower than the lower limit frequency of the preset dark count noise characteristic frequency band of 40MHz. The measured stopband attenuation provided to the noise signal component at 40MHz is 26dB, which is greater than the preset noise suppression threshold of 20dB.

[0084] It should be further explained that in this embodiment, the front-end passive filter network is configured with the second set of passive component parameters, including:

[0085] S1061. A second low-pass filter network topology is constructed using a second tuning capacitor and a second tuning inductor. By adjusting the capacitance value of the second tuning capacitor and the inductance value of the second tuning inductor, the -3dB cutoff frequency of the second low-pass filter network topology is lower than the upper limit frequency of the equivalent bandwidth of the pulse leading edge, and the stopband start frequency of the second low-pass filter network topology is lower than the lower limit frequency of the preset dark count noise characteristic frequency band.

[0086] In this embodiment, the same LC low-pass topology as the pulse fidelity mode is adopted. By increasing the capacitance and inductance values, the resonant frequency of the filter network is reduced, thereby shifting the cutoff frequency and stopband start frequency downwards as a whole, causing the target noise frequency band to fall deep into the stopband. As a specific example, in this embodiment, the upper limit frequency of the equivalent bandwidth of the pulse leading edge is 150MHz. To ensure that the cutoff frequency is significantly lower than this value, the capacitance value of the second tuning capacitor is selected as 390pF, and the inductance value of the second tuning inductor is selected as 680nH. The measured -3dB cutoff frequency is 9.8MHz, and its stopband start frequency is approximately 12MHz, which is significantly lower than the lower limit frequency of the preset dark count noise characteristic band of 40MHz, ensuring that the noise in this band is effectively attenuated.

[0087] S1062. Set the order of the second low-pass filter network topology so that the stopband attenuation provided by the second low-pass filter network topology for signal components whose frequency is within the preset dark count noise characteristic frequency band is greater than the preset noise suppression threshold.

[0088] In this embodiment, the stopband attenuation slope of a single-order LC low-pass filter network is approximately 20 dB per decade. When the preset noise suppression threshold is high and the dark count noise characteristic frequency band is close to the cutoff frequency, the single-order network may not provide sufficient attenuation. By cascading multiple LC filters to form a higher-order filter network, the stopband attenuation slope increases exponentially with the order, achieving a greater attenuation depth for the same frequency offset. As a specific example, in this embodiment, since the preset noise suppression threshold is 20 dB, and the lower limit of the dark count noise characteristic frequency band (40 MHz) is less than one decade from the 9.8 MHz cutoff frequency, the attenuation of the single-order network is only about 16 dB, which does not meet the requirements. Therefore, the order of the second low-pass filter network topology is set to third order, i.e., it consists of three cascaded LC filter sections. Its stopband attenuation slope is approximately 60 dB per decade, and the measured stopband attenuation at 40 MHz reaches 26 dB, which is greater than the preset noise suppression threshold of 20 dB, meeting the design requirements.

[0089] S107. Obtain the first output impedance presented at the output terminal of the front-end passive filter network when using the first set of passive component parameters in pulse fidelity mode; or, obtain the second output impedance presented at the output terminal of the front-end passive filter network when using the second set of passive component parameters in noise suppression mode.

[0090] In this embodiment, the output impedance of the front-end passive filter network is not a constant value, but a complex impedance that varies with the parameters of the connected passive components and the operating frequency. The real and imaginary parts of this output impedance are necessary prerequisites for achieving accurate conjugate matching in the subsequent impedance matching circuit. In a practical system, this impedance can be obtained through offline measurement or online calculation. As a specific example, in this embodiment, a vector network analyzer is used to measure the single-port S-parameters of the front-end passive filter network under two sets of component parameter configurations during the system calibration phase. The first output impedance at the equivalent bandwidth center frequency of 125MHz at the pulse leading edge is (50-j10)Ω, and the second output impedance at the upper limit frequency of the dark counting noise characteristic band of 40MHz is (68+j25)Ω. These two sets of complex impedance values ​​are stored as calibration data in the lookup table of the back-end processor for use by the impedance matching control logic. In the description of this embodiment, "j" is the imaginary unit, used in electronic engineering to represent the imaginary part of the complex impedance, where "-j10Ω" represents a capacitive reactance component of 10 ohms.

[0091] S108. Adjust the reactance value of the variable reactance element in the impedance matching circuit according to the first output impedance or the second output impedance, so that the input impedance of the impedance matching circuit and the output impedance presented by the front-end passive filter network in the current working mode satisfy the conjugate matching condition that the real parts are equal and the absolute values ​​of the imaginary parts are equal and opposite in sign, so that the reflection coefficient of the output terminal of the front-end passive filter network is greater than or equal to zero and less than the preset reflection coefficient threshold, and outputs a conditioned charge pulse without pulse ringing.

[0092] In this embodiment, according to transmission line theory, when the load impedance and source impedance are conjugate, there is no reflected wave on the transmission path, and the energy is completely absorbed by the load. If there is impedance mismatch, some signal energy will be reflected back and forth between the output of the filter network and the input of the subsequent charge-time converter, which manifests as a decaying oscillation superimposed on the pulse waveform in the time domain, i.e., pulse ringing. This ringing directly interferes with the charging process of the charge integrating capacitor, causing nonlinear errors in the energy-time conversion. By dynamically adjusting the variable reactance element, the conjugate matching of the output impedance of the filter network is achieved, eliminating reflection at the source and ensuring the purity of the pulse waveform. As a specific example, in this embodiment, the variable reactance element in the impedance matching circuit is implemented using a voltage-controlled varactor diode, whose bias voltage is provided by a 12-bit digital-to-analog converter, and the capacitance adjustment range is 5pF to 50pF. When the first output impedance is (50–j10)Ω, the control logic of the impedance matching circuit adjusts the bias voltage of the varactor diode to present an inductive reactance of approximately +j10Ω, which cancels out the -j10Ω capacitive reactance of the filter network. At this point, the measured reflection coefficient is 0.02. When the second output impedance is (68+j25)Ω, the control logic adjusts the varactor diode to present a capacitive reactance of approximately -j25Ω, resulting in a measured reflection coefficient of 0.04. In both modes, the reflection coefficient is less than the preset reflection coefficient threshold of 0.05, and no discernible pulse ringing is observed at the output, meeting the system's requirements for the quality of the conditioned charge pulse waveform. In this embodiment, the impedance matching circuit employs a tunable resonant topology with a varactor diode and a fixed inductor in parallel to achieve continuously variable reactance adjustment. The fixed inductor has a value of 22nH and forms a parallel resonant network with the voltage-controlled varactor diode, whose capacitance adjustment range is 5pF to 50pF, with a resonant frequency of approximately 150MHz. When the bias voltage of the varactor diode is adjusted so that its capacitance is less than the resonant point capacitance, the entire network exhibits inductive reactance. When the capacitance is greater than the resonant point capacitance, it exhibits capacitive reactance. This allows for continuously adjustable reactance from -30Ω to +30Ω within the 40MHz to 125MHz operating frequency band, fully meeting the conjugate matching requirements of both operating modes. In this embodiment, the preset reflection coefficient threshold is set based on the system's control standard for pulse waveform quality in the signal conditioning link. In the signal conditioning stage, if there is a mismatch between the output impedance of the front-end passive filter network and the input impedance of the subsequent charge-time converter, the signal energy will undergo repeated reflections along the transmission path, manifesting in the time domain as a decaying oscillation superimposed on the conditioned charge pulse, i.e., pulse ringing. This ringing directly interferes with the charging process of the charge integrating capacitor, causing a non-monotonic change in the integrated voltage, which in turn introduces a nonlinear error in the energy-time conversion. In this embodiment, based on transmission line theory, the preset reflection coefficient threshold is set to 0.05, which corresponds to a voltage standing wave ratio of approximately 1.1, indicating that the reflected power is only 0.25% of the incident power.When the reflection coefficient is suppressed below the threshold, the reflected energy on the transmission path has decayed to a negligible level, and no discernible pulse ringing appears at the output. This ensures the purity of the conditioned charge pulse waveform from the source, ensuring that the charge pulses received by the subsequent charge-time converter strictly correspond to the total input charge.

[0093] This embodiment achieves adaptive switching between pulse fidelity mode and noise suppression mode by detecting the rising slope of the leading edge of the charge pulse and comparing it with a preset slope threshold. When the leading edge of the pulse is steep and less affected by dark counting noise, pulse fidelity mode is entered. The first set of passive component parameters is selected such that the -3dB cutoff frequency of the front-end passive filter network is higher than the equivalent bandwidth of the leading edge of the pulse. This ensures that the amplitude attenuation of the signal components within the equivalent bandwidth of the leading edge after passing through the filter network is lower than the preset fidelity attenuation threshold, and the timing jitter of the leading edge of the conditioned charge pulse is less than the preset timing jitter tolerance. This maximizes the preservation of the high-frequency timing spectral components carried by the leading edge of the pulse, constraining the timing jitter introduced in this step within the system's time resolution budget. When the leading edge of the pulse has been broadened by dark counting noise, noise suppression mode is entered. The filter network's -3dB cutoff frequency is selected such that the equivalent bandwidth of the leading edge of the pulse is lower than the preset lower limit frequency of the dark counting noise characteristic frequency band. The second set of passive component parameters is used, and the order of the filter network is set to make the stopband attenuation in the noise characteristic frequency band greater than the preset noise suppression threshold. This reduces the residual power of dark counting noise to a level that does not interfere with subsequent charge-time conversion, even when the signal-to-noise ratio of the high-frequency components at the pulse leading edge has been severely deteriorated. Based on this, the first or second output impedance presented at the output end of the filter network in two working modes is obtained respectively. The reactance value of the variable reactance element in the impedance matching circuit is adjusted so that the input impedance of the matching circuit and the output impedance of the filter network satisfy the conjugate matching condition that the real parts are equal and the absolute values ​​of the imaginary parts are equal but opposite in sign. The output reflection coefficient is suppressed to below the preset reflection coefficient threshold, thereby eliminating pulse ringing caused by impedance mismatch, ensuring the purity of the conditioned charge pulse waveform, and providing the subsequent charge-time converter with a distortion-free charge pulse that strictly corresponds to the total input charge. This ensures the accuracy of energy digitization data and the consistency between channels from the source of signal conditioning.

[0094] It should be further explained that this embodiment generates an energy-time pulse signal whose pulse width is proportional to the total input charge, including:

[0095] S201. Obtain the peak amplitude of the conditioned charge pulse.

[0096] In this embodiment, the peak amplitude of the conditioned charge pulse is directly related to the deposited energy of the gamma photon event, serving as the direct basis for distinguishing between small-energy and large-energy events and thus determining the input value of the integrating capacitor. Accurately capturing this peak amplitude provides a reliable threshold judgment input for subsequent dynamic capacitor adjustment. As a specific example, this embodiment employs a broadband peak detection circuit with the same architecture as the aforementioned pulse leading-edge slope detection circuit. This circuit consists of a high-speed sample-and-hold circuit with a bandwidth of 500MHz, locking the peak level when the conditioned charge pulse arrives. The holding time is set sufficiently to cover the setup and logic decision delay of the subsequent comparator, thereby providing a stable amplitude comparison input for S202.

[0097] S202. The peak amplitude is compared with the upper limit threshold of the preset linear interval, and the input capacitance value of the integral capacitor is determined according to the comparison result.

[0098] In this embodiment, a preset upper limit threshold for the linear range divides the dynamic range of the input energy into a low-energy range and a high-energy range. In the low-energy range, the signal charge is small; if a large capacitor is used for integration, the integrated voltage changes gradually, taking too long to reach the reference threshold, and is susceptible to noise interference, leading to increased time fluctuations. In the high-energy range, the signal charge is large; if a small capacitor is used for integration, the integrated voltage rises extremely rapidly, easily exceeding the upper limit of the integrator's output swing, causing saturation distortion and disrupting the linear relationship between pulse width and charge. Therefore, by adaptively switching the capacitor size based on the comparison result of the peak amplitude relative to the threshold, sensitivity and linearity can be simultaneously considered across the entire dynamic range. As a specific example, in this embodiment, the aforementioned LYSO scintillation crystal coupled silicon photomultiplier tube detector unit with a photosensitive area of ​​3 mm x 3 mm is used. The peak amplitude of the conditioned charge pulse generated by 511 keV gamma photons is typically distributed in the range of 200 mV to 800 mV. To ensure that the energy linearity coverage range is 250 keV to 750 keV, after circuit simulation and actual measurement calibration, the preset upper limit threshold for the linear range is set to 500 mV.

[0099] It should be further explained that the upper limit threshold of the preset linear interval mentioned in this embodiment is determined through the following steps:

[0100] A101. Obtain the first charging characteristic curve and the second charging characteristic curve when the first capacitor value and the second capacitor value are respectively connected to the integration node, and the peak value of the integration voltage changes with the amount of input charge.

[0101] In this embodiment, the first and second capacitance values ​​constitute two different charge-voltage conversion functions at the integration node. These functions intersect on the input charge axis in a region determined by the capacitance ratio and the integrator output swing. The charge coordinates of this intersection region serve as the physical basis for threshold division. This intersection position can be accurately determined by measuring two charging characteristic curves. As a specific example, in this embodiment, during the offline calibration phase, the on-chip charge injection circuit scans the input charge in 10-picocoulomb steps within the range of 25 to 50 picocoulombs. The peak integrated voltage corresponding to the first capacitance value of 50 pF and the second capacitance value of 60 pF are recorded, resulting in two sets of discrete data points. After linear fitting, the first and second charging characteristic curves are formed and stored in the calibration parameter table.

[0102] A102. On the first charging characteristic curve, determine the first critical input charge amount corresponding to the value of the integral voltage reaching the upper limit of the preset integrator output swing.

[0103] In this embodiment, the first capacitor value is 50pF and the second capacitor value is 60pF. Since the first capacitor value is smaller than the second capacitor value, the slope of the integral voltage change corresponding to the first capacitor value is higher under the same input charge, and it will reach the upper limit of the integrator output swing first. This first critical input charge value marks the minimum energy event position where saturation distortion will occur if the capacitor is not switched; it is a hard boundary for determining the upper limit of the threshold. As a specific example, in this embodiment, the preset upper limit of the integrator output swing is 1.2V, the first capacitor value is 50pF, and the input charge value corresponding to the peak integral voltage reaching 1.2V is found on the first charging characteristic curve. The measured first critical input charge value is 45 picocoulombs, with an equivalent deposited energy of approximately 460keV.

[0104] A103. The preset linear interval upper limit threshold is set as follows: when the peak amplitude of the conditioned charge pulse is equal to the preset linear interval upper limit threshold, the input charge carried by the conditioned charge pulse is less than or equal to the first critical input charge, and when the second capacitor value is connected, the peak value of the integral voltage does not exceed the preset integrator output swing upper limit.

[0105] In this embodiment, the threshold setting must simultaneously satisfy two constraints. First, when integrating all energy events in the range at and below the threshold with the first capacitor value, the peak value of the integrated voltage must not exceed the upper limit of the swing. That is, the threshold selection must ensure that the maximum input charge in this range is less than the first critical input charge of 45 picocoulons, thereby guaranteeing that there is no saturation in the low-energy range. Second, when integrating all energy events in the range above the threshold with the second capacitor value, the peak value of the integrated voltage must also not exceed the upper limit of the swing. That is, after switching to the second capacitor value, the peak value of the integrated voltage corresponding to the input charge at the threshold point is within a safe range, thereby guaranteeing that there is no saturation in the high-energy range. The intersection of the two constraints determines the safe range of the threshold value. As a specific example, in this embodiment, the peak amplitude of the conditioned charge pulse and the input charge are linearly related after front-end gain calibration. The maximum input charge corresponding to 511 keV full energy deposition is 50 picocoulons, and the peak amplitude is 800 mV. The peak amplitude corresponding to the first critical input charge of 45 picocoulons is approximately 720 mV. To ensure a certain safety margin in the low-energy range and that the peak value of the integrated voltage after switching to the high-energy range is far below the upper limit of the swing, within the range of 200mV to 720mV, combined with the requirement of the linear energy coverage range of 250keV to 750keV for the LYSO scintillation crystal, the peak amplitude of 500mV is determined as the upper limit threshold of the preset linear range. The input charge corresponding to this threshold is 31.25 picocoulombs, which is less than the first critical input charge of 45 picocoulombs. Furthermore, when integrated with the second capacitance value of 50pF, the corresponding peak value of the integrated voltage is approximately 625mV, which is far below the upper limit of the 1.2V swing. Sufficient safety margin is maintained under both constraints. In this embodiment, the linear conversion relationship between the input charge and the peak amplitude of the conditioned charge pulse is calibrated offline by an on-chip high-precision charge injection circuit. This calibration circuit can output standard charge pulses in 1pC increments within the range of 1pC to 100pC. By injecting a standard pulse with a known charge into the input of the signal conditioning link, the peak amplitude of the corresponding conditioned charge pulse is measured, and the linear conversion formula between the charge and the peak amplitude is obtained by fitting: "peak amplitude (mV) = 16 × input charge (pC)", that is, the charge-to-voltage conversion gain is 16mV / pC. Thus, the 50pC input charge corresponding to the 511keV full energy deposition can be determined, and its peak amplitude is 800mV, which is completely consistent with the calibration value in the embodiment.

[0106] S2021. When the peak amplitude is less than or equal to the upper limit threshold of the preset linear interval, the integrating capacitor is configured to a first capacitance value. The integrated capacitor connected with the first capacitance value is charged using the conditioned charge pulse. At the first moment when the integrated voltage across the integrating capacitor rises from the initial level to the preset reference threshold, the comparator is triggered to generate a first flip edge. At the second moment when the conditioned charge pulse is detected to end, the comparator is triggered to generate a second flip edge, thereby obtaining an energy-time pulse signal with a pulse width equal to the time interval between the first moment and the second moment.

[0107] In this embodiment, the detection of the end time of the conditioned charge pulse and the generation of the second flip edge of the energy-time pulse are achieved through a trailing edge zero-crossing detection circuit in conjunction with an RS flip-flop. The trailing edge zero-crossing detection circuit is constructed using a high-speed comparator, with its inverting input connected to a 0V reference level and its non-inverting input connected to the conditioned charge pulse. When the trailing edge of the pulse drops to 0V, the comparator output flips, and this flipping moment is the end time of the charge pulse. The set input of the RS flip-flop is connected to the output of the integrating capacitor voltage comparator to obtain the first flip edge, and the reset input is connected to the output of the trailing edge zero-crossing detection circuit to obtain the second flip edge. The Q output of the RS flip-flop is the complete energy-time pulse signal, and its pulse width is precisely equal to the time interval between the set and reset flip edges.

[0108] In this embodiment, a smaller first capacitor value is used in the low-energy range, resulting in a larger slope of the integral voltage change per unit input charge. The integrating capacitor can quickly cross the comparator threshold, reducing time jitter caused by signal fluctuations and noise. Simultaneously, because the total input charge is limited, the peak value of the integral voltage will not approach the upper limit of the integrator output swing, ensuring the charge-time conversion sensitivity and linearity within this range. As a specific example, in this embodiment, the first capacitor value is 50pF, the integrator initial level is set to zero, and the preset reference threshold is set to 200mV. When a conditioned charge pulse with a peak amplitude of 400mV, corresponding to a deposition energy of approximately 350keV, is input, the moment when the integrating capacitor charges from zero to 200mV is taken as the first flip edge, and the moment the pulse ends is taken as the second flip edge, with a measured pulse width of 15 nanoseconds. For the smallest measurable charge event, corresponding to a deposition energy of approximately 250keV, the pulse width is approximately 5 nanoseconds. This minimum pulse width is much larger than the single-shot quantization resolution of the multi-channel time-to-digital converter, ensuring the time measurement accuracy in the low-energy range.

[0109] It should be further explained that the first capacitance value in this embodiment is predetermined through the following steps:

[0110] S20211. During the offline calibration phase of the charge-time converter, the integrator is excited multiple times with a calibration charge pulse having the minimum input charge amount. Before each excitation, the calibration capacitor value connected to the integrator is adjusted in a decreasing manner with a preset step value, and the pulse width measurement value of the energy-time pulse signal generated under each excitation is recorded simultaneously.

[0111] In this embodiment, in the low-energy range, the value of the integrating capacitor directly determines the slope of the integrated voltage change per unit input charge. The smaller the capacitance value, the faster the integrated voltage rises, and the narrower the energy-time pulse width. By scanning in descending order starting from a larger capacitance value, a systematic correspondence between the capacitance value and the pulse width corresponding to the minimum energy event can be established, providing a data basis for determining the optimal capacitance value that ensures sufficient pulse width resolution without introducing unnecessary noise sensitivity. As a specific example, in this embodiment, the conversion of gamma photon deposition energy to the output charge of the silicon photomultiplier tube is expressed by the formula: "Input charge (pC) = Deposited energy (keV) × Light yield (photons / keV) × Photon detection efficiency × Silicon photomultiplier tube gain × Electron charge (C) × 10" 12 "Quantitative calculations were completed, with the LYSO scintillation crystal yield set at 32 photons / keV, the silicon photomultiplier tube photon detection efficiency set at 40%, and the single-photon gain set at 1.5 × 10⁻⁶." 6 The electron charge is taken as 1.6 × 10⁻⁶. -19 Substituting C into the calculation, the input charge corresponding to a 250keV gamma photon is approximately 25pC, consistent with the calibrated value of the minimum input charge in the embodiment. The calibration charge pulse is generated by the on-chip charge injection circuit, and its total injected charge is equivalent to the minimum input charge of 25 picocoulombs corresponding to the minimum deposition energy of a 250keV gamma photon. The adjustment range of the calibration capacitor is 5pF to 100pF, with a preset step value of 5pF, decreasing sequentially from 100pF to 5pF for a total of 20 levels. After each excitation, the pulse width value of the generated energy-time pulse signal is measured and recorded by a multi-channel time-to-digital converter to form a capacitance-pulse width mapping table.

[0112] S20212. Compare each recorded pulse width measurement value with a preset minimum pulse tolerance limit, and select multiple candidate calibration capacitor values ​​that make the pulse width measurement value greater than or equal to the preset minimum pulse tolerance limit for the first time.

[0113] In this embodiment, the preset minimum pulse tolerance is set based on the single-shot quantization resolution of the multi-channel time-to-digital converter and the system's allocation requirements for low-energy measurement accuracy. A narrow pulse width leads to an increased proportion of time quantization error in the pulse width measurement, reducing the energy resolution in the low-energy range. Therefore, using the minimum pulse tolerance as a constraint, a subset of candidate values ​​that meet the time measurement accuracy requirements is selected from all measured capacitance values. All subsequent smaller capacitance values ​​are retained starting from the first value that meets the condition because smaller capacitance values ​​result in a larger integral voltage slope and shorter time jitter, which is a better choice while still meeting the pulse width resolution. However, further optimization is needed in subsequent steps, combined with integrator saturation constraints. As a specific example, in this embodiment, the single-shot quantization resolution of the multi-channel time-to-digital converter is 50 ps, ​​and the preset minimum pulse tolerance is set to 100 times this, i.e., 5 nanoseconds, to ensure that the quantization error of the low-energy pulse width measurement is less than one percent. Comparison revealed that the pulse width measurement was 22 nanoseconds when the calibration capacitor was 100pF, meeting the tolerance; 18 nanoseconds for 80pF; 12 nanoseconds for 60pF; 7 nanoseconds for 40pF; and 4.8 nanoseconds for 20pF, falling below the tolerance for the first time. Therefore, the four ranges of 100pF, 80pF, 60pF, and 40pF, which met the pulse tolerance, were selected as candidate calibration capacitor values, while 20pF and below were excluded due to excessively narrow pulse widths.

[0114] S20213. Among the multiple candidate calibration capacitor values, the calibration charge pulse corresponding to the maximum input charge is used to excite the integrator connected with each candidate calibration capacitor value, and the peak value of the integral voltage generated under each candidate calibration capacitor value is recorded synchronously. Candidate calibration capacitor values ​​that cause the peak value of the integral voltage to exceed the upper limit of the preset integrator output swing are eliminated, and the smallest capacitor value is selected from the remaining candidate calibration capacitor values ​​as the first capacitor value.

[0115] In this embodiment, the selection of the first capacitor value needs to achieve an optimal balance between two constraints: low-energy pulse width resolution and the integrator's non-saturation within the full dynamic range. Among the candidate capacitor values ​​that meet the minimum pulse tolerance limit, the smallest capacitor value should be selected first, because a smaller capacitor value provides a higher integration voltage slope in the low-energy range, which can shorten the time for the integration voltage to reach the preset reference threshold, reduce time jitter caused by signal jitter and noise, and improve the time measurement accuracy at the low-energy end. However, an excessively small capacitor value may cause the integrator to saturate in the high-energy range. Therefore, a saturation test is required using the maximum input charge, and after eliminating candidate values ​​that do not meet the swing constraint, the smallest capacitor value is selected as the final set value. As a specific example, in this embodiment, the candidate calibration capacitor values ​​include four levels: 100pF, 80pF, 60pF, and 40pF. The integrator output swing limit is preset to 1.2V. Excitation is performed using a maximum input charge of 50 picocoulombs corresponding to an equivalent 511keV full energy deposition. The measured peak integral voltages for each candidate capacitance value are: 480mV for 100pF, 600mV for 80pF, 800mV for 60pF, and 1.22V for 40pF. The peak integral voltage for 40pF exceeds the 1.2V swing limit and is therefore rejected. Among the remaining three candidate values ​​of 100pF, 80pF, and 60pF, 60pF is the smallest capacitance value and satisfies both the low-energy pulse tolerance limit and the high-energy unsaturation constraint. Therefore, 60pF is selected as the final set value for the first capacitance value and written to the system configuration register for use in normal acquisition mode.

[0116] S2022. When the peak amplitude is greater than the upper limit threshold of the preset linear interval, the integrating capacitor is configured with a second capacitance value. The integrated capacitor connected with the second capacitance value is charged using the conditioned charge pulse. At a third moment when the integrated voltage across the integrating capacitor rises to the preset reference threshold, the comparator is triggered to generate the first flip edge. At a fourth moment when the conditioned charge pulse is detected to have ended, the comparator is triggered to generate the second flip edge, resulting in an energy-time pulse signal with a pulse width equal to the time interval between the third and fourth moments, wherein the second capacitance value is greater than the first capacitance value. The value of the second capacitor is configured such that when the conditioned charge pulse has the maximum input charge, the peak value of the integral voltage does not exceed the upper limit of the preset integrator output swing; wherein, the second capacitor value is determined as follows: when the total input charge of the conditioned charge pulse is any measured value within the full preset dynamic range, the absolute value of the deviation between the pulse width measurement value of the energy-time pulse signal corresponding to the measured value and the ideal linear pulse width value is less than the preset pulse width nonlinearity tolerance; the ideal linear pulse width value is the linear interpolation determined by the pulse width reference value corresponding to the minimum input charge and the pulse width full-scale value corresponding to the maximum input charge.

[0117] In this embodiment, in the high-energy range, the integrating capacitor is switched to a larger second capacitor value to reduce the slope of the integrating voltage change with the input charge, ensuring that the peak integrating voltage under the maximum input charge remains within the upper limit of the integrator output swing, fundamentally eliminating pulse width compression errors caused by integrator saturation. Simultaneously, by precisely selecting the second capacitor value, the deviation between the measured pulse width at both ends of the full dynamic range and the ideal linear interpolation is constrained within a preset pulse width nonlinearity tolerance, thereby obtaining a predictable linear energy-time transfer function across the entire energy range. As a specific example, in this embodiment, the second capacitor value is 60pF, the first capacitor value is 50pF, the second capacitor value is greater than the first capacitor value, and the preset upper limit of the integrator output swing is 1.2V. Under the condition of the maximum input charge event, corresponding to a full energy deposition of 511keV and a conditioning pulse peak amplitude of approximately 800mV, the measured peak integrating voltage is approximately 800mV, not exceeding the 1.2V swing upper limit. The preset pulse width nonlinearity tolerance is set to 200 ps. The minimum input charge corresponds to a pulse width reference value of 5 nanoseconds, and the maximum input charge corresponds to a pulse width full scale value of 30 nanoseconds. Through actual measurement and verification using ten energy points selected at uniform intervals, the absolute value of the deviation between the pulse width value of each measurement point and the ideal linear pulse width value is less than 200 ps, ​​which meets the requirements of PET imaging for energy linearity.

[0118] It should be further explained that, in this embodiment, the second capacitance value is predetermined through the following steps:

[0119] S20221. During the offline calibration phase of the charge-time converter, the integrator is excited multiple times with a calibration charge pulse having the maximum input charge. Before each excitation, the calibration capacitor value connected to the integrator is adjusted incrementally with a preset step value, and the peak value of the integral voltage generated under each excitation is recorded simultaneously.

[0120] In this embodiment, before the system is officially run, a calibration charge pulse simulating the maximum energy event is injected to traverse a series of candidate capacitance values ​​and measure the corresponding integrated voltage peak value. A correspondence table between capacitance values ​​and integrated voltage peak values ​​is established, providing a data foundation for subsequent screening. An incremental step adjustment method ensures coverage of the complete capacitance range from undercompensated to overcompensated, avoiding omission of optimal solutions. As a specific example, in this embodiment, the calibration charge pulse is generated by an on-chip charge injection circuit, and the total injected charge is equivalent to the maximum input charge of 50 picocoulombs corresponding to a 511 keV gamma photon full-energy deposition. The adjustment range of the calibration capacitor is 5 pF to 100 pF, with a preset step value of 5 pF. The calibration capacitor is sequentially set to 5 pF, 10 pF, 15 pF up to 100 pF, a total of 20 levels. After each excitation, the on-chip 10-bit analog-to-digital converter samples and records the integrated voltage peak value, forming a complete capacitance-voltage mapping table.

[0121] S20222. Compare each recorded peak value of the integral voltage with the preset upper limit of the output swing of the integrator, and select multiple candidate calibration capacitor values ​​that will ensure that the peak value of the integral voltage does not exceed the preset upper limit of the output swing of the integrator for the first time.

[0122] In this embodiment, the upper limit of the integrator output swing is used as a hard constraint to select a candidate subset that meets the unsaturation condition from all measured capacitance values. All subsequent larger capacitance values ​​are retained starting from the first value that meets the condition because larger capacitance values ​​result in lower integrated voltage peaks, still satisfying the unsaturation condition, but requiring further optimization in subsequent steps using linearity indicators. As a specific example, in this embodiment, the preset upper limit of the integrator output swing is 1.2V. Comparison shows that with a calibration capacitor of 5pF, the integrated voltage peak is 3.6V, severely saturated; at 10pF, it is 1.9V, still exceeding the limit; at 15pF, it is 1.3V, slightly exceeding the limit; and at 20pF, the integrated voltage peak is 1.1V, initially below the 1.2V swing limit. Therefore, all ranges corresponding to 20pF, 25pF, 30pF up to 100pF are listed as candidate calibration capacitor values.

[0123] S20223. Among the multiple candidate calibration capacitor values, select the candidate calibration capacitor value that minimizes the absolute value of the deviation between the measured pulse width of the energy-time pulse signal and the ideal linear pulse width value, and is lower than the preset pulse width nonlinearity tolerance, as the second capacitor value. In this embodiment, in the set of candidate capacitor values ​​that satisfy the unsaturation constraint, linearity is used as the optimality criterion for secondary screening to select the capacitor value that minimizes the fitting deviation between the measured pulse width value and the ideal linear model across the entire dynamic range. The physical basis of this method is that although an excessively large capacitor value can make the integrated voltage far from the saturation region, it will compress the dynamic range of the pulse width, leading to resolution loss and nonlinearity deterioration at the low energy end. Therefore, it is necessary to select the smallest possible capacitor value under the premise of unsaturation to balance sensitivity and linearity. The preset pulse width nonlinearity tolerance is set based on the energy linearity allocation requirements of the PET imaging system, and its value is determined to be less than one-tenth of the time error corresponding to the system's target energy resolution. As a specific example, in this embodiment, the preset pulse width nonlinearity tolerance is 200 ps, ​​the minimum input charge corresponds to a pulse width reference value of 5 nanoseconds, and the maximum input charge corresponds to a pulse width full-scale value of 30 nanoseconds. Within the candidate range of 20 pF to 100 pF, the pulse width of each candidate capacitance value is measured at ten equally spaced energy points, and the absolute value of the deviation between the measured pulse width value at each point and the ideal linear pulse width value is calculated. The actual test results show that when the calibration capacitance is 20 pF, the maximum deviation is 350 ps, ​​exceeding the tolerance; when it is 30 pF, the maximum deviation is 220 ps, ​​slightly exceeding the tolerance; when it is 40 pF, the maximum deviation is 150 ps, ​​meeting the tolerance; when it is 50 pF, the maximum deviation is 80 ps, ​​which is the smallest deviation among all candidate values; when it is 60 pF and above, although the deviation also meets the tolerance, it shows a gradually increasing trend. Accordingly, 50 pF is selected as the final set value of the second capacitance value and written into the system configuration register for use in normal acquisition mode.

[0124] This embodiment acquires the peak amplitude of the conditioned charge pulse and compares it with a preset upper limit threshold of the linear range. When the peak amplitude is below the threshold, a smaller first capacitor value is applied; when the peak amplitude is above the threshold, a larger second capacitor value is applied. This achieves adaptive switching of the integration capacitor value according to the input energy range. In the low-energy range, the smaller first capacitor value gives the integration voltage a higher slope, allowing the integration capacitor to quickly cross the preset reference threshold. This effectively reduces time jitter caused by signal jitter and noise, ensuring the sensitivity and accuracy of time measurement for low-energy events. Simultaneously, the selection of the first capacitor value is constrained by the minimum pulse tolerance, ensuring that the pulse width at the low-energy end is much larger than the single-shot quantization resolution of the time-to-digital converter, avoiding the degradation of energy resolution by quantization errors. In the high-energy range, switching to a larger second capacitor value reduces the slope of the integration voltage with respect to the input charge, confining the peak value of the integration voltage at the maximum input charge to within the preset upper limit of the integrator output swing, fundamentally eliminating pulse width compression errors caused by integrator saturation. The upper limit threshold of the preset linear range is scientifically determined based on the charging characteristic curves of the first and second capacitor values, as well as the upper limit of the integrator output swing. This ensures that there is no saturation throughout the integration with the first capacitor value in the low energy range, and similarly, no saturation throughout the integration with the second capacitor value in the high energy range, with the two ranges seamlessly connected at the threshold. The determination of the second capacitor value uses linearity across the entire preset dynamic range as the optimal criterion. By measuring the deviations of the pulse widths of multiple candidate capacitor values ​​at various energy points from the ideal linear pulse width, the value with the smallest deviation is selected as the final set value. This ensures that the absolute value of the deviation between the pulse width at any measurement point and the linear interpolation is less than the preset pulse width nonlinearity tolerance, thereby obtaining a highly linear energy-time transfer function across the entire dynamic range. This ensures the accuracy and consistency of the mapping relationship between energy digitization data and gamma photon deposition energy, providing a reliable energy measurement basis for high-precision PET image reconstruction under conditions of multi-channel parallel processing and no independent channel calibration.

[0125] A step in constructing a charge-time converter, characterized by comprising:

[0126] B201. Configure an integrator node, which receives the conditioned charge pulse via an input switch.

[0127] In this embodiment, the integrator node is the core physical node for charge-time conversion, where all input charge accumulates and is converted into a voltage signal. The function of the input switch is to connect the integrator node to the preceding signal path during the arrival of the conditioned charge pulse, ensuring that the charge pulse energy is fully injected into the integrating capacitor; and to disconnect the input path after the pulse ends, preventing the voltage on the integrating capacitor from being discharged through the output impedance of the preceding circuit, ensuring that the integrated voltage is determined only by the amount of charge injected in this event. As a specific example, in this embodiment, the input switch is implemented using a single-channel CMOS analog switch with an on-resistance designed to be less than 5Ω to reduce the attenuation of the leading edge of the charge pulse; the control signal of the switch is generated by the zero-crossing detection circuit of the conditioned charge pulse, closing the switch when the leading edge of the pulse crosses zero and opening the switch when the trailing edge of the pulse returns to zero, ensuring that the charge is fully injected into the integrator node throughout the entire pulse period.

[0128] B202. A capacitor array is connected between the integrator node and the reference ground. The capacitor array includes at least one first capacitor and one second capacitor. The first capacitor and the second capacitor are each connected to the integrator node through a selection switch. The selection switch is controlled by a capacitor configuration control signal to connect the first capacitor value or the second capacitor value to the integrator node.

[0129] In this embodiment, the capacitor array serves as the physical carrier for adaptive switching of the integrating capacitor value. The first capacitor corresponds to the low-energy range and has a smaller capacitance value to achieve higher charge-to-voltage conversion gain and faster integration speed. The second capacitor corresponds to the high-energy range and has a larger capacitance value to reduce the integration voltage slope and prevent integrator output saturation. Each capacitor is equipped with an independent selection switch, ensuring that only one capacitor is connected to the integration node at any given time, preventing the equivalent capacitance value from deviating from the preset value due to parallel capacitors. The selection switch is driven by a capacitor configuration control signal, which is derived from the comparison result of the aforementioned peak amplitude and the upper limit threshold of the preset linear range, realizing automatic identification of the energy range and capacitor switching. As a specific example, in this embodiment, the first capacitor is implemented using a metal-insulator-metal capacitor with a capacitance value of 50pF, and its selection switch uses a CMOS transmission gate with an on-resistance of less than 3Ω; the second capacitor is also implemented using a metal-insulator-metal capacitor with a capacitance value of 60pF, and its selection switch structure is the same as that of the first capacitor. The capacitor configuration control signal is generated by level shifting the output of the peak amplitude comparator in S202. When the peak amplitude is less than or equal to 500mV, the first capacitor is selected; when the peak amplitude is greater than 500mV, the second capacitor is selected.

[0130] B203. A comparator is connected between the integrator node and a preset reference threshold voltage. The non-inverting input of the comparator is connected to the integrator node, the inverting input is connected to the preset reference threshold voltage, and the output of the comparator outputs the energy-time pulse signal.

[0131] In this embodiment, the comparator is a key component in the charge-time converter for voltage-time boundary detection. The integrator node is connected to the non-inverting input of the comparator, and a preset reference threshold voltage is connected to the inverting input. When the integrated voltage rises from its initial level and crosses the preset reference threshold voltage, the comparator output flips for the first time, marking the start edge of the energy-time pulse. When the conditioned charge pulse ends and the integrated voltage stops rising, a trailing edge zero-crossing detection circuit, in conjunction with an RS flip-flop, triggers a second flip of the comparator output, marking the end edge of the energy-time pulse. The time interval between the two flips is the pulse width, which is proportional to the total injected charge. As a specific example, in this embodiment, the comparator is implemented using a high-speed comparator with a propagation delay of less than 500 ps. Its input offset voltage is compensated to less than 2 mV by an automatic zero-calibration circuit, ensuring that the accuracy of the threshold comparison is not affected by process deviations and temperature drift. The preset reference threshold voltage is generated by a resistor divider from an on-chip bandgap reference voltage and is set to 200 mV. The divider resistors are temperature-coefficient matched precision polysilicon resistor pairs to ensure the stability of the threshold voltage across the entire operating temperature range.

[0132] B204. A reset switch is connected in parallel across the integrator node. The reset switch is controlled by a reset control signal and resets the integrator node to its initial level after each energy-time conversion.

[0133] In this embodiment, the reset switch functions to rapidly discharge the accumulated charge on the integrating capacitor to the reference ground after completing one energy-time conversion, restoring the integrating node voltage to its initial level and preparing for the next event. If the reset is incomplete, the residual voltage on the integrating node will be superimposed on the integrating voltage of the next event, introducing inter-channel memory effects and energy measurement errors. The reset timing must be triggered after the trailing edge of the energy-time pulse signal and completed before the arrival of the next conditioned charge pulse to ensure the independence between each conversion. As a specific example, in this embodiment, the reset switch is implemented using an NMOS transistor with an on-resistance of less than 2Ω, and its gate is driven by a reset control signal. The reset control signal is triggered by the second flip edge of the comparator output, and a 10-nanosecond wide reset pulse is generated by a pulse shaping circuit. This pulse width is much larger than the discharge time constant formed by the integrating capacitor and the on-resistance of the reset switch, ensuring that the integrating node voltage is completely restored to its initial zero-level state within each event cycle. In this embodiment, the timing constraints and anti-collision mechanisms of the reset pulse are strictly limited by hardware logic. The reset pulse width is set to 10ns, which is determined by the discharge time constant formed by the maximum integrating capacitor of 60pF and the on-resistance of the reset switch of less than 2Ω. This ensures that the error of the integrating capacitor discharging to the initial level is less than 0.1%, avoiding baseline drift caused by residual charge. During the reset, the input switch is forcibly disconnected to shield new pulse input and avoid conversion errors caused by charge injection during the reset process. After the reset is completed, a 2ns dead time window is set. The input switch is closed again only after the window ends to ensure that the circuit is completely restored to the initial state and to avoid crosstalk and data errors between adjacent events.

[0134] It should be further explained that the digital time data characterizing gamma photon energy information obtained in this embodiment includes:

[0135] S301. The energy-time pulse signals output from each channel are respectively connected to the delay chain input terminal of the corresponding channel in the multi-channel time-to-digital converter, so that the energy-time pulse signals propagate step by step along the unit delay unit of the delay chain. The output state of each stage of the delay chain is latched by a global reference clock synchronized with the time reference, so that the pulse width of the energy-time pulse signal is quantized in the delay chain to be an integer multiple of the unit delay unit of the delay chain, and coarse count data and fine count data corresponding to the pulse width are obtained.

[0136] In this embodiment, the core operation of this step is to inject the energy-time pulse signals of each channel into the corresponding delay chain in parallel, completing the pulse width to digital conversion under the unified drive of the global reference clock. Its physical principle is based on the well-known Nutt interpolation time-to-digital conversion architecture: the measured time interval is decomposed into a coarse measurement part in units of reference clock cycles and a fine measurement part in units of delay unit delay. The coarse measurement is performed by a counter, and the fine measurement is performed by interpolation in the delay chain. The combination of these two methods can achieve sub-nanosecond time resolution without significantly increasing the reference clock frequency. As a specific example, the frequency of the global reference clock is set to 400MHz, corresponding to a reference clock period of 2.5 nanoseconds; the delay chain consists of 32 cascaded unit delay units, and the nominal delay of each unit delay unit is determined by the ratio of the reference clock period to the number of delay chain stages, which is approximately 78 picoseconds; when the minimum pulse width of the energy-time pulse signal is 5 nanoseconds, the coarse count is approximately 2 reference clock cycles, and the fine count is approximately 0 unit delay units; when the maximum pulse width is 30 nanoseconds, the coarse count is approximately 12 reference clock cycles, and the fine count is determined by interpolation of the delay chain. The fine time quantization error across the entire dynamic range is ±39 picoseconds, and this error value will be compared with the preset time quantization error tolerance in subsequent steps.

[0137] It should be further explained that the construction steps of the multi-channel time-to-digital converter in this embodiment include:

[0138] S3011. Configure a global reference clock generator, which generates a frequency-stable global reference clock signal, the period of which constitutes the time reference of the multi-channel time-to-digital converter.

[0139] In this embodiment, the core operation of this step is to generate a low-jitter, highly stable global reference clock through frequency synthesis technology, providing a unified time measurement benchmark for all channels. The engineering principle is that the measurement accuracy of the time-to-digital converter is ultimately limited by the periodic stability and phase noise of the reference clock; the jitter of the reference clock directly translates into random errors in the time measurements of each channel. Therefore, a well-known phase-locked loop (PLL)-based frequency synthesis technique is employed, using a high-precision crystal oscillator as the reference source. The PLL multiplies the low-frequency crystal oscillator signal to the target frequency, while a loop filter suppresses the phase noise of the voltage-controlled oscillator. As a specific example, a temperature-compensated crystal oscillator with a frequency stability of ±2.5 ppm and an output frequency of 25 MHz is selected. The PLL multiplies the 25 MHz to 400 MHz, corresponding to a reference clock period of 2.5 nanoseconds. The loop bandwidth is set to 1 MHz to balance locking speed and phase noise suppression. The measured root mean square jitter of the output clock is less than 2 picoseconds, which is less than the time jitter tolerance allocated to the time reference stage by the system.

[0140] S3012. Configure a delay chain for each channel. The delay chain is composed of N cascaded unit delay units. The unit delay units have equal unit delay amounts. The energy-time pulse signal is input to the delay chain and propagates step by step along each stage of the unit delay unit. The global reference clock signal drives the latch corresponding to each stage of the unit delay unit, so that the pulse width of the energy-time pulse signal is quantized in the delay chain to be an integer multiple of the unit delay unit.

[0141] In this embodiment, the core operation of this step is to construct a delay chain consisting of multiple cascaded delay units in each channel, expanding one cycle of the reference clock into N equally spaced sampling nodes on the time axis. The physical principle is as follows: the signal propagates sequentially through the cascaded delay units. There is a defined time delay between the input and output of each delay unit. When the total delay of the N delay units exactly covers one reference clock cycle, the outputs of each stage of the delay chain constitute a multi-phase sampled signal uniformly distributed in the time domain. By latching the state of these sampled signals at the arrival time of the pulse transition edge, the precise position information of the pulse edge within one reference clock cycle can be obtained. The unit delay unit is implemented using a differential buffer, which is well-known in the art, and its delay amount can be controlled by adjusting the bias current of the buffer. As a specific example, the number of stages N in the delay chain is set to 32 stages based on the ratio of the reference clock period to the target time resolution. Each unit delay has a nominal delay of 78 picoseconds, and the total nominal delay of the entire chain is 2.5 nanoseconds, matching the reference clock period. The bias current of each delay unit is uniformly provided by an on-chip current-to-analog converter, and the resolution of the current-to-analog converter is set to 6 bits by those skilled in the art according to the requirements of delay adjustment accuracy.

[0142] S3013. Configure a coarse counter for each channel. The coarse counter uses the global reference clock signal as the counting clock, starts counting when the first flip edge of the energy-time pulse signal arrives, and stops counting when the second flip edge of the energy-time pulse signal arrives. Record the integer number of cycles of the global reference clock signal as coarse count data.

[0143] In this embodiment, the core operation of this step is to count the number of complete clock cycles contained in the high-level duration of the energy-time pulse signal, using a global reference clock as the beat, to obtain the high-bit data of the pulse width digitization. The engineering principle is as follows: the coarse counter is essentially a synchronous binary adder. During the pulse width's effective period, each rising edge of the reference clock triggers the count value to increment by one. After the pulse width ends, the count value is latched and read out. The counter's start and stop are triggered by the pulse's flip edge via an edge detection circuit, which must have sufficient noise margin to prevent false triggering. The coarse counter is implemented using a synchronous binary counter known in the art, and the edge detection circuit is implemented using a Schmitt trigger known in the art. As a specific example, the maximum measurable pulse width is 30 nanoseconds, the reference clock period is 2.5 nanoseconds, the maximum coarse count value is 12, and the coarse counter bit width is set to 4 bits; the hysteresis voltage of the Schmitt trigger is set to 50mV by those skilled in the art based on the noise amplitude of the signal edge.

[0144] S3014. A fine time measurement circuit is configured for each channel. The fine time measurement circuit latches the first status code of the delay chain when the first flip edge of the energy-time pulse signal arrives, and latches the second status code of the delay chain when the second flip edge arrives. Fine count data is obtained according to the unit delay unit position corresponding to the first status code and the second status code in the delay chain.

[0145] In this embodiment, the core operation of this step is to perform snapshot latching of the logic state of each stage of the delay chain output at the instants of the pulse's start and end edges, respectively, converting the state codes at the two latching moments into fine-grained position information of the pulse width within one reference clock cycle. The physical principle is as follows: the outputs of each stage of the delay chain constitute a set of multi-phase signals evenly distributed in the time domain. The propagation position of the pulse edge in the delay chain directly reflects the state distribution where the delay unit output is high after that position and low before it. This state distribution encodes the coordinates of the edge in the delay chain in the form of thermometer codes. The latching operation is implemented using a D flip-flop array known in the art, and the thermometer code conversion is implemented using a thermometer code-to-binary code conversion circuit known in the art. As a specific example, the delay chain has 32 stages. The output of each delay unit is connected to the data input of a D flip-flop. The clock of the D flip-flop is driven by the pulse flip edge. When the edge arrives, the states of all 32 stages are latched simultaneously to obtain a 32-bit thermometer code. After conversion, a 5-bit binary fine count data is obtained. The quantization error is ±0.5 delay units, which is ±39 picoseconds.

[0146] S3015. Configure an encoding and readout circuit for each channel. The encoding and readout circuit merges the coarse count data and the fine count data, converts them into binary digital time data that characterizes the pulse width of the energy-time pulse signal, and serially outputs the digital time data through a parallel-to-serial converter.

[0147] In this embodiment, the core operation of this step is to concatenate the coarse count data as the high-order bit and the fine count data as the low-order bit according to their weighting relationship to form a complete digital time value, and then convert the parallel data into a serial data stream to save output pins. The engineering principle is as follows: the weight of the coarse count data is the full-scale value of the fine count; that is, each increment of 1 in the coarse count value represents a complete reference clock cycle, which contains a delay unit of the full-scale value of the fine count. Therefore, the digitized result of the complete pulse width is the coarse count value multiplied by the full-scale value of the fine count and then added to the fine count value. The arithmetic operations are implemented using hardware multipliers and adders known in the art, and the parallel-to-serial conversion is implemented using a shift register serialization circuit known in the art. As a specific example, the coarse counter has a bit width of 4 bits, the fine counter has a full scale of 32, and the total bit width of the digitized time data is 9 bits, which can represent a delay of up to 415 delay units, corresponding to approximately 32.3 nanoseconds, which is sufficient to cover the maximum pulse width of 30 nanoseconds; the parallel-to-serial converter converts the 9-bit parallel data into a single-bit serial data stream, and the serial output rate is set by those skilled in the art to 200MHz according to the data transmission bandwidth requirements.

[0148] S3016. Configure a calibration circuit for the multi-channel time-to-digital converter. The calibration circuit measures the actual delay of the unit delay unit of each channel during the offline calibration stage and establishes a delay deviation lookup table between channels for calibrating the delay deviation of the fine count data of each channel during online measurement.

[0149] In this embodiment, the core operation of this step is to measure the deviation of the actual delay of each delay unit in each channel from the nominal value due to manufacturing process deviations using a calibration circuit before the system officially starts working, and to store this deviation for subsequent compensation. Its engineering principle is based on the well-known code density testing method in the art: In this embodiment, the random pulses used for code density testing are generated by an on-chip independent ring oscillator. The power supply of this ring oscillator is completely isolated from the power supply of the reference clock phase-locked loop, and the oscillation frequency is set to 1.17 times the reference clock frequency (not an integer multiple) to ensure that the random pulses are completely asynchronous with the global reference clock; the high-level width of the random pulses is set to be greater than the total delay of the delay chain and less than the reference clock period to ensure that each pulse can propagate completely to the end of the delay chain; the total number of test pulses is not less than 1 million to ensure that the statistical error of each delay unit does not exceed 1 ps. The delay chain is input with random pulses whose arrival times are uniformly distributed within 0 to the reference clock cycle. The probability that the output of each delay unit is latched as a logic high level in a large number of events is statistically analyzed. Under the premise of uniform input time distribution, the probability of each delay unit outputting a high level is proportional to the cumulative delay amount before that unit. From this, the actual absolute delay amount of each delay unit can be deduced. The deviation between the actual delay amount and the nominal value of each unit in each channel is stored in a lookup table. During online measurement, the deviation value is read from the lookup table to correct the fine count data. As a specific example, the random pulse source for code density testing is generated by an on-chip ring oscillator, and the number of test pulses is set to more than 1 million to ensure statistical accuracy better than 1 picosecond. The delay deviation lookup table is stored in an on-chip one-time programmable memory with a storage depth equal to the number of channels multiplied by the delay chain level. Each deviation value is represented by an 8-bit signed integer, covering a deviation range of ±30 picoseconds.

[0150] S302. For the current processing channel in each channel, obtain the fine count data of the current processing channel, extract the phase offset feature value caused by crosstalk between the current processing channel and the adjacent channel in the fine count data, and compare the phase offset feature value with a preset crosstalk tolerance threshold.

[0151] In this embodiment, the core operation of this step is to perform inter-channel crosstalk detection on the fine count data of each channel, and determine whether the phase shift caused by crosstalk exceeds the tolerable range, so as to decide whether to enable crosstalk compensation correction. The physical principle is as follows: In a high-density multi-channel time-to-digital converter, the delay chains of each channel are arranged in close parallel on the chip layout. The rapid transition signals of the delay chains of adjacent channels are coupled to the current channel delay chain through parasitic capacitance and mutual inductance between the wirings. This causes the equivalent delay of each delay unit in the current channel to undergo a slight dynamic shift with the activity of the adjacent channel signals, resulting in a systematic error in the fine count data related to the activity of adjacent channels. The preset crosstalk tolerance threshold is set based on comparing the equivalent time error caused by inter-channel crosstalk in the fine count data with the tolerance allocated to the time digitization stage according to the system target time resolution. This tolerance is derived from the system target time resolution using the square root allocation method known in the art. When the equivalent time error caused by crosstalk is greater than one-tenth of this allocated tolerance, it is determined that crosstalk compensation is required. As a specific example, the system target meets a time resolution of 300 picoseconds. The allowable error for the square root of the sum of squares allocated to the time digitization stage is 100 picoseconds. One-tenth of this allowable error, i.e., 10 picoseconds, is taken as the equivalent time error limit corresponding to the preset crosstalk tolerance threshold. This is converted into fine count data of approximately 0.13 unit delay units. The preset crosstalk tolerance threshold is uniformly set to 0.13 unit delay units, which is consistent with the dimension of the phase offset characteristic value.

[0152] It should be further explained that, in this embodiment, the phase shift feature value extracted from the fine count data caused by crosstalk between the current processing channel and adjacent channels includes:

[0153] S3021. Obtain the fine count data of the current processing channel, and the fine count data of at least one reference channel among the adjacent channels that is closest to the physical location of the current processing channel.

[0154] In this embodiment, the core operation of this step is to determine the reference channel range for crosstalk detection and collect corresponding fine-count data samples. The physical basis for this is that the crosstalk intensity between channels decreases exponentially with increasing physical distance in the chip's three-dimensional layout structure. Only the one or two nearest channels significantly contribute to the crosstalk of the current channel, while the crosstalk influence of channels further away is submerged in the noise floor. Therefore, only the nearest channel needs to be selected as the reference channel. The determination of the reference channel is based on the analysis results of the parasitic capacitance matrix of the delay chain wiring using layout parasitic parameter extraction tools known in the art. As a specific example, the delay chains of each channel are arranged at equal intervals of 50 micrometers on the layout. The parasitic parameter extraction results show that the mutual capacitance between adjacent channels is approximately 5 times that between the next nearest channels. Therefore, one nearest channel on each side of the current channel is selected as the reference channel, for a total of two reference channels.

[0155] S3022. Perform cross-correlation operation on the fine count data of the current processing channel and the fine count data of the reference channel to obtain the cross-correlation function.

[0156] In this embodiment, the core operation of this step is to extract the coupling characteristics of the current channel fine count data and the reference channel fine count data on the time delay axis through cross-correlation analysis. Its mathematical principle is based on the well-known definition of the cross-correlation function: the cross-correlation value of two discrete time series at a delay offset m is equal to the sum of the products of one series and the other series after a delay of m samples; when the signal activity of the reference channel is coupled to the current channel through crosstalk, the current channel fine count data will contain fluctuation components related to the reference channel fine count data at a specific delay, which are expressed as local maxima on the cross-correlation function except for the zero-delay point. The cross-correlation operation can be implemented using the well-known time-domain sliding dot product method. As a specific example, the sliding window length of the cross-correlation operation is set to 128 consecutive event periods, and the cross-correlation value is calculated at 512 delay offset positions, with a total computational load of 128 x 512 multiplications and accumulations. Under the condition that the current channel event rate is approximately 100kHz, the computation delay does not exceed 5 microseconds.

[0157] S3023. In the cross-correlation function, find the peak position other than the zero delay point, and determine the delay offset corresponding to the peak position as the phase offset characteristic value.

[0158] In this embodiment, the time dimension conversion from the sample offset corresponding to the peak position of the cross-correlation function to the phase offset feature value is completed by the formula "phase offset feature value (ps) = sample offset corresponding to the peak position × time step corresponding to a single sample". The time step corresponding to a single sample in the cross-correlation operation is equal to the nominal delay of 78 ps per unit delay unit in the delay chain. If the sample offset corresponding to the peak position is 0.13 units, the phase offset feature value is 10 ps, ​​which corresponds perfectly to the preset crosstalk tolerance threshold in this embodiment, enabling accurate quantitative judgment of crosstalk exceeding the limit. The peak lookup adopts a threshold comparison method known in the art. The preset peak criterion threshold is 3 times the root mean square value of the noise floor of the cross-correlation function to ensure detection confidence. As a specific example, among the 128 delay offset positions of the cross-correlation function, the cross-correlation value at the zero-delay point is the autocorrelation peak value. A peak with an amplitude exceeding 3 times the noise floor is detected at the 15th sample delay offset position. The delay offset corresponding to this position is the phase offset feature value.

[0159] S303. When the phase offset characteristic value is greater than the preset crosstalk tolerance threshold, crosstalk compensation correction is performed on the coarse count data or fine count data of the current processing channel to obtain corrected digitized time data, and the corrected digitized time data is output as the digitized time data.

[0160] In this embodiment, the core operation of this step is to initiate a compensation and correction process when crosstalk exceeds the limit, subtracting the crosstalk induction from the measurement data to recover the true time data. The engineering principle is as follows: there is a linear relationship between the fine count data offset caused by crosstalk and the signal activity of adjacent channels, determined by layout parasitic parameters. This relationship has been quantitatively described by the crosstalk coefficient matrix obtained from offline calibration. During online operation, the crosstalk induction can be calculated in real time based on the current fine count data of adjacent channels and the pre-stored coefficient matrix. Subtracting this from the measurement value containing the error yields the correction value.

[0161] It should be further explained that this embodiment performs crosstalk compensation correction on the coarse or fine count data of the current processing channel, including:

[0162] S3031. Based on the pre-calibrated inter-channel crosstalk coefficient matrix, calculate the crosstalk induction of the current processing channel from the fine count data of the adjacent channels.

[0163] In this embodiment, the core operation of this step is to calculate the crosstalk induction of the current channel online using the crosstalk coefficient matrix obtained from offline calibration and the real-time fine count data of adjacent channels. Its engineering principle is based on a linear crosstalk model known in the art: the crosstalk induction of the current channel is equal to the linear sum of the fine count data of each reference channel multiplied by the corresponding crosstalk coefficient; each crosstalk coefficient represents the offset caused by a unit of reference channel signal activity in the fine count data of the current channel, with the dimension being the fine count data offset per unit of reference channel fine count data. During offline calibration, those skilled in the art use an on-chip pulse generator to sequentially inject pulses of known pulse widths into each reference channel individually, measuring the change in the fine count data of the current channel. The ratio of the change to the pulse width of the reference channel is the corresponding coefficient. After calibration, the coefficient matrix is ​​written to the on-chip one-time programmable memory for online recall. As a specific example, the inter-channel crosstalk coefficient matrix is ​​a 2x32 real number matrix, corresponding to 2 reference channels and 32 delay units, with each coefficient stored in 16-bit fixed-point decimal format.

[0164] S3032. Subtract the crosstalk induction from the fine count data of the current processing channel to obtain the corrected fine count data.

[0165] In this embodiment, the core operation of this step is to subtract the crosstalk induction calculated in S3031 from the fine count data measurement value of the current channel to eliminate the additional offset caused by crosstalk. The subtraction operation is implemented using a signed integer subtractor known in the art. The overflow protection strategy of the subtractor clamps the corrected fine count data between zero and the full scale value. The clamping interval is set by those skilled in the art to be zero to 31 according to the fine count full scale value.

[0166] S3033. The corrected fine count data is combined with the coarse count data of the current processing channel to form the corrected digitized time data.

[0167] In this embodiment, the core operation of this step is to reassemble the compensated fine count data and the coarse count data into complete digital time data. The merging method is the same as the operation rule of the encoding circuit in S3015, that is, the coarse count value is multiplied by the full-scale value of the fine count and then added to the corrected fine count value.

[0168] S304. When the phase offset characteristic value is less than or equal to the preset crosstalk tolerance threshold, the coarse count data and fine count data of the current processing channel are merged and directly output as the digitized time data.

[0169] In this embodiment, the core operation of this step is to skip the compensation calculation when the crosstalk does not exceed the limit, and directly merge and output the original coarse and fine count data to save power consumption and computational delay of the digital circuit. The decision logic is designed by those skilled in the art as a pipelined compare-select circuit, which completes the decision and data merging output in the next clock cycle after obtaining the phase offset characteristic value in S302, without introducing an additional waiting cycle.

[0170] The delay amount of each unit delay in the delay chain is determined by the period of the time reference and the number of stages in the delay chain. The delay amount of each unit delay is configured such that the quantization error of the digitized time data is less than a preset time quantization error tolerance across the entire dynamic range of the energy-time pulse signal, from the minimum pulse width to the maximum pulse width. In this embodiment, the delay amount of each unit delay is obtained by dividing the reference clock period of 2.5 nanoseconds by the number of delay chain stages of 32, with a nominal value of 78 picoseconds, corresponding to a fine-time measurement quantization error of ±39 picoseconds. The preset time quantization error tolerance is set based on the allowable error allocated to the time digitization stage by the square root allocation method to achieve the system's target time resolution. The time quantization error must be less than half of this allowable error to ensure that its contribution to the final time resolution is negligible. As a specific example, the system aims to meet a time resolution of 300 picoseconds. The total tolerance is allocated to the three stages of signal conditioning, charge-time conversion, and time digitization using the square root allocation method known in the art. The tolerance obtained by allocating the time digitization stage is 100 picoseconds. The quantization error corresponding to the unit delay unit of 78 picoseconds is ±39 picoseconds, which is less than half of the tolerance, i.e., 50 picoseconds, thus meeting the design requirements for time digitization accuracy.

[0171] This embodiment constructs a multi-channel time-to-digital converter (TD-SCDMA) comprising a global reference clock generator, a delay chain, a coarse counter, a fine time measurement circuit, an encoding readout circuit, and a calibration circuit. It performs parallel digital measurement of the pulse width of the energy-time pulse signal for each channel under a unified time reference. The coarse counter records the number of complete reference clock cycles contained within the pulse width, and the delay chain interpolates to obtain the fine position information of the pulse width within one reference clock cycle. By merging coarse and fine data, sub-nanosecond time resolution is achieved without significantly increasing the reference clock frequency. This architecture balances the high throughput requirements of multi-channel parallel processing with the picosecond-level time measurement accuracy requirements. In the offline stage, the calibration circuit uses a code density test method to measure the actual delay of each channel's unit delay and establishes a channel delay deviation lookup table. During online measurement, the fine count data for each channel is calibrated for delay deviation, effectively eliminating inter-channel delay inconsistencies caused by manufacturing process deviations and ensuring the consistency of time measurement values ​​for thousands of channels without independent channel calibration. Based on this, by acquiring the fine count data of each channel and extracting the phase shift characteristic value caused by crosstalk between adjacent channels, the phase shift characteristic value is compared with the preset crosstalk tolerance threshold. When the crosstalk exceeds the limit, the crosstalk induction is calculated online according to the pre-calibrated inter-channel crosstalk coefficient matrix and subtracted from the current channel fine count data to complete the correction. When the crosstalk does not exceed the limit, the original data is directly output to save computing power and latency. Thus, under the condition of high-density parallel operation of multiple channels, the degradation of time measurement accuracy by inter-channel crosstalk is effectively suppressed, and the equivalent time error introduced by crosstalk is controlled within one-tenth of the system's time resolution allocation tolerance. At the same time, the delay of the unit delay unit is determined by the ratio of the global reference clock period to the delay chain stage, which is approximately 78 picoseconds. This makes the quantization error of the digitized time data in the full dynamic range ±39 picoseconds, which is less than the 50 picoseconds that are allocated to the time digitization link by the square root allocation method according to the system's target time resolution, ensuring the accuracy margin of time quantization. The above measures together ensure that the energy digitization data has sub-picosecond time measurement accuracy and excellent inter-channel consistency across the entire dynamic range, providing accurate and reliable time and energy information input for subsequent conformity selection and PET image reconstruction.

[0172] It should be further explained that this embodiment aggregates and transmits the time data packets from multiple channels to the back-end integrated circuit via a high-speed serial interface, including:

[0173] S401. Configure a high-speed serial link for each group of a preset number of channels. Each high-speed serial link is connected to a serial data transmission port. The preset number is determined by the maximum integer number of links obtained by dividing the total number of board-level interconnect pins by the number of pins required for each high-speed serial link.

[0174] In this embodiment, the core operation of this step is to calculate the maximum number of high-speed serial links that the board can support based on the total number of available board-level interconnect pins and the number of pins required for each high-speed serial link. This determines the number of channels that each high-speed serial link needs to carry, dividing all detector channels into several channel groups. The engineering principle is as follows: the number of signal output pins on a multi-channel positron emission tomography (PET) detector board is limited by the connector pin density and the number of printed circuit board wiring layers. If each detector channel is allocated a separate serial data transmission port, the total number of pins required for thousands of channels will far exceed the physical pin capacity of the board. Therefore, a converged transmission architecture where multiple channels share the same high-speed serial link must be adopted, exchanging the number of links for the carrying capacity of a single link channel, achieving lossless transmission of data across all channels under pin constraints. The determination of the preset number follows a resource constraint allocation calculation method known in the art: the preset number equals the total number of board-level interconnect pins divided by the number of pins required for each high-speed serial link, and the quotient rounded down is the maximum number of configurable links. The number of pins required for each high-speed serial link is determined by the selected serial data transmission physical layer standard. As a specific example, in this embodiment, the total number of detector channels on the single board is 4096, and the total number of pins available for data transmission via board-level interconnection is 128. Each high-speed serial link adopts a well-known low-voltage differential signal transmission standard, requiring only one pair of differential signal lines, i.e., two pins. Therefore, the maximum number of configurable high-speed serial links on the single board is calculated to be 64. The preset number for each group is 4096 divided by 64, which equals 64 channels. That is, every 64 detector channels share one high-speed serial link for data aggregation and transmission. The low-voltage differential signal transmission standard is a well-known physical layer interface standard, and its electrical characteristics are selected and configured by those skilled in the art based on transmission rate and distance requirements.

[0175] S402. When any channel generates the time data packet, the time data packet of that channel is written into the channel buffer queue corresponding to that channel. The depth of the channel buffer queue is configured to be at least greater than the number of time data packets accumulated by that channel under the maximum event rate and the maximum arbitration waiting time.

[0176] In this embodiment, the core operation of this step is to configure an independent data buffer queue for each detector channel. When a time data packet is generated by a channel, it is immediately written into the corresponding channel buffer queue for temporary storage, awaiting subsequent arbitration logic to grant the channel the right to transmit. The engineering principle is as follows: gamma photon events of each detector channel arrive randomly in time. Multiple channels may generate time data packets simultaneously or sequentially within a very short time window. However, among all channels sharing the same high-speed serial link, only one channel can obtain the right to transmit at any given time and send its data frame to the link. During the arbitration period while waiting to obtain the right to transmit, newly generated time data packets must be reliably stored in the channel buffer queue. If the depth of the channel buffer queue is insufficient to accommodate the maximum number of data packets accumulated during the arbitration waiting period under the worst-case operating conditions, buffer overflow will occur, leading to event data loss. This loss will directly reduce the number of valid event pairs available in the subsequent conformity selection process, impairing system sensitivity. Therefore, the design of the channel buffer queue depth must meet the worst-case accumulated data packet count under the product of the maximum event rate and the maximum arbitration waiting time. The maximum event rate is determined by those skilled in the art based on the detector's irradiation dose rate, the scintillation crystal's luminescence decay time, and the system's dead time model. The maximum arbitration waiting time is calculated by those skilled in the art through queuing theory analysis based on the number of channels sharing the same high-speed serial link, the serial transmission duration of a single time data packet, and the longest waiting time of the adopted arbitration strategy. As a specific example, in this embodiment, the channel buffer queue depth is designed based on the M / D / 1 queuing theory model, fully considering the instantaneous fluctuation characteristics of the Poisson distribution of PET event arrivals. Here, 100kHz represents the peak-to-average count rate of a single channel, and in clinical scenarios, the instantaneous peak count rate of a single channel can reach more than 5 times the average count rate. Under the conditions of 64-channel round-robin arbitration and a service intensity of 0.2, the calculated queue overflow probability is less than 10%. -9The minimum required queue depth is 3. In this embodiment, the queue depth is set to 4, which satisfies the no-overflow requirement under the worst-case scenario and also reserves a safety margin of 1.3 times, which can fully adapt to the instantaneous fluctuations in the event rate under clinical conditions. The maximum event rate of a single channel under typical clinical positron emission tomography irradiation conditions is statistically approximately 100 kHz. The data frame length of a single time data packet after encapsulation is 98 bits. Under the condition of a high-speed serial link transmission rate of 5 gigabits per second, the transmission time of a single frame is 19.6 nanoseconds. There are 64 channels in the arbitration domain. When a round-robin priority arbitration strategy is adopted, in the worst-case scenario, a channel must wait for the other 63 channels in the same group to each send a data frame before it can regain the right to transmit. The maximum arbitration waiting time is 63 times 19.6 nanoseconds, which is approximately 1235 nanoseconds. During this worst-case waiting time, the maximum cumulative number of time data packets is 100 kHz times 1235 nanoseconds, which is approximately 0.13, rounded up to 1 time data packet. To ensure sufficient safety margin to accommodate instantaneous statistical fluctuations in the event rate, the channel buffer queue depth is set by those skilled in the art to four time data packets, i.e., four times the safety margin. The channel buffer queue is implemented using a first-in-first-out (FIFO) memory, as is known in the art, and its read / write pointer management follows FIFO queue operation rules.

[0177] S403. According to a preset arbitration strategy, select the channel currently granted transmission rights from among multiple channel buffer queues belonging to the same high-speed serial link, including:

[0178] S4031. Using the channel group corresponding to the channel group identifier as the arbitration domain, number each channel within the arbitration domain to obtain the channel sequence number of each channel within the arbitration domain.

[0179] In this embodiment, the core operation of this step is to form an arbitration domain by using all channels sharing the same high-speed serial link (i.e., a channel group). Within the arbitration domain, each channel is assigned a unique channel number, which serves as the basis for channel addressing and polling sorting in the arbitration logic. The engineering principle is that the channel numbers form a continuous integer address space within the arbitration domain. The arbitration state machine traverses this address space to sequentially query all channels within the domain. The continuity and uniqueness of the numbers ensure that no channel is missed or repeatedly queried in each arbitration cycle. As a specific example, in this embodiment, each arbitration domain corresponds to a channel group containing 64 channels, numbered sequentially from 0 to 63. The binary representation of the channel number is 6 bits, which can be directly used as the addressing input signal for the arbitration state machine without the need for additional address encoding conversion circuitry.

[0180] S4032. At the beginning of each arbitration cycle, starting from the next channel number of the service channel of the previous arbitration cycle, the empty / full status of the channel buffer queue of each channel is queried in the order of the channel number cyclically increasing.

[0181] In this embodiment, the core operation of this step is that, within each arbitration cycle, using the channel number as the traversal index, the arbitration state machine queries the current state of each channel's buffer queue in the domain one by one in a cyclically increasing order according to the starting position updated in the previous cycle, to determine whether there are any time data packets to be sent in the queue. Its engineering principle is based on the well-known polling arbitration mechanism: all channels in the arbitration domain are checked sequentially according to a pre-assigned fixed sequence number. Each channel's buffer queue status is queried once within the arbitration time slot corresponding to its channel number. This mechanism structurally ensures that each channel has an equal chance of obtaining the right to send, avoiding the problem of a certain channel being unable to receive service for a long time due to random competition. The arbitration state machine is implemented using a well-known finite state machine, with the state encoded as the currently queried channel number. The channel number is incremented once every system clock cycle, and the corresponding channel's buffer queue empty / full state is read and latched within that clock cycle. As a specific example, in this embodiment, the clock frequency of the arbitration state machine system is the same as that of the high-speed serial link transmission clock, set to 200 MHz, with each clock cycle being 5 nanoseconds, which is sufficient to cover the timing requirements of a buffer queue state query and comparison operation.

[0182] S4033. When the first non-empty state of the channel buffer queue is found, the channel is determined as the channel that currently has the right to send. After the time data packet of the channel is read, the query start position is updated to the next channel number of the channel, and the query for the next arbitration cycle begins.

[0183] In this embodiment, the core operation of this step is that once a non-empty buffer queue of a certain channel is detected during the polling query process, the current round of query is immediately stopped and the sending right is granted to that channel. After the data frame of that channel is encapsulated and sent, the arbitration state machine sets the query start position of the next arbitration cycle to the next channel number of that channel, and a new round of polling query begins from that position. Its engineering principle is based on the well-known round-robin priority arbitration algorithm: after each round of arbitration, the query start position is dynamically updated to the next channel number of the channel that received service in the previous round, rather than being fixed to channel zero. This ensures that all channels that were not served in the previous round move forward in priority in the next round, guaranteeing the long-term fairness of the arbitration service opportunity among all channels and preventing low-order channels from gaining implicit high priority due to a fixed reset of the query start position. The update of the query start position is achieved by adding 1 to the channel number of the channel that currently has the sending right and then performing a modulo operation. The modulus of the modulo operation is the total number of channels in the arbitration domain. As a specific example, in this embodiment, if the channel number of the currently obtained transmission right channel is 25, the query start position is updated to 26; if the channel number of the currently obtained transmission right channel is 63, which is the maximum number in the arbitration domain, the next query start position wraps around to 0 after modulo operation.

[0184] S404. Read the time data packet from the channel buffer queue of the channel, and encapsulate the time data packet into a serial data frame containing the channel group identifier and the time data packet during reading.

[0185] In this embodiment, the core operation of this step is to read a time data packet from its channel buffer queue in a first-in-first-out order after the current channel obtains the right to transmit. Then, according to the requirements of the serial data transmission protocol, a start-of-frame delimiter, a frame header field, a cyclic redundancy check (CRC) field, and a end-of-frame delimiter are added to this time data packet to form a complete serial data frame that can be independently transmitted and identified on a high-speed serial link. The engineering principle is as follows: the high-speed serial link receiver relies on the start-of-frame delimiter to locate the start boundary of the data frame, relies on the end-of-frame delimiter to determine the end position of the data frame, relies on the channel group identifier in the frame header field to route and distribute the data frame to the corresponding receiving and processing module, and relies on the CRC field to detect whether bit errors have occurred during the transmission of the data frame.

[0186] It should be further noted that, after the time data packet of this channel is read, this embodiment also includes:

[0187] S4041. When the channel buffer queues of all channels within the arbitration domain are found to be empty for K consecutive arbitration cycles, the arbitration domain is determined to have entered a link idle state. Arbitration operations for this arbitration domain are suspended, and idle data codes are continuously sent to the high-speed serial link until the channel buffer queue of any channel is detected to be non-empty. At this point, arbitration operations for this arbitration domain are resumed, and the transmission of the serial data frame is restarted. Here, K is determined by those skilled in the art based on the maximum permissible idle interval for link synchronization maintenance and the duration of a single arbitration cycle.

[0188] In this embodiment, the core operation of this step is to achieve a balance between optimizing the sleep power consumption of the arbitration operation and maintaining serial link synchronization during the time period when there is no valid data to be transmitted on the link. Its engineering principle consists of two aspects: First, the receiving end of the high-speed serial link uses a clock data recovery circuit, known in the art, to extract the synchronization clock from the received serial data stream. This circuit relies on the transition edges of logic levels in the data stream to continuously adjust the oscillation frequency and phase of the internal phase-locked loop, keeping the recovered clock synchronized with the transmitting clock. If no data is transmitted on the link for a long time, resulting in a continuous high or low level, the receiving end clock data recovery circuit will gradually lose lock due to the loss of transition edge reference, leading to frame header loss or bit slippage errors in subsequent recovered data frames. Therefore, even during idle periods when no valid data frames are transmitted, the link transmitting end must continuously transmit idle data codes with sufficient logic transition density to maintain the locked state of the receiving end clock data recovery circuit. On the other hand, during the period when all channel buffer queues are confirmed to be continuously empty, there is actually no valid data to be sent in the arbitration domain. If the arbitration state machine continues to perform polling operations cycle by cycle, it will waste dynamic power consumption. By setting K consecutive empty arbitration cycles as the threshold condition for determining that the link is idle, the steady-state idle state can be reliably identified, thereby safely suspending the arbitration operation to reduce power consumption. The number of consecutive idle cycles K is set based on the ratio of the maximum allowable idle interval for link synchronization to the duration of a single arbitration cycle. The maximum allowable idle interval for link synchronization is determined by the hold time characteristics of the phase-locked loop of the receiver clock data recovery circuit. The idle data code adopts the idle character sequence defined in the standard 8-bit to 10-bit encoding scheme known in the art. As a specific example, in this embodiment, the hold time index of the phase-locked loop of the receiver clock data recovery circuit is 5 microseconds, the duration of a single arbitration cycle is the total time required to query all 64 channels, that is, 64 clock cycles, each clock cycle is 5 nanoseconds, and the duration of a single arbitration cycle is 320 nanoseconds. The maximum permissible idle interval for link synchronization maintenance is determined by those skilled in the art to be 1 microsecond, corresponding to approximately 3 arbitration cycles, based on a safety factor of 0.2 after taking the holding time of the phase-locked loop in the receiver clock data recovery circuit. The K value is set to 3 by those skilled in the art, meaning that when all 64 channel buffer queues are detected to be empty for 3 consecutive arbitration cycles, the arbitration domain is determined to have entered a link idle state, arbitration operation is stopped, and the system switches to continuous idle data code transmission mode. When any channel buffer queue becomes non-empty due to the arrival of a new event, the buffer queue state change signal serves as a wake-up trigger, immediately resuming arbitration operation.

[0189] It should be further explained that, in this embodiment, the time data packet is encapsulated into a serial data frame containing the channel group identifier and the time data packet during reading, including:

[0190] S4042. After reading the time data packet, a frame start delimiter and a frame header field containing the channel group identifier are added to the beginning of the time data packet, and a cyclic redundancy check (CRC) field and a frame end delimiter are added to the end of the time data packet to obtain the serial data frame. The frame start delimiter and the frame end delimiter respectively use standard 8B / 10B control codes, and the CRC field is generated by a person skilled in the art through calculation of a check polynomial based on the data payload length and bit error rate requirements.

[0191] In this embodiment, the core operation of this step is to sequentially add a frame start delimiter, a frame header field, a cyclic redundancy check (CRC) field, and a frame end delimiter to the raw time data packet read from the channel buffer queue according to the frame structure template specified by the serial data transmission protocol, encapsulating it into a complete serial data frame. The engineering principle is as follows: the frame start delimiter is the reference codeword for frame synchronization at the receiving end; the receiving end determines the starting bit position of the data frame by continuously searching for this codeword; the frame end delimiter indicates the end of the current data frame; the receiving end considers a frame of data reception complete upon detecting this codeword; the frame header field carries the channel group identifier, used by the receiving end to route and distribute the data frame to the receiving processing module corresponding to that channel group; the CRC field is a checksum calculated by the sending end based on all bits of the time data packet and the frame header field using a specific generator polynomial; after receiving the data frame, the receiving end recalculates the checksum using the same generator polynomial and compares it with the received CRC field; if the two are inconsistent, it is determined that a bit error occurred during the transmission of the data frame. The standard 8B / 10B control codes are special control characters defined in 8-bit to 10-bit encoding schemes known in the art. The 10-bit encoding of these control characters has a sufficient Hamming distance to distinguish them from the 10-bit encoding of ordinary data characters, facilitating reliable differentiation at the receiving end. The selection of the parity check polynomial belongs to the cyclic redundancy check (CRC) code design method known in the art. The selection of the polynomial needs to comprehensively consider the data payload length, the target error detection rate, and the computational hardware complexity. As a specific example, in this embodiment, the start-of-frame delimiter uses the K28.5 control character defined in the 8B / 10B encoding scheme. Its 10-bit encoding has a unique comma alignment characteristic, which facilitates byte boundary alignment at the receiving end. The end-of-frame delimiter uses the K28.1 control character defined in the 8B / 10B encoding scheme. The channel group identifier in the frame header field has a bit width of 6 bits, corresponding to a maximum of 64 channel groups. The time data packet payload length is 64 bits. The cyclic redundancy check (CRC) field uses an 8-bit CRC generator polynomial known in the art, i.e., the generator polynomial is x^8 + x^2 + x^1 + 1. This polynomial can detect all single-bit errors, all double-bit errors, all odd-numbered bit errors, and burst errors with a length not exceeding 8 bits. The calculated check field length is 8 bits. In this embodiment, the CRC-8 check algorithm is used in the cyclic redundancy check field of the serial data frame. The complete parameter configuration is as follows: the generator polynomial hexadecimal representation is 0x07; the initial value is 0x00; the input data and output check value are not reversed in bit order; the output XOR value is 0x00; the check range covers the 6-bit channel group identifier in the frame header field and the 64-bit time data packet payload, and the high bits of any part that is less than a whole byte are padded with zeros to ensure that the check rules at both the sending and receiving ends are completely consistent, so as to achieve reliable detection of transmission errors.The total number of bits in a complete serial data frame is: 10 bits for the frame start delimiter, 6 bits for the frame header field, 64 bits for the time data packet payload, 8 bits for the cyclic redundancy check field, and 10 bits for the frame end delimiter, for a total of 98 bits.

[0192] S405. The serial data frame is sent to the back-end integrated circuit through the high-speed serial link, and an idle data code is sent within the frame interval of the serial data frame to maintain the synchronization state of the high-speed serial link.

[0193] In this embodiment, the core operation of this step is to sequentially send the encapsulated serial data frames as a bit stream to the physical layer serial transmitter. The serial transmitter converts the parallel data into a high-speed serial differential signal and drives it onto the differential signal line. During the frame interval between two consecutive serial data frames, the transmitter automatically inserts an idle data code, ensuring that the signal on the link remains a continuous bit stream without interruption. Its engineering principle is consistent with the idle data code transmission mechanism described in S4041, that is, maintaining the logic transition density in the data stream to ensure the continuous locking of the clock data recovery circuit at the receiving end. The difference from S4041 is that the link idle state involved in S4041 is a relatively long continuous idle period, accompanied by the pause of arbitration operations; while the frame interval involved in this step is a short gap that inevitably exists between every two data frames, occurring periodically during normal data transmission, and its duration is usually several clock cycles. The insertion of the idle data code is an operation automatically completed by the transmitter hardware logic, without the need for intervention from the upper-layer arbitration logic. As a specific example, in this embodiment, during the frame interval between two consecutive serial data frames, the transmitter hardware automatically sends 2 to 3 8B / 10B encoded idle characters. Each idle character contains more than 5 logic transitions in its 10-bit encoding, and the transition density meets the minimum transition density requirement of the receiver's clock data recovery circuit. The physical layer serial transmitter is implemented using a low-voltage differential signal driver known in the art, with its output common-mode voltage set to 1.2 volts and differential voltage swing set to 350 millivolts. These electrical parameters are matched and set by those skilled in the art based on the electrical specifications of the input buffer of the back-end integrated circuit receiver and the characteristic impedance of the transmission line.

[0194] S406. On the receiving side of the back-end integrated circuit, the time data packet is distributed to the corresponding conformity selection channel processing unit according to the channel group identifier and the channel identifier carried in the time data packet.

[0195] In this embodiment, the core operation of this step is that, within the back-end integrated circuit, based on the channel group identifier carried in the frame header field of the received and parsed serial data frame and the channel identifier carried in the intra-frame time data packet, the recovered time data packet is routed and distributed via the internal data bus to the conformance selection channel processing unit responsible for processing the detector channel events. The engineering principle is as follows: the channel group identifier constitutes the first-level routing address, used to distribute the data frame from the serial link receiving module to the channel group receiving buffer corresponding to that channel group, achieving demultiplexing from the link level to the channel group level; the channel identifier constitutes the second-level routing address, used within the channel group to further distribute the time data packet to the conformance selection channel processing unit uniquely corresponding to that channel, achieving demultiplexing from the channel group level to the single-channel level. This two-level address mapping constitutes a well-known hierarchical data routing addressing scheme, which can effectively reduce the decoding complexity of single-level routing. The coincidence selection channel processing unit is a coincidence selection logic circuit known in the art. Its function is to perform time window coincidence judgment on the event timestamps carried in the time data packets of different channels according to a preset standard time discrimination window, and identify two gamma photon event pairs belonging to the same positron annihilation event. As a specific example, in this embodiment, the back-end integrated circuit receiving side is configured with a total of 64 front-end data receiving modules. Each front-end data receiving module corresponds to a channel group. The 6-bit address signal of the channel group identifier is used to generate an enable signal for selection by a 6-to-64 address decoder. Each front-end data receiving module is configured with 64 coincidence selection channel processing units, corresponding to 64 detector channels. The 6-bit address signal of the channel identifier is used to generate an enable signal for selection by a 6-to-64 address decoder. The entire back-end integrated circuit contains a total of 4096 coincidence selection channel processing units, which correspond one-to-one with the total number of detector channels, realizing the full pipeline operation of time data packets from serial link reception, frame parsing, two-level routing distribution to coincidence selection processing.

[0196] This embodiment divides thousands of detector channels into several channel groups based on board-level interconnection pin constraints. Each group shares a high-speed serial link, achieving board-level transmission of 4096 channels' data within a limited 128-pin constraint using a converged transmission architecture with multiple channels sharing a single link. This fundamentally resolves the contradiction between pin count and channel size. By configuring a first-in-first-out (FIFO) buffer queue with a depth determined by worst-case queuing theory analysis for each channel, a safety design with a buffer depth four times the maximum accumulated data packet count ensures zero-loss temporary storage of time data packets while waiting for transmission rights, under conditions of a maximum arbitration waiting time of approximately 1235 nanoseconds and a maximum single-channel event rate of 100 kHz. This avoids event loss and system sensitivity degradation due to buffer overflow. A dynamic query mechanism based on a round-robin priority arbitration strategy is employed. The buffer queue status is queried channel by channel in ascending order of channel number, and the query start position is updated to the next sequence number after serving the current channel. This ensures long-term fairness in the transmission rights acquisition opportunity for each channel and avoids the implicit priority problem of lower-sequence channels. By encapsulating time data packets into standard serial data frames containing a start-of-frame delimiter, channel group identifier, cyclic redundancy check (CRC) field, and end-of-frame delimiter, and continuously transmitting idle data codes with sufficient transition density during frame intervals and link idle periods to maintain the locked state of the receiver's clock data recovery circuit, the link remains synchronized and uninterrupted between data frames and during arbitration sleep periods. Simultaneously, a link idle determination mechanism with three consecutive empty arbitration cycles safely suspends arbitration operations to reduce dynamic power consumption. By routing and distributing data frames at the back-end integrated circuit receiver based on a two-level address mapping of channel group identifier and channel identifier, the time data packets for 4096 channels are accurately delivered to the corresponding compliance selection channel processing units. This achieves a fully pipelined, non-blocking data path from serial link reception to compliance selection processing, providing complete, reliable, and real-time full-channel time and energy data input for the back-end compliance selection stage.

[0197] It should be further explained that the compliance determination in this embodiment is performed in the back-end integrated circuit, including the following steps:

[0198] S501. Parse the received time data packets from each channel, extract the channel identifier, event timestamp, and digitized time data representing gamma photon energy information carried in each time data packet, and store the extraction results in the event queue of the corresponding channel according to the time order of the event timestamp.

[0199] In this embodiment, the timestamps for all-channel synchronization events are generated through a global synchronization clock architecture. The 400MHz reference clock output by the global reference clock generator is distributed to the timestamp counters of each channel via a full-chip balanced clock tree, ensuring that the phase deviation of the clocks of all channel counters is less than 10ps. Each channel is configured with a 32-bit free-running timestamp counter, with the counting clock being the same 400MHz global reference clock and a counting step size of 2.5ns. When the first flip edge of the channel energy-time pulse signal arrives, the value of the current timestamp counter is immediately latched as the event timestamp, ensuring that the timestamps of all channels are based on the same global time reference, and the synchronization error between channels is less than 50ps, providing a unified time scale for the back-end full-channel compliance selection. In this embodiment, the core operation of this step is to perform frame parsing and data field extraction on the serial data frames received and recovered from each high-speed serial link at the input interface layer of the back-end integrated circuit. The three elements of each event, namely the channel identifier, the event timestamp, and the digitized time data, are separated and stored in the independent event queue of each channel according to the order of the timestamps, providing a time-ordered data view for subsequent time sorting and compliance pairing. The engineering principle is as follows: event data from different channels on the same high-speed serial link are interleaved and transmitted in an arbitration round-robin order. The timestamps of events in each channel within the recovered event stream are not strictly globally monotonically increasing. If a coincidence selection is directly performed on the unordered event stream, a large number of missed matches will occur due to time disorder. Therefore, by configuring an event queue ordered by timestamp for each channel, the time order of events can be restored within the channel, and time alignment of all channel events can be achieved through a global comparison of the timestamps at the head of each channel's queue. The event queue is implemented using a priority queue based on content-addressable memory, a method known in the art. Its insertion operation automatically maintains the order within the queue according to the timestamp size. As a specific example, in this embodiment, the back-end integrated circuit is configured with 4096 channel event queues, corresponding one-to-one with the detector channels. The maximum depth of each queue is determined by those skilled in the art to be 8 events based on the maximum event rate and the processing delay of a single coincidence selection cycle, which is sufficient to cover the worst-case event accumulation number generated by the same channel within a time window of approximately 800 nanoseconds.

[0200] S502. In the event queue of each channel, the minimum timestamp of the event at the head of each queue is used as the current reference timestamp. Events in all channels whose event timestamps are less than the current reference timestamp minus half the width of the preset standard time discrimination window are marked as timeout events, and the timeout events are removed from the corresponding event queue.

[0201] In this embodiment, the core operation of this step is to establish a dynamically sliding time window benchmark for matching selection through global time benchmark maintenance and expired event removal. Expired events that can no longer be matched with any unprocessed events are promptly removed from the queue, preventing the unlimited growth of the event queue and the infinite expansion of downstream matching operations. The judgment logic is as follows: the current benchmark timestamp is defined as the minimum value of the timestamps of the first events in all non-empty event queues. The preset standard time discrimination window is full width W, and half width W / 2. If the timestamp of an event is less than T0 - W / 2 (T0 is the current benchmark timestamp), then the time difference between the event and T0 exceeds half the window width. Since T0 is the earliest global unprocessed event timestamp, this event can never be matched with any subsequent unprocessed events and can be safely removed. The removal operation of expired events releases the storage space of the corresponding event queue, and the removed events are marked as single-photon background events and discarded. As a specific example, in this embodiment, the preset standard time discrimination window has a full width of 18 nanoseconds and a half width of 9 nanoseconds. If the current reference timestamp is 100 nanoseconds, all events with timestamps less than 91 nanoseconds are judged as timeout events and removed. The preset standard time discrimination window with a full width of 18 nanoseconds is based on the balance between the system's efficiency in capturing true coincidence events and suppressing random coincidence noise. Its value is determined by multiplying the sum of the squares of the time broadening components of each stage by a coverage coefficient.

[0202] The standard time discrimination window is set based on a complete link from physical processes to electronic measurements. The embodiment specifies that the maximum time difference caused by the uncertainty of the positron annihilation position, the pulse arrival time jitter caused by the decay time of the scintillation crystal, the time measurement errors introduced by various front-end electronics components, and the system target time resolution are all considered. The total time broadening value is obtained by combining these time broadening components using the root of square. Specifically, the embodiment calculates the maximum path difference (light speed flight time) corresponding to a detector ring diameter of 80 cm to be approximately 2.7 nanoseconds; the pulse time jitter caused by the decay time of the LYSO scintillation crystal is controlled to within approximately 0.5 nanoseconds after front-end signal conditioning; the total time error introduced by various front-end electronics components is measured to be approximately 0.3 nanosecond root mean square; and the system target time resolution is set to 1 nanosecond. The total time broadening after combining the above components using the root of square is approximately 3 nanoseconds.

[0203] Based on this, the embodiment uses ±3 times the standard deviation, or ±9 nanoseconds, as the preset standard time discrimination window, with a total window width of 18 nanoseconds. This coverage coefficient is set according to the 3σ principle of normal distribution in statistics. When the window width covers the interval corresponding to 3 times the standard deviation of the total time span, the capture efficiency for true matching event pairs is no less than 99.7%, minimizing the possibility of missing true matching events due to time fluctuations, while effectively excluding random matching events outside the window. This ensures both accuracy and reliability in matching selection while maintaining high-sensitivity imaging of the system.

[0204] S503. Perform full-channel pairing of candidate events in all non-empty event queues within the time window corresponding to the current reference timestamp, calculate the timestamp difference for each pair of candidate events, and when the absolute value of the timestamp difference is less than or equal to the preset standard time discrimination window, determine the pair of candidate events as a pair of matching events.

[0205] In this embodiment, the core operation of this step is to perform pairwise time difference calculation and window decision on all candidate events from different channels within the effective time range defined by the standard time discrimination window centered on the current reference timestamp, using time correlation as the sole physical criterion for conformity determination. The engineering principle is that if two gamma photon events from different channels can form a conformity pair, their timestamp difference must fall within the standard time discrimination window; conversely, if the timestamp difference of the two events exceeds the window, the probability that they originate from different annihilation events is dominant. The pairing process is only performed between different channels. Two events arriving in the same channel cannot originate from the same annihilation due to their opposite flight directions, and are directly excluded from pairing to reduce invalid computation. The full-channel pairing is implemented in hardware using a pipelined comparison tree architecture known in the art, which copies and distributes the events to be paired to multiple parallel comparison units. Each comparison unit is responsible for calculating the pairwise time difference within a subset of channels, and the calculation results are aggregated at the next level and a conformity determination flag is output. As a specific example, in this embodiment, when there are 4096 channel event queues and 150 non-empty queues at a certain moment, the pairing operation is 150 multiplied by 149 divided by 2, which is approximately 11175 time difference comparisons. Under the condition of a system clock of 200 MHz, all comparisons can be completed within a single compliance selection cycle through pipelined processing by 64 parallel comparison units.

[0206] S504. When multiple candidate events simultaneously meet the matching conditions with the same event, the candidate event that best matches the energy information and the digitized time data corresponding to the 511keV full-energy deposition is selected according to the preset multi-event arbitration strategy to form a matching event pair.

[0207] In this embodiment, the core operation of this step is to handle the common multi-event pairing ambiguity problem in the selection process: due to the high event rate and relatively wide time window, there may be situations where the time difference between one event and multiple events from different channels are all within the standard discrimination window. This step eliminates ambiguity by introducing an energy window constraint. The physical basis is that the energy deposited in the scintillation crystal by a true 511keV annihilation photon pair is all 511keV full energy, and the corresponding energy digitization time data should fall within a preset energy window. If multiple pairs meet the time compliance condition, the pair with the energy closest to the center value of the 511keV photoelectric peak is selected; if none meet the energy window, all are discarded. The center value of the preset energy window is the nominal value of the energy digitization time data corresponding to 511keV, and the window width is determined by those skilled in the art based on the system's target energy resolution. As a specific example, in this embodiment, the nominal value of the digitized time data corresponding to 511keV full energy deposition is 2048, the system target energy resolution is 12%, and the preset energy window is set to the range of ±15% of the nominal value, i.e., 1741 to 2355. When both candidate events meet the time matching condition with the event, the absolute value of the difference between the digitized time data of the two candidate events and 2048 is calculated, and the candidate event with the smaller absolute value is selected to form a matching event pair.

[0208] S505. Pack the channel identifier, event timestamp, and energy digitization time data carried by each of the two events in the identified matching event pair into a matching event data packet, and output it to the PET image reconstruction unit.

[0209] In this embodiment, the core operation of this step is to encapsulate and output the relevant information of the successfully matched event pair according to the format required by the reconstruction unit. The matched event data packet includes the channel identifiers of the two paired channels, the precise timestamps of the two events, the energy digitization time data of the two events, and the time-of-flight difference calculated from the two timestamps. The PET image reconstruction unit is an image reconstruction computer or hardware accelerator known in the art. After receiving the matched event data packet, it generates a three-dimensional image reflecting the tracer distribution through a time-of-flight reconstruction algorithm. As a specific example, in this embodiment, the total length of the matched event data packet is 128 bits, including 6 bits of source channel identifier, 6 bits of destination channel identifier, 32 bits of source event timestamp, 32 bits of destination event timestamp, 12 bits of source energy digitization time data, 12 bits of destination energy digitization time data, and 16 bits of the time-of-flight difference calculated in real time by the hardware subtractor. The remaining 12 bits are reserved fields. The matched event data packet is transmitted to the image reconstruction unit through the high-speed peripheral interconnect interface of the back-end integrated circuit. The transmission bandwidth is set by those skilled in the art based on the maximum matched event rate of the system.

[0210] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the protection scope of the present invention.

Claims

1. A method for high-integration processing of energy-time converted multi-channel PET signals, characterized in that, include: The configured sensor system acquires the charge pulse signals generated by each channel of the silicon photomultiplier tube in response to gamma photons arriving at the scintillation crystal. The charge pulse signals are conditioned by a front-end passive filter network and an impedance matching circuit, and the conditioned charge pulses are output. The conditioned charge pulse is input into the charge-time converter, and the conditioned charge pulse is used to charge the internal integrating capacitor. When the voltage of the integrating capacitor reaches a preset reference threshold, the comparator is triggered to flip, generating an energy-time pulse signal whose pulse width is proportional to the total amount of input charge. The energy-time pulse signal output from each channel is measured by a multi-channel time-to-digital converter, and the pulse width or time interval of the energy-time pulse signal is digitized using a time reference to obtain digital time data characterizing gamma photon energy information. The digitized time data, along with the corresponding channel identifier and event timestamp, is encapsulated into a time data packet. The time data packets from multiple channels are then aggregated and transmitted to the back-end integrated circuit via a high-speed serial interface. The back-end integrated circuit performs a matching judgment on the timestamps carried in the time data packets of different channels according to a preset standard time discrimination window, identifies two gamma photon event pairs belonging to the same annihilation event, and extracts the corresponding energy information and time information for PET image reconstruction.

2. The energy-time converted multi-channel PET signal high-integration processing method according to claim 1, wherein, The step of conditioning the charge pulse signal through a front-end passive filter network and impedance matching circuit to output a conditioned charge pulse includes: The leading edge of the charge pulse signal is detected to obtain the rising slope value of the leading edge; The rising slope value of the pulse leading edge is compared with a preset slope threshold, and the signal conditioning mode is determined based on the comparison result: When the rising slope of the pulse leading edge is greater than or equal to the preset slope threshold, the pulse fidelity mode is entered. When the rising slope of the pulse leading edge is less than the preset slope threshold, noise suppression mode is entered. In the pulse fidelity mode, the first set of passive component parameters is selected to configure the front-end passive filter network. The first set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network higher than the equivalent bandwidth of the leading edge of the charge pulse signal, so that the amplitude attenuation of the component in the charge pulse signal whose frequency is within the equivalent bandwidth of the leading edge of the pulse is lower than the preset fidelity attenuation threshold after passing through the front-end passive filter network. In addition, the first set of passive component parameters makes the leading edge time jitter of the conditioned charge pulse less than the preset time jitter tolerance.

3. The energy-time converted multi-channel PET signal high-integration processing method according to claim 2, characterized in that, The step of conditioning the charge pulse signal through a front-end passive filter network and impedance matching circuit to output a conditioned charge pulse further includes: In noise suppression mode, the second set of passive component parameters is selected to configure the front-end passive filter network. The second set of passive component parameters makes the -3dB cutoff frequency of the front-end passive filter network lower than the equivalent bandwidth of the pulse leading edge, and makes the stopband start frequency of the front-end passive filter network lower than the lower limit frequency of the preset dark count noise characteristic frequency band, so that the stopband attenuation provided by the front-end passive filter network for signal components whose frequency is within the preset dark count noise characteristic frequency band is greater than the preset noise suppression threshold. Obtain the first output impedance presented at the output terminal of the front-end passive filter network when using the first set of passive component parameters in pulse fidelity mode; or, obtain the second output impedance presented at the output terminal of the front-end passive filter network when using the second set of passive component parameters in noise suppression mode. Based on the first or second output impedance, adjust the reactance value of the variable reactance element in the impedance matching circuit so that the input impedance of the impedance matching circuit and the output impedance presented by the front-end passive filter network in the current operating mode satisfy the conjugate matching condition that the real parts are equal and the absolute values ​​of the imaginary parts are equal but opposite in sign. This ensures that the reflection coefficient at the output of the front-end passive filter network is greater than or equal to zero and less than the preset reflection coefficient threshold, resulting in a conditioned charge pulse without pulse ringing.

4. The energy-time converted multi-channel PET signal high-integration processing method according to claim 3, characterized in that, The generation of the energy-time pulse signal with a pulse width proportional to the total input charge includes: Obtain the peak amplitude of the conditioned charge pulse; The peak amplitude is compared with a preset upper limit threshold of the linear interval, and the input capacitance value of the integrating capacitor is determined based on the comparison result, specifically as follows: When the peak amplitude is less than or equal to the upper limit threshold of the preset linear interval, the integrating capacitor is configured to a first capacitance value. The integrated capacitor connected with the first capacitance value is charged using the conditioned charge pulse. At the first moment when the integrated voltage across the integrating capacitor rises from the initial level to the preset reference threshold, the comparator is triggered to generate a first flip edge. At the second moment when the conditioned charge pulse is detected to have ended, the comparator is triggered to generate a second flip edge, thereby obtaining an energy-time pulse signal with a pulse width equal to the time interval between the first moment and the second moment.

5. The energy-time converted multi-channel PET signal high-integration processing method according to claim 4, characterized in that, The generation of the energy-time pulse signal with a pulse width proportional to the total input charge also includes: When the peak amplitude is greater than the upper limit threshold of the preset linear interval, the integrating capacitor is configured with a second capacitance value. The integrated capacitor connected with the second capacitance value is charged using the conditioned charge pulse. At a third moment when the integrated voltage across the integrating capacitor rises to the preset reference threshold, the comparator is triggered to generate a first flip edge. At a fourth moment when the conditioned charge pulse is detected to have ended, the comparator is triggered to generate a second flip edge, resulting in an energy-time pulse signal with a pulse width equal to the time interval between the third and fourth moments. The second capacitance value is greater than the first capacitance value, and the... The second capacitor value is configured such that when the conditioned charge pulse has the maximum input charge, the peak value of the integral voltage does not exceed the upper limit of the preset integrator output swing; wherein, the second capacitor value is determined as follows: when the total input charge of the conditioned charge pulse is any measured value within the entire preset dynamic range, the absolute value of the deviation between the pulse width measurement value of the energy-time pulse signal corresponding to that measured value and the ideal linear pulse width value is less than a preset pulse width nonlinearity tolerance; the ideal linear pulse width value is a linear interpolation determined by the pulse width reference value corresponding to the minimum input charge and the pulse width full-scale value corresponding to the maximum input charge.

6. The method for highly integrated processing of multi-channel PET signals with energy-time conversion as described in claim 5, characterized in that, The digitized time data used to obtain gamma photon energy information includes: The energy-time pulse signals output from each channel are respectively connected to the delay chain input of the corresponding channel in the multi-channel time-to-digital converter, so that the energy-time pulse signals propagate step by step along the unit delay unit of the delay chain. The output state of each stage of the delay chain is latched by a global reference clock synchronized with the time base, so that the pulse width of the energy-time pulse signal is quantized in the delay chain to be an integer multiple of the unit delay unit of the delay chain, thereby obtaining coarse count data and fine count data corresponding to the pulse width. For the current processing channel in each channel, obtain the fine count data of the current processing channel, extract the phase offset feature value caused by crosstalk between the current processing channel and the adjacent channel in the fine count data, and compare the phase offset feature value with a preset crosstalk tolerance threshold. When the phase offset characteristic value is greater than the preset crosstalk tolerance threshold, crosstalk compensation correction is performed on the coarse count data or fine count data of the current processing channel to obtain corrected digitized time data, and the corrected digitized time data is output as the digitized time data.

7. The method for highly integrated processing of multi-channel PET signals with energy-time conversion as described in claim 6, characterized in that, The digitized time data used to obtain gamma photon energy information also includes: When the phase offset characteristic value is less than or equal to the preset crosstalk tolerance threshold, the coarse count data and fine count data of the current processing channel are merged and directly output as the digitized time data; The delay amount of a unit delay unit in the delay chain is determined by the period of the time reference and the number of stages in the delay chain. The delay amount of the unit delay unit is configured such that the quantization error of the digitized time data is less than a preset time quantization error tolerance in the full dynamic range of the energy-time pulse signal from the minimum pulse width to the maximum pulse width.

8. The highly integrated multi-channel PET signal processing method for energy-time conversion as described in claim 7, characterized in that, The step of aggregating and transmitting the multi-channel time data packets to the back-end integrated circuit via a high-speed serial interface includes: A high-speed serial link is configured for each group of a preset number of channels, and each high-speed serial link is connected to a serial data transmission port. The preset number is determined by the maximum integer number of links obtained by dividing the total number of board-level interconnect pins by the number of pins required for each high-speed serial link. When any channel generates the time data packet, the time data packet of the channel is written into the channel buffer queue corresponding to the channel. The depth of the channel buffer queue is configured to be at least greater than the number of time data packets accumulated by the channel under the maximum event rate and the maximum arbitration waiting time. According to the preset arbitration strategy, the channel that currently has the right to send is selected among multiple channel buffer queues belonging to the same high-speed serial link. The time data packet is read from the channel buffer queue of the channel, and the time data packet is encapsulated into a serial data frame containing the channel group identifier and the time data packet during reading.

9. The highly integrated multi-channel PET signal processing method with energy-time conversion as described in claim 8, characterized in that, The method of aggregating and transmitting the multi-channel time data packets to the back-end integrated circuit via a high-speed serial interface further includes: The serial data frame is sent to the back-end integrated circuit through the high-speed serial link, and an idle data code is sent within the frame interval of the serial data frame to maintain the synchronization state of the high-speed serial link. On the receiving side of the back-end integrated circuit, the time data packet is distributed to the corresponding conformity selection channel processing unit according to the channel group identifier and the channel identifier carried in the time data packet.

10. The highly integrated multi-channel PET signal processing method for energy-time conversion as described in claim 9, characterized in that, The step of selecting the channel currently granted transmission rights from multiple channel buffer queues belonging to the same high-speed serial link according to a preset arbitration strategy includes: Using the channel group identifier corresponding to the channel group as the arbitration domain, each channel is numbered within the arbitration domain to obtain the channel sequence number of each channel within the arbitration domain. At the beginning of each arbitration cycle, starting from the next channel number of the service channel of the previous arbitration cycle, the empty / full status of the channel buffer queue of each channel is queried in the order of the channel number cyclically increasing. When the first non-empty state of the channel buffer queue is found, the channel is determined as the channel that currently has the right to send. After the time data packet of the channel is read, the query start position is updated to the next channel number of the channel, and the query for the next arbitration cycle begins.

11. The highly integrated multi-channel PET signal processing method with energy-time conversion as described in claim 10, characterized in that, After the time data packet in the channel is read, the process further includes: When the channel buffer queues of all channels within the arbitration domain are found to be empty for K consecutive arbitration cycles, the arbitration domain is determined to have entered a link idle state. Arbitration operations for the arbitration domain are suspended, and the idle data code is continuously sent to the high-speed serial link until the channel buffer queue of any channel is detected to be non-empty. Then, the arbitration operations for the arbitration domain are resumed, and the transmission of the serial data frame is restarted.

12. The highly integrated multi-channel PET signal processing method with energy-time conversion as described in claim 11, characterized in that, The step of encapsulating the time data packet into a serial data frame containing the channel group identifier and the time data packet during reading includes: After reading the time data packet, a frame start delimiter and a frame header field containing the channel group identifier are added to the beginning of the time data packet, and a cyclic redundancy check field and a frame end delimiter are added to the end of the time data packet to obtain the serial data frame.

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