A deterministic service guarantee method for a multi-tenant solid state disk, a master control chip and a storage medium

Abstract

The application discloses a deterministic service guarantee method of a multi-tenant solid state disk, a main control chip and a storage medium. The method comprises the following steps: configuring a data stream as a virtual function unit, locking a physical address by using an address boundary protection circuit to divide an independent buffer partition; time consumption of a macro instruction is evaluated and the macro instruction is disassembled into a micro instruction sequence with the same length, and a metadata label is added; when a micro instruction identifier matches a white list, a transmission path is guided from a shared bus to a point-to-point cross switch matrix, and a vertical through-hole silicon direct connection flash memory interface is used; at an exit of a flash memory channel, a difference between an actual occupation time length and a standard execution unit is calculated, and a time slot is forced to switch when a difference trigger blocking signal is triggered; a physical operation delay state is collected as a congestion measurement index, a token deduction coefficient is calculated when the index exceeds a delay trigger threshold, and a token generation rate is dynamically adjusted. The application solves the storage jitter problem in the multi-tenant environment and ensures the high-deterministic service quality.

Description

Technical Field

[0001] This application relates to the field of storage control technology, and in particular to a deterministic service assurance method for a multi-tenant solid-state drive, a controller chip, and a storage medium. Background Technology

[0002] In multi-tenant cloud computing or virtualized storage platforms, multiple virtual machines share the same physical solid-state drive (SSD) through single-root input / output virtualization (SR-IOV) technology. Read and write requests from different virtual machines converge within the SSD controller, competing for the on-chip static random access memory (SRAM), direct memory access (DMA) engine, on-chip system bus, and back-end flash memory channels.

[0003] Traditional technologies typically employ dynamic buffer allocation and simple weighted round-robin scheduling at the software layer. However, this design operates in a "best-effort" transmission mode. When faced with mixed read / write conditions, low-priority consecutive large block write requests (such as 128KB) and high-priority small block random read requests (such as 4KB) are prone to resource contention within the controller, resulting in severe latency jitter for high-priority requests.

[0004] When large amounts of data are queued in SRAM, the large space they occupy and the long processing time can cause the buffer to remain saturated for extended periods. If, at this point, the back-end flash memory chips trigger a data read retry at the lower level due to physical wear or temperature fluctuations (resulting in a tiny delay of only tens of microseconds per attempt), this minor physical fluctuation can bypass the saturated queuing chain of the buffer memory and be instantly amplified into cascading blockages lasting hundreds of microseconds or even milliseconds. This causes the tail latency (P99.99) of high-priority read requests to completely spiral out of control.

[0005] Therefore, existing technologies have the technical problem of being unable to prevent the cascading coupling between front-end buffer congestion and back-end media fluctuations. Summary of the Invention

[0006] The application provides a deterministic service assurance method, controller chip, and storage medium for multi-tenant solid-state drives, which can solve the aforementioned technical problems existing in related technologies. The technical solution is as follows: Firstly, a deterministic service guarantee method for multi-tenant solid-state drives is provided, including the following steps: S1: Configure the data stream processed by the solid-state drive controller chip as at least one virtual functional unit, allocate physical buffer capacity to each virtual functional unit according to the preset service level agreement parameters, and divide the static random access memory into independent buffer partitions with non-contiguous addresses using the address boundary protection circuit. The address boundary protection circuit is configured with a start address register and a length limit register. Lock the physical address boundary of the partition through the start address register and the length limit register, so that the data addressing space of each virtual functional unit is in a physically isolated state. S2: Evaluate the time consumption of macro instructions entering the solid-state drive controller chip, decompose them into multiple micro-instruction sequences with the same expected physical operation time, and add a micro-instruction identifier to each micro-instruction. The micro-instruction identifier contains metadata tags used to characterize the business source and execution priority information. S3: Parse the microinstruction identifier. When the identifier matches the preset service whitelist, trigger the switching control level and redirect the transmission path from the system shared bus to the point-to-point cross switch matrix. The microinstruction data is then directly connected to the flash memory control interface via the vertical metal silicon via array, allowing the microinstruction data to bypass the bus arbitration logic for transmission. S4: Periodically perform time slot allocation at the flash channel exit, monitor the actual occupancy time of concurrent service channels through the difference calculation matrix, calculate the difference between the actual occupancy time and the preset standard execution unit, and when the difference triggers a blocking signal, reject the enable request of the channel and force a switch to the time slot of the next service. S5: The physical operation delay status of the underlying flash interface is collected through the physical state feedback loop as a congestion metric. When the congestion metric exceeds the preset delay trigger threshold, the token deduction coefficient is calculated using the physical state feedback loop and applied to the token bucket counter of the corresponding service channel to dynamically adjust the token generation rate and control the congestion within the local physical link.

[0007] In one possible implementation, the physical buffer capacity is determined in step S1 as follows: Using the product of the average queue depth and the maximum data packet size of each virtual functional unit as a baseline value, the product of the unit's traffic standard deviation and the preset security margin coefficient is accumulated, and then multiplied by the service level agreement allocation weight to obtain the specific value of the physical buffer capacity.

[0008] In one possible implementation, the mechanism for locking the physical address boundaries of the partition in step S1 is as follows: The bus monitoring circuit in the address boundary protection circuit compares the target address of the real-time storage access instruction with the range defined by the start address register and the length limit register. If the target address exceeds the defined range, the hardware logic circuit automatically rejects the storage access request.

[0009] In one possible implementation, step S2, which involves evaluating the time consumption of macro instructions entering the solid-state drive controller chip and breaking them down into multiple microinstruction sequences with the same expected physical operation duration, specifically includes: Collect the physical state parameters of the target flash memory chip pointed to by the macro instruction, including the number of wear erase cycles, programming write mode, and channel queuing depth; Calculate the expected physical operation time curve of the macro instruction in the logical address space based on the physical state parameters; The macro instruction is divided into multiple micro instruction sequences by dividing the expected physical operation time curve into equal integral values, with the dividing nodes as the dividing boundaries, so that the expected physical operation time deviation between adjacent micro instructions is less than a preset time deviation threshold.

[0010] In one possible implementation, step S3 specifically includes: The microinstruction identifier is parsed. When the identifier matches the preset service whitelist, the switching control level is triggered, driving the transmission path to switch from the system shared bus to the point-to-point cross switch matrix, and establishing a physical direct connection with the flash memory control interface via the vertical metal silicon via array. The physical connectivity level of the point-to-point cross switch matrix is ​​monitored in real time by the routing status detection circuit. When an abnormal connectivity level is detected, the switching control level is controlled to force the transmission path back to the system shared bus and a path status warning signal is sent to the main control chip register.

[0011] In one possible implementation, step S4 specifically includes: The difference calculation matrix is ​​used to calculate in real time the difference between the actual occupancy time of the business channel corresponding to each virtual functional unit and the preset standard execution unit; When the difference triggers the blocking signal, the enable request for the service channel is rejected, and the service is forcibly switched to the next service time slot. The blocking signal synchronously updates the time slot weight of the time slot allocator in the next cycle to dynamically adjust the allocation ratio of subsequent enable requests, thereby achieving closed-loop control of flash channel occupancy time and time slot allocation.

[0012] In one possible implementation, step S5 involves collecting the physical operation latency status of the underlying flash interface via a physical state feedback loop as a congestion metric. When the congestion metric exceeds a preset latency trigger threshold, the token deduction coefficient is calculated using the physical state feedback loop. Specifically, this includes: The physical state feedback loop calculates a token deduction coefficient that is inversely proportional to the congestion metric based on the degree to which the congestion metric exceeds the preset delay trigger threshold. The token bucket counter responds to the token deduction coefficient by reducing the token generation frequency until the congestion metric falls back to within the preset delay trigger threshold.

[0013] In one possible implementation, step S5, which involves using the token bucket counter of the corresponding service channel to dynamically adjust the token generation rate, further includes: After the token bucket counter responds to the token deduction coefficient by reducing the token generation frequency, it sends the current remaining total number of tokens to the feedback unit. The feedback unit compares the rate of decrease of the congestion metric before and after the token deduction coefficient takes effect to determine whether the preset transmission stability benchmark is met. When it is determined that the rate of decrease of the congestion metric has not reached the preset transmission stability benchmark, the feedback unit sends an incremental adjustment command to the physical state feedback loop to drive the physical state feedback loop to increase the token deduction coefficient until the congestion metric falls back to within the preset delay trigger threshold.

[0014] Secondly, a deterministic service assurance master control chip is provided, the master control chip comprising: Address boundary protection circuit, macro instruction splitting and reconfiguration hardware, point-to-point cross switch matrix, difference calculation matrix and physical state feedback loop; The address boundary protection circuit, macro instruction splitting and reconstructing hardware, point-to-point cross switch matrix, difference calculation matrix and physical state feedback loop are physically connected through internal circuit topology to construct hardware logic execution link; in: The address boundary protection circuit includes a start address register and a length limit register, and its output is connected to the bus enable control terminal. The macro instruction segmentation and reconstruction hardware includes an instruction parsing circuit, a time consumption calculation unit, and an integral segmentation logic, the output of which is connected to the first-in-first-out queue of the flash memory controller. The point-to-point cross switch matrix includes a bypass trigger register and a multiplexer, and its output is connected to the flash memory control interface through a vertical through-silicon via. The difference calculation matrix includes a subtractor array and a comparator network, and its output blocking signal is connected to a time slot distributor. The physical state feedback loop includes a hardware timer and a token deduction coefficient generator, the output of which is connected to a token bucket counter.

[0015] Thirdly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect and its possible implementations.

[0016] The beneficial effects of the technical solution provided in this application include at least the following: This application establishes a deterministic input / output dedicated line directly to the flash memory medium at the hardware level of the solid-state drive controller chip through the synergistic effect of five steps. Step S1 achieves spatial isolation of each virtual functional unit in the on-chip buffer memory, cutting off the spatial coupling between different tenants; Step S2 divides large-size write macro instructions into time-equivalent micro-instruction sequences, eliminating the non-homogeneity of instruction execution time; Step S3 opens a physical bypass channel for high-priority micro-instructions, realizing direct physical transmission at the nanosecond level; Step S4 performs guaranteed time allocation and anti-intrusion compensation at the flash channel exit, realizing absolute fair decision-making for microsecond-level time slots; Step S5, through string-stabilized feedback adjustment, collects the physical operation latency status of the underlying flash interface in real time, dynamically adjusts the token generation rate, and locally smooths out flash physical fluctuations.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a deterministic service guarantee method for multi-tenant solid-state drives provided in an embodiment of this application. Figure 2 This is a schematic diagram of the structure of a deterministic service assurance main control chip provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] In multi-tenant shared SSD scenarios, the reason why the tail latency of high-priority read requests deteriorates from tens of microseconds to milliseconds is rooted in the "cascading amplification effect" of congestion in the front-end on-chip buffer and physical random latency of the back-end flash memory. Specifically, when low-priority large-block write requests fill the buffer space, if the back-end flash memory chips trigger read retry due to physical wear or temperature fluctuations (each retry lasting only tens of microseconds), this tiny fluctuation is instantly amplified along the saturated queuing chain, ultimately causing the latency of high-priority read requests to completely spiral out of control. To break this cascading coupling, a single isolation or scheduling algorithm cannot be relied upon; a complete closed-loop control system must be built from the buffer to the flash memory channel. Based on this understanding, this application provides a deterministic service guarantee method for multi-tenant SSDs.

[0023] See Figure 1 , Figure 1 This is a flowchart illustrating a deterministic service assurance method for multi-tenant solid-state drives provided in this application embodiment. The method includes the following steps: Step S1: Configure the data stream processed by the solid-state drive controller chip as at least one virtual functional unit, and allocate physical buffer capacity to each virtual functional unit according to the preset service level agreement parameters. Utilize the address boundary protection circuit in the solid-state drive controller chip to divide the static random access memory into independent buffer partitions with non-contiguous addresses. The address boundary protection circuit is configured with a start address register and a length limit register for limiting each buffer partition, so as to lock the physical address boundary of the partition through the start address register and the length limit register, so that the data addressing space of each virtual functional unit is in a physically isolated state.

[0024] In a multi-tenant scenario, read and write data from different virtual functional units first enters the on-chip static random access memory (SRAM) of the main control chip. If all data is coexisting in the same memory area, large blocks of low-priority write data will quickly fill the buffer space, leaving no place for high-priority read requests, thus creating the first level of congestion. Therefore, the core problem to be solved in step S1 is: how to completely isolate the buffer spaces of different virtual functional units at the physical level.

[0025] Specifically, the first issue to be addressed is how much buffer capacity should be allocated to each virtual functional unit.

[0026] During the initialization self-test or factory configuration phase of the SSD controller chip, the scheduler calculates a physical buffer budget capacity with a locked boundary for each configured virtual functional unit (VFU). The firmware scheduler reads the Service Level Agreement (SLA) parameters pre-stored in the non-volatile flash memory, obtains the historical peak read / write ratio and maximum queue depth of each enabled VFU in the current physical SSD, and establishes a traffic characteristic profile. Based on the characteristic profile of each VFU, the controller processor first calculates a baseline value: the product of the average queue depth and the maximum packet size of each VFU is used as the baseline value. Then, the product of the standard deviation of the unit's traffic and a preset safety margin coefficient is accumulated, and finally, the SLA allocation weight is multiplied to obtain the specific value of the physical buffer capacity. Here, the baseline buffer value represents the basic buffer space required by the VFU under normal load, the safety margin coefficient is used to absorb sudden fluctuations in traffic, and the preferred value range of the safety margin coefficient is 1.2 to 1.5. The SLA allocation weight reflects the priority differences between different VFUs. Through this static budget calculation, the originally dynamically fluctuating memory allocation requirements are transformed into physical constants that can be directly controlled by the chip registers during the initialization phase.

[0027] After solving the capacity allocation problem, it is still necessary to solve the problem of how to ensure that the physical address boundaries between partitions are not crossed.

[0028] The static memory allocation module within the main control chip divides the entire on-chip static random access memory into multiple physically non-contiguous hard-isolated segments, each called a dedicated buffer partition. For each virtual functional unit, the address boundary protection logic circuit within the main control chip is configured with a dedicated set of hardware registers, including a physical start address register and an address boundary limit register. Through the bus monitoring circuit within the solid-state drive main control chip, the target address of the real-time storage access instruction is compared with the range defined by the start address register and the length limit register. If the target address exceeds the defined range, the hardware logic circuit automatically rejects the storage access request. Specifically, the address boundary protection logic circuit contains a hardware comparator. One input of this comparator receives the target address of the current storage access instruction, and the other input receives the valid address range defined by the start address register and the address boundary limit register corresponding to the virtual functional unit. When the target address is within the valid range, the comparator outputs a high level, which acts as an enable signal and remains valid, allowing normal memory access. When the target address is outside the range, the comparator outputs a low level, and the hardware logic immediately pulls the enable signal low, automatically rejecting the memory access request and triggering a hardware interrupt. This mechanism ensures that read and write operations between each dedicated buffer partition do not interfere with or penetrate each other.

[0029] After completing the partition configuration, the next step is to address how to efficiently write data to the corresponding dedicated buffer partition. During the normal operation of the solid-state drive (SSD), when data read / write requests are sent to the main controller chip via the Fast Peripheral Component Interconnect (FPCI) and Fast Non-Volatile Memory Protocol (FPNMT), the front-side bus (FSB) interface parsing module intercepts the sent instruction data packets and extracts an identifier carried in the packet header, called the virtual function physical number. Before performing data transfer, the Direct Memory Access (DMI) controller does not need to query the global memory allocation table or perform dynamic page table translation through the central processing unit (CPU). Instead, it directly reads the base address in the physical start address register corresponding to the virtual function physical number through hardware hard-wired logic, uses this base address as the destination address, and transfers and directly writes the data to the dedicated buffer partition corresponding to the virtual function unit. This writing process is completely parallel and lock-free within the hardware chip and does not involve any garbage collection or reallocation of memory blocks, thus severing the spatial coupling between different virtual function units in the on-chip buffer memory stage from the source.

[0030] Step S2: Evaluate the time consumption of macro instructions entering the solid-state drive controller chip, decompose them into multiple micro-instruction sequences with the same expected physical operation time, and add a micro-instruction identifier to each micro-instruction. The micro-instruction identifier contains metadata tags used to characterize the business source and execution priority information.

[0031] After spatial isolation is completed, the data of each virtual functional unit is queued in independent buffers. However, if a 128KB macro instruction is issued in a low-priority buffer, while a 4KB random read instruction is issued in a high-priority buffer, the macro instruction will still monopolize the physical channel for a long time when they converge on the back-end flash memory channel. This is because the physical execution time of instructions of different sizes on the flash memory medium varies greatly. Therefore, the core problem to be solved in step S2 is: how to break down large macro instructions according to their physical execution time, making them equivalent to read instructions in the time dimension.

[0032] Specifically, the first problem to be solved is how to obtain the actual time consumption characteristics of macro instructions on the underlying medium.

[0033] The instruction parsing circuit inside the main control chip monitors and captures write macro instructions that overflow or are issued from each dedicated buffer partition configured in step S1 in real time. When the write instruction logic block size of a certain non-critical virtual functional unit is detected to exceed a preset filtering threshold, hardware interception logic is triggered. The preferred value of this preset filtering threshold is 16 kilobytes, that is, when the logic block size of the write instruction is greater than 16KB, the splitting process is triggered. At the same time, the flash conversion layer firmware sends a query request to the target flash channel through the hardware monitoring bus to collect the physical state parameters of the target flash chip pointed to by the macro instruction. These parameters include: wear erase count, programming write mode (single-layer cell or three-layer cell), and channel queuing depth.

[0034] After obtaining the physical state parameters, the problem to be solved is how to establish the time consumption distribution curve of macro instructions in the logical address space.

[0035] The timing calculation hardware unit built into the main control chip takes the target physical address, data size, and flash memory physical state parameters of the collected macro instructions as input to calculate the expected physical operation time. This expected physical operation time includes three components: the flash physical programming write time required to write the target flash page, the channel bus transmission time required for the direct memory access controller to transfer data to the target flash channel, and the additional overhead time for flash physical data error correction introduced by the increased number of erases on the target physical flash block. Taking a specific flash memory chip as an example, the typical page programming time in single-level physical memory cell mode is 50 microseconds, and the typical page programming time in three-level physical memory cell mode is 200 microseconds; the channel bus transmission time is calculated by dividing the data length by the channel physical bandwidth, for example, 4KB of data takes approximately 4 microseconds at a bandwidth of 1000MT / s; the additional overhead time for error correction introduced by the increased number of erases can gradually increase from 10 microseconds to 80 microseconds over the lifetime of the flash memory. Through the above calculations, the main control chip establishes a one-dimensional, continuous expected physical operation time curve in the logical address space for the entire large-size macro instruction.

[0036] After establishing the time consumption curve, it is necessary to solve the problem of how to determine the split point so that the execution time of each microinstruction after splitting is equal on the physical medium.

[0037] The main control chip's hardware computing unit integrates along the expected physical operation time curve and sets segmentation nodes at the points where the integral value is evenly divided. Based on the de Boer equidistant distribution principle, the spacing between each segmentation node on the logical block address is adjusted so that the surface integral values ​​between two adjacent segmentation nodes are strictly equal, or the deviation of the integral value is less than a preset time deviation threshold. The preferred value of this time deviation threshold is 5%. For example, if the standard execution time of a single standard microinstruction is 50 microseconds, then the actual expected execution time of each microinstruction should be controlled between 47.5 microseconds and 52.5 microseconds. Under this division, the size of the segmented logical block address intervals is uneven. The data size divided in the three-level cell slow write area is smaller, and the data size divided in the single-level cell fast write area is larger. However, the expected physical operation time generated by each interval on the flash memory channel is completely equal and uniform. Thus far, this step uses the partitioning nodes as the dividing boundary to decompose the macro instruction into multiple micro instruction sequences, so that the expected physical operation time deviation between adjacent micro instructions is less than the preset time deviation threshold (preferably 5%).

[0038] Finally, it is necessary to solve the problem of how to assemble the segmented micro-instructions and inject them into the underlying queue.

[0039] The internal macro instruction refactoring hardware divides the original large macro instruction into multiple independent micro instructions based on the calculated logical block address. For example, a 128KB large write macro instruction, if the flash memory medium is currently in three-level cell mode and the channel bandwidth is 1000MT / s, can generate approximately 20 to 30 micro instructions through the above division process, each with an expected physical operation time of about 50 microseconds. The refactoring hardware injects an expected physical operation time metadata tag into each generated micro instruction, which contains information such as the expected physical operation duration of the micro instruction. In addition, a micro instruction identifier is added to each micro instruction, which contains metadata tags that characterize the service source and execution priority information. Then, the refactored micro instruction sequence is sequentially pushed into the first-in-first-out (FIFO) queue of the back-end flash memory controller for delivery. Because these microinstructions have a highly uniform expected physical occupancy time on the underlying medium, when they are interleaved and transmitted in the channel with high-priority random read microinstructions, there will be no long-tailed queuing jitter caused by high-priority random read microinstructions being waited indefinitely due to the excessive programming time of a single microinstruction.

[0040] Step S3: Parse the microinstruction identifier. When the identifier matches the preset service whitelist, trigger the switching control level and redirect the transmission path from the system shared bus to the preset point-to-point cross switch matrix. The microinstruction data is then directly connected to the flash memory control interface via the vertical metal silicon via array, allowing the microinstruction data to bypass the bus arbitration logic for transmission.

[0041] After step S2, the large macro instructions have been divided into time-equal micro instructions. However, inside the chip, even if the micro instructions are time-equal, if they are still queuing on the congested shared system bus, bus arbitration itself will introduce several microseconds of jitter. High-priority micro instructions must be given priority on the physical circuitry. Therefore, the core problem to be solved in step S3 is: how to enable high-priority micro instructions to bypass the shared bus and reach the flash memory channel entry point with nanosecond-level latency.

[0042] Specifically, this step first needs to address the issue of how to identify which micro-instructions belong to high-priority services.

[0043] The front-side bus routing module of the main control chip obtains the microinstruction, which has been equivalently split and carries a unified physical operation time tag, from step S2. The hardware decoding circuit in the instruction extracts the virtual function physical number and the associated service level protocol level carried in the microinstruction. The hardware classification circuit inside the chip determines whether the virtual function physical number matches the preset high-priority hard isolation whitelist (i.e., the preset service whitelist). This service whitelist is configured during system initialization, for example, adding virtual function unit 1 and virtual function unit 2 to the whitelist. If the match is successful, the hardware classification circuit sets the high-priority bypass trigger register to a high level, generating a physical path switching control signal; if the match fails, the microinstruction is routed to the regular shared on-chip bus allocation queue.

[0044] After identifying high-priority microinstructions, the next step is to figure out how to physically disconnect the shared bus connection and switch to a dedicated channel.

[0045] Upon receiving a high-level switching control signal, the physical hard-isolation bus bypass circuit located at the shared on-chip bus entry point is activated. This bypass circuit controls the multiplexing circuit of the shared bus interface to forcibly pull down the level of its corresponding physical port, physically disconnecting the high-priority microinstructions from the logical occupancy and signal interaction of the main-chip system bus. Simultaneously, the bypass circuit switches the high-priority data stream to a pre-planned and fixed, absolutely independent point-to-point crossbar switch matrix circuit in the main control chip layout. This crossbar switch matrix circuit is implemented using static physical hard connections without dynamic arbitration, eliminating the need for dynamic routing table lookups and traversals.

[0046] After the switch is completed, the problem of how to transfer data to the flash interface with the shortest physical path needs to be solved.

[0047] Solid-state drive (SSD) controller chips typically consist of multiple vertically stacked functional dies. A dedicated point-to-point crossbar switch matrix circuit, when transmitting data to the backend flash memory die, invokes a pre-built hard routing plan within the chip to direct high-priority micro-instructions to the vertical through-silicon vias (TSVs) or micro-physical bumps reserved at the physical edges of the controller chip's multi-die assembly. The data flow directly crosses the physical boundary between the processor die and the flash memory physical interface die through this channel, without needing any intermediate serial registers or signal relays. Using this bypass path, transmission latency can be reduced to less than 10 nanoseconds, a reduction of three orders of magnitude.

[0048] In addition, to ensure the robustness of the system, this step also addresses how to backtrack when an anomaly occurs in the bypass channel.

[0049] The solid-state drive controller chip monitors the physical connectivity level of the point-to-point crossbar switch matrix in real time through a dedicated circuit (called the "routing status detection circuit"). When an abnormal connectivity level is detected, the control switch level forces the transmission path back to the system shared bus and sends a path status warning signal to the controller chip register.

[0050] Step S4: Periodically perform time slot allocation at the flash channel exit, monitor the actual occupancy time of concurrent service channels through the difference calculation matrix, calculate the difference between the actual occupancy time and the preset standard execution unit, and when the difference triggers a blocking signal, reject the enable request of the channel and force a switch to the time slot of the next service.

[0051] After step S3, high-priority micro-instructions have reached the flash channel entry point directly through the physical bypass, while ordinary-priority micro-instructions have reached the same exit point through the shared bus. Now, multiple micro-instructions converge at the exit point of the flash physical channel, requiring a final arbitration mechanism to determine which one passes first. Therefore, the core problem to be solved in step S4 is: how to achieve microsecond-level fair scheduling at the flash channel exit point, preventing both low-priority services from being starved and low-priority services from momentarily encroaching on high-priority services.

[0052] Specifically, the first problem to be solved is how to monitor the busy / idle status and queuing situation of each channel in real time.

[0053] The hardware time-sharing scheduler circuit monitors the status pins of each flash physical channel in real time. When the idle depth of the first-in-first-out (FIFO) transmit buffer register of the target channel reaches a preset instruction issuance threshold, a channel ready enable pulse is generated. The preferred value of this preset instruction issuance threshold is 50% of the total depth of the FIFO buffer. For example, if the buffer depth is 32 instruction slots, a ready enable pulse is generated when the idle depth reaches 16 slots. While generating the ready pulse, the scheduler circuit scans in parallel and reads the dedicated buffer partitions divided in step S1 for each virtual functional unit from the hardware registers, extracts the microinstructions at the head of each dedicated buffer partition queue, and obtains their service level protocol level and expected physical operation time metadata tags.

[0054] Then, it is necessary to solve the problem of how to ensure that each virtual functional unit gets at least the basic channel time to prevent starvation.

[0055] The hardware scheduler includes a cyclic allocation window and a master clock counter for this window to count the number of physical clock cycles actually occupied by each virtual functional unit (VFU) on the flash memory physical channel within the current cycle. The preferred duration of this cyclic allocation window is 1 millisecond. Within the current allocation window, each VFU is pre-allocated a minimum guaranteed time slot share. An example of this minimum guaranteed time slot share configuration is as follows: high-priority VFUs (such as financial transaction data) are allocated a 200-microsecond guaranteed time slot share, medium-priority VFUs are allocated a 100-microsecond guaranteed time slot share, and low-priority VFUs are allocated a 50-microsecond guaranteed time slot share. The hardware comparator circuit compares the actual number of clock cycles occupied by each VFU with the minimum guaranteed time slot share in real time. If it is determined that the actual channel time occupied by a VFU is lower than its guaranteed allocation, the master scheduling circuit immediately sets the guaranteed priority flag of that VFU to high, ensuring that it has priority in obtaining channel allocation rights before the current window ends.

[0056] After the minimum requirements are met, it is necessary to solve the problem of how to prevent low-priority services from momentarily encroaching on high-priority services due to continuous usage.

[0057] The difference calculation matrix is ​​used to calculate in real time the difference between the actual occupancy time of the service channel corresponding to each virtual functional unit and the preset standard execution unit. The difference calculation matrix circuit inside the main control chip calculates in real time the difference between the actual occupancy time of any two concurrent virtual functional units within the current window. The typical value of the preset standard execution unit is 50 microseconds, corresponding to the expected physical operation time of a single microinstruction on the flash memory medium after being segmented in step S2. If the cumulative occupancy time of a low-priority virtual functional unit exceeds the preset standard execution unit of a high-priority virtual functional unit, it is determined that the low-priority unit has encroached on the channel. At this time, the difference calculation matrix outputs a high level as a blocking signal. When the blocking signal is triggered, the enable request of the service channel is immediately rejected, and the time slot of the next service is forcibly switched.

[0058] Finally, it is necessary to solve the problem of how to convert the arbitration results into actual hardware control signals and achieve closed-loop regulation.

[0059] The internal logic AND gate array of the chip logically merges the backup allocation result and the priority compensation result to determine the target virtual functional unit that will ultimately receive the allocation power, and generates the corresponding chip select enable level and read / write enable clock pulse. At the same time, the blocking signal synchronously updates the time slot weight of the time slot allocator in the next cycle to dynamically adjust the allocation ratio of subsequent enable requests, thereby realizing closed-loop control of flash channel occupancy time and time slot allocation.

[0060] Step S5: Collect the physical operation delay status of the underlying flash interface through the physical state feedback loop as a congestion metric. When the congestion metric exceeds the preset delay trigger threshold, use the physical state feedback loop to calculate the token deduction coefficient and apply it to the token bucket counter of the corresponding service channel to dynamically adjust the token generation rate and control the congestion within the local physical link.

[0061] Steps S1 to S4 can guarantee deterministic low latency under ideal operating conditions. However, flash memory itself is a system with random physical fluctuations. Once a physical read retry occurs at the lower level, the flash memory physical channel will be physically blocked, and even if the arbitration in step S4 is fair, it will be impossible to push data into the busy flash memory. Therefore, the core problem that step S5 needs to solve is: how to monitor the underlying physical fluctuations in real time and dynamically reduce the data injection rate of non-critical channels when congestion occurs, so that the congestion is dissipated locally and does not propagate upwards.

[0062] Specifically, the first problem to be solved is how to acquire the physical operation latency of the flash memory medium in real time.

[0063] The hardware timer inside the main control chip measures the duration of the high-level signal on the flash memory status pin in real time, defining this duration as the random physical operation latency. The typical range of the random physical operation latency is 20 to 50 microseconds under normal read operations, and can reach 200 microseconds to 2 milliseconds when triggering a retry of the underlying read. This step presets a latency trigger threshold, preferably 200 microseconds; that is, when the random physical operation latency exceeds 200 microseconds, it is determined to be a congested state. Simultaneously, the controller polls the queuing depth of each dedicated buffer partition, calculates the difference between the current queuing depth and the preset safe queuing block threshold, and defines this difference as the queue backlog deviation. The preset safe queuing block threshold is preferably 80% of the total capacity of each dedicated buffer partition. For example, if the total capacity of a buffer partition is 128 data blocks, then the safe queuing block threshold is 102 data blocks.

[0064] After obtaining the physical delay data, the problem to be solved is how to determine whether the current congestion will lead to cascading amplification.

[0065] The main control chip models the queue backlog depth of each buffer partition and the data flow of the flash physical channels as a discrete chain of physical particles. A dedicated module within the chip, called the "feedback calculation unit," constructs a hardware-level "quadratic dissipation energy function" based on the queue backlog deviation and the average throughput within the current window. This function quantifies the system energy accumulated due to queuing congestion in the entire storage system. The feedback calculation unit performs string stability checks, calculating the expected L2 gain of system energy transferred upwards between different dedicated buffer partitions when random physical operation delays occur at the lower level. The feedback calculation unit determines whether the string stability condition holds: whether the expected value of the mathematical integral of the trigonometric tangent function after weighting the random physical operation delay with specific physical constants is less than or equal to the reciprocal of the trigonometric tangent value of the "maximum transmission interval time" preset by the main control chip with the same weighting. The preferred value for the maximum transmission interval is 200 microseconds. The channel queuing deviation attenuation rate scalar is pre-calculated by the hardware linear matrix inequality solver inside the main control chip based on the physical bandwidth of the static random access memory and the read / write resource quota, with a typical value range of 0.1 to 0.5. If this relationship holds, the system is in a stable state; if this relationship does not hold, dynamic rate limiting is triggered.

[0066] When it is determined that flow restriction is necessary, the problem of how to calculate and apply the flow control deduction coefficient needs to be solved.

[0067] The physical state feedback loop calculates a value inversely proportional to the congestion metric, called the token deduction factor, based on the degree to which the current congestion metric exceeds a preset delay trigger threshold. For example, when a physical operation delay reaches 500 microseconds, the token deduction factor can be set to 0.5, reducing the token generation rate to 50%; when the physical operation delay reaches 1 millisecond, the token deduction factor can be set to 0.2, reducing the token generation rate to 20%. Each service channel corresponds to a token bucket counter, which controls the data injection rate into the on-chip buffer. The token bucket counter responds to the token deduction factor, reducing its token accumulation value per clock cycle, thereby reducing the token generation frequency until the congestion metric falls back below the preset delay trigger threshold. The feedback calculation unit applies the token deduction factor to the dedicated token generation register of non-critical virtual function units, forcibly reducing their token accumulation value, i.e., damping the data injection rate. Because non-critical traffic is compressed, the freed-up bandwidth allows high-priority data to be sent at extremely high speeds.

[0068] With non-critical injection rates suppressed, the challenge lies in how to dissipate the backlog of congestion locally and restore stability.

[0069] The flash physical channel controller centralizes chip select enable time to fully process critical read requests backlogged in the FIFO buffer, allowing congestion to be discharged locally at the media outlet. When the hardware timer detects that the flash pins have returned to normal levels, the queuing backlog and energy function decrease, the system falls back to the stable boundary, and the flow controller automatically releases the restrictions on non-critical virtual functions, smoothly restoring their throughput quotas.

[0070] In addition, to ensure rapid response of feedback regulation and stable system operation, this step also addresses how to optimize the effect of feedback regulation.

[0071] After the token bucket counter responds to the token reduction factor by decreasing the token generation frequency, it sends the current remaining total number of tokens to a dedicated monitoring and adjustment unit, called the "feedback unit." The feedback unit compares the rate of decrease in congestion metrics before and after the token reduction factor takes effect to determine whether a preset "transmission stability benchmark" is met. This transmission stability benchmark is preferably defined as follows: within 100 microseconds after the token reduction factor takes effect, the rate of decrease in congestion metrics should reach a delay reduction of at least 50 microseconds per second, meaning the congestion state should be effectively alleviated in a short time. When it is determined that the rate of decrease in congestion metrics has not reached the preset transmission stability benchmark, the feedback unit sends an "incremental adjustment command" to the physical state feedback loop to drive the physical state feedback loop to increase the token reduction factor until the congestion metrics fall back to within a preset delay trigger threshold.

[0072] In addition, such as Figure 2As shown, this application also provides a deterministic service assurance master control chip for executing the above method. The master control chip includes: an address boundary protection circuit 10, macro instruction splitting and reconfiguration hardware 20, a point-to-point crossbar switch matrix 30, a difference calculation matrix 40, and a physical state feedback loop 50. These five modules are interconnected with other units of the master control chip (such as the processor core, direct memory access controller, flash memory controller, etc.) via an on-chip bus and dedicated signal lines, jointly forming a hardware logic execution link.

[0073] Address Boundary Protection Circuit 10: This circuit consists of multiple sets of start address registers, length limit registers, and a hardware comparator array. Each set of registers corresponds to a virtual functional unit, storing the base address and capacity boundary of its dedicated buffer in static random access memory. One input of the hardware comparator array is connected to the target address signal output by the front-side bus interface parsing module, and the other input is connected to the register value corresponding to the current access. The comparator outputs are directly connected to the enable control terminal and interrupt controller of the bus interface. When the target address exceeds the boundary, the comparator outputs a low level, forcibly pulling down the bus enable signal and triggering an illegal access interrupt.

[0074] Macro instruction segmentation and reconfiguration hardware 20: This hardware module includes an instruction parsing circuit, a time-consuming calculation hardware unit, an integral segmentation logic, and a micro-instruction reconfiguration queue. The instruction parsing circuit is connected to the read port of each dedicated buffer partition to detect the size and address of the macro instructions written in real time. The time-consuming calculation hardware unit collects the physical status parameters (wear and erase count, programming mode, queue depth) of the flash memory channel through the hardware monitoring bus, and has three built-in adders to accumulate the programming time, transmission time, and error correction overhead, respectively, and outputs the expected physical operation time value. The integral segmentation logic performs discrete integration on the expected physical operation time curve, generates a segmentation pulse at the equal integration point, controls the reconfiguration queue to split the macro instruction data into several micro-instructions, attaches a metadata tag (containing business source and priority information) to each micro-instruction, and finally pushes the micro-instructions into the first-in-first-out queue of the flash memory controller.

[0075] Point-to-point crossbar switch matrix 30: This matrix is ​​a non-arbitrated, statically hardwired crossbar switch, consisting of a bypass trigger register, a multiplexer array, and a vertical through-silicon via (TSV) interface. The input of the bypass trigger register is connected to the determination result of the hardware classification circuit, and the output controls the selection signal of the multiplexer. One of the matrix's input ports is connected to the output of the shared bus bypass circuit, and the output port is directly connected to the drive circuit of the TSV. When the bypass trigger register is high, the multiplexer directly bypasses the input data to the TSV, bypassing the shared bus arbitration logic. The other end of the TSV is directly connected to the FIFO buffer register of the flash memory control interface. Furthermore, the matrix integrates a routing status detection circuit (composed of a level comparator and a latch) to monitor the physical connectivity level of the TSV in real time. In case of an anomaly, the selection signal is switched back to the shared bus via a backoff control line, and a warning bit is sent to the register.

[0076] Difference Calculation Matrix 40: This matrix consists of a subtractor array, a flip-flop array, and a comparator network. The inputs of the subtractor array are connected to the channel occupancy timers (hardware counters) of each virtual functional unit, and the output is the difference in occupancy time between each pair of channels. The flip-flop array latches the cumulative difference within the current window. The comparator network compares this difference with a preset standard execution unit register (configured to the number of clock cycles corresponding to 50 microseconds). When the difference is greater than or equal to this value, a blocking signal (high-level pulse) is output. The blocking signal is connected to the priority encoder of each channel enable control logic, forcibly masking the enable requests of low-priority channels and triggering time slot switching. At the same time, the blocking signal is also fed back to the time slot allocation weight table (a set of configurable registers), automatically updating the time slot allocation ratio for the next cycle.

[0077] Physical state feedback loop 50: This loop includes a hardware timer, a secondary dissipation energy calculator, a token deduction coefficient generator, and a feedback comparison unit. The input pin of the hardware timer is connected to the "ready / busy" signal line of the flash memory channel, measures the duration of the busy level, and outputs a random physical operation delay value. The secondary dissipation energy calculator calculates the current congestion energy value based on the queue depth deviation and average throughput (from performance counters) of each buffer partition. The token deduction coefficient generator has a built-in divider that calculates a deduction coefficient (coefficient range 0.1~1.0) based on the proportion of congestion energy exceeding the threshold, and applies this coefficient to the token bucket counter of non-critical virtual functional units (one for each virtual functional unit) through a hardware multiplier, reducing its token generation rate in real time. The feedback comparison unit monitors the rate of change of the delay value before and after deduction. If the rate of change is lower than a preset transmission stability benchmark (stored in a register), it sends an increment instruction to the deduction coefficient generator to gradually increase the deduction intensity.

[0078] The five hardware modules mentioned above are tightly coupled through dedicated signal lines (including control lines, status lines, and data lines) and a shared bus (used only during rollback), enabling them to complete the entire hardware processing chain from spatial isolation, instruction splitting, bypass acceleration, time slot arbitration to congestion feedback without processor intervention.

[0079] Finally, this application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the aforementioned deterministic service guarantee method for multi-tenant solid-state drives.

[0080] Specifically, the computer program includes one or more machine-executable instructions. When these instructions are loaded and executed by the processor (or embedded microcontroller) in the solid-state drive controller chip, the controller chip causes the following operations: configuring the processed data stream as at least one virtual functional unit, allocating physical buffer capacity to each virtual functional unit according to service level agreement parameters, and locking physical address boundaries using address boundary protection circuitry; performing time-consuming evaluation on macro instructions, breaking them down into multiple microinstruction sequences with the same expected physical operation duration, and adding microinstruction identifiers; parsing the microinstruction identifiers, and when the identifier matches... When a preset service whitelist is configured, a switching control level is triggered, directing the transmission path from the system shared bus to a point-to-point crossbar switch matrix, and then directly connecting to the flash memory control interface via a vertical metal-silicon via. Time slot allocation is periodically performed at the flash memory channel exit. The actual occupancy time of concurrent service channels is monitored through a difference calculation matrix, and the difference between the actual occupancy time and the standard execution unit is calculated. When the difference triggers a blocking signal, a time slot is forcibly switched. The physical operation delay status of the underlying flash memory interface is collected through a physical state feedback loop as a congestion metric. When this metric exceeds the delay trigger threshold, a token deduction coefficient is calculated, and the token generation rate is dynamically adjusted.

[0081] The computer-readable storage medium can be any tangible medium capable of storing computer programs, including but not limited to: read-only memory (ROM), random access memory (RAM), flash memory, the solid-state drive itself, magnetic disks, optical disks, etc. This medium can exist independently of the solid-state drive controller chip (e.g., pre-installed in the firmware at the factory) or be integrated within the chip (e.g., embedded non-volatile memory). When this medium is used in an existing solid-state drive, updating the firmware or loading the driver enables the solid-state drive to possess the aforementioned deterministic service guarantee capabilities without modifying the hardware.

[0082] It should be noted that the main control chip embodiment and the storage medium embodiment of this application are based on the same inventive concept as the aforementioned method embodiment, and their specific implementation details can be referred to the description in the method embodiment, which will not be repeated here.

[0083] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0084] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0085] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this application.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A deterministic service guarantee method for multi-tenant solid-state drives, characterized in that, Includes the following steps; S1. Configure the data stream processed by the solid-state drive controller chip as at least one virtual functional unit, and allocate physical buffer capacity to each virtual functional unit according to the preset service level agreement parameters. Utilize the address boundary protection circuit in the solid-state drive controller chip to divide the static random access memory into independent buffer partitions with non-contiguous addresses. The address boundary protection circuit is configured with a start address register and a length limit register for limiting each buffer partition, so as to lock the physical address boundary of the partition through the start address register and the length limit register, so that the data addressing space of each virtual functional unit is in a physically isolated state. S2. Evaluate the time consumption of macro instructions entering the solid-state drive controller chip, decompose them into multiple micro-instruction sequences with the same expected physical operation time, and add a micro-instruction identifier to each micro-instruction. The micro-instruction identifier contains metadata tags used to characterize the business source and execution priority information. S3. Parse the microinstruction identifier. When the identifier matches the preset service whitelist, trigger the switching control level and redirect the transmission path from the system shared bus to the preset point-to-point cross switch matrix. The microinstruction data is then directly connected to the flash memory control interface via the vertical metal silicon via array, allowing the microinstruction data to bypass the bus arbitration logic for transmission. S4. Periodically perform time slot allocation at the flash channel exit, monitor the actual occupancy time of concurrent service channels through the difference calculation matrix, calculate the difference between the actual occupancy time and the preset standard execution unit, and when the difference triggers a blocking signal, reject the enable request of the channel and force a switch to the time slot of the next service. S5. The physical operation delay status of the underlying flash interface is collected through the physical state feedback loop as a congestion metric. When the congestion metric exceeds the preset delay trigger threshold, the token deduction coefficient is calculated using the physical state feedback loop and applied to the token bucket counter of the corresponding service channel to dynamically adjust the token generation rate and control the congestion within the local physical link.

2. The method according to claim 1, characterized in that, In step S1, the method for determining the physical buffer capacity... The formula is: Using the product of the average queue depth and the maximum data packet size of each virtual functional unit as a baseline value, the product of the unit's traffic standard deviation and the preset security margin coefficient is accumulated, and then multiplied by the service level agreement allocation weight to obtain the specific value of the physical buffer capacity.

3. The method according to claim 1, characterized in that, In step S1, the physical location of the locked partition is... The address boundary has the following locking mechanism: The bus monitoring circuit inside the solid-state drive controller chip compares the target address of the real-time storage access command with the range defined by the start address register and the length limit register. If the target address exceeds the defined range, the hardware logic circuit automatically rejects the storage access request.

4. The method according to claim 1, characterized in that, In step S2, the process of entering the solid-state drive... The main control chip's macro instructions are evaluated for time consumption, and then broken down into multiple microinstruction sequences with the same expected physical operation duration. This includes: Collect the physical state parameters of the target flash memory chip pointed to by the macro instruction, including the number of wear erase cycles, programming write mode, and channel queuing depth; Calculate the expected physical operation time curve of the macro instruction in the logical address space based on the physical state parameters; The macro instruction is divided into multiple micro instruction sequences by dividing the expected physical operation time curve into equal integral values, with the dividing nodes as the dividing boundaries, so that the expected physical operation time deviation between adjacent micro instructions is less than a preset time deviation threshold.

5. The method according to claim 1, characterized in that, Step S3 includes: The microinstruction identifier is parsed. When the identifier matches the preset service whitelist, the switching control level is triggered, driving the transmission path to switch from the system shared bus to the point-to-point cross switch matrix, and establishing a physical direct connection with the flash memory control interface via the vertical metal silicon via array. The solid-state drive controller chip monitors the physical connectivity level of the point-to-point cross switch matrix in real time through a routing status detection circuit. When an abnormal connectivity level is detected, the chip controls the switching control level to force the transmission path back to the system shared bus and sends a path status warning signal to the controller chip register.

6. The method according to claim 1, characterized in that, Step S4 includes: The difference calculation matrix is ​​used to calculate in real time the difference between the actual occupancy time of the business channel corresponding to each virtual functional unit and the preset standard execution unit; When the difference triggers the blocking signal, the enable request for the service channel is rejected, and the service is forcibly switched to the next service time slot. The blocking signal synchronously updates the time slot weight of the time slot allocator in the next cycle to dynamically adjust the allocation ratio of subsequent enable requests, thereby achieving closed-loop control of flash channel occupancy time and time slot allocation.

7. The method according to claim 1, characterized in that, In step S5, the physical state feedback is... The physical operation latency status of the underlying flash memory interface is used as a congestion metric. When the congestion metric exceeds a preset latency trigger threshold, the step of calculating a token deduction coefficient using the physical state feedback loop includes: The physical state feedback loop calculates a token deduction coefficient that is inversely proportional to the congestion metric based on the degree to which the congestion metric exceeds the preset delay trigger threshold. The token bucket counter responds to the token deduction coefficient by reducing the token generation frequency until the congestion metric falls back to within the preset delay trigger threshold.

8. The method according to claim 1, characterized in that, In step S5, the action applied to the corresponding service channel The token bucket counter, used to dynamically adjust the token generation rate, includes the following steps: The token bucket counter responds to the token deduction coefficient by reducing the token generation frequency and sends the current remaining total number of tokens to the feedback unit; The feedback unit compares the rate of decrease of the congestion metric before and after the token deduction coefficient takes effect to determine whether the preset transmission stability benchmark is met. When it is determined that the rate of decrease of the congestion metric has not reached the preset transmission stability benchmark, the feedback unit sends an incremental adjustment command to the physical state feedback loop to drive the physical state feedback loop to increase the token deduction coefficient until the congestion metric falls back to within the preset delay trigger threshold.

9. A deterministic service assurance master control chip, characterized in that, include: The system comprises an address boundary protection circuit, macro instruction segmentation and reconstruction hardware, a point-to-point cross switch matrix, a difference calculation matrix, and a physical state feedback loop. These components are physically connected through an internal circuit topology to form a hardware logic execution link. The address boundary protection circuit includes a start address register and a length limit register, and its output is connected to the bus enable control terminal. The macro instruction segmentation and reconstruction hardware includes an instruction parsing circuit, a time consumption calculation unit, and an integral segmentation logic, the output of which is connected to the first-in-first-out queue of the flash memory controller. The point-to-point cross switch matrix includes a bypass trigger register and a multiplexer, and its output is connected to the flash memory control interface through a vertical through-silicon via. The difference calculation matrix includes a subtractor array and a comparator network, and its output blocking signal is connected to a time slot distributor. The physical state feedback loop includes a hardware timer and a token deduction coefficient generator, the output of which is connected to a token bucket counter.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program When executed by a processor, it implements the method of any one of claims 1 to 8.

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