A wear leveling control method and system for SLC NAND flash memory controllers

Abstract

The application relates to the technical field of intelligent chips, and discloses a wear leveling control method and system of an SLC NAND flash memory controller. The method comprises the following steps: acquiring flash memory wear data, calculating wear scores of each control node, and dividing a high-wear node set and a low-wear node set; screening a write request from the high-wear node set, counting access frequency characteristics and accumulated write data volume, determining a hotspot write request, and reading a pending routing path; performing life difference determination according to the high-wear node set and the low-wear node set, obtaining a wear gap, and reading a low-wear node resource state; correcting the remaining life of the low-wear node based on the resource state, obtaining an expected value of the remaining life, selecting a target node, and updating the pending routing path to obtain a target routing path; performing page writing according to the target routing path, generating a shunting completion record, updating a node wear state, and obtaining updated flash memory wear data. The method can solve the problem that wear between nodes is difficult to balance.

Description

Technical Field

[0001] This invention relates to the field of smart chip technology, and in particular to a wear leveling control method and system for an SLC NAND flash memory controller. Background Technology

[0002] With the continued application of intelligent chip technology in data centers, edge computing, smart terminals, and video processing equipment, on-chip storage control capabilities and external flash memory access capabilities have become crucial factors affecting system stability. Intelligent chips frequently need to perform data writing, reading, and address mapping management during data acquisition, caching, inference computation, and task scheduling. Among these, SLC NAND flash memory-based storage arrays are widely used in high-reliability data caching and long-term storage scenarios due to their high read / write stability, strong erase / write tolerance, and fast response speed.

[0003] Existing wear-leveling methods schedule physical blocks within a single control node. After receiving write data, the controller queries the address mapping table based on the logical address to determine the physical block where the original data resides. When data needs to be updated, the new data is written to an idle physical block with a low write / erase count within the current control node, and the original physical block is marked as invalid. The write / erase count of the corresponding physical block is subsequently updated during garbage collection or erasure. In this way, write pressure can be distributed among multiple physical blocks within the same control node, keeping the write / erase counts of each physical block within the node relatively similar. However, in a multi-controller architecture, different control nodes carry different service loads. Hot data will be written to a fixed control node for a long time. Even if the physical block rotation within that node has been completed, its overall write / erase count will still remain higher than other low-load nodes, causing the difference in lifetime margin between nodes to widen continuously, ultimately causing high-load control nodes to approach their write / erase lifetime limit prematurely.

[0004] In summary, existing technologies suffer from hotspot writing and hardening, which makes it difficult to achieve even wear between nodes. Summary of the Invention

[0005] This invention provides a wear leveling control method and system for an SLC NAND flash memory controller to solve the problem of difficulty in balancing wear between nodes.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a wear leveling control method for an SLC NAND flash memory controller, comprising: Obtain flash memory wear data; The wear score of each control node is calculated based on the flash memory wear data, and the control nodes are divided into a set of high-wear nodes and a set of low-wear nodes based on the wear score. Write requests are filtered from the set of high-wear nodes, and the access frequency characteristics and cumulative written data volume of the write requests are statistically analyzed. Hotspot writes are determined based on the access frequency characteristics and the cumulative written data volume to obtain hotspot write requests, and the pending routing path corresponding to the hotspot write requests is read. The lifespan difference is determined based on the high-wear node set and the low-wear node set to obtain the wear gap value, and the resource status of the low-wear node set is read based on the wear gap value; Based on the resource status, the set of low-wear nodes is subjected to lifetime correction processing to obtain the expected value of remaining lifetime. The low-wear node with the largest expected value of remaining lifetime is selected as the target node. The pending route path is updated based on the physical address of the target node to obtain the target route path. Page writing is performed according to the target routing path to obtain a traffic splitting completion record, and the node wear status is updated according to the traffic splitting completion record to obtain updated flash memory wear data.

[0007] In a second aspect, the present invention provides a wear leveling control system for an SLC NAND flash memory controller, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the wear leveling control method for the SLC NAND flash memory controller as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the wear leveling control method for an SLC NAND flash memory controller as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention calculates the wear score of each control node based on the current cumulative number of erase / write cycles, the erase / write growth rate per unit time, the node load, and the number of available physical blocks, and divides the high-wear node set and the low-wear node set accordingly. Since the wear score reflects the degree of node wear, the wear growth rate, the current processing pressure, and the remaining amount of available physical blocks, it can accurately identify nodes with continuous high write volume and low-wear nodes with sufficient capacity, providing clear targets for subsequent write routing and avoiding the problem of failing to detect wear differences between nodes by simply rotating physical blocks within a single node.

[0010] (2) This invention filters write requests from a set of high-wear nodes and statistically analyzes the access frequency characteristics and cumulative written data volume within a preset statistical window according to the data block identifier. When both exceed the corresponding threshold, hotspot write requests are identified. This process does not uniformly migrate all write requests, but first locates the high-frequency, large-volume write requests that cause the high-wear nodes to increase their write activity, thereby reducing invalid migrations and allowing the diversion objects to directly correspond to the sources of accelerated node wear, thus reducing the rate at which high-wear nodes continue to accumulate write activity.

[0011] (3) This invention calculates the remaining lifetime value based on the current cumulative number of erase / write operations and the erase / write growth rate per unit time for each control node in the high-wear node set and the low-wear node set, and obtains the wear difference value through the average remaining lifetime value of the two types of nodes. When the wear difference value exceeds the preset wear balance threshold, the resource status of the low-wear node set is then read. This process can perform resource reading and subsequent traffic splitting only after the lifetime difference between nodes reaches the adjustment condition, avoiding frequent route rewriting when the wear difference is small. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the wear leveling control method for an SLC NAND flash memory controller provided in the first embodiment of the present invention. Detailed Implementation

[0013] The SLC NAND flash controller described in this embodiment is applied in a multi-controller storage array. The multi-controller storage array includes a host interface, a request scheduling unit, multiple control nodes, and SLC NAND flash chips connected to each control node. Each control node corresponds to an independent flash control channel. The control node includes a controller number, a channel number, and a chip number, and accesses at least one SLC NAND flash chip through the corresponding channel. Each SLC NAND flash chip is managed according to physical blocks and pages, with physical blocks used as the erase unit and pages as the write unit. The controller maintains an address mapping table, a free block table, a physical block erase / write count table, a request scheduling record table, and a task scheduling table in the flash translation layer. Specifically, the address mapping table records the correspondence between logical block addresses and physical block addresses; the free block table records unallocated, unlocked, and unmarked bad physical blocks; the physical block erase / write count table records the number of erases for each physical block; the request scheduling record table records currently pending write requests; and the task scheduling table records the number of currently concurrent tasks. The control node, target control node, target physical block address, node load, number of available physical blocks, and current cumulative erase / write count in subsequent steps are all obtained based on the above hardware structure and its operation records.

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Reference Figure 1 The first embodiment of the present invention provides a wear leveling control method for an SLC NAND flash memory controller, comprising the following steps: S11, acquire flash memory wear data; S12, calculate the wear score of each control node based on the flash memory wear data, and divide the control nodes into a set of high wear nodes and a set of low wear nodes based on the wear score; S13, filter write requests from the set of high-wear nodes, and statistically analyze the access frequency characteristics and cumulative written data volume of the write requests. Based on the access frequency characteristics and the cumulative written data volume, determine hotspot write requests, obtain hotspot write requests, and read the pending routing path corresponding to the hotspot write requests. S14, determine the lifespan difference based on the set of high-wear nodes and the set of low-wear nodes, obtain the wear gap value, and read the resource status of the set of low-wear nodes based on the wear gap value; S15, perform lifetime correction processing on the set of low-wear nodes based on the resource status to obtain the expected value of remaining lifetime, select the low-wear node with the largest expected value of remaining lifetime as the target node, and update the pending route path based on the physical address of the target node to obtain the target route path. S16, perform page writing according to the target routing path to obtain a traffic splitting completion record, and update the node wear status according to the traffic splitting completion record to obtain updated flash memory wear data.

[0016] In step S11, flash memory wear data is acquired.

[0017] It's worth noting that the flash memory wear data includes the control node identifier, current cumulative erase / write count, erase / write growth rate per unit time, node load, and number of available physical blocks. The control node identifier is the controller number, channel number, and chip number in a multi-controller architecture. The current cumulative erase / write count is read from the physical block erase / write count table maintained by the flash memory translation layer. Each time a physical block completes an erase operation, its erase / write count is incremented by one. At the end of the statistical period, the controller reads the erase / write counts of all valid physical blocks under the same control node and writes the average of these counts as the current cumulative erase / write count for that control node into the flash memory wear data. A valid physical block refers to a physical block belonging to the corresponding control node and having a valid erase / write count record in the erase / write count table. The erase / write growth rate per unit time is obtained by subtracting the current cumulative erase / write count at the beginning of the statistical period from the current cumulative erase / write count at the end of the current statistical period, and then dividing by the duration of the statistical period. Node load is determined by the number of read / write requests and concurrent tasks. First, within the same statistical period, the total number of read / write requests in the request scheduling queue and the number of concurrent tasks in the task scheduling table are read. Then, these are divided by the rated request processing capacity and the rated concurrent task limit of the control node, respectively, to obtain the request occupancy ratio and the concurrency occupancy ratio. The average of these two ratios is taken as the node load. The number of available physical blocks is read from the free block management table, counting the number of unallocated, unlocked, and not marked as bad blocks.

[0018] Rated request processing capacity refers to the maximum number of read / write requests a single control node is allowed to complete within a statistical period. This value is read from the controller firmware configuration table, which is written by the controller during the system initialization load testing phase. During load testing, the control node runs in continuous read / write mode for a complete statistical period, recording the maximum number of read / write requests that can be stably completed without request drop within that period. This number is taken as the rated request processing capacity of the control node. For example, if a control node can stably complete 500,000 read / write requests within a 10-second statistical period, then the rated request processing capacity of that control node is 500,000. Rated concurrent task limit refers to the maximum number of tasks a single control node is allowed to simultaneously remain in an incomplete state in the task scheduling table. This value is determined by the number of available records in the task scheduling table and is read from the controller firmware configuration table.

[0019] In step S12, a wear score for each control node is calculated based on the flash memory wear data, and the control nodes are divided into a high-wear node set and a low-wear node set based on the wear score, including: The flash memory wear data includes the control node identifier, current cumulative erase / write count, erase / write growth rate per unit time, node load, and number of available physical blocks; The current cumulative number of erase / write operations, the erase / write growth rate per unit time, and the number of available physical blocks are normalized to obtain the erase / write occupancy ratio, the growth occupancy ratio, and the space shortage ratio. The wear score is obtained by weighting the erase / write occupancy ratio, the growth occupancy ratio, the node load, and the space shortage ratio. When the wear score is greater than a preset high wear threshold, the control node identifier is written into the high wear node set; when the wear score is less than a preset low wear threshold, the control node identifier is written into the low wear node set.

[0020] It is worth noting that the current cumulative number of erase / write operations, the erase / write growth rate per unit time, the node load, and the number of available physical blocks are all normalized to convert the data into comparable values ​​between 0 and 1. Specifically, the current cumulative number of erase / write operations is divided by the rated erase / write lifespan of the SLC NAND chip to obtain the erase / write occupancy ratio; the rated erase / write lifespan is obtained by the controller reading the chip specification parameters during system initialization. The erase / write growth rate per unit time is used to calculate the growth occupancy ratio. The controller reads the erase / write growth rate per unit time of all control nodes within the same statistical period and determines the maximum erase / write growth rate per unit time. When the maximum erase / write growth rate per unit time is greater than 0, the erase / write growth rate per unit time of the current control node is divided by this maximum erase / write growth rate per unit time to obtain the growth occupancy ratio. When the erase / write growth rate per unit time of all control nodes within the same statistical period is 0, it indicates that no observable erase / write growth has occurred in this statistical period, and the growth occupancy ratio of each control node is recorded as 0. The node load is directly taken from the load value obtained in step S11. The available physical blocks are divided by the total number of manageable valid physical blocks of the control node to obtain the available block ratio. Then, the available block ratio is subtracted from 1 to obtain the space shortage ratio. The total number of manageable valid physical blocks is read from the physical block management table by the controller after initializing bad block scanning, reserved block partitioning, and isolated block removal. If the above normalization result is greater than 1, it is counted as 1; if it is less than 0, it is counted as 0, ensuring that all normalization results are between 0 and 1.

[0021] Subsequently, the wear score is obtained by multiplying the erase / write occupancy ratio, growth occupancy ratio, node load, and space shortage ratio by their respective weights and then summing them.

[0022] After obtaining the wear score, the wear score of the control node is compared with the preset high wear threshold and low wear threshold. When the wear score is greater than the preset high wear threshold, the corresponding control node is written to the high wear node set; when the wear score is less than the low wear threshold, the corresponding control node is written to the low wear node set; the remaining control nodes remain as ordinary nodes and do not participate in this round of write distribution.

[0023] The preset high wear threshold and preset low wear threshold are determined by historical operating data of the same batch of SLC NAND under the same business pressure. Specifically, the wear scores of each control node in multiple statistical periods are first read when cross-control node traffic splitting is not performed, and invalid records with incomplete sampling time, missing erase / write counts, or zero available physical blocks are removed to obtain historical wear score samples. Then, the historical wear score samples are arranged in ascending order, and the wear score corresponding to the 25th percentile is taken as the preset low wear threshold, and the wear score corresponding to the 95th percentile is taken as the preset high wear threshold. For example, after sorting the historical wear score samples, the wear score corresponding to the 25th percentile is 0.45 and the wear score corresponding to the 95th percentile is 0.75. Then, 0.45 is set as the preset low wear threshold and 0.75 is set as the preset high wear threshold.

[0024] The weights for each parameter are determined based on correlation coefficients from historical operational data. Specifically, historical records of SLCNAND nodes in the same batch under the same business pressure are read, and the correlation coefficients between the erase / write occupancy ratio, growth occupancy ratio, node load, space shortage ratio, and the actual wear increment in the next statistical period are calculated. The actual wear increment is obtained by subtracting the current cumulative erase / write count from the current cumulative erase / write count in the next statistical period. After obtaining the four correlation coefficients, they are added together to obtain the total correlation coefficient. Then, each correlation coefficient is divided by the total correlation coefficient to obtain the weight of the corresponding parameter. For example, if the four correlation coefficients are 0.72, 0.80, 0.48, and 0.40, the total correlation coefficient is 2.40, and the corresponding weights are 0.30, 0.33, 0.20, and 0.17, respectively. If any correlation coefficient is less than 0, it is counted as 0. If the sum of the four correlation coefficients is 0, they are used in the wear scoring calculation with equal weight coefficients.

[0025] In step S13, write requests are filtered from the set of high-wear nodes, and the access frequency characteristics and cumulative written data volume of the write requests are statistically analyzed, including: Obtain a write request, which includes the currently pointed-to control node identifier, data block identifier, request arrival timestamp, number of bytes to be written, and logical block address; compare the control node identifier in the high-wear node set with the currently pointed-to control node identifier to obtain a candidate write request table; The data block identifier in the candidate write request table is used as the collection basis, and multiple write requests for the same data block located within a preset statistical window are filtered according to the request arrival timestamp to obtain the write request set within the window. Based on the number of write requests in the write request set within the window and the duration of the preset statistical window, the access frequency characteristics are obtained, and the cumulative written data volume is obtained by summing the number of bytes written in the write request set within the window.

[0026] It is worth noting that the controller first reads the write requests that have not yet been written to disk from the internally maintained pending request record. The pending request record is generated by the controller when it receives a host write request. For each host write request received, the controller records the logical block address, data block identifier, request arrival timestamp, number of bytes to be written, and the current control node identifier.

[0027] Subsequently, the control node identifier currently pointed to by each write request is compared one by one with the control node identifiers in the set of high-wear nodes. When the two match, the write request is written to the candidate write request table. Each record in the candidate write request table retains the logical block address, data block identifier, request arrival timestamp, and number of bytes requested to be written.

[0028] Next, using the data block identifier as the aggregation basis, multiple write requests for the same data block within a preset statistical window are merged and statistically analyzed to obtain the access frequency characteristic and the cumulative written data volume. The access frequency characteristic is obtained by dividing the number of write requests for the same data block within the statistical window by the duration of the statistical window, and the cumulative written data volume is obtained by adding the number of bytes written to the same data block in each instance within the statistical window.

[0029] The preset statistics window is determined based on the window adaptation value. Specifically, the controller first reads the duration of a write scheduling cycle and sets the candidate statistics window based on this write scheduling cycle. The lower limit of the candidate statistics window is 10 write scheduling cycles to ensure that at least multiple write schedulings are covered within the window; the upper limit of the candidate statistics window is the allowed traffic splitting response time to ensure that route updates and write traffic splitting can still be performed after hotspot statistics are completed; between the lower and upper limits, the candidate statistics window is set in integer multiples of the write scheduling cycle. A continuous write segment refers to a sequence of consecutive requests in the write record with the same data block identifier and the arrival time difference between two adjacent write requests is no greater than one write scheduling cycle; when the data block identifier changes, or the arrival time difference between two adjacent write requests is greater than one write scheduling cycle, the current continuous write segment ends. If the start and end times of a continuous write segment both fall within the candidate statistics window, it is determined that the continuous write segment is completely contained by the candidate statistics window. For each candidate statistical window, the controller divides the number of consecutively written segments fully included by the total number of consecutively written segments to obtain the consecutive write coverage rate. Simultaneously, it subtracts the candidate statistical window duration from the allowed offloading response time and then divides it by the allowed offloading response time to obtain the offloading response margin. Both the consecutive write coverage rate and the offloading response margin are dimensionless proportional values ​​between 0 and 1, and the larger the value, the more suitable the candidate statistical window is for hotspot write statistics. Therefore, the two are multiplied to obtain the window fit value. Using this multiplication method can simultaneously constrain consecutive write coverage and offloading response timeliness. When either indicator is low, the window fit value decreases, thus avoiding the selection of statistical windows with sufficient coverage but lagging response, or fast response but insufficient coverage. For example, if a write scheduling cycle is 100 milliseconds and the allowed offloading response time is 10 seconds, then the candidate statistical windows can be 1 second, 5 seconds, and 10 seconds. If an additional 20-second window is set, it will not participate in subsequent selection because it exceeds the allowed offloading response time. If the continuous write coverage rates for 1-second, 5-second, and 10-second windows are 0.42, 0.78, and 0.93, respectively, and the shunting response margins are 0.90, 0.50, and 0, respectively, then the corresponding window adaptation values ​​are 0.378, 0.390, and 0, respectively. Therefore, 5 seconds is selected as the preset statistical window.

[0030] In step S13, hotspot write determination is performed based on the access frequency characteristics and the cumulative written data volume to obtain hotspot write requests, and the pending routing path corresponding to the hotspot write request is read, including: The access frequency feature is compared with a preset access frequency threshold, and the cumulative written data volume is compared with a preset data volume threshold. When the access frequency feature is greater than the preset access frequency threshold and the cumulative written data volume is greater than the preset data volume threshold, the corresponding candidate write request is determined as a hot write request. The current address mapping table is read based on the logical block address of the hotspot write request to obtain the pending routing path corresponding to the hotspot write request.

[0031] It is worth noting that the access frequency characteristics are compared with the preset access frequency threshold, and the cumulative written data volume is compared with the preset data volume threshold. When the access frequency characteristics are greater than the preset access frequency threshold and the cumulative written data volume is greater than the preset data volume threshold, the corresponding candidate write request is identified as a hot write request.

[0032] After identifying a hotspot write request, the controller reads the flash translation layer address mapping table based on the logical block address of the request, obtains the current target control node identifier, the current physical block address, and the current mapping table entry number, and combines the logical block address, the current target control node identifier, the current physical block address, and the current mapping table entry number into a pending routing path.

[0033] The preset access frequency threshold and preset data volume threshold are determined by historical write records when cross-control node traffic splitting is not performed. Specifically, under the same business pressure, the number of writes and the cumulative write data volume of each data block within the preset statistical window are read. The number of writes is divided by the preset statistical window duration to obtain the historical access frequency of each data block. Then, all historical access frequencies are sorted in ascending order, and the access frequency corresponding to the 95th percentile is taken as the preset access frequency threshold. In the same way, the cumulative write data volume of each data block within the preset statistical window is sorted in ascending order, and the cumulative write data volume corresponding to the 95th percentile is taken as the preset data volume threshold. For example, under a 5-second statistical window, if the 95th percentile of the historical access frequency is 3 times / second and the 95th percentile of the historical cumulative write data volume is 10240KB, then 3 times / second is set as the preset access frequency threshold, and 10240KB is set as the preset data volume threshold.

[0034] If a candidate write request does not simultaneously meet the above two thresholds, it will not be identified as a hot write request, and its original pending status will be retained.

[0035] In step S14, a lifetime difference determination is performed based on the high-wear node set and the low-wear node set to obtain a wear gap value, and the resource status of the low-wear node set is read based on the wear gap value, including: Based on the current cumulative number of erase / write operations and the erase / write growth rate per unit time for each control node in the set of high-wear nodes and the set of low-wear nodes, calculate the remaining lifetime value for each control node. The average remaining lifetime value of each control node in the high wear node set is calculated to obtain the average remaining lifetime value of the high wear node set, and the average remaining lifetime value of each control node in the low wear node set is calculated to obtain the average remaining lifetime value of the low wear node set. The wear gap value is obtained by calculating the difference between the average remaining lifetime of the low-wear node set and the average remaining lifetime of the high-wear node set. When the wear difference value is greater than the preset wear balance threshold, the resource status of each control node in the low wear node set is read.

[0036] It is worth noting that the average remaining lifetime of the high-wear node set and the low-wear node set are calculated separately. For any control node, the remaining lifetime value is obtained by subtracting the current cumulative number of erase / write cycles from the rated erase / write lifetime of the SLC NAND, and then dividing by the erase / write growth rate used for lifetime calculation. The erase / write growth rate used for lifetime calculation preferentially adopts the erase / write growth rate per unit time obtained for this control node in S11; when the erase / write growth rate per unit time is 0, it indicates that the control node has not generated observable erase growth in the current statistical period. If it is directly used in the division calculation, the remaining lifetime will be uncertain. Therefore, a preset minimum growth rate is used as the alternative divisor for this remaining lifetime calculation. This substitution process is only used for the remaining lifetime calculation in S14 and does not change the erase / write growth rate per unit time recorded in S11.

[0037] The preset minimum growth rate is determined by historical operating data of the same batch of SLC NAND under the same business pressure, the same statistical period, and the same flash conversion layer management strategy. Specifically, the controller reads the unit-time erase / write growth rate of each control node in the historical operating data for each statistical period, and removes records with a value of 0 to obtain a sample of non-zero erase / write growth rates. Subsequently, the non-zero erase / write growth rate samples are sorted in ascending order, and the value corresponding to the 5th percentile is taken as the preset minimum growth rate. The 5th percentile is used to represent the minimum erase / write growth level that can still be observed for low-speed wear nodes, avoiding the use of excessively large surrogate values ​​to suppress the remaining lifetime estimate of low-wear nodes, and also avoiding the inability to perform remaining lifetime calculations due to a growth rate of 0.

[0038] After obtaining the remaining lifetime value of each control node, the remaining lifetime values ​​of all control nodes in the high-wear node set are summed and divided by the number of control nodes in that set to obtain the average remaining lifetime value of the high-wear node set. Similarly, the remaining lifetime values ​​of all control nodes in the low-wear node set are summed and divided by the number of control nodes in that set to obtain the average remaining lifetime value of the low-wear node set. Finally, the average remaining lifetime value of the high-wear node set is subtracted from the average remaining lifetime value of the low-wear node set to obtain the wear difference value.

[0039] The wear difference value is compared with a preset wear balance threshold. When the wear difference value is greater than the preset wear balance threshold, the resource status of each control node in the low wear node set is read; when the wear difference value is not greater than the preset wear balance threshold, the resource status is not read, and the pending routing path remains unchanged.

[0040] When the wear difference is not greater than the preset wear balance threshold, the controller does not perform target node selection and pending route path update, and executes the current write request according to the pending route path. The resource status includes the current cumulative number of erase / write operations, the erase / write growth rate per unit time, the number of available physical blocks, and the current number of concurrent connections.

[0041] The current concurrent connection count is read from the controller's connection record table. This table generates connection records when a host write request enters the controller and deletes the corresponding records upon completion of the write or timeout. The controller counts the number of unreleased connection records at any given time to obtain the current concurrent connection count. For example, if a low-wear control node has 120 unreleased connection records at the current time, then the current concurrent connection count for that control node is 120. Each connection record includes a connection identifier, a target control node identifier, a connection establishment timestamp, and a connection status, which includes two states: not released and released.

[0042] For example, the SLC NAND has a rated erase / write lifetime of 100,000 cycles. The current cumulative erase / write cycles of two control nodes in the high-wear node set are 80,000 and 76,000, respectively, with erase / write growth rates of 0.002315 cycles / second and 0.001852 cycles / second, respectively. Since 80,000 cycles corresponds to 20,000 remaining erase / write cycles, dividing 20,000 by 0.002315 cycles / second yields approximately 8,640,000 seconds, or 100 days; and 76,000 cycles corresponds to 24,000 remaining erase / write cycles, dividing 24,000 by 0.001852 cycles / second yields approximately 12,960,000 seconds, or 150 days. Therefore, the average remaining lifetime of the high-wear node set is 125 days. The current cumulative write / erase counts of the two control nodes in the low-wear node set are 30,000 and 36,000 respectively, with write / erase rates per second of 0.001157 and 0.000926 times per second respectively. Therefore, their remaining lifetimes are 700 days and 800 days respectively, and the average remaining lifetime of the low-wear node set is 750 days. Thus, the wear gap is 750 days minus 125 days, resulting in 625 days. If the preset wear balance threshold is 400 days, it is determined that the wear gap between nodes has exceeded the allowable range. The current cumulative write / erase counts, write / erase rate per second, available physical blocks, and current concurrent connections of each node in the low-wear node set are then read to form the resource status of each node in the low-wear node set, which serves as input for subsequent target node selection.

[0043] The preset wear balance threshold is determined by the historical wear difference value when cross-control node traffic splitting was not performed. Specifically, under the same batch of SLC NAND and the same service pressure, the difference between the average remaining lifetime of the low-wear node set and the average remaining lifetime of the high-wear node set is calculated according to the statistical period to obtain the historical wear difference value. All historical wear difference values ​​are sorted from smallest to largest, and the value corresponding to the 95th percentile is taken as the preset wear balance threshold. For example, if the historical wear difference value corresponding to the 95th percentile is 400 days, then 400 days is set as the preset wear balance threshold.

[0044] In step S15, the set of low-wear nodes is subjected to lifetime correction processing based on the resource status to obtain the expected remaining lifetime value. The low-wear node with the largest expected remaining lifetime value is selected as the target node, and the pending routing path is updated based on the physical address of the target node to obtain the target routing path, including: Extract the current cumulative number of erase / write operations, erase / write growth rate per unit time, and current concurrent connection count of each control node from the resource status, and calculate the ratio based on the corresponding baseline parameters to obtain the erase / write occupancy ratio, growth occupancy ratio, and load occupancy ratio. The erase / write occupancy ratio, the growth occupancy ratio, and the load occupancy ratio are normalized and constrained to obtain normalized constraint results. The normalized constraint results are then weighted and calculated to obtain a comprehensive pressure factor. The remaining life value of each control node is corrected and calculated based on the comprehensive pressure factor to obtain the expected remaining life value. The expected remaining lifetime values ​​of each low-wear node are sorted, and the low-wear node with the largest expected remaining lifetime value is selected as the target node. Read the physical address information of the target node and write the physical address information into the mapping entry corresponding to the undetermined routing path in the flash translation layer address mapping table to obtain the target routing path.

[0045] It is worth noting that the current cumulative erase / write count, erase / write growth rate per unit time, and current concurrent connection count of each low-wear control node are extracted from the resource status, and the erase / write occupancy ratio, growth occupancy ratio, and load occupancy ratio are calculated respectively. Specifically, the erase / write occupancy ratio is obtained by dividing the current cumulative erase / write count by the rated erase / write lifetime of the SLC NAND, which is read from the chip specification parameters; the growth occupancy ratio is obtained by dividing the erase / write growth rate per unit time of the low-wear control node by the maximum erase / write growth rate per unit time among all control nodes within the same statistical period, where the same statistical period is the statistical period corresponding to the flash memory wear data generated in step S11. If the erase / write growth rate per unit time of all control nodes within the same statistical period is 0, then a preset minimum growth rate is used as the growth rate benchmark value; the load occupancy ratio is obtained by dividing the current concurrent connection count by the number of available records in the connection record table, which is allocated by the controller according to the task scheduling table capacity during system initialization, and is used to limit the number of unreleased connection records that the control node can simultaneously store.

[0046] Subsequently, the erase / write normalized constraint results, growth normalized constraint results, and load normalized constraint results are weighted according to the corrected weights to obtain the comprehensive pressure factor. The corrected weights are determined based on the correlation coefficients between the three normalized constraint results in historical operating data and the actual lifetime consumption in the next statistical period. The actual lifetime consumption is obtained by subtracting the remaining lifetime value of the next statistical period from the remaining lifetime value of the current statistical period, and is used to represent the lifetime reduction of the control node in the next statistical period. The controller calculates the correlation coefficients between the erase / write normalized constraint results, growth normalized constraint results, and load normalized constraint results and the actual lifetime consumption, respectively, and adds the three correlation coefficients to obtain a total correlation coefficient. Then, each correlation coefficient is divided by the total correlation coefficient to obtain the erase / write correction weight, growth correction weight, and load correction weight. If any correlation coefficient is less than 0, it is counted as 0; if the sum of the three correlation coefficients is 0, they are used with the same weight in the calculation.

[0047] Based on the erase / write correction weight, growth correction weight, and load correction weight, the controller multiplies the erase / write normalization constraint result, growth normalization constraint result, and load normalization constraint result by their respective correction weights and then sums them to obtain the comprehensive stress factor. This comprehensive stress factor is used to correct the remaining lifetime value of low-wear nodes, giving a higher proportion of influence to stress factors that are more closely related to the actual lifetime consumption. Subsequently, the remaining lifetime value is multiplied by one and the result of subtracting the comprehensive stress factor to obtain the expected remaining lifetime value.

[0048] A physical address resolution operation is performed on the target node. The corresponding rack identifier, storage slot identifier, and target physical block address are read from the flash translation layer address mapping table. The physical address information is written into the mapping entry corresponding to the pending route path in the flash translation layer address mapping table, overwriting the original route pointing relationship, so that the write request is switched from the original path to the target node path, and the target route path is generated.

[0049] For example, if a control node has accumulated 60,000 erase / write cycles and the SLC NAND has a rated erase / write lifetime of 100,000 cycles, then the erase / write occupancy rate is 0.6. The node's erase / write growth rate per unit time is 0.002315 times / second, and the maximum erase / write growth rate per unit time among all control nodes within the same statistical period is 0.04630 times / second, then the growth occupancy rate is 0.5. The node currently has 80 concurrent connections, and the number of available records in the connection record table is 100, then the load occupancy rate is 0.8. If the three correction weights are 0.30, 0.45, and 0.25 respectively, then the comprehensive stress factor is 0.6×0.30+0.5×0.45+0.8×0.25=0.605. The remaining write cycles for this node are 100,000 - 60,000 = 40,000. At a rate of 0.002315 cycles per second, the remaining lifetime is approximately 17,280,000 seconds, or 200 days. Therefore, the expected remaining lifetime is 200 × (1 - 0.605) = 79 days. After performing the above calculations for all low-wear nodes, the node with the largest expected remaining lifetime is selected as the target node. Its target control node identifier and target physical block address are read and written into the mapping entry corresponding to the pending routing path to obtain the target routing path.

[0050] In step S16, page writing is performed according to the target routing path to obtain a traffic splitting completion record, including: The target control node is located based on the target control node identifier in the target routing path, and the physical block to be written in the target control node is located based on the target physical block address in the target routing path. The number of bytes to be written corresponding to the physical block to be written is determined based on the number of writable pages of the physical block to be written, and the target control node identifier, the target physical block address and the number of bytes to be written are written into the execution record; According to the write execution record, the hotspot write request is sent to the target control node and page write is performed. The number of bytes written is accumulated. When the number of bytes written is equal to the number of bytes requested to be written, a flow splitting completion record is generated.

[0051] It is worth noting that the target routing path includes a target control node identifier and a target physical block address. The target control node identifier is used to locate the node that issues the hotspot write request, and the target physical block address is used to locate the write position of the hotspot write request within the target node. The controller locates the target control node based on the target control node identifier in the target routing path, and locates the physical block to be written within that target control node based on the target physical block address.

[0052] Subsequently, the controller reads the number of pages yet to be written in the physical block to be written, obtaining the number of writable pages. This writable page number is then multiplied by the capacity of the main data area per page to obtain the number of writable bytes that the physical block to be written can handle. The capacity of the main data area per page is determined by the controller during system initialization. The controller first reads the device identification information of the SLC NAND chip and then queries the firmware configuration table for the page capacity parameter corresponding to that chip. This page capacity parameter refers to the main data area capacity per page, excluding the redundant bytes used for bad block marking, checksums, and error correction information. If the firmware configuration table records the main data area capacity of the SLC NAND chip as 4KB, the controller uses 4KB / page as the main data area capacity per page in the calculation of the number of writable bytes. Specifically, if the number of pages yet to be written in the physical block to be written is 128 pages, and the main data area capacity per page is 4KB / page, then the number of writable bytes that the physical block to be written can handle is 128 pages multiplied by 4KB / page, resulting in 512KB. The controller then reads the remaining number of bytes to be written in the hotspot write requests that have not yet been completed. It compares the number of writable bytes with the remaining number of bytes to be written, and takes the smaller value as the number of bytes to be written for the physical block to be written. Subsequently, the target control node identifier, the target physical block address, and the number of bytes to be written are written to the execution record. This number of bytes to be written is the number of bytes allocated for writing the current physical block in this write operation. When the total number of bytes to be written in the hotspot write requests is greater than the capacity of a single physical block, the controller allocates the write operation block by block, performing the aforementioned smaller value selection operation for each physical block allocation.

[0053] Based on the write execution record, the controller sends the hotspot write request to the target control node and performs page writing according to the target physical block address. If the data length of the hotspot write request is greater than the single page write length, the hotspot write request is divided into multiple consecutive page write units according to the SLCNAND page size, and the page addresses in the target physical block are written sequentially. If the number of remaining pages in the target physical block is insufficient, the next available physical block is locked from the free block table of the target control node, and the remaining page write units are continued. During the write process, the controller accumulates the number of bytes written. When the number of bytes written equals the number of bytes requested to be written, a splitting completion record is generated.

[0054] In step S16, and based on the recorded wear status of the split-through node, updated flash memory wear data is obtained, including: The target control node is located based on the target control node identifier in the traffic diversion completion record, and the read / write request volume and concurrent task number of the target control node in the current statistical period are updated to obtain the updated node load. The target control node's free block table is updated based on the actual number of physical blocks written in the diversion completion record to obtain the updated number of available physical blocks; Read the physical block address and erase count of the erase operation in the traffic completion record, update the erase count table, and summarize the updated current cumulative erase count and erase growth rate per unit time according to the target control node; Updated flash memory wear data is generated based on the updated current cumulative erase / write count, the erase / write growth rate per unit time, the node load, and the number of available physical blocks.

[0055] It is worth noting that, based on the traffic splitting completion record, the controller updates the node load of the target control node. The traffic splitting completion record includes the target control node identifier, the actual number of physical blocks written, the number of bytes written, the physical block address where an erase operation occurred, and the number of erases. The controller first locates the target control node's scheduling record table based on the target control node identifier and reads the number of read / write requests and concurrent tasks for that target control node in the current statistical period. Then, the hot write requests completed in this traffic split are included in the read / write request volume of the current statistical period, and the corresponding concurrent tasks are released from the task scheduling table after the hot write request is completed, resulting in the updated read / write request volume and the updated number of concurrent tasks. If the node load is represented numerically, the updated read / write request volume is divided by the target control node's rated request processing capacity to obtain the request occupancy ratio; the updated number of concurrent tasks is divided by the target control node's rated concurrent task limit to obtain the concurrency occupancy ratio; and the request occupancy ratio and the concurrency occupancy ratio are then averaged to obtain the updated node load.

[0056] Subsequently, the controller updates the number of available physical blocks on the target control node based on the traffic splitting completion record. Any physical blocks that were locked and written with data during this traffic splitting process are removed from the target control node's free block table, and the number of available physical blocks decreases according to the actual number of physical blocks written.

[0057] After updating the number of available physical blocks, the controller reads the addresses and erase counts of the physical blocks that underwent erase operations during this split write process, and updates the erase count of the target control node accordingly. For physical blocks that underwent erase operations before this split write, the controller reads the erase count at the corresponding physical block address and adds this erase count to the erase count table; for physical blocks that only underwent page writes and did not undergo block erases, the erase count is not increased. Subsequently, the erase counts of each physical block are averaged according to the target control node identifier to obtain the updated current cumulative erase count, and the updated erase growth rate per unit time is obtained based on the ratio of the new erase count in the current statistical period to the duration of the statistical period.

[0058] Based on the updated current cumulative erase / write count, erase / write growth rate per unit time, node load, and number of available physical blocks, the controller generates updated flash memory wear data. For example, if a hotspot write request requests 16MB of bytes, the target routing path points to the target control node N3 and the target physical block P1208, and the main data area capacity of a certain SLC NAND chip is 4KB / page, then the controller will divide the request into 4096 page write units and write them to N3. If each physical block in N3 can write 128 pages, then the amount of data that a single physical block can handle is 128 × 4KB = 512KB; this 16MB hotspot write request requires writing 4096 pages, corresponding to 32 physical blocks. The controller removes P1208 and the subsequent 31 locked available physical blocks from the free block table of N3, reducing the number of available physical blocks in N3 by 32. If an erase operation is performed on one of the physical blocks before writing, the erase count is added to the erase / write count table of the corresponding physical block, increasing the erase / write count of that physical block by 1. For node load, if N3 has 250,000 read / write requests and 256 concurrent tasks before the current statistical period is completed, after the hot write request is distributed, this write will be included in the read / write request count for the current statistical period, resulting in an updated read / write request count of 250,001. After the hot write request is completed, the corresponding concurrent task will be released from the task scheduling table, resulting in an updated concurrent task count of 255. If N3's rated request processing capacity is 500,000 and its rated concurrent task limit is 512, then the request occupancy ratio is 250,001 divided by 500,000, resulting in 0.5000; the concurrency occupancy ratio is 255 divided by 512, resulting in 0.4980. Averaging the request occupancy ratio and the concurrency occupancy ratio yields an updated node load of 0.4990. If N3's current cumulative erase / write count at the start of the current statistical period is 35000.0000 times, and its current cumulative erase / write count at the end of the statistical period is 35000.0020 times, and the statistical period duration is 10 seconds, then the increment of the current cumulative erase / write count within the current statistical period is 0.0020 times, and the erase / write growth rate per unit time is 0.0020 divided by 10 seconds, resulting in 0.0002 times / second. The controller writes the updated current cumulative erase / write count, erase / write growth rate per unit time, node load, and number of available physical blocks from N3 into the updated flash memory wear data.

[0059] In this article, historical operational data of SLC NAND flash memory under the same business pressure refers to operational records collected under the same model, capacity, page size, number of physical blocks, controller firmware version, and flash conversion layer management strategy. The same business pressure means that the historical samples and the current pending business are at the same business pressure level. This business pressure level is determined by the number of read / write requests, the percentage of write requests, the average number of bytes written per request, the peak number of concurrent tasks, the average write bandwidth, and the percentage of hot data within a statistical period. Specifically, if the statistical period is 10 seconds, and the current pending business has 72,000 read / write requests, a write request percentage of 70%, an average number of bytes written per request of 16KB, a peak number of concurrent tasks of 256, an average write bandwidth of approximately 80MB / s, and a hot data percentage of 30% within a statistical period, then samples with the above six indicators at the same business pressure level are selected from the historical operational data as the threshold setting samples. The average write bandwidth is determined by the number of read / write requests, the proportion of write requests, the average number of bytes written per request, and the duration of the statistical period. Of the 72,000 read / write requests, approximately 50,400 were write requests. Multiplying 50,400 by 16KB yields approximately 806,400KB of written data, which, when divided by 10 seconds, gives approximately 80MB / s. When collecting historical samples, the controller did not perform cross-control node traffic splitting and recorded the current cumulative erase / write count, erase / write growth rate per unit time, node load, number of available physical blocks, access frequency characteristics, and cumulative written data volume for each control node according to the same statistical period. Samples with incomplete sampling time, missing erase / write counts, zero available physical blocks, or abnormal connection records were removed from the historical samples. The remaining samples were used as the data source for threshold setting and weight calculation.

[0060] In this paper, if the current storage array is in its initial deployment phase, or if sufficient historical operational data has not yet been generated under the current business load level, the controller performs a system initialization test phase before officially undertaking business, generating initial short-term operational data. During the system initialization test phase, the controller issues continuous write, random write, and mixed read / write test requests to each control node according to the default address distribution strategy, ensuring that the average number of bytes written, the proportion of write requests, the number of concurrent tasks, and the write bandwidth of the test requests cover the business load level that the current storage array is expected to bear. After each test statistical period, the controller records the current cumulative number of erase / write operations, the erase / write growth rate per unit time, the node load, the number of available physical blocks, the wear score, the remaining lifetime value, the wear gap value, and the actual wear increment for the next test statistical period for each control node; simultaneously, it records the number of write requests, the cumulative amount of written data, and the coverage of continuous write segments for each data block within each test statistical window, thereby forming the initial short-term operational data.

[0061] The preset sample lower limit for initial short-term running data is determined jointly based on percentile calculation and weight calculation. Since this method requires the 95th percentile as the calculation basis for high wear determination, hotspot write determination, and wear balance determination, to ensure that at least 10 samples are retained above the 95th percentile, the total sample size is at least 200. Simultaneously, the wear score involves four data items: erase / write occupancy ratio, growth occupancy ratio, node load, and space shortage ratio. Each data item is divided into five value intervals from 0 to 1. To ensure at least 10 valid records are retained in each interval, a total of 200 valid records are required for the four data items. Therefore, this embodiment sets the preset sample lower limit for valid records of node wear type to 200, and also sets the preset sample lower limit for valid records of write window type to 200. A control node forms one valid record of node wear type after one test statistical cycle, and a data block forms one valid record of write window type within one test statistical window. If the number of valid records formed during the initialization test phase is less than 200, the test statistical cycle or the number of test statistical windows is extended until the above sample lower limit is met.

[0062] After the initial short-term running data reaches the preset sample lower limit, the controller determines the preset high wear judgment threshold, preset low wear judgment threshold, wear scoring weight, preset statistical window, preset access frequency threshold, preset data volume threshold, preset minimum growth rate, preset wear balance threshold, and growth occupancy ratio calculation benchmarks required for the cold start phase, using the same calculation method as historical running data. After the system officially starts running, the controller continues to accumulate historical running data under actual business conditions; when the historical running data reaches the corresponding sample requirements, the controller stops using the initial short-term running data and recalculates the above parameters and thresholds based on the historical running data, so that subsequent wear scoring, hotspot write judgment, life difference judgment, and life correction processing are all performed based on the actual business running status.

[0063] In this paper, the statistical period is a fixed time interval during which the controller collects flash memory wear data and updates the node wear status. Its start time is the moment the previous round of flash memory wear data generation is completed, and its end time is the moment after a preset statistical duration. The preset statistical duration is determined based on the write scheduling cycle and the erase count update time. Specifically, the controller first reads one write scheduling cycle and takes the time of at least 100 write scheduling cycles as the statistical lower limit, ensuring that a sufficient number of write scheduling processes are covered within one statistical period. Simultaneously, during the system initialization test phase, the controller records the longest time required from the completion of physical block erasure to the completion of the erase count table update, and uses this time as the complete erase count update time. Subsequently, the larger value between the statistical lower limit and the complete erase count update time is taken and rounded up to an integer multiple of the write scheduling cycle to obtain the statistical period. For example, if one write scheduling cycle is 100 milliseconds, then 100 write scheduling cycles equal 10 seconds; if the longest update time of the erase count table is 2 seconds, then the statistical period is the larger of the two, 10 seconds.

[0064] In summary, this invention discloses a wear leveling control method for an SLC NAND flash memory controller, comprising: firstly, acquiring flash memory wear data and calculating the wear score of each control node based on the data, dividing the control nodes into a high-wear node set and a low-wear node set, enabling the controller to clearly identify nodes with concentrated wear pressure and nodes with remaining lifespan. Subsequently, this invention filters write requests from the high-wear node set and determines hotspot write requests based on access frequency characteristics and cumulative write data volume, thereby limiting the processing targets to the main write sources that continuously increase the node's erase / write count, avoiding indiscriminate adjustments to ordinary write requests. Further, this invention determines the lifespan difference based on the high-wear node set and the low-wear node set, obtaining a wear gap value, and reading the resource status of the low-wear node set when imbalance conditions are met, ensuring that subsequent write redirection is based on the lifespan difference between nodes and the carrying capacity of low-wear nodes. Then, this invention corrects the remaining lifespan of low-wear nodes based on resource status, obtaining an expected remaining lifespan value, selecting the low-wear node with the largest expected remaining lifespan value as the target node, and updating the pending routing path based on the physical address of the target node to obtain the target routing path. Finally, page writing is performed according to the target routing path, a traffic splitting completion record is generated, and the node wear status is updated based on the traffic splitting completion record to obtain updated flash memory wear data. This invention solves the problem of uneven wear among nodes by updating flash memory wear data.

[0065] The second embodiment of the present invention provides a wear leveling control system for an SLC NAND flash memory controller, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the wear leveling control method for the SLC NAND flash memory controller as described above.

[0066] It should be noted that the wear leveling control system for an SLC NAND flash memory controller provided in this embodiment of the invention is used to execute all the process steps of the wear leveling control method for an SLC NAND flash memory controller in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0067] It should be noted that the wear leveling control system embodiment of the SLC NAND flash memory controller described above is merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0068] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A wear leveling control method for an SLC NAND flash memory controller, characterized in that, include: Acquire flash memory wear data; calculate the wear score of each control node based on the flash memory wear data, and divide the control nodes into a set of high-wear nodes and a set of low-wear nodes based on the wear score; Write requests are filtered from the set of high-wear nodes, and the access frequency characteristics and cumulative written data volume of the write requests are statistically analyzed. When the access frequency characteristics are greater than a preset access frequency threshold and the cumulative written data volume is greater than a preset data volume threshold, the corresponding candidate write request is determined as a hot write request, and the pending routing path corresponding to the hot write request is read. Calculate the average remaining lifetime of each control node in the high wear node set and the low wear node set respectively, and calculate the difference between the average remaining lifetime of the low wear node set and the average remaining lifetime of the high wear node set as the wear gap value; when the wear gap value is greater than the preset wear balance threshold, read the resource status of each control node in the low wear node set. Extract the current cumulative erase / write count, erase / write growth rate per unit time, and current concurrent connection count of each control node from the resource status, and calculate the ratios based on the corresponding benchmark parameters to obtain the erase / write occupancy ratio, growth occupancy ratio, and load occupancy ratio. Normalize the erase / write occupancy ratio, growth occupancy ratio, and load occupancy ratio to obtain normalized constraint results. Weight the normalized constraint results to obtain a comprehensive pressure factor. Based on the comprehensive pressure factor, correct the remaining lifetime value of each control node to obtain the expected remaining lifetime value. Select the low-wear node with the largest expected remaining lifetime value as the target node, and update the pending routing path based on the physical address of the target node to obtain the target routing path. Page writing is performed according to the target routing path to obtain a traffic splitting completion record, and the node wear status is updated according to the traffic splitting completion record to obtain updated flash memory wear data.

2. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, The step of calculating the wear score of each control node based on the flash memory wear data, and dividing the control nodes into a high-wear node set and a low-wear node set based on the wear score, includes: The flash memory wear data includes the control node identifier, current cumulative erase / write count, erase / write growth rate per unit time, node load, and number of available physical blocks; The current cumulative number of erase / write operations, the erase / write growth rate per unit time, and the number of available physical blocks are normalized to obtain the erase / write occupancy ratio, the growth occupancy ratio, and the space shortage ratio. The wear score is obtained by weighting the erase / write occupancy ratio, the growth occupancy ratio, the node load, and the space shortage ratio. When the wear score is greater than a preset high wear threshold, the control node identifier is written into the high wear node set; when the wear score is less than a preset low wear threshold, the control node identifier is written into the low wear node set.

3. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, The step of filtering write requests from the set of high-wear nodes and statistically analyzing the access frequency characteristics and cumulative written data volume of the write requests includes: Obtain a write request, which includes the currently pointed-to control node identifier, data block identifier, request arrival timestamp, number of bytes to be written, and logical block address; compare the control node identifier in the high-wear node set with the currently pointed-to control node identifier to obtain a candidate write request table; The data block identifier in the candidate write request table is used as the collection basis, and multiple write requests for the same data block located within a preset statistical window are filtered according to the request arrival timestamp to obtain the write request set within the window. Based on the number of write requests in the write request set within the window and the duration of the preset statistical window, the access frequency characteristics are obtained, and the cumulative written data volume is obtained by summing the number of bytes written in the write request set within the window.

4. The wear leveling control method for an SLC NAND flash memory controller according to claim 3, characterized in that, Read the pending route path corresponding to the hotspot write request, including: The current address mapping table is read based on the logical block address of the hotspot write request to obtain the pending routing path corresponding to the hotspot write request.

5. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, Calculate the average remaining lifetime of each control node in the high-wear node set and the low-wear node set respectively. Calculate the difference between the average remaining lifetime of the low-wear node set and the average remaining lifetime of the high-wear node set as the wear gap value, including: Based on the current cumulative number of erase / write operations and the erase / write growth rate per unit time for each control node in the set of high-wear nodes and the set of low-wear nodes, calculate the remaining lifetime value for each control node. The average remaining lifetime value of each control node in the high wear node set is calculated to obtain the average remaining lifetime value of the high wear node set, and the average remaining lifetime value of each control node in the low wear node set is calculated to obtain the average remaining lifetime value of the low wear node set. The wear gap value is obtained by calculating the difference between the average remaining lifetime of the low-wear node set and the average remaining lifetime of the high-wear node set.

6. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, The low-wear node with the largest expected remaining lifetime is selected as the target node, and the pending routing path is updated based on the physical address of the target node to obtain the target routing path, including: The expected remaining lifetime values ​​of each low-wear node are sorted, and the low-wear node with the largest expected remaining lifetime value is selected as the target node. Read the physical address information of the target node and write the physical address information into the mapping entry corresponding to the undetermined routing path in the flash translation layer address mapping table to obtain the target routing path.

7. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, The step of performing page writing according to the target routing path to obtain the traffic splitting completion record includes: The target control node is located based on the target control node identifier in the target routing path, and the physical block to be written in the target control node is located based on the target physical block address in the target routing path. The number of bytes to be written corresponding to the physical block to be written is determined based on the number of writable pages of the physical block to be written, and the target control node identifier, the target physical block address and the number of bytes to be written are written into the execution record; According to the write execution record, the hotspot write request is sent to the target control node and page write is performed. The number of bytes written is accumulated. When the number of bytes written is equal to the number of bytes requested to be written, a flow splitting completion record is generated.

8. The wear leveling control method for an SLC NAND flash memory controller according to claim 1, characterized in that, The process of updating the flash memory wear data by recording and updating the node wear status based on the traffic splitting includes: The target control node is located based on the target control node identifier in the traffic diversion completion record, and the read / write request volume and concurrent task number of the target control node in the current statistical period are updated to obtain the updated node load. The target control node's free block table is updated based on the actual number of physical blocks written in the diversion completion record to obtain the updated number of available physical blocks; Read the physical block address and erase count of the erase operation in the traffic completion record, update the erase count table, and summarize the updated current cumulative erase count and erase growth rate per unit time according to the target control node; Updated flash memory wear data is generated based on the updated current cumulative erase / write count, the erase / write growth rate per unit time, the node load, and the number of available physical blocks.

9. A wear-leveling control system for an SLC NAND flash memory controller, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the wear leveling control method for the SLC NAND flash memory controller according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the steps of the wear leveling control method for the SLC NAND flash memory controller as described in any one of claims 1 to 8.

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