High-performance PE computing units, accelerators and methods

Abstract

The application belongs to the technical field of signal processing and acceleration, and relates to a high-performance PE operation unit, an accelerator and a method. Four single-precision floating-point multipliers, four single-precision floating-point cumulative adders, a multiplexer and a global mode configuration register are integrated in a single PE operation unit. Data paths are uniformly scheduled by mode control logic and the multiplexer MUX. The switching between the two modes does not exist an intermediate transition state. Once the hardware path is switched, it immediately enters a full-speed operation state. The idle waste of computing power is eliminated from the root of the architecture. External multi-PE operation unit interconnection and cooperation are not needed. Real number and complex number multiplexing unified hardware interface and software driving are used. Development and switching overhead is significantly reduced. Therefore, the operation performance is greatly improved. The application can be widely applied to the fields of digital beam forming, image processing, scientific computing and artificial intelligence in radar signal processing, so as to improve the system performance.

Description

Technical Field

[0001] This invention belongs to the field of signal processing and acceleration technology, and relates to a high-performance PE computing unit, accelerator and method. Background Technology

[0002] In computationally intensive fields such as radar signal processing (e.g., digital beamforming (DBF)), image processing, scientific computing, and artificial intelligence, matrix multiplication is one of the core fundamental operations, and its computational efficiency directly determines the performance of the entire system. The matrix data in these applications includes both real and complex numbers; for example, radar I / Q data is typical complex data, and it needs to support matrix operations of different scales. Therefore, high-performance and flexible hardware accelerators are crucial for improving system performance.

[0003] Current mainstream PE (Processing Element) acceleration solutions employ two independent MAC (Macro-Machine) hardware sets for real and complex numbers. Internally, the chip uses separate MAC hardware designs for real and complex number multiplication / accumulation units, with these two types of MAC hardware resources isolated and unable to be reused. In single-task scenarios where only real or complex number operations are performed, the entire MAC hardware set corresponding to the other type of operation remains idle, and its computing power cannot be fully utilized. Furthermore, because the two types of operation hardware have independent data input channels, storage address spaces, and control configuration registers, two separate sets of driver scheduling logic need to be written at the software level. Real and complex number operations cannot share the same program execution flow. Therefore, this presents both software-level problems, such as doubling the amount of code in engineering development and significantly increasing the complexity of program debugging and maintenance, and hardware-level problems, such as the parallel consumption of chip wiring and storage resources by the two sets of hardware, resulting in a significant increase in hardware area and lower computing power density.

[0004] A single fixed-function PE only supports real numbers or only complex numbers. Internally, the PE is configured with only one 32-bit floating-point multiplication-addition path. On the one hand, if a fixed PE supporting only real numbers is used to perform complex number operations, complex multiplication involves four scalar multiplications and two addition / subtraction operations. However, a real-number PE can only complete one set of 32-bit real-number multiplications and additions at a time. The hardware itself cannot handle the coordinated computation of the real and imaginary parts of complex numbers in one go. The software must manually split the real and imaginary parts of the complex number, scheduling the same multiplication-addition hardware four times in a time-sharing serial manner to complete the four-term product calculation. Each round of complex number operations requires repeated reading and writing of intermediate real and imaginary temporary data, generating a large amount of redundant storage access and scheduling instruction overhead, significantly reducing data processing efficiency.

[0005] On the other hand, if a fixed PE that only supports complex numbers is used to perform real number operations, the complex PE hardware supports a 64-bit complex number input path, but real number operations only require a 32-bit single scalar to participate in the calculation. During the operation, only the real part path outputs a valid result, while the imaginary part path performs invalid calculations synchronously with the complex number operation process. Real number operations require input in a complex number format with all imaginary parts zero. The corresponding arithmetic unit and storage bandwidth of the imaginary part are occupied throughout the process, but the calculation result has no practical utility, resulting in a halving of the effective floating-point output per unit cycle, low hardware utilization, and the need to occupy more computation cycles for the same computational scale, thus slowing down the overall real number data processing speed. In summary, existing PE arithmetic units still have technical problems in handling mixed real and complex number operation scenarios, such as serious waste of computing power, low hardware resource utilization, additional latency caused by software data splitting, and high development and maintenance costs, resulting in insufficient computing performance. Summary of the Invention

[0006] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a high-performance PE operation unit, accelerator, and method, which can realize a high-performance PE operation unit and support free switching between real number and complex number operations.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a high-performance PE operation unit is provided, in which a single PE operation unit integrates four single-precision floating-point multipliers, four single-precision floating-point accumulators, a multiplexer and a global mode configuration register. The multiplexer is connected to each single-precision floating-point multiplier, each single-precision floating-point accumulator and the global mode configuration register respectively. The multiplexer selectively reconstructs the internal data path of the PE arithmetic unit according to the mode configuration signal of the global mode configuration register. In real number parallel operation mode, the PE arithmetic unit splits the four single-precision floating-point multipliers and four single-precision floating-point accumulators into four independent parallel multiplication-addition data paths for parallel execution of four independent real number multiplication-addition operations. In real number parallel operation mode, the 4 single-precision floating-point multipliers and four single-precision floating-point accumulators are reassembled into a complete complex number multiplication-addition operation path for closed-loop completion of complete complex number multiplication-addition operations within a single PE arithmetic unit.

[0008] In one embodiment, when the mode configuration signal of the global mode configuration register is set to the first value, the PE arithmetic unit is configured in real number parallel arithmetic mode. The multiplexer switches the internal data path of the PE arithmetic unit into four independent and non-interfering data paths. The four single-precision floating-point multipliers and four single-precision floating-point accumulators form four independent multiply-add paths. Each path performs real number multiplication and addition operations synchronously and independently, and there is no data exchange between the paths.

[0009] In one embodiment, when the mode configuration signal of the global mode configuration register is set to the second value, the PE operation unit is configured in complex number complete operation mode; The multiplexer reconstructs the interconnected data paths within the PE arithmetic unit. The four single-precision floating-point multipliers and four single-precision floating-point accumulators within the PE arithmetic unit work together and automatically allocate computational tasks in hardware. This enables the complete complex multiplication and addition operations, including all scalar multiplications, addition and subtraction of real and imaginary parts, and accumulation of results, to be performed in a closed loop within a single PE arithmetic unit.

[0010] In one embodiment, the overall operational precision within the PE arithmetic unit is IEEE 754 single-precision floating-point; The data width in real number parallel operation mode is 32 bits; In the complex number complete operation mode, the data bit width is 64 bits, which consists of a 32-bit real part and a 32-bit imaginary part. The working mode of the global mode configuration register is switched to single-bit register switching.

[0011] In one embodiment, in the real number parallel operation mode, the PE operation unit stores four sets of 32-bit real number results in parallel through the local SRAM_C storage area; in the complex number complete operation mode, the PE operation unit stores one set of 64-bit complex number results through the local SRAM_C storage area; the address step and data bit width of the local SRAM_C storage area are adaptively and dynamically adjusted by the external access control module according to the current operation mode, so as to automatically match the corresponding data length to complete the read and write operations.

[0012] In one embodiment, in the complex number complete operation mode, after two sets of 64-bit complex numbers A(a, b) and B(c, d) are sent to the input bus of the PE operation unit, they are automatically split into four 32-bit scalars by the PE operation unit hardware and sent to four single-precision floating-point multipliers respectively; where a and c represent the real parts of the two sets of complex numbers, and b and d represent the imaginary parts of the two sets of complex numbers respectively. The complete complex multiplication and addition operation performed inside the PE arithmetic unit is (a+bj)(c+dj)=(ac-bd)+(ad+bc)j; where the real part of the complex number ac-bd is obtained by subtraction by one of the single-precision floating-point accumulator adders, and the imaginary part of the complex number ad+bc is obtained by addition by another single-precision floating-point accumulator adder. The real part of the complex number and the historical real part accumulated value read from the local SRAM_C storage area, and the imaginary part of the complex number and the historical imaginary part accumulated value read from the local SRAM_C storage area are respectively accumulated by the other two single-precision floating-point accumulators.

[0013] In one embodiment, in real-number parallel operation mode, the execution process in each clock cycle includes: During the first clock cycle, the two input buses of the PE arithmetic unit send four sets of independent real number pairs to four single-precision floating-point multipliers in parallel; the elements of each set of independent real numbers are 32-bit single-precision floating-point numbers. During the second clock cycle, the four single-precision floating-point multipliers perform multiplication operations respectively, and output the four multiplication results synchronously to the corresponding single-precision floating-point accumulators and adders. At the same time, the four historical accumulation components are read in parallel from the local SRAM_C storage area and sent to the single-precision floating-point accumulators and adders via multiplexers. In the third clock cycle, the four single-precision floating-point accumulators and adders respectively complete the accumulation operation of the multiplication result and the corresponding historical accumulation component, and synchronously generate four independent 32-bit real number results; In the fourth clock cycle, the four 32-bit real number results are merged and written in parallel to the local SRAM_C storage area.

[0014] In one embodiment, in the complex number complete operation mode, the execution process in each clock cycle includes: In the first clock cycle, the input bus of the PE arithmetic unit sends in two sets of 64-bit complex numbers, which are automatically split into four 32-bit scalars by the PE arithmetic unit hardware and sent to four single-precision floating-point multipliers FMUL0 to FMUL3 respectively. In the second clock cycle, single-precision floating-point multiplier FMUL0 calculates ac, single-precision floating-point multiplier FMUL1 calculates bd, single-precision floating-point multiplier FMUL2 calculates ad, and single-precision floating-point multiplier FMUL3 calculates bc. The four products are synchronously output to single-precision floating-point accumulator adder FADD0 and single-precision floating-point accumulator adder FADD1. In the third clock cycle, the single-precision floating-point accumulator adder FADD0 performs a subtraction operation to obtain the real part of the complex number ac-bd, and the single-precision floating-point accumulator adder FADD1 performs an addition operation to obtain the imaginary part of the complex number ad+bc. After synchronously reading the historical real part accumulation value and the historical imaginary part accumulation value of the complex number from the local SRAM_C storage area, they are sent to the single-precision floating-point accumulator adder FADD2 and the single-precision floating-point accumulator adder FADD3 respectively through a multiplexer. In the fourth clock cycle, the single-precision floating-point accumulator adder FADD2 completes the accumulation of the complex real part and the historical real part accumulated value, and the single-precision floating-point accumulator adder FADD3 completes the accumulation of the complex imaginary part and the historical imaginary part accumulated value. In the fifth clock cycle, the accumulated 64-bit complex number result is streamed out and written to the local SRAM_C storage area.

[0015] On the other hand, a matrix multiplication hardware accelerator is also provided, including at least one of the above-mentioned high-performance PE operation units. Each PE operation unit receives a mode configuration signal through a global mode configuration register and performs free switching between real number parallel operation mode and complex number complete operation mode.

[0016] On the other hand, a control method for a high-performance PE computing unit is also provided, applied to the high-performance PE computing unit as described above. The control method includes the following steps: The mode configuration signal is written to the global mode configuration register according to the current data type to be operated on; the mode configuration signal is synchronously sent to the multiplexer in the PE operation unit to complete the switching and reconstruction of the data path in a single cycle, and synchronously triggers the PE operation unit to reset and the local SRAM_C storage area to refresh and clear. According to the mode configuration results, the PE operation unit performs real number multiplication and addition operations synchronously through 4 independent parallel multiplication and addition paths in the real number parallel operation mode; in the complex number complete operation mode, the reorganized complex number operation path performs all scalar multiplication, real and imaginary part addition and subtraction operations and result accumulation of complete complex number multiplication and addition operations in a closed loop within a single PE operation unit. After the operation is completed, the result is written back to the local SRAM_C storage area. In the real number parallel operation mode, four sets of real number results are stored in parallel, and in the complex number complete operation mode, one set of complex number results is stored. The local SRAM_C access control module adaptively adjusts the address step and data bit width according to the current operation mode to automatically match the corresponding data length to complete the read and write operations.

[0017] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned high-performance PE (Precision Execution Unit) arithmetic unit, accelerator, and method integrate four single-precision floating-point multipliers, four single-precision floating-point accumulators, a multiplexer, and a global mode configuration register within a single PE arithmetic unit. Through mode control logic and the multiplexer MUX, the data path is uniformly scheduled. There is no intermediate transition between the two modes; the hardware path immediately enters full-speed operation upon switching. This eliminates idle computing power at the architectural level, eliminates the need for external interconnection and collaboration among multiple PE arithmetic units, and reuses a unified hardware interface and software driver for real and complex numbers. Development and switching overhead are significantly reduced, thereby greatly improving computational performance. It can be widely applied in computationally intensive fields such as digital beamforming, image processing, scientific computing, and artificial intelligence in radar signal processing to enhance system performance. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The internal structure of the PE arithmetic unit to support real number operations; Figure 2 Internal structure diagram of the PE arithmetic unit to support complex number operations; Figure 3 This is a schematic diagram of the structure of a high-performance PE computing unit in one embodiment; Figure 4 This is a flowchart illustrating the process of a high-performance PE arithmetic unit supporting free switching between real and complex number operations in one embodiment. Figure 5 This is a flowchart illustrating the control method of a high-performance PE computing unit in one embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0021] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, and includes such combinations.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] Current mainstream accelerated PE units such as Figure 1 and Figure 2As shown, register A is used to read weight parameters from the RAM channel, register B is used to latch external input, and register C is used to accumulate the result register; a and c represent the real parts of two complex numbers, b and d represent the imaginary parts of two sets of complex numbers, circle X represents multiplication operation, circle + represents addition operation, and circle... The symbol represents a subtraction operation. For clarity, terms appearing for the first time are explained uniformly here. PE stands for Processing Element, the basic arithmetic unit in a matrix multiplication hardware accelerator. FMUL stands for Single-Precision Floating-Point Multiplier, an inherent hardware unit that performs IEEE 754 single-precision floating-point multiplication. FADD stands for Single-Precision Floating-Point Accumulator Adder, an inherent hardware unit that performs IEEE 754 single-precision floating-point addition and historical value accumulation. A multiplexer (MUX) is a hardware switching component that selects different data paths based on control signals; it can be implemented using existing MUXs, as long as they are compatible. SRAM stands for Static Random Access Memory, used for local storage of intermediate results and historical accumulated values. The Global Mode Configuration Register is a register used to store the current arithmetic mode configuration signal for the PE arithmetic unit. IEEE 754 is a floating-point arithmetic standard defined by the IEEE. DBF stands for Digital Beamforming. MAC stands for Multiply-Accumulate Unit. I / Q data is complex data representing in-phase and quadrature components in radar signal processing.

[0024] The technical bottlenecks addressed by this invention can be further subdivided as follows: how to achieve free switching between parallel real number operations and complete complex number operations within a single set of hardware resources, avoiding the mutual isolation and idleness of real number operation hardware and complex number operation hardware; how to fully utilize all floating-point multiply-accumulate hardware resources in real number operation mode to produce multiple sets of independent real number results in parallel, avoiding resource waste caused by invalid operations on the imaginary part path; how to enable a single PE operation unit to complete a complete complex number multiply-accumulate operation in a closed loop within the complex number operation mode, avoiding cross-PE data transmission and software splitting steps; and how to achieve mode switching through a single configuration signal, avoiding the development and scheduling overhead caused by two independent drivers.

[0025] In one embodiment, such as Figure 3As shown, a high-performance PE (Precision Execution) arithmetic unit is provided. A single PE arithmetic unit integrates four single-precision floating-point multipliers (FMUL), four single-precision floating-point accumulators (FADD), a multiplexer (MUX), and a global mode configuration register. The MUX connects to each single-precision floating-point multiplier, each single-precision floating-point accumulator, and the global mode configuration register. Based on the mode configuration signal of the global mode configuration register, the MUX selectively reconstructs the internal data path of the PE arithmetic unit. In real-number parallel operation mode, the four single-precision floating-point multipliers and four single-precision floating-point accumulators are split into four independent parallel multiplication-addition data paths for executing four independent sets of real-number multiplication-addition operations in parallel. In real-number parallel operation mode, the four single-precision floating-point multipliers and four single-precision floating-point accumulators are recombined into a complete complex-number multiplication-addition operation path, used to complete a complete complex-number multiplication-addition operation within a closed loop within the single PE arithmetic unit.

[0026] It is understandable that the challenge lies in fundamentally eliminating the idle computing power problem caused by the isolation between real number and complex number computation hardware in traditional solutions through hardware resource reuse and data path reconstruction within a single PE (Programmable Execution Unit). In existing technologies, real number MAC (Macro- ...

[0027] The high-performance PE arithmetic unit provided in this embodiment integrates four single-precision floating-point multipliers FMUL, four single-precision floating-point accumulators FADD, a multiplexer MUX, and a global mode configuration register within a single PE arithmetic unit. The close collaboration of these four core components is the key to achieving free switching between real and complex numbers.

[0028] Specifically, the global mode configuration register provides mode recognition and switching signals, serving as the mode control center for the entire PE arithmetic unit. The multiplexer (MUX) receives this mode configuration signal and completes the physical reconstruction of all internal data paths within a single cycle, acting as the execution mechanism for dynamic switching of data paths. Four single-precision floating-point multipliers (FMUL) form a parallel scalar multiplication array, providing core floating-point multiplication computing power. Four single-precision floating-point accumulators (FADD) form an accumulation array, providing the accumulation computing power for multiplication results and historical values.

[0029] When the mode configuration signal output by the global mode configuration register is set to its first value (e.g., low level 0 or high level 1), the multiplexer MUX splits the data path inside the PE arithmetic unit into four completely independent and non-interfering multiply-accumulate paths. Each path consists of an FMUL and a FADD connected in series, forming a parallel real number arithmetic mode. In this mode, a single PE arithmetic unit can be equivalent to four independent real number PEs working simultaneously, producing four independent sets of real number multiply-accumulate results in a single cycle.

[0030] When the mode configuration signal output by the global mode configuration register is set to the second value (e.g., high level 1 or low level 0), the multiplexer MUX reconstructs the interconnect data paths within the PE arithmetic unit, recombining the four FMULs and four FADDs into a cohesive complex number operation unit. In this mode, a single PE arithmetic unit completes the entire process of a complex number multiplication and addition operation within a closed loop.

[0031] First, the collaboration between the global mode configuration register and the multiplexer (MUX) enables instantaneous mode recognition and rapid path reconstruction, completing the entire process from signal transmission to physical path switching within a single cycle—a prerequisite for low-latency mode switching. Second, the collaboration between the multiplexer (MUX), four FMULs, and four FADDs allows the same hardware resources to assume different operational topology roles in different modes: as independent parallel units in real number mode and as cascaded collaborative units in complex number mode. Without the reconfiguration capability of the multiplexer (MUX), the four sets of multiply-accumulate hardware would always maintain a fixed topology, failing to achieve dynamic resource reuse. Third, the single-bit switching design of the global mode configuration register, combined with the physical path reconstruction capability of the multiplexer (MUX), allows all mode switching to be completed with only one bit of control information. Compared to the traditional dual-independent MAC scheme, which requires managing two complete sets of configuration registers separately, the control complexity is significantly reduced.

[0032] While this embodiment defines the core components of the PE (Programmable Execution Unit)—namely, four basic components and their functional relationships: four FMULs, four FADDs, a MUX (Multi-channel Execution Unit), and a global mode configuration register—it does not rely on a specific number of PE arrays, a specific manufacturing process node, or a specific SRAM capacity or external bus protocol. Those skilled in the art can adaptively adjust the PE array size, select appropriate semiconductor processes, and configure suitable local storage capacity based on the aforementioned core architecture, according to actual application requirements.

[0033] The aforementioned high-performance PE (Precision Execution Unit) integrates four single-precision floating-point multipliers, four single-precision floating-point accumulators, a multiplexer (MUX), and a global mode configuration register within a single PE unit. Through mode control logic and the MUX, the data path is uniformly scheduled, eliminating intermediate transitions between modes. The hardware path immediately enters full-speed operation upon switching, eliminating idle computing power at the architectural level. It eliminates the need for external interconnection and collaboration among multiple PE units, and uses a unified hardware interface and software driver for real and complex numbers. Development and switching overhead are significantly reduced, thereby greatly improving computing performance. It can be widely applied in computationally intensive fields such as digital beamforming, image processing, scientific computing, and artificial intelligence in radar signal processing to enhance system performance.

[0034] In one embodiment, when the mode configuration signal of the global mode configuration register is set to the first value, the PE arithmetic unit is configured in real number parallel operation mode. The multiplexer MUX switches the internal data path of the PE arithmetic unit into four independent and non-interfering data paths. The four single-precision floating-point multipliers and the four single-precision floating-point accumulators form four independent multiply-accumulate paths, and each path performs real number multiply-accumulate operations synchronously and independently, with no data exchange between the paths.

[0035] When the system only needs to perform real number multiplication and addition operations, it is necessary to study how to make full use of all four sets of multiplication and addition hardware inside the PE operation unit to produce the maximum number of valid real number results, rather than as in the existing technology for complex PE, where only half of the hardware produces valid results and the other half performs invalid imaginary part operations.

[0036] In this embodiment, when the mode configuration signal of the global mode configuration register is set to the first value (taking low level 0 as an example), the PE arithmetic unit enters the real number parallel operation mode. The multiplexer MUX switches the internal data path of the PE arithmetic unit into four completely independent and non-interfering data paths. The four FMULs and four FADDs constitute four independent multiply-add paths, each path containing one FMUL and one FADD. Each path synchronously and independently performs real number multiply-add operations, and there is no data interaction between the paths.

[0037] The four completely independent data paths ensure that the input data, multiplication operations, accumulation operations, and result output of each path are unaffected by the other paths. This means that any anomaly or delay in one path will not propagate to the others, guaranteeing the independence and reliability of the computation results. Furthermore, the four paths execute their operations synchronously within the same clock cycle, achieving complete parallelism in the time dimension.

[0038] The key role of the multiplexer (MUX) here is to achieve physical isolation of the four paths. In real number mode, the multiplexer disconnects the cross-connections between the outputs of each multiplier and the multiple adders, fixing the output of each FMUL to a unique corresponding FADD, thus avoiding data crosstalk. This path isolation function, along with the pattern recognition function of the multiplexer (MUX) mentioned earlier, constitutes two operating states of the same hardware component, demonstrating the core scheduling role of the multiplexer (MUX) in the entire PE arithmetic unit.

[0039] Thus, in real number operation mode, a single PE (Programmer) can produce four independent 32-bit real number multiplication and addition results in parallel, achieving an effective real number computing power output that is four times that of a traditional PE that only supports complex numbers in the same clock cycle. This is because in traditional complex number fixed PE operations, the imaginary path is occupied throughout but produces invalid results, resulting in only one effective real number result per unit cycle. However, by using the real-time path splitting of the multiplexer (MUX), all four sets of hardware resources are dedicated to effective real number operations.

[0040] In one embodiment, when the mode configuration signal of the global mode configuration register is set to the second value, the PE arithmetic unit is configured in complex full arithmetic mode. The multiplexer MUX reconstructs the internal interconnection data path of the PE arithmetic unit. The four single-precision floating-point multipliers and four single-precision floating-point accumulators inside the PE arithmetic unit work together and automatically allocate arithmetic tasks in hardware. This is used to perform all scalar multiplication, real and imaginary part addition and subtraction operations, and result accumulation of complete complex multiplication and addition operations in a closed loop within a single PE arithmetic unit.

[0041] It is understandable that when the system needs to perform complex multiplication and addition operations, it is also necessary to study how to enable a single PE operation unit to complete the complete complex multiplication and addition operation in an internal closed loop, without relying on software to manually split the real and imaginary parts of the data, schedule the hardware multiple times in time-sharing, and repeatedly read and write intermediate data as in traditional real number PEs, and without needing to transmit the intermediate results of the real and imaginary parts across multiple PE units as in traditional complex number schemes based on multiple PE splicing.

[0042] In this embodiment, when the mode configuration signal of the global mode configuration register is set to the second value (taking high level 1 as an example), the PE arithmetic unit enters the complex number full arithmetic mode. The multiplexer MUX reconstructs the interconnection data path inside the PE arithmetic unit, enabling the four FMULs and four FADDs to work collaboratively, and the hardware automatically allocates arithmetic tasks. Specifically, the collaboration method is as follows: the four FMULs synchronously perform four-term scalar multiplication calculations of complex numbers, two of the four FADDs are used to calculate the real and imaginary parts of the complex number, respectively, and the other two are used to perform real part accumulation and imaginary part accumulation, respectively.

[0043] In traditional solutions, completing a full complex multiplication and addition operation requires the cooperation of multiple PE units or the software to schedule the same PE multiple times. However, this embodiment reconstructs the internal interconnection through a multiplexer (MUX). Within a single PE, the four FMUL and four FADD are topologically reorganized according to the mathematical logic of complex operations. This allows the entire process of decomposition, calculation, and accumulation of complex multiplication to be completed in a closed loop within a single PE unit, without relying on other external PE operation units.

[0044] In complex mode, the multiplexer MUX connects the outputs of the four FMULs to FADD0 and FADD1 simultaneously. This allows FADD0 to receive the product of ac and bd to perform subtraction to obtain the real part, and FADD1 to receive the product of ad and bc to perform addition to obtain the imaginary part. At the same time, the multiplexer MUX routes the historical real part accumulation value and the historical imaginary part accumulation value read from the local SRAM_C storage area to FADD2 and FADD3 respectively, completing the final accumulation with the current real and imaginary parts.

[0045] In this way, a single PE (Programmer) operation unit can complete a full complex multiplication and addition operation in a closed loop, without the need to transmit real and imaginary data across PEs or to split and reassemble the data in software. With the same number of PE operation units and top-level architecture, the number of deployable complex parallel channels is four times that of traditional multi-PE splicing schemes.

[0046] In one embodiment, the overall operational precision within the PE arithmetic unit is IEEE 754 single-precision floating-point. The data width is 32 bits in real number parallel operation mode and 64 bits in complex number full operation mode. The 64 bits consist of a 32-bit real part and a 32-bit imaginary part, and the global mode configuration register switches to a single-bit register switching mode.

[0047] It is understandable that in an architecture that allows free switching between real and complex number operations, it is necessary to consider how to determine the data bit width and operation precision specifications so that the calculation precision in both modes can meet the high-precision calculation requirements of radar signal processing and artificial intelligence, while minimizing the overhead of control information transmission during mode switching.

[0048] This embodiment further limits the overall operational precision within the PE arithmetic unit to IEEE 754 single-precision floating-point. In real number parallel arithmetic mode, the data width is 32 bits; in complex number full arithmetic mode, the data width is 64 bits, consisting of a 32-bit real part and a 32-bit imaginary part. Simultaneously, the global mode configuration register switches to a single-bit register switching mode, meaning that only 1 bit of information needs to be written to complete the entire switching operation between real and complex number arithmetic modes.

[0049] The choice of the IEEE 754 single-precision floating-point specification matches the accuracy requirements of target applications such as radar signal processing and artificial intelligence inference, achieving lower data bit width and storage bandwidth requirements while ensuring computational accuracy. The design of 64-bit complex numbers consisting of a 32-bit real part and a 32-bit imaginary part ensures that the total width of complex data is exactly twice the width of real data, and the physical width of the input bus can be multiplexed in two modes.

[0050] In this embodiment, single-bit register switching means that mode switching can be completed with only 1 bit of control signal. This implies that the CPU only needs to perform a single register write operation to synchronously send the mode configuration to all PE operation units, resulting in extremely low switching latency. The simplicity of single-bit register switching makes the MUX decoding logic extremely simple, and the physical delay of the mode switching control path is controllable, ensuring the determinism of mode switching.

[0051] In this way, by using a unified IEEE 754 single-precision floating-point precision level and a single-bit register switching mechanism, the PE arithmetic unit can provide industry-standard computational precision in both arithmetic modes, while the control overhead of mode switching is reduced to the theoretical minimum.

[0052] In one embodiment, in the real number parallel operation mode, the PE operation unit stores four sets of 32-bit real number results in parallel through the local SRAM_C storage area; in the complex number complete operation mode, the PE operation unit stores one set of 64-bit complex number results through the local SRAM_C storage area; the address step and data bit width of the local SRAM_C storage area are adaptively and dynamically adjusted by the external access control module according to the current operation mode, so as to automatically match the corresponding data length to complete the read and write operations.

[0053] It is understandable that the PE (Programming Execution Unit) produces results with different bit widths and numbers of groups in real and complex modes; that is, it produces four 32-bit groups in real mode and one 64-bit group in complex mode. If the local storage area adopts a fixed bit width and fixed address step access method, it will inevitably lead to data concatenation or splitting for storage operations in one mode, increasing access latency and potentially introducing data alignment errors.

[0054] Therefore, in this embodiment, the PE arithmetic unit is connected to a local SRAM_C storage area for storing arithmetic results. In real-number parallel arithmetic mode, the local SRAM_C storage area stores four sets of 32-bit real-number results in parallel; in complex-number complete arithmetic mode, the local SRAM_C storage area stores one set of 64-bit complex-number results. The address step and data bit width of the local SRAM_C storage area can be dynamically adjusted adaptively by an external access control module according to the current arithmetic mode to automatically match the corresponding data length for read / write operations, without requiring manual software configuration of the address offset.

[0055] When the mode configuration signal of the global mode configuration register changes, the signal is synchronously transmitted to the access control module inherent in the local SRAM_C storage area, so that the address stepping strategy and data bit width settings on the storage side are completely consistent with the mode state on the operation side. Thus, after the mode switch, the read and write behavior of the local SRAM_C storage area can automatically adapt to the new data format without additional software intervention, completely eliminating the need for software to configure storage parameters.

[0056] The physical memory array of the local SRAM_C memory area reuses the same memory bank in both modes, and achieves conflict-free access to different data bit widths only by switching the address stepping strategy. This design avoids the practice of allocating independent memory areas for the two modes, and further reduces the occupation of chip memory resources.

[0057] In this way, the result write-back and read-out operations of the PE operation unit in both operation modes are completely completed by hardware adaptively. The software only needs to focus on the preparation of input data and the reading of output data, without having to process or perceive the bit width difference and address alignment details of the underlying storage, which greatly simplifies the software programming model.

[0058] In one embodiment, in the complex number complete operation mode, after two sets of 64-bit complex numbers A(a, b) and B(c, d) are sent to the input bus of the PE operation unit, they are automatically split into four 32-bit scalars by the PE operation unit hardware and sent to four single-precision floating-point multipliers respectively; where a and c represent the real parts of the two sets of complex numbers, and b and d represent the imaginary parts of the two sets of complex numbers respectively.

[0059] The complete complex multiplication and addition operation performed internally by the PE arithmetic unit is (a+bj)(c+dj)=(ac-bd)+(ad+bc)j. Here, the real part of the complex number ac-bd is obtained by subtraction performed by one of the single-precision floating-point accumulators, and the imaginary part ad+bc is obtained by addition performed by the other single-precision floating-point accumulator. The real part of the complex number is accumulated with the historical real part read from the local SRAM_C storage area, and the imaginary part of the complex number is accumulated with the historical imaginary part read from the local SRAM_C storage area, respectively, by the other two single-precision floating-point accumulators.

[0060] It is understandable that, in complex mode, the PE operation unit hardware should automatically and correctly split the two sets of input complex data into four scalars, and reasonably distribute the results of the four scalar multiplications to each adder to correctly implement the mathematical operation of complex multiplication and addition, so as to ensure that the final complex result produced by the hardware is completely consistent with the mathematical definition of complex multiplication and addition.

[0061] In this embodiment, under the complex number complete operation mode, two sets of 64-bit complex numbers A(a, b) and B(c, d) are sent into the input bus. The PE operation unit hardware automatically splits them into four 32-bit scalars: a, b, c, and d, and sends them into four single-precision floating-point multipliers FMUL0 to FMUL3 respectively.

[0062] The complete complex multiplication and addition operation performed internally by the PE arithmetic unit corresponds to (a+bj)(c+dj)=(ac-bd)+(ad+bc)j. Specifically, FMUL0 calculates ac, FMUL1 calculates bd, FMUL2 calculates ad, and FMUL3 calculates bc. FADD0 receives the product of ac and bd and performs a subtraction operation ac-bd to obtain the real part of the complex number. FADD1 receives the product of ad and bc and performs an addition operation ad+bc to obtain the imaginary part of the complex number. Subsequently, FADD2 accumulates the real part ac-bd with the historical accumulated value of the real part read from the local SRAM_C memory area. FADD3 accumulates the imaginary part ad+bc with the historical accumulated value of the imaginary part read from the local SRAM_C memory area.

[0063] The multiplication task allocation of FMUL0 to FMUL3 strictly corresponds to the four-term scalar multiplication expansion of complex multiplication. An incorrect task allocation for any multiplier can lead to errors in the calculation of the real or imaginary part of the final result. The task allocations of FADD0 and FADD1 correspond to the subtraction of the real part and the addition of the imaginary part in the algebraic expression of the complex multiplication result, respectively, demonstrating a precise mapping between the hardware operation topology and the mathematical expression. The accumulation operations of FADD2 and FADD3 are strictly coordinated with the timing of reading historical values ​​to ensure that the results of the current calculation batch are correctly superimposed on the historical accumulated results.

[0064] The aforementioned design utilizes a complete mapping link from mathematical expressions to hardware circuits: the mathematical expansion of complex multiplication is reconstructed and mapped through the data path of the multiplexer (MUX) into a five-stage hardware pipeline consisting of four parallel scalar multiplications, two component calculations, and two accumulations. This allows the hardware to automatically complete the entire process of solving the real and imaginary parts of complex numbers, scalar multiplication allocation, component calculations, and historical accumulation. The entire operation is completed in a closed loop within a single PE, and the calculation results strictly conform to the mathematical definition of complex multiplication and addition.

[0065] In one embodiment, in real number parallel operation mode, the execution process in each clock cycle may include: During the first clock cycle, the two input buses of the PE arithmetic unit send four independent pairs of real numbers in parallel to four single-precision floating-point multipliers FMUL0 to FMUL3; the elements of each pair of independent real numbers are 32-bit single-precision floating-point numbers.

[0066] In the second clock cycle, the four single-precision floating-point multipliers FMUL0 to FMUL3 perform multiplication operations respectively, and output the four multiplication results synchronously to the corresponding single-precision floating-point accumulators FADD0 to FADD3. At the same time, four historical accumulation components are read in parallel from the local SRAM_C storage area and sent to the single-precision floating-point accumulators FADD0 to FADD3 via the multiplexer MUX. In this clock cycle, the multiplication operation and the SRAM read operation are performed synchronously, realizing the time multiplexing of calculation and storage access without adding extra clock overhead.

[0067] During the third clock cycle, four single-precision floating-point accumulators FADD0 to FADD3 perform the accumulation operation of the multiplication result and the corresponding historical accumulation component, respectively, and synchronously generate four independent 32-bit real number results. In the fourth clock cycle, the four 32-bit real number results are merged and written in parallel to the local SRAM_C storage area.

[0068] The four clock cycles described above constitute a complete real number multiply-accumulate pipeline stage. The entire process from loading input data to writing back the final result requires only four clock cycles, and the pipeline can simultaneously handle different batches of data at different processing stages in each clock cycle under steady-state conditions.

[0069] In this embodiment, the cooperative function of the multiplexer (MUX) in the second clock cycle is that it simultaneously routes the physical paths of the four historical accumulated components read from the SRAM to their respective FADDs. Since the switching of the MUX has been completed during the mode configuration phase, the read path does not require additional switching latency during the operation phase. Thus, in real number mode, the PE (Multiply-Accumulate) arithmetic unit completes the full multiplication-accumulation operation and result write-back in a pipelined manner within four clock cycles. The number of valid real number results produced per unit time by the four fully parallel operations is four times that of the traditional single multiplication-accumulation path PE.

[0070] In one embodiment, how do the four FMUL and four FADD in complex number mode collaboratively complete the five-stage pipelined operation of complex multiplication—decomposition calculation, component synthesis, and historical accumulation—to ensure correct data transfer between stages without timing conflicts? In this embodiment, under the complete complex number operation mode, the execution process in each clock cycle may specifically include: During the first clock cycle, two sets of 64-bit complex numbers are sent into the input bus of the PE arithmetic unit. The PE arithmetic unit hardware automatically splits them into four 32-bit scalars and sends them to four single-precision floating-point multipliers FMUL0 to FMUL3.

[0071] In the second clock cycle, single-precision floating-point multiplier FMUL0 calculates ac, single-precision floating-point multiplier FMUL1 calculates bd, single-precision floating-point multiplier FMUL2 calculates ad, and single-precision floating-point multiplier FMUL3 calculates bc. The four products are synchronously output to single-precision floating-point accumulator adders FADD0 and FADD1. The outputs of single-precision floating-point multipliers FMUL0 and FMUL1 are connected to single-precision floating-point accumulator adder FADD0 for subsequent subtraction, and the outputs of single-precision floating-point multipliers FMUL2 and FMUL3 are connected to single-precision floating-point accumulator adder FADD1 for subsequent addition. This connection is established by the multiplexer MUX in the current mode configuration.

[0072] In the third clock cycle, the single-precision floating-point accumulator adder FADD0 performs a subtraction operation to obtain the real part of the complex number ac-bd, and the single-precision floating-point accumulator adder FADD1 performs an addition operation to obtain the imaginary part of the complex number ad+bc. After synchronously reading the historical real part accumulation value and the historical imaginary part accumulation value of the complex number from the local SRAM_C storage area, they are sent to the single-precision floating-point accumulator adder FADD2 and the single-precision floating-point accumulator adder FADD3 respectively via the multiplexer MUX. In this clock cycle, the component calculation of the adder and the reading of the historical value of SRAM are performed in parallel, realizing the time multiplexing of calculation and storage operations.

[0073] In the fourth clock cycle, the single-precision floating-point accumulator adder FADD2 completes the accumulation of the complex real part and the historical real part accumulated value, and the single-precision floating-point accumulator adder FADD3 completes the accumulation of the complex imaginary part and the historical imaginary part accumulated value. In the fifth clock cycle, the accumulated 64-bit complex number result is streamed out and written to the local SRAM_C storage area.

[0074] In this embodiment, the addition and subtraction operations of single-precision floating-point accumulator adders FADD0 and FADD1 in the third clock cycle, together with the accumulation operations of single-precision floating-point accumulator adders FADD2 and FADD3 in the fourth clock cycle, form a two-stage addition pipeline.

[0075] Thus, in complex mode, the PE arithmetic unit completes the full complex multiplication and addition operation through a five-stage pipeline within five clock cycles. The hardware automatically completes the entire process of real and imaginary part solution, four-term scalar multiplication, component synthesis, and historical accumulation, without the need for external PE collaboration or software intervention.

[0076] The design of the aforementioned high-performance PE arithmetic unit supports a process that allows for free switching between real and complex number operations, as follows: Figure 4 As shown, compared with existing technologies: First, a single PE (Programmer) operation unit integrates four complete multiply-accumulate hardware sets, ensuring full-load operation of all hardware in both modes, eliminating idle computing power at the architectural level. Each PE operation unit incorporates four single-precision floating-point multipliers and four adders, with data paths uniformly scheduled through mode control logic and a multiplexer (MUX): in real number mode, it is split into four independent parallel channels for synchronous operation; in complex number mode, it is reassembled into a complete complex number operation path, with all four multipliers participating in the four scalar calculations and accumulations. The hardware utilization rate is close to 100% in both modes, solving the problems of resource waste in traditional dual-independent MAC (Multi-MAC Access Control) systems and low utilization of fixed-function PEs. This stems from the close collaboration between the multiplexer (MUX) and the global mode configuration register: the global mode configuration register provides mode recognition signals, and the multiplexer (MUX) completes the physical reconstruction of all data paths within a single cycle. There is no intermediate transition between the two modes; the hardware path immediately enters full-speed operation upon switching, achieving zero computing power waste through their combined operation.

[0077] Secondly, a single PE (Programmer) operation unit completes the full complex multiplication and addition operation within a closed loop, eliminating the need for external interconnection and collaboration among multiple PE operation units. In this invention, a single PE operation unit can independently complete all scalar multiplication, addition, subtraction, and result accumulation of complex multiplication, all within a closed loop within the unit. This eliminates the need for cross-PE data transmission of real and imaginary components and software splitting and reassembly. Under the premise of a consistent number of array PE operation units and top-level architecture scale, this invention can deploy four times the number of parallel complex channels compared to traditional multi-PE splicing schemes. This is due to the interconnection and reconstruction of four single-precision floating-point multipliers (FMUL) and four single-precision floating-point accumulators (FADD) in complex mode via a multiplexer (MUX). This allows a single PE to decompose complex multiplication into four parallel scalar multiplications at once and automatically allocate adders to complete the calculation of real and imaginary components and historical accumulation. The collaborative reassembly of these hardware components in complex mode ensures that complex operations are completely closed-loop within a single PE, completely eliminating cross-PE communication bottlenecks.

[0078] Third, the unified hardware interface and software driver for real and complex numbers significantly reduce development and switching overhead. This invention switches operation types solely through global mode configuration registers, and the multiplexer (MUX) can reconstruct the internal path in a single cycle, eliminating the need to develop two independent control programs and drastically reducing development, debugging, and maintenance costs. Compared to the traditional dual-MAC architecture, this invention eliminates the need to reconfigure the entire register set or refresh two cache areas for task switching, effectively reducing scheduling latency. This is due to the synergy between the single-bit switching mechanism of the global mode configuration registers and the instantaneous response capability of the multiplexer (MUX): only a 1-bit control signal is needed to trigger the complete switching process from register issuance to data path reconstruction. Compared to traditional solutions that require reconfiguring multiple complete register sets, the switching latency is significantly reduced.

[0079] Fourth, the local SRAM_C and the access control module adaptively adapt the data bit width and address step in both modes. In real number mode, it automatically accesses four sets of results in parallel in 32-bit units, and in complex number mode, it automatically accesses one set of results in 64-bit units. The software does not need to be aware of the underlying storage details or manually calculate the address offset. This is due to the linkage design between SRAM_C and the global mode configuration register: that is, the global mode configuration signal is simultaneously transmitted to the access control module, enabling it to synchronously adapt to the read and write modes. This cooperative feature ensures complete consistency among the three aspects of operation accuracy, storage bit width, and mode switching.

[0080] In one embodiment, a matrix multiplication hardware accelerator is also provided, including at least one of the above-mentioned high-performance PE operation units. Each PE operation unit receives a mode configuration signal uniformly through a global mode configuration register and performs free switching between real number parallel operation mode and complex number complete operation mode.

[0081] It is understood that this embodiment studies how to integrate multiple PE operation units that can freely switch between real and complex number operations into a matrix multiplication hardware accelerator system to achieve array-level unified mode management and collaborative operation.

[0082] In this embodiment, the matrix multiplication hardware accelerator includes at least one PE operation unit as described in the previous embodiment. Each PE operation unit receives a mode configuration signal uniformly through a global mode configuration register. When the CPU writes the mode configuration signal to the global mode configuration register, the signal is synchronously sent to all PE operation units within the accelerator. All PEs complete the data path switching and reconstruction of their respective internal multiplexers (MUX) within the same clock cycle, and the entire PE array synchronously enters the corresponding operation mode.

[0083] Each PE (Process Execution Unit) has its own independent local SRAM_C storage area. The result storage and retrieval operations of each PE are adaptively managed by its respective access control module according to the unified mode configuration signal, without interference between them. The global mode configuration register provides array-level consistency control, ensuring that all PEs are in the same operation mode at the same time, avoiding data misalignment problems caused by inconsistencies between different PE modes. At the same time, each PE independently executes operations and manages its local storage in the unified mode, ensuring the scalability of the array and the independence of each PE's operations.

[0084] The aforementioned matrix multiplication hardware accelerator, through unified global mode configuration and arrayed PE deployment, enables the accelerator system to achieve N×4 independent real-number parallel computing capabilities in real-number mode and N complete complex-number parallel computing capabilities in complex-number mode, where N is the number of PE computing units. For explanations regarding the high-performance PE computing units in this embodiment, please refer to the corresponding explanations in the aforementioned embodiments of high-performance PE computing units.

[0085] In one embodiment, such as Figure 5 As shown, a control method for a high-performance PE computing unit is also provided, applied to the high-performance PE computing unit as described above. The control method may include the following steps S10 to S14: S10: Write a mode configuration signal to the global mode configuration register according to the current data type to be operated on; The mode configuration signal is synchronously sent to the multiplexer in the PE operation unit to complete the switching and reconstruction of the data path in a single cycle, and synchronously triggers the PE operation unit to reset and the local SRAM_C storage area to refresh and clear. S12, According to the mode configuration result, the PE operation unit performs real number multiplication and addition operations synchronously through 4 independent parallel multiplication and addition paths in the real number parallel operation mode; wherein, in the complex number complete operation mode, the complete complex number multiplication and addition operation, including all scalar multiplication, real and imaginary part addition and subtraction operations, and result accumulation, is performed in a closed loop within a single PE operation unit through the reorganized complex number operation path. S14. After the operation is completed, the operation result is written back to the local SRAM_C storage area. In the real number parallel operation mode, four sets of real number results are stored in parallel, and in the complex number complete operation mode, one set of complex number results is stored. The local SRAM_C access control module adaptively adjusts the address step and data bit width according to the current operation mode to automatically match the corresponding data length to complete the read and write operation.

[0086] The control method for the aforementioned high-performance PE (Precision Execution Unit) is based on integrating four single-precision floating-point multipliers, four single-precision floating-point accumulators, a multiplexer, and a global mode configuration register within a single PE unit. Data paths are uniformly scheduled through mode control logic and the multiplexer (MUX). There is no intermediate transition between the two modes; the hardware path immediately enters full-speed operation upon switching. This eliminates idle computing power at the architectural level, eliminates the need for external interconnection and collaboration among multiple PE units, and reuses a unified hardware interface and software driver for real and complex numbers. Development and switching overhead are significantly reduced, thereby greatly improving computing performance. This method can be widely applied in computationally intensive fields such as digital beamforming, image processing, scientific computing, and artificial intelligence in radar signal processing to enhance system performance.

[0087] It is understood that the explanations of the features in the control method of the above-mentioned high-performance PE computing unit can be understood by referring to the corresponding explanations in the embodiments of the above-mentioned high-performance PE computing unit.

[0088] It should be understood that, although the above process Figure 5 The steps in the diagram are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above process... Figure 5 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A high-performance PE computing unit, characterized in that, Each PE arithmetic unit integrates four single-precision floating-point multipliers, four single-precision floating-point accumulators, a multiplexer, and a global mode configuration register. The multiplexer is connected to each single-precision floating-point multiplier, each single-precision floating-point accumulator, and the global mode configuration register, respectively. The multiplexer selectively reconstructs the internal data path of the PE arithmetic unit according to the mode configuration signal of the global mode configuration register. In real number parallel operation mode, the PE arithmetic unit splits the four single-precision floating-point multipliers and four single-precision floating-point accumulators into four independent parallel multiplication-addition data paths for parallel execution of four independent real number multiplication-addition operations. In real number parallel operation mode, the 4 single-precision floating-point multipliers and four single-precision floating-point accumulators are reassembled into a complete complex number multiplication-addition operation path for closed-loop completion of complete complex number multiplication-addition operations within a single PE arithmetic unit.

2. The high-performance PE computing unit according to claim 1, characterized in that, When the mode configuration signal of the global mode configuration register is set to the first value, the PE arithmetic unit is configured in real number parallel arithmetic mode; The multiplexer switches the internal data path of the PE arithmetic unit into four independent and non-interfering data paths. The four single-precision floating-point multipliers and four single-precision floating-point accumulators form four independent multiply-add paths. Each path performs real number multiplication and addition operations synchronously and independently, and there is no data exchange between the paths.

3. The high-performance PE computing unit according to claim 1, characterized in that, When the mode configuration signal of the global mode configuration register is set to the second value, the PE arithmetic unit is configured in complex number full arithmetic mode; The multiplexer reconstructs the interconnected data paths within the PE arithmetic unit. The four single-precision floating-point multipliers and four single-precision floating-point accumulators within the PE arithmetic unit work together and automatically allocate computational tasks in hardware. This enables the complete complex multiplication and addition operations, including all scalar multiplications, addition and subtraction of real and imaginary parts, and accumulation of results, to be performed in a closed loop within a single PE arithmetic unit.

4. The high-performance PE computing unit according to any one of claims 1 to 3, characterized in that, The overall operational precision within the PE arithmetic unit is IEEE 754 single-precision floating-point. The data width in the real number parallel operation mode is 32 bits; The data width in the complex number full operation mode is 64 bits, which consists of a 32-bit real part and a 32-bit imaginary part. The working mode of the global mode configuration register is switched to single-bit register switching.

5. The high-performance PE computing unit according to claim 1, characterized in that, In real number parallel operation mode, the PE operation unit stores four sets of 32-bit real number results in parallel through the local SRAM_C storage area; in complex number complete operation mode, the PE operation unit stores one set of 64-bit complex number results through the local SRAM_C storage area; the address step and data bit width of the local SRAM_C storage area are adaptively and dynamically adjusted by the external access control module according to the current operation mode, which is used to automatically match the corresponding data length to complete the read and write operations.

6. The high-performance PE computing unit according to claim 1 or 3, characterized in that, In the complex number complete operation mode, after two sets of 64-bit complex numbers A(a, b) and B(c, d) are sent to the input bus of the PE operation unit, they are automatically split into four 32-bit scalars by the PE operation unit hardware and sent to four single-precision floating-point multipliers respectively; where a and c represent the real parts of the two sets of complex numbers, and b and d represent the imaginary parts of the two sets of complex numbers respectively. The complete complex multiplication and addition operation performed inside the PE arithmetic unit is (a+bj)(c+dj)=(ac-bd)+(ad+bc)j; where the real part of the complex number ac-bd is obtained by subtraction by one of the single-precision floating-point accumulator adders, and the imaginary part of the complex number ad+bc is obtained by addition by another single-precision floating-point accumulator adder. The real part of the complex number and the historical real part accumulated value read from the local SRAM_C storage area, and the imaginary part of the complex number and the historical imaginary part accumulated value read from the local SRAM_C storage area are respectively accumulated by the other two single-precision floating-point accumulators.

7. The high-performance PE computing unit according to claim 2, characterized in that, In real number parallel operation mode, the execution process in each clock cycle includes: During the first clock cycle, the two input buses of the PE arithmetic unit send four sets of independent real number pairs to four single-precision floating-point multipliers in parallel; the elements of each set of independent real numbers are 32-bit single-precision floating-point numbers. During the second clock cycle, the four single-precision floating-point multipliers perform multiplication operations respectively, and output the four multiplication results synchronously to the corresponding single-precision floating-point accumulators and adders. At the same time, the four historical accumulation components are read in parallel from the local SRAM_C storage area and sent to the single-precision floating-point accumulators and adders via multiplexers. In the third clock cycle, the four single-precision floating-point accumulators and adders respectively complete the accumulation operation of the multiplication result and the corresponding historical accumulation component, and synchronously generate four independent 32-bit real number results; In the fourth clock cycle, the four 32-bit real number results are merged and written in parallel to the local SRAM_C storage area.

8. The high-performance PE computing unit according to claim 6, characterized in that, In the complex number complete operation mode, the execution process in each clock cycle includes: In the first clock cycle, the input bus of the PE arithmetic unit sends in two sets of 64-bit complex numbers, which are automatically split into four 32-bit scalars by the PE arithmetic unit hardware and sent to four single-precision floating-point multipliers FMUL0 to FMUL3 respectively. In the second clock cycle, single-precision floating-point multiplier FMUL0 calculates ac, single-precision floating-point multiplier FMUL1 calculates bd, single-precision floating-point multiplier FMUL2 calculates ad, and single-precision floating-point multiplier FMUL3 calculates bc. The four products are synchronously output to single-precision floating-point accumulator adder FADD0 and single-precision floating-point accumulator adder FADD1. In the third clock cycle, the single-precision floating-point accumulator adder FADD0 performs a subtraction operation to obtain the real part of the complex number ac-bd, and the single-precision floating-point accumulator adder FADD1 performs an addition operation to obtain the imaginary part of the complex number ad+bc. After synchronously reading the historical real part accumulation value and the historical imaginary part accumulation value of the complex number from the local SRAM_C storage area, they are sent to the single-precision floating-point accumulator adder FADD2 and the single-precision floating-point accumulator adder FADD3 respectively through a multiplexer. In the fourth clock cycle, the single-precision floating-point accumulator adder FADD2 completes the accumulation of the complex real part and the historical real part accumulated value, and the single-precision floating-point accumulator adder FADD3 completes the accumulation of the complex imaginary part and the historical imaginary part accumulated value. In the fifth clock cycle, the accumulated 64-bit complex number result is streamed out and written to the local SRAM_C storage area.

9. A matrix multiplication hardware accelerator, characterized in that, It includes at least one high-performance PE operation unit as described in any one of claims 1 to 8, wherein each PE operation unit receives a mode configuration signal uniformly through a global mode configuration register and performs free switching between real number parallel operation mode and complex number complete operation mode.

10. A control method for a high-performance PE computing unit, applied to the high-performance PE computing unit as described in any one of claims 1 to 8, characterized in that, Including the following steps: The mode configuration signal is written to the global mode configuration register according to the current data type to be operated on; the mode configuration signal is synchronously sent to the multiplexer in the PE operation unit to complete the switching and reconstruction of the data path in a single cycle, and synchronously triggers the PE operation unit to reset and the local SRAM_C storage area to refresh and clear. According to the mode configuration results, the PE operation unit performs real number multiplication and addition operations synchronously through 4 independent parallel multiplication and addition paths in the real number parallel operation mode; in the complex number complete operation mode, the reorganized complex number operation path performs all scalar multiplication, real and imaginary part addition and subtraction operations and result accumulation of complete complex number multiplication and addition operations in a closed loop within a single PE operation unit. After the operation is completed, the result is written back to the local SRAM_C storage area. In the real number parallel operation mode, four sets of real number results are stored in parallel, and in the complex number complete operation mode, one set of complex number results is stored. The local SRAM_C access control module adaptively adjusts the address step and data bit width according to the current operation mode to automatically match the corresponding data length to complete the read and write operations.

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