Accumulator structure, arithmetic device and accumulator control method

Abstract

This invention provides an accumulator structure, a computing device, and an accumulator control method. The accumulator structure includes a multi-stage accumulator circuit module and a controller. In a first mode, the controller provides a data sequence to the input of the multi-stage accumulator circuit module and feeds back the first output of the multi-stage accumulator circuit module to the accumulation point of the multi-stage accumulator circuit module based on a first feedback path. In a second mode, the controller further feeds back the second output of the multi-stage accumulator circuit module to the input of the multi-stage accumulator circuit module based on a second feedback path. This improves the performance of the accumulator.

Description

Technical Field

[0001] This invention relates to a circuit structure, and more particularly to an accumulator structure, an arithmetic device, and an accumulator control method. Background Technology

[0002] Traditional accumulators may employ a multi-stage pipelined architecture to improve operating clock speed. However, due to the feedback dependency of accumulation operations, pipeline latency may prevent the accumulation result from being used in subsequent accumulation operations in a timely manner, thus affecting the implementation of the accumulation function. In addition, in practice, supporting the pipelined architecture of the accumulator may also require more cache space for final data merging, leading to increased system implementation costs. Summary of the Invention

[0003] The present invention provides an accumulator structure, a computing device, and an accumulator control method, which can improve the above-mentioned problems.

[0004] An exemplary embodiment of the present invention provides an accumulator structure including a multi-stage accumulator circuit module and a controller. The controller is connected to the multi-stage accumulator circuit module. The controller is configured to: in a first mode, provide a data sequence to the input terminal of the multi-stage accumulator circuit module; in the first mode, feed back a first output of the multi-stage accumulator circuit module to the accumulation point of the multi-stage accumulator circuit module based on a first feedback path; and in a second mode, feed back a second output of the multi-stage accumulator circuit module to the input terminal of the multi-stage accumulator circuit module based on a second feedback path.

[0005] In an exemplary embodiment of the present invention, the controller is further configured to: in the first mode, after the target data segment in the data sequence enters the input terminal of the multi-level accumulation circuit module, trigger the multi-level accumulation circuit module to enter the second mode in the next clock cycle.

[0006] In an exemplary embodiment of the present invention, the target data segment includes an empty data segment.

[0007] In an exemplary embodiment of the present invention, the target data segment is located at the very end of the data sequence.

[0008] In an exemplary embodiment of the present invention, the operation of the controller triggering the multi-level accumulation circuit module to enter the second mode in the next clock cycle includes: adding a tail mark to the end of the target data segment in the data sequence; and controlling the multi-level accumulation circuit module to enter the second mode according to the tail mark in the next clock cycle.

[0009] In an exemplary embodiment of the present invention, the controller is further configured to: in a first mode, activate the first feedback path and deactivate the second feedback path; and in a second mode, activate the second feedback path and deactivate the first feedback path.

[0010] In an exemplary embodiment of the present invention, the controller is further configured to: after feeding back the second output of the multi-level accumulation circuit module to the input of the multi-level accumulation circuit module, control the multi-level accumulation circuit module to return to the first mode; and in the first mode, control the multi-level accumulation circuit module to accumulate the second output fed back via the second feedback path and the first output fed back via the first feedback path to generate a third output.

[0011] In an exemplary embodiment of the present invention, the multi-stage accumulation circuit module includes a multiplexer circuit connected to the input terminal of the multi-stage accumulation circuit module. In a first mode, the controller provides a data sequence to the input terminal of the multiplexer circuit and provides the data sequence to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit. In a second mode, the controller provides a second output to the input terminal of the multiplexer circuit through a second feedback path and provides the second output to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit.

[0012] In an exemplary embodiment of the present invention, the multi-level accumulator circuit module further includes multiple accumulator circuits and multiple register circuits. The multiple register circuits are connected to the multiple accumulator circuits and the multiplexer circuit. The multiple register circuits include a first register circuit. The multiple accumulator circuits include a first accumulator circuit. The input terminal of the first register circuit is connected to the output terminal of the multiplexer circuit. The output terminal of the first register circuit is connected to the first input terminal of the first accumulator circuit. The second input terminal of the first accumulator circuit is the accumulation operation point and is connected to the first feedback path.

[0013] In an exemplary embodiment of the present invention, the plurality of register circuits further include a second register circuit. The plurality of accumulator circuits further include a second accumulator circuit. The input terminal of the second register circuit is connected to the output terminal of the second accumulator circuit. In a first mode, the output terminal of the second register circuit is connected to the second input terminal of the first accumulator circuit via a first feedback path. In a second mode, the output terminal of the second register circuit is connected to the input terminal of the multiplexer circuit via a second feedback path.

[0014] An exemplary embodiment of the present invention also provides a computing device including a processor and a plurality of execution units. At least one of the plurality of execution units includes an accumulator structure. The accumulator structure includes a multi-stage accumulator circuit module and a controller. The controller is connected to the multi-stage accumulator circuit module. The controller is configured to: in a first mode, provide a data sequence to the input of the multi-stage accumulator circuit module; in the first mode, feed back a first output of the multi-stage accumulator circuit module to an accumulation point of the multi-stage accumulator circuit module based on a first feedback path, wherein the input of the multi-stage accumulator circuit module is different from the accumulation point; and in a second mode, feed back a second output of the multi-stage accumulator circuit module to the input of the multi-stage accumulator circuit module based on a second feedback path.

[0015] An exemplary embodiment of the present invention further provides an accumulator control method, comprising: providing a data sequence to the input terminal of a multi-stage accumulator circuit module in a first mode; feeding back a first output of the multi-stage accumulator circuit module to an accumulation operation point of the multi-stage accumulator circuit module based on a first feedback path in the first mode, wherein the input terminal of the multi-stage accumulator circuit module is different from the accumulation operation point; and feeding back a second output of the multi-stage accumulator circuit module to the input terminal of the multi-stage accumulator circuit module based on a second feedback path in a second mode.

[0016] In an exemplary embodiment of the present invention, the accumulator control method further includes: in the first mode, after the target data segment in the data sequence enters the input terminal of the multi-level accumulator circuit module, in the next clock cycle, triggering the multi-level accumulator circuit module to enter the second mode.

[0017] In an exemplary embodiment of the present invention, the step of triggering the multi-level accumulation circuit module to enter the second mode in the next clock cycle includes: adding a tail mark to the end of the target data segment in the data sequence; and controlling the multi-level accumulation circuit module to enter the second mode according to the tail mark in the next clock cycle.

[0018] In an exemplary embodiment of the present invention, the accumulator control method further includes: in a first mode, turning on the first feedback path and turning off the second feedback path; and in a second mode, turning on the second feedback path and turning off the first feedback path.

[0019] In an exemplary embodiment of the present invention, the accumulator control method further includes: after feeding back the second output of the multi-level accumulator circuit module to the input terminal of the multi-level accumulator circuit module, controlling the multi-level accumulator circuit module to return to the first mode; and in the first mode, controlling the multi-level accumulator circuit module to accumulate the second output fed back via the second feedback path and the first output fed back via the first feedback path to generate a third output.

[0020] In an exemplary embodiment of the present invention, the multi-stage accumulation circuit module includes a multiplexer circuit connected to the input terminal of the multi-stage accumulation circuit module. In a first mode, the step of providing a data sequence to the input terminal of the multi-stage accumulation circuit module includes: providing the data sequence to the input terminal of the multiplexer circuit and providing the data sequence to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit. In a second mode, the step of feeding back a second output of the multi-stage accumulation circuit module to the input terminal of the multi-stage accumulation circuit module based on a second feedback path includes: providing a second output to the input terminal of the multiplexer circuit through the second feedback path and providing the second output to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit.

[0021] Based on the above, in the accumulator structure, arithmetic device, and accumulator control method proposed in the exemplary embodiments of the present invention, the output of the multi-level accumulator circuit module can be fed back to the accumulation operation point or input terminal of the multi-level accumulator circuit module through different feedback paths for different situations and / or different operating modes. Therefore, by dynamically switching the feedback path during the operation of the multi-level accumulator circuit module, no additional external buffer space is required, and the multi-level accumulator circuit module itself can complete efficient data accumulation. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of an accumulator structure operating in a first mode, as shown in an exemplary embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of an accumulator structure operating in the second mode according to an exemplary embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of an accumulator structure operating in a first mode, as shown in an exemplary embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of an accumulator structure operating in the second mode according to an exemplary embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the operation flow of a multi-level accumulator circuit module operating in the first mode, as shown in an exemplary embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of the operation flow of a multi-level accumulator circuit module operating in the second mode, as shown in an exemplary embodiment of the present invention.

[0028] Figure 7 This is a schematic diagram of a computing device according to an exemplary embodiment of the present invention;

[0029] Figure 8 This is a flowchart illustrating an accumulator control method according to an exemplary embodiment of the present invention. Detailed Implementation

[0030] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0031] The present invention is illustrated below with several exemplary embodiments; however, the invention is not limited to these exemplary embodiments. Suitable combinations between the exemplary embodiments are also permitted. The term "connection" as used throughout this specification (including the claims) may refer to any direct or indirect connection means. For example, if the text describes a first device connected to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some connection means. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

[0032] Figure 1 This is a schematic diagram of an accumulator structure operating in the first mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 1 The accumulator structure 10 can be used to receive a data sequence DS and perform accumulation (also called accumulation operation) on multiple data segments (also called data segments) in the data sequence DS, and produce an accumulation result corresponding to the data sequence DS. For example, assuming that the data sequence DS includes 3 "1"s, the accumulator structure 10 can accumulate these 3 "1"s to obtain the accumulation result (i.e., 1 + 1 + 1 = 3). However, the data segments in the data sequence DS can correspond to different values, and the present invention does not limit this.

[0033] The accumulator structure 10 may include a multi-stage accumulator circuit module 11 and a controller 12. The multi-stage accumulator circuit module 11 is connected to the controller 12. The controller 12 can be used to control the multi-stage accumulator circuit module 11 to perform the above-described accumulation operation. In addition, the controller 12 can be used to control the multi-stage accumulator circuit module 11 to feed back its output to different endpoints and / or different nodes based on different feedback paths under different conditions and / or different operating modes.

[0034] In one exemplary embodiment, in a certain mode (also referred to as the first mode), the controller 12 can provide the data sequence DS to the input of the multi-level accumulator module 11. By providing the data sequence DS to the input of the multi-level accumulator module 11, multiple data segments in the data sequence DS can be sequentially input to the multi-level accumulator module 11 to perform the aforementioned accumulation operation.

[0035] In one exemplary embodiment, in a first mode, the controller 12 may activate feedback path 101 (also referred to as the first feedback path). Furthermore, in the first mode, the controller 12 may, based on feedback path 101, feed back (i.e., provide) the output OUT(1) (also referred to as the first output) of the multi-level accumulator module 11 to a specific node (also referred to as the accumulation point) of the multi-level accumulator module 11. For example, the output OUT(1) (i.e., the first output) fed back to the accumulation point may be accumulated at the accumulation point with a data segment from the input of the multi-level accumulator module 11.

[0036] Figure 2 This is a schematic diagram of an accumulator structure operating in the second mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 2 In one exemplary embodiment, in another mode (also referred to as the second mode), the controller 12 can activate the feedback path 102 (also referred to as the second feedback path). Furthermore, in the second mode, the controller 12 can feed back (i.e., provide) the output OUT(2) (also referred to as the second output) of the multi-stage accumulator module 11 to the input of the multi-stage accumulator module 11 based on the feedback path 102. For example, the output OUT(2) fed back to the input of the multi-stage accumulator module 11 can be used to (temporarily) replace the data sequence DS and input to the multi-stage accumulator module 11.

[0037] In one exemplary embodiment, in the first mode, the controller 12 can trigger the multi-level accumulator module 11 to enter the second mode after a specific data segment (also referred to as the target data segment) in the data sequence DS enters the input terminal of the multi-level accumulator module 11. More specifically, in one exemplary embodiment, in the first mode, the controller 12 can trigger the multi-level accumulator module 11 to enter the second mode in the next clock cycle after the target data segment in the data sequence DS enters the input terminal of the multi-level accumulator module 11.

[0038] In one exemplary embodiment, the target data segment includes an empty data segment. This empty data segment may not carry any data to be processed in the original data sequence DS.

[0039] In one exemplary embodiment, the target data segment is located at the very end of the data sequence DS. In one exemplary embodiment, after obtaining the data sequence DS (i.e., the original data sequence DS), the controller 12 can add the target data segment to the very end of the data sequence DS.

[0040] In one exemplary embodiment, after adding the target data segment, the controller 12 may also add a specific marker (also known as a tail marker) to the end of the target data segment in the data sequence DS. In one exemplary embodiment, this tail marker may reflect the end position of the modified data sequence DS after adding the target data segment. In one exemplary embodiment, after the target data segment in the data sequence DS enters the input terminal of the multi-stage accumulator circuit module 11, in the next clock cycle, the controller 12 may control the multi-stage accumulator circuit module 11 to enter the second mode according to the aforementioned tail marker.

[0041] In one exemplary embodiment, in a first mode, controller 12 can enable feedback path 101 and disable feedback path 102. In response to feedback path 101 being enabled, the output of multi-stage accumulator module 11 (e.g., ...) Figure 1 The output OUT(1) can be fed back to the accumulation point of the multi-level accumulation circuit module 11, such as Figure 1 As shown.

[0042] In one exemplary embodiment, in the second mode, the controller 12 can activate feedback path 102 and deactivate feedback path 101. In response to feedback path 102 being activated, the output of the multi-stage accumulator module 11 (e.g., Figure 2 The output OUT(2) can be fed back to the input of the multi-stage accumulator circuit module 11, such as Figure 2 As shown.

[0043] Figure 3 This is a schematic diagram of an accumulator structure operating in the first mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 3 In one exemplary embodiment, the multi-stage accumulator circuit module 11 may include a multiplexer circuit 31. The multiplexer circuit 31 may be connected to the input of the multi-stage accumulator circuit module 11.

[0044] In one exemplary embodiment, in a first mode, the controller 12 may provide the data sequence DS to the input of the multiplexer circuit 31 (also referred to as the first input). Then, the controller 12 may provide the data sequence DS to the input of the multi-stage accumulator circuit module 11 through the output of the multiplexer circuit 31 (i.e., input the data sequence DS to the multi-stage accumulator circuit module 11).

[0045] Figure 4 This is a schematic diagram of an accumulator structure operating in the second mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 4In one exemplary embodiment, in the second mode, the controller 12 can provide the output OUT(2) to the input of the multiplexer circuit 31 via the feedback path 102. Then, the controller 12 can provide the output OUT(2) to the input of the multi-stage accumulator circuit module 11 via the output of the multiplexer circuit 31. At this time, the output OUT(2) can replace the data sequence DS as the input of the multi-stage accumulator circuit module 11.

[0046] Please refer to Figure 3 In one exemplary embodiment, it is assumed that the multi-stage accumulator module 11 is a two-stage accumulator module. The multi-stage accumulator module 11 may include register circuits 32(1) to 32(3) and accumulator circuits 33(1) and 33(2). Register circuits 32(1) to 32(3) are connected to accumulator circuits 33(1) and 33(2).

[0047] In one exemplary embodiment, register circuits 32(1) to 32(3) are also referred to as multi-level register circuits. In one exemplary embodiment, accumulator circuits 33(1) and 33(2) are also referred to as multi-level accumulator circuits.

[0048] In one exemplary embodiment, the input of register circuit 32(1) can be connected to the output of multiplexer circuit 31. The output of register circuit 32(1) can be connected to the input of accumulator circuit 33(1) (also referred to as the first input). The other input of accumulator circuit 33(1) (also referred to as the second input) can be connected to feedback path 101. Furthermore, the output of accumulator circuit 33(1) can be connected to the input of register circuit 32(2).

[0049] In one exemplary embodiment, the output of register circuit 32(2) may be connected to the input of accumulator circuit 33(2). Furthermore, the output of accumulator circuit 33(2) may be connected to the input of register circuit 32(3).

[0050] In one exemplary embodiment, in a first mode, the output of register circuit 32(3) can be connected to the second input (i.e., the accumulation point) of accumulator circuit 33(1) via feedback path 101. In one exemplary embodiment, in response to feedback path 101 being turned on, the data currently cached in register circuit 32(3) (i.e., output OUT(1)) can be provided to the second input of accumulator circuit 33(1) via feedback path 101.

[0051] Please refer to Figure 4In one exemplary embodiment, in the second mode, the output of register circuit 32 (3) can be connected to the input of multiplexer circuit 31 (also referred to as the second input) via feedback path 102. In one exemplary embodiment, in response to feedback path 102 being turned on, the data currently buffered in register circuit 32 (3) (i.e., output OUT (2)) can be provided to the input of multi-stage accumulator circuit module 11 via feedback path 102 to replace the data sequence DS.

[0052] In one exemplary embodiment, after the multi-level accumulator module 11 enters the second mode and feeds back its output OUT(2) to the input of the multi-level accumulator module 11, after one clock cycle, the controller 12 can control the multi-level accumulator module 11 to return to the first mode. Then, in the first mode, the controller 12 can control the multi-level accumulator module 11 to accumulate the output OUT(2) fed back via feedback path 102 and the output OUT(1) fed back via feedback path 101 to generate another output (also called a third output). For example, the third output can reflect the calculation result (i.e., the final calculation result) obtained by the multi-level accumulator module 11 after accumulating each data segment in the data sequence DS.

[0053] Figure 5 This is a schematic diagram illustrating the operation flow of a multi-level accumulator circuit module in the first mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 5 In one exemplary embodiment, it is assumed that the data sequence DS includes data segments D(0) to D(6). Each data segment D(i) may be followed by an accumulation instruction ACC, where i is an integer between 0 and 6. The accumulation instruction ACC can be used to instruct the multi-level accumulation circuit module 11 to accumulate the data segment D(i) following the accumulation instruction ACC. Furthermore, Figure 5 Each cycle in the text refers to one clock cycle.

[0054] In one exemplary embodiment, during periods T(0) to T(7), the multi-level accumulation circuit module 11 is operable in a first mode, and the controller 12 sequentially provides data segments D(0) to D(6) to the input of the multiplexer circuit 31 to sequentially input the data segments D(0) to D(6) into the multi-level accumulation circuit module 11 for accumulation. During period T(8), the multi-level accumulation circuit module 11 is operable in a second mode. Furthermore, during periods T(9) to T(11), the multi-level accumulation circuit module 11 is operable in the first mode.

[0055] Specifically, in period T(0), data segment D(0) can be pushed to register circuit 32(1) via multiplexer circuit 31. In period T(1), data segment D(0) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and data segment D(1) can be pushed to register circuit 32(1) via multiplexer circuit 31. Furthermore, in period T(1), accumulator circuit 33(1) can process data segment D(0) and cache the processing result (i.e., D(0)) in register circuit 32(2).

[0056] During period T(2), data segment D(0) in register circuit 32(2) can be pushed to accumulator circuit 33(2), data segment D(1) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and data segment D(2) can be pushed to register circuit 32(1) via multiplexer circuit 31. During period T(2), accumulator circuit 33(2) can process data segment D(0) and cache the processing result (i.e., D(0)) in register circuit 32(3). In addition, during period T(2), accumulator circuit 33(1) can process data segment D(1) and cache the processing result (i.e., D(1)) in register circuit 32(2).

[0057] During period T(3), the processing result (i.e., D(0)) cached in register circuit 32(3) can be fed back to accumulator circuit 33(1) through feedback path 101. Data segment D(1) in register circuit 32(2) can be pushed to accumulator circuit 33(2), data segment D(2) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and data segment D(3) can be pushed to register circuit 32(1) via multiplexer circuit 31. During period T(3), accumulator circuit 33(2) can process data segment D(1) and cache the processing result (i.e., D(1)) in register circuit 32(3). In addition, during period T(3), accumulator circuit 33(1) can process (i.e., accumulate) the processing result (i.e., D(0)) from feedback path 101 and data segment D(2) and cache the processing result (i.e., D(2) + D(0)) in register circuit 32(2).

[0058] During period T(4), the processing result (i.e., D(1)) cached in register circuit 32(3) can be fed back to accumulator circuit 33(1) through feedback path 101. The processing result (i.e., D(2)+D(0)) in register circuit 32(2) can be pushed to accumulator circuit 33(2). The data segment D(3) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and the data segment D(4) can be pushed to register circuit 32(1) via multiplexer circuit 31. During period T(4), accumulator circuit 33(2) can process the processing result (i.e., D(2)+D(0)) and cache the processing result (i.e., D(2)+D(0)) in register circuit 32(3). In addition, during period T(4), the accumulator circuit 33(1) can process (i.e. accumulate) the processing result (i.e. D(1)) from the feedback path 101 and the data segment D(3) and cache the processing result (i.e. D(3)+D(1)) in the register circuit 32(2).

[0059] During period T(5), the processing result (i.e., D(2)+D(0)) cached in register circuit 32(3) can be fed back to accumulator circuit 33(1) through feedback path 101. The processing result (i.e., D(3)+D(1)) in register circuit 32(2) can be pushed to accumulator circuit 33(2). The data segment D(4) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and the data segment D(5) can be pushed to register circuit 32(1) via multiplexer circuit 31. During period T(5), accumulator circuit 33(2) can process the processing result (i.e., D(3)+D(1)) and cache the processing result (i.e., D(3)+D(1)) in register circuit 32(3). In addition, during period T(5), the accumulator circuit 33(1) can process (i.e. accumulate) the processing result (i.e., data segment D(2)+D(0)) and data segment D(4) from the feedback path 101 and cache the processing result (i.e., D(4)+D(2)+D(0)) in the register circuit 32(2).

[0060] During period T(6), the processing result (i.e., D(3)+D(1)) cached in register circuit 32(3) can be fed back to accumulator circuit 33(1) through feedback path 101. The processing result (i.e., D(4)+D(2)+D(0)) in register circuit 32(2) can be pushed to accumulator circuit 33(2). The data segment D(5) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and the data segment D(6) can be pushed to register circuit 32(1) via multiplexer circuit 31. During period T(6), accumulator circuit 33(2) can process the processing result (i.e., D(4)+D(2)+D(0)) and cache the processing result (i.e., D(4)+D(2)+D(0)) in register circuit 32(3). In addition, during period T(6), the accumulator circuit 33(1) can process (i.e. accumulate) the processing result (i.e. D(3)+D(1)) from the feedback path 101 and the data segment D(5) and cache the processing result (i.e. D(5)+D(3)+D(1)) in the register circuit 32(2).

[0061] During period T(7), the processing result (i.e., D(4)+D(2)+D(0)) buffered in register circuit 32(3) can be fed back to accumulator circuit 33(1) through feedback path 101. The processing result (i.e., D(5)+D(3)+D(1)) in register circuit 32(2) can be pushed to accumulator circuit 33(2). The data segment D(6) in register circuit 32(1) can be pushed to accumulator circuit 33(1), and the empty data segment NOP (i.e., the target data segment) can be pushed to register circuit 32(1) via multiplexer circuit 31. For example, the empty data segment NOP can be actively added by controller 12 after data segment D(6) (i.e., at the end of data sequence DS).

[0062] During period T(7), the accumulator circuit 33(2) processes the processing result (i.e., D(5)+D(3)+D(1)) and caches the processing result (i.e., D(5)+D(3)+D(1)) in the register circuit 32(3). In addition, during period T(7), the accumulator circuit 33(1) processes (i.e., accumulates) the processing result (i.e., D(4)+D(2)+D(0)) from the feedback path 101 and the data segment D(6) and caches the processing result (i.e., D(6)+D(4)+D(2)+D(0)) in the register circuit 32(2).

[0063] Figure 6 This is a schematic diagram illustrating the operation flow of a multi-level accumulator circuit module in the second mode, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 6 , continuing Figure 5In an exemplary embodiment, after cycle T(7), cycle T(8) is entered. In cycle T(8), according to the instruction ACC with a tail marker (TAG), controller 12 can control the multi-stage accumulator module 11 to enter a second mode. For example, the tail marker (TAG) can be actively added by controller 12 after the empty data segment NOP to reflect the end position of the modified data sequence DS. In the second mode, feedback path 102 can be activated.

[0064] During period T(8), the processing result (i.e., D(5)+D(3)+D(1)) buffered in register circuit 32(3) can be fed back to the input of multiplexer 31 through feedback path 102. The processing result (i.e., D(6)+D(4)+D(2)+D(0)) in register circuit 32(2) can be pushed to accumulator circuit 33(2). The empty data segment NOP in register circuit 32(1) can be pushed to accumulator circuit 33(1). The processing result (i.e., D(5)+D(3)+D(1)) can be pushed to register circuit 32(1) via multiplexer circuit 31.

[0065] During period T(8), the accumulator circuit 33(2) can process the processing result (i.e., D(6)+D(4)+D(2)+D(0)) and cache the processing result (i.e., D(6)+D(4)+D(2)+D(0)) in the register circuit 32(3).

[0066] Please return Figure 5 After cycle T(8), cycle T(9) begins. In cycle T(9), controller 12 can control the multi-level accumulator circuit module 11 to return to the first mode. In the first mode, feedback path 101 can be activated.

[0067] During period T(9), the processing result (i.e. D(6)+D(4)+D(2)+D(0)) cached in register circuit 32(3) can be fed back to the accumulator circuit 33(1) through feedback path 101. The empty data segment NOP in register circuit 32(2) can be pushed to the accumulator circuit 33(2), and the processing result (i.e. D(5)+D(3)+D(1)) in register circuit 32(1) can be pushed to the accumulator circuit 33(1).

[0068] It should be noted that in period T(9), the accumulator circuit 33(1) can process (i.e., accumulate) the processing result from feedback path 101 (i.e., D(6)+D(4)+D(2)+D(0)) and the processing result in register circuit 32(1) (i.e., D(5)+D(3)+D(1)), and cache the processing result (i.e., D(6)+D(4)+D(2)+D(0)+D(5)+D(3)+D(1)) in register circuit 32(2). In an exemplary embodiment, the original data sequence DS is a accumulator sequence that has been split into two parts and then merged (i.e., accumulated) in period T(9).

[0069] In period T(10), the empty data segment NOP in register circuit 32(3) can be ejected, and the processing result (i.e., D(0)+…+D(6)) buffered in register circuit 32(2) can be pushed to accumulator circuit 33(2). Then, accumulator circuit 33(2) can buffer the processing result (i.e., D(0)+…+D(6)) in register circuit 32(3). Finally, in period T(11), the processing result (i.e., D(0)+…+D(6)) in register circuit 32(3) can be output (i.e., output OUT(3)= D(0)+…+D(6)). Thus, the accumulation of data segments D(0)~D(6) in data sequence DS is completed.

[0070] It should be noted that in the foregoing exemplary embodiments, the multi-level accumulation circuit module 11 is described using a two-level accumulation circuit module as an example. However, in one exemplary embodiment, the multi-level accumulation circuit module 11 may also include a three-level accumulation circuit module or a four-level accumulation circuit module, etc., and the present invention is not limited thereto. In addition, the form of the data sequence DS may also vary according to practical needs, and the present invention is not limited thereto.

[0071] In one exemplary embodiment, the accumulator structure 10 may be applied in a computing device. In one exemplary embodiment, this computing device may include a smartphone, tablet computer, laptop computer, desktop computer, server, game console, or various computing devices disposed in a mobile carrier (e.g., vehicle, ship, or aircraft).

[0072] In one exemplary embodiment, the computing device may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar devices, or combinations thereof.

[0073] In one exemplary embodiment, the computing device may further include processors dedicated to assisting in performing neural network operations and / or image processing, such as a Vision Processing Unit (VPU), a Neural Network Processing Unit (NPU), and / or a Tensor Processing Unit (TPU).

[0074] Figure 7 This is a schematic diagram of a computing device according to an exemplary embodiment of the present invention. Please refer to... Figure 7 In one exemplary embodiment, the computing device 70 includes a processor 71 and a plurality of execution units 72(1) to 72(N), where N is any integer greater than 1. The processor 71 may include any form of processor, microprocessor, or control circuit, which is used to control the overall operation of the computing device 70. The execution units 72(1) to 72(N) are all hardware computing units implemented in hardware form. The execution units 72(1) to 72(N) can execute the computing work (or computing tasks) assigned by the processor 71 individually or in combination.

[0075] In one exemplary embodiment, at least one of the execution units 72(1) to 72(N) may include an accumulator structure 10. In one exemplary embodiment, each of the execution units 72(1) to 72(N) includes an accumulator structure 10. Any of the execution units 72(1) to 72(N) may also include other types of circuit structures, which are not limited by the present invention.

[0076] Figure 8 This is a flowchart illustrating an accumulator control method according to an exemplary embodiment of the present invention. Please refer to... Figure 8In step S801, in the first mode, the data sequence is provided to the input terminal of the multi-level accumulator circuit module. In step S802, in the first mode, based on the first feedback path, the first output of the multi-level accumulator circuit module is fed back to the accumulation point of the multi-level accumulator circuit module. In step S803, in the second mode, based on the second feedback path, the second output of the multi-level accumulator circuit module is fed back to the input terminal of the multi-level accumulator circuit module.

[0077] However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple pieces of code or circuits; this invention is not limited thereto. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0078] In summary, this invention enables a multi-stage accumulation circuit module to complete the accumulation operation of data sequences under high clock speeds and a multi-stage pipelined architecture by switching different feedback paths in different modes. Thus, it balances computational performance with the realization of the accumulation function.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An accumulator structure, characterized in that, include: Multi-level accumulation circuit module; as well as The controller is connected to the multi-stage accumulation circuit module. The controller is used to: In the first mode, the data sequence is provided to the input of the multi-stage accumulation circuit module; In the first mode, based on the first feedback path, the first output of the multi-level accumulation circuit module is fed back to the accumulation operation point of the multi-level accumulation circuit module, wherein the input terminal of the multi-level accumulation circuit module is different from the accumulation operation point; as well as In the second mode, based on the second feedback path, the second output of the multi-level accumulation circuit module is fed back to the input terminal of the multi-level accumulation circuit module.

2. The accumulator structure according to claim 1, wherein the controller is further configured to: In the first mode, after the target data segment in the data sequence enters the input terminal of the multi-level accumulation circuit module, the multi-level accumulation circuit module is triggered to enter the second mode in the next clock cycle.

3. The accumulator structure according to claim 2, wherein the target data segment includes an empty data segment.

4. The accumulator structure according to claim 2, wherein the target data segment is located at the very end of the data sequence.

5. The accumulator structure according to claim 2, wherein the operation of the controller triggering the multi-stage accumulator circuit module to enter the second mode in the next clock cycle includes: Add a tail marker to the end of the target data segment in the data sequence; as well as In the next clock cycle, the multi-level accumulation circuit module is controlled to enter the second mode according to the tail mark.

6. The accumulator structure according to claim 1, wherein the controller is further configured to: In the first mode, the first feedback path is activated and the second feedback path is deactivated; and In the second mode, the second feedback path is turned on and the first feedback path is turned off.

7. The accumulator structure according to claim 1, wherein the controller is further configured to: After feeding back the second output of the multi-level accumulator circuit module to the input terminal of the multi-level accumulator circuit module, the multi-level accumulator circuit module is controlled to return to the first mode; and In the first mode, the multi-level accumulation circuit module is controlled to accumulate the second output fed back via the second feedback path and the first output fed back via the first feedback path to generate a third output.

8. The accumulator structure according to claim 1, wherein the multi-stage accumulator circuit module comprises: The multiplexer circuit is connected to the input terminal of the multi-stage accumulator circuit module. In the first mode, the controller is used to provide the data sequence to the input terminal of the multiplexer circuit, and to provide the data sequence to the input terminal of the multi-level accumulation circuit module through the output terminal of the multiplexer circuit; as well as In the second mode, the controller is used to provide the second output to the input terminal of the multiplexer circuit through the second feedback path, and to provide the second output to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit.

9. The accumulator structure according to claim 8, wherein the multi-stage accumulator circuit module further comprises: Multiple accumulation circuits; as well as Multiple register circuits are connected to the multiple accumulator circuits and the multiplexer circuit; The plurality of register circuits includes a first register circuit, and the plurality of accumulator circuits includes a first accumulator circuit. The input terminal of the first register circuit is connected to the output terminal of the multiplexer circuit. The output of the first register circuit is connected to the first input of the first accumulator circuit, and The second input terminal of the first accumulator circuit is the accumulator operation point and is connected to the first feedback path.

10. The accumulator structure according to claim 9, wherein the plurality of register circuits further includes a second register circuit, and the plurality of accumulation circuits further includes a second accumulation circuit. The input of the second register circuit is connected to the output of the second accumulator circuit. In the first mode, the output of the second register circuit is connected to the second input of the first accumulator circuit through the first feedback path, and In the second mode, the output of the second register circuit is connected to the input of the multiplexer circuit through the second feedback path.

11. A computing device, characterized in that, include: processor; as well as Multiple execution units, At least one of the plurality of execution units includes an accumulator structure. The accumulator structure includes: Multi-level accumulation circuit module; and The controller is connected to the multi-stage accumulation circuit module. The controller is used to: In the first mode, the data sequence is provided to the input of the multi-stage accumulation circuit module; In the first mode, based on the first feedback path, the first output of the multi-level accumulation circuit module is fed back to the accumulation operation point of the multi-level accumulation circuit module, wherein the input terminal of the multi-level accumulation circuit module is different from the accumulation operation point; and In the second mode, based on the second feedback path, the second output of the multi-level accumulation circuit module is fed back to the input terminal of the multi-level accumulation circuit module.

12. The computing device of claim 11, wherein the controller is further configured to: In the first mode, after the target data segment in the data sequence enters the input terminal of the multi-level accumulation circuit module, the multi-level accumulation circuit module is triggered to enter the second mode in the next clock cycle.

13. The computing device according to claim 12, wherein the target data segment includes an empty data segment.

14. The computing device of claim 12, wherein the target data segment is located at the very end of the data sequence.

15. The computing device of claim 12, wherein the operation of the controller triggering the multi-level accumulation circuit module to enter the second mode in the next clock cycle includes: Add a tail marker to the end of the target data segment in the data sequence; as well as In the next clock cycle, the multi-level accumulation circuit module is controlled to enter the second mode according to the tail mark.

16. The computing device of claim 11, wherein the controller is further configured to: In the first mode, the first feedback path is activated and the second feedback path is deactivated; and In the second mode, the second feedback path is turned on and the first feedback path is turned off.

17. The computing device of claim 11, wherein the controller is further configured to: After feeding back the second output of the multi-level accumulator circuit module to the input terminal of the multi-level accumulator circuit module, the multi-level accumulator circuit module is controlled to return to the first mode; and In the first mode, the multi-level accumulation circuit module is controlled to accumulate the second output fed back via the second feedback path and the first output fed back via the first feedback path to generate a third output.

18. The computing device according to claim 11, wherein the multi-level accumulation circuit module comprises: The multiplexer circuit is connected to the input terminal of the multi-stage accumulator circuit module. In the first mode, the controller is used to provide the data sequence to the input terminal of the multiplexer circuit, and to provide the data sequence to the input terminal of the multi-level accumulation circuit module through the output terminal of the multiplexer circuit; as well as In the second mode, the controller is used to provide the second output to the input terminal of the multiplexer circuit through the second feedback path, and to provide the second output to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit.

19. The computing device according to claim 18, wherein the multi-level accumulation circuit module further comprises: Multiple accumulation circuits; as well as Multiple register circuits are connected to the multiple accumulator circuits and the multiplexer circuit; The plurality of register circuits includes a first register circuit, and the plurality of accumulator circuits includes a first accumulator circuit. The input terminal of the first register circuit is connected to the output terminal of the multiplexer circuit. The output of the first register circuit is connected to the first input of the first accumulator circuit, and The second input terminal of the first accumulator circuit is the accumulator operation point and is connected to the first feedback path.

20. The arithmetic apparatus of claim 19, wherein the plurality of register circuits further comprises a second register circuit, and the plurality of accumulation circuits further comprises a second accumulation circuit. The input of the second register circuit is connected to the output of the second accumulator circuit. In the first mode, the output of the second register circuit is connected to the second input of the first accumulator circuit through the first feedback path, and In the second mode, the output of the second register circuit is connected to the input of the multiplexer circuit through the second feedback path.

21. An accumulator control method, characterized in that, include: In the first mode, the data sequence is provided to the input of the multi-stage accumulator circuit module; In the first mode, based on the first feedback path, the first output of the multi-level accumulation circuit module is fed back to the accumulation operation point of the multi-level accumulation circuit module, wherein the input terminal of the multi-level accumulation circuit module is different from the accumulation operation point; as well as In the second mode, based on the second feedback path, the second output of the multi-level accumulation circuit module is fed back to the input terminal of the multi-level accumulation circuit module.

22. The accumulator control method according to claim 21, further comprising: In the first mode, after the target data segment in the data sequence enters the input terminal of the multi-level accumulation circuit module, the multi-level accumulation circuit module is triggered to enter the second mode in the next clock cycle.

23. The accumulator control method according to claim 22, wherein the target data segment includes an empty data segment.

24. The accumulator control method according to claim 22, wherein the target data segment is located at the very end of the data sequence.

25. The accumulator control method according to claim 22, wherein the step of triggering the multi-level accumulator circuit module to enter the second mode in the next clock cycle includes: Add a tail marker to the end of the target data segment in the data sequence; as well as In the next clock cycle, the multi-level accumulation circuit module is controlled to enter the second mode according to the tail mark.

26. The accumulator control method according to claim 21, further comprising: In the first mode, the first feedback path is turned on and the second feedback path is turned off; as well as In the second mode, the second feedback path is turned on and the first feedback path is turned off.

27. The accumulator control method according to claim 21 further includes: After feeding back the second output of the multi-level accumulation circuit module to the input terminal of the multi-level accumulation circuit module, the multi-level accumulation circuit module is controlled to return to the first mode; as well as In the first mode, the multi-level accumulation circuit module is controlled to accumulate the second output fed back via the second feedback path and the first output fed back via the first feedback path to generate a third output.

28. The accumulator control method according to claim 21, wherein the multi-stage accumulator circuit module comprises: The multiplexer circuit is connected to the input terminal of the multi-stage accumulator circuit module. In the first mode, the step of providing the data sequence to the input terminal of the multi-level accumulator circuit module includes: In the first mode, the data sequence is provided to the input terminal of the multiplexer circuit, and the data sequence is provided to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit. In the second mode, the step of feeding back the second output of the multi-level accumulator circuit module to the input terminal of the multi-level accumulator circuit module based on the second feedback path includes: In the second mode, the second output is provided to the input terminal of the multiplexer circuit through the second feedback path, and the second output is provided to the input terminal of the multi-stage accumulation circuit module through the output terminal of the multiplexer circuit.

29. The accumulator control method according to claim 28, wherein the multi-stage accumulator circuit module further comprises: Multiple accumulation circuits; as well as Multiple register circuits are connected to the multiple accumulator circuits and the multiplexer circuit; The plurality of register circuits includes a first register circuit, and the plurality of accumulator circuits includes a first accumulator circuit. The input terminal of the first register circuit is connected to the output terminal of the multiplexer circuit. The output of the first register circuit is connected to the first input of the first accumulator circuit, and The second input terminal of the first accumulator circuit is the accumulator operation point and is connected to the first feedback path.

30. The accumulator control method according to claim 29, wherein the plurality of register circuits further includes a second register circuit, and the plurality of accumulation circuits further includes a second accumulation circuit. The input of the second register circuit is connected to the output of the second accumulator circuit. In the first mode, the output of the second register circuit is connected to the second input of the first accumulator circuit through the first feedback path, and In the second mode, the output of the second register circuit is connected to the input of the multiplexer circuit through the second feedback path.

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