A cross-execution domain state transition and deterministic execution control system and method

Abstract

This invention discloses a cross-execution domain state transition and deterministic execution control system and method for multi-execution domain parallel computing environments. The system includes: an Execution State Table (EST), stored in memory, containing a timestamp sorting field, a state version vector field, and a commit index field; a Deterministic Execution Control Unit (DECU), communicatively connected to the EST, used to read state information and generate execution scheduling control signals; and a synchronization barrier mechanism used to control the execution order among multiple execution domains. The EST, DECU, and synchronization barrier mechanism are connected through internal control signal links, and the three form a closed-loop execution control structure through a unified control timing dependency, achieving cross-execution domain state consistency control and execution order coordination. This invention also provides a corresponding control method. This invention improves the state consistency and execution determinism of parallel execution systems and can be applied to multi-core processors, GPUs, and distributed computing systems.

Description

Technical Field

[0001] This invention relates to the fields of computer architecture and parallel computing control technology, specifically to a control system and method for state consistency control, execution order management, and state transition in a multi-execution domain environment. Background Technology

[0002] In multi-core processors, graphics processing units (GPUs), and distributed parallel computing systems, multiple execution domains typically execute computational tasks simultaneously. Existing technologies mainly suffer from the following problems:

[0003] (1) Dispersed execution status: The status information of each execution unit is distributed in the cache, registers and main memory, lacking unified structured management, which makes it difficult to track the status.

[0004] (2) Uncontrollable execution order: During parallel execution, there is a lack of stable control mechanism for the execution order between execution domains, which leads to uncertainty in the execution results.

[0005] (3) Difficulty in state consistency: When multiple execution domains are transitioning between states, inconsistency in state can easily occur, affecting the reliability of the system.

[0006] (4) The synchronization mechanism has high overhead: Traditional barrier mechanisms rely on software instructions or weak hardware synchronization, which has large delays and uncertainties.

[0007] Therefore, a system is needed that can achieve unified management and deterministic control of execution status in a hardware and software collaborative environment. Summary of the Invention

[0008] (a) Purpose of the invention

[0009] The present invention aims to provide a cross-execution domain state transition and deterministic execution control system and method to achieve: unified management of execution state, consistency control across multiple execution domains, controllable execution order, and improved reliability of state transition.

[0010] (II) Technical Solution

[0011] This invention provides the following technical solution:

[0012] 1. Execution Status Table (EST)

[0013] The execution status table is stored in memory and is used to record the execution status information of each execution domain. The execution status table includes:

[0014] Timestamp sorting structure: used to record the temporal order of state transitions in each execution domain;

[0015] State version vector: used to identify the state version of each execution domain;

[0016] Commit index: Used to record the monotonically increasing sequence number of confirmed executions.

[0017] 2. Deterministic Execution Control Unit (DECU)

[0018] The deterministic execution control unit is communicatively connected to the execution status table and is used for:

[0019] Read the status information from the execution status table;

[0020] Perform state analysis based on preset execution rules;

[0021] Generate execution scheduling control signals.

[0022] 3. Synchronization Barrier Mechanism

[0023] Used to control the execution order among multiple execution domains, including:

[0024] Production line pause control unit;

[0025] Storage access barrier control unit.

[0026] 4. Closed-loop dependency

[0027] In this invention, the Execution State Table (EST), the Deterministic Execution Control Unit (DECU), and the synchronization barrier mechanism form a closed-loop execution control structure through unified control timing dependencies. Specifically:

[0028] The decision output of DECU depends on the current state of EST;

[0029] The triggering of the synchronization barrier mechanism depends on the decision output of the DECU;

[0030] EST updates depend on the execution result of the synchronization barrier mechanism.

[0031] Therefore, the output of any module simultaneously serves as the input constraint for other modules, forming an inseparable closed-loop control logic.

[0032] The aforementioned execution status table, deterministic execution control unit, and synchronization barrier mechanism are connected through an internal control signal link to achieve cross-execution domain state consistency control and execution sequence coordination.

[0033] (III) Beneficial Effects

[0034] Compared with the prior art, the present invention has at least the following advantages:

[0035] Improve state consistency across multiple execution domains;

[0036] Enhance the controllability and determinism of the execution order;

[0037] Reduce the system overhead caused by the synchronization mechanism;

[0038] Improve the reliability of state transitions;

[0039] Provides a unified execution control structure suitable for hardware and software co-working architectures. Detailed Implementation

[0040] Example 1 (Software Implementation)

[0041] In a software environment:

[0042] The execution status table is stored in system memory;

[0043] The deterministic execution control unit is implemented by the processor executing the program;

[0044] The synchronization barrier mechanism is implemented through software synchronization commands.

[0045] Example 2 (Hardware Implementation)

[0046] In a hardware environment:

[0047] The execution status table is stored in on-chip memory or a register file;

[0048] The deterministic execution control unit is implemented by hardware logic circuitry;

[0049] The synchronization barrier mechanism is implemented by pipeline control circuit and storage barrier circuit;

[0050] Each module is connected through an on-chip control signal link, forming a closed-loop dependency relationship.

[0051] System Workflow

[0052] This system operates according to the following steps:

[0053] Step S1: System initialization, establishing an execution status table in memory;

[0054] Step S2: The deterministic execution control unit reads the status information from the execution status table;

[0055] Step S3: The deterministic execution control unit evaluates based on preset execution rules and generates execution scheduling control signals;

[0056] Step S4: The synchronization barrier mechanism controls the execution order of multiple execution domains by using pipeline pause or storage barriers based on control signals;

[0057] Step S5: Feedback the execution results to update the execution status table, forming a control closed loop;

[0058] Step S6: When cross-domain migration is required, perform state freeze, transfer, consistency check and resynchronization operations. Attached Figure Description

[0059] Figure 1 The overall system structure diagram shows the execution state table, deterministic execution control unit, synchronization barrier mechanism and their connections, including control signal flow and feedback signal flow;

[0060] Figure 2 The execution status table structure diagram shows the timestamp sorting field, the status version vector field, and the commit index field.

[0061] Figure 3 The execution control flowchart illustrates the process of state reading, rule evaluation, control signal generation, and feedback update of the EST.

[0062] Figure 4 The state transition flowchart illustrates the process of state freezing, snapshot generation, state transfer, consistency verification, commit index increment, target domain activation, and resynchronization.

Claims

1. A cross-execution domain state transition and consistency control system for a multi-execution domain parallel computing environment, characterized in that, include: An execution state table (EST) is stored in memory, and the execution state table includes: Timestamp sorting field Status version vector field, Submit indexed fields; A deterministic execution control unit (DECU), communicatively connected to the execution status table, is used for: Read the status information from the execution status table. Generate execution scheduling control signals based on preset execution rules; A synchronization barrier mechanism is used to control the execution order among multiple execution domains, including: Production line pause control unit Storage access barrier control unit; The execution state table, deterministic execution control unit, and synchronization barrier mechanism are connected through an internal control signal link. The three form a closed-loop execution control structure through a unified control timing dependency relationship, so that the output of any module can simultaneously serve as the input constraint condition of other modules, thereby achieving cross-execution domain state consistency control and execution order coordination.

2. The system according to claim 1, characterized in that: The deterministic execution control unit is implemented by a software program executed by a processor, and is used to generate execution scheduling instructions based on the status information in the execution status table.

3. The system according to claim 1, characterized in that: The deterministic execution control unit is implemented as a hardware logic circuit, the execution status table is stored in on-chip memory or a register file, and the synchronization barrier mechanism is implemented as the following hardware unit: Production line pause control circuit, Storage access barrier circuit, Execute the synchronization control circuit; The execution results of each module form a closed-loop dependency in the on-chip control signal link.

4. The system according to claim 1, characterized in that: The system achieves at least one of the following technical effects through state interaction between the execution status table and the execution control unit: Enhanced state consistency across execution domains; The determinism of the execution order is improved; State conflicts are reduced during parallel execution.

5. The system according to claim 1, characterized in that, Also includes: The state transition control module is used to transfer execution state between different execution domains; The consistency verification module is used to verify the consistency of the migrated state. The resynchronization module is used to restore the state when an inconsistency is detected.

6. A method for state transition and consistency control across execution domains, characterized in that, include: Maintain the execution status table in memory; The execution status table is read by the deterministic execution control unit; Deterministic execution sorting is performed on multiple execution domains based on the commit index in the execution status table; Generate execution scheduling control signals based on execution rules; The execution order between multiple execution domains is controlled through a synchronization barrier mechanism; Perform state transitions and consistency verification between execution domains.

7. The system according to claim 1, characterized in that: The execution state table, deterministic execution control unit, and synchronization barrier mechanism work together through on-chip control logic and storage structure to support deterministic state control in a parallel execution environment.

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