An instruction packet level power balancing scheduling method and system

Abstract

The application discloses a kind of instruction package level power consumption equalization scheduling method and system, method includes: obtaining initial sensitive instruction package;The resource occupation and power consumption leakage risk of initial sensitive instruction package are evaluated, and power consumption leakage score is calculated;If power consumption leakage score does not satisfy preset equalization condition, executes power consumption equalization operation to initial sensitive instruction package, generates target instruction package satisfying preset equalization condition, and power consumption equalization operation includes insertion operation and instruction rearrangement operation, insertion operation is used to supplement resource overhead, and instruction rearrangement operation is used to reduce resource overhead;According to target instruction package generation security metadata, and security metadata includes security attribute information, power consumption leakage score, the operation result information of power consumption equalization operation and preset transmission width;Target instruction package and security metadata are sent to very long instruction word processor, so that very long instruction word processor executes target instruction package.The application can improve the anti-power side channel attack ability of sensitive instruction package.

Description

Technical Field

[0001] This application relates to the field of instruction scheduling technology, and in particular to an instruction packet-level power balancing scheduling method and system. Background Technology

[0002] Very Long Instruction Word (VLIW) processors rely on static scheduling by the compiler. During the compilation phase, the compiler arranges multiple parallelizable operations into the same VLIW instruction package based on data dependencies and processor functional unit resources. This architecture features relatively simple hardware control logic, high instruction-level parallelism, and suitability for both dedicated and embedded processors.

[0003] In traditional VLIW compilation, scheduling goals typically include increasing parallelism, reducing execution cycles, minimizing resource conflicts, and improving performance. However, in sensitive applications such as cryptographic algorithms, security authentication, key processing, and privacy computing, the number of slots occupied, the start / stop status of functional units, the number of register ports used, memory access behavior, and bus activity in instruction packets may vary with changes in sensitive data or paths. Attackers can analyze these changes through power side-channel analysis to infer sensitive information within the program. Therefore, relying solely on ordinary VLIW scheduling strategies is insufficient to meet the requirements for resisting side-channel attacks in secure computing scenarios.

[0004] Existing methods for mitigating side-channel attacks mainly include constant-time programming, masking techniques, randomized execution, insertion of pseudo-instructions, cache isolation, and compiler backend protection. Previous research has also focused on mitigating power side-channel attacks through compilers or reducing the risk of power attacks through instruction reordering. However, for VLIW architectures, existing methods still have the following problems: 1. Insufficient consideration of VLIW instruction packet level leakage: The power consumption characteristics of VLIW come not only from a single instruction, but also from the combination of parallel activities of multiple slots and functional units within the same instruction packet.

[0005] 2. Empty slots cause significant power consumption fluctuations: Empty slots often exist in VLIW instruction packets. The number of empty slots varies in different cycles, which will cause differences in transmit width and functional unit activity, forming observable power consumption characteristics.

[0006] 3. Ordinary pseudo-instruction insertion is not precise enough: Simply inserting pseudo-instructions may not guarantee the overall resource usage balance of the instruction package, nor can it constrain factors such as register ports, memory access ports, and bus activity.

[0007] 4. Traditional compilers prioritize performance in their scheduling objectives: Ordinary VLIW compilers mainly focus on performance and resource conflicts, lacking balanced constraints on power consumption side channels.

[0008] 5. Lack of compiler-processor coordination mechanism: Even if the compiler inserts pseudo-operations, if the processor discards or simplifies these operations during the execution phase, it will also destroy the power balancing effect. Summary of the Invention

[0009] This application aims to propose an instruction packet-level power balancing scheduling method and system, which can achieve instruction packet-level power balancing during the compilation stage and ensure coordinated execution of the processor during the execution stage through security metadata, thereby improving the resistance of sensitive instruction packets to power side-channel attacks.

[0010] In a first aspect, embodiments of this application provide an instruction packet-level power balancing scheduling method, applied to a very long instruction word compiler, the instruction packet-level power balancing scheduling method comprising: Obtain the initial sensitive instruction packet; The resource consumption and power leakage risks of the initial sensitive instruction packet are assessed, and a power leakage score is calculated. If the power leakage score does not meet the preset equalization conditions, a power equalization operation is performed on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Security metadata is generated based on the target instruction packet. The security metadata includes security attribute information, power leakage score, operation result information of the power equalization operation, and preset transmit width. The target instruction packet and the security metadata are sent to a Very Long Instruction Word (VLE) processor, so that the VLE processor executes the target instruction packet based on the security metadata.

[0011] Secondly, embodiments of this application provide an instruction packet-level power balancing scheduling system, including a very long instruction word (VLSI) compiler and a VLSI processor, wherein: The Very Long Instruction Word (VLTB) compiler is used to obtain an initial sensitive instruction packet, assess the resource consumption and power leakage risk of the initial sensitive instruction packet, calculate a power leakage score, and if the power leakage score does not meet the preset equalization conditions, perform a power equalization operation on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Based on the target instruction packet, security metadata is generated. The security metadata includes security attribute information, power leakage score, operation result information of the power equalization operation, and a preset transmit width. The target instruction packet and the security metadata are sent to the VLTB ​​processor. The Very Long Instruction Word (VLTB) processor is used to execute the target instruction package based on the security metadata.

[0012] The instruction packet-level power balancing scheduling method and system of this application, by quantitatively assessing the power leakage risk of the initial sensitive instruction packet and adopting appropriate power balancing operations for different scoring conditions, can effectively reduce the power characteristic differences between instruction packets. This solves the problems of lack of instruction packet-level leakage protection, power fluctuation caused by empty slots, and insufficient granularity of conventional protection methods in the existing VLIW architecture. At the same time, it realizes the collaborative scheduling of the VLIW compiler and the VLIW processor through security metadata, ensuring that the power balancing constraints generated in the compilation stage are accurately implemented in the execution stage, avoiding the optimization processing in the execution stage from destroying the preset power balancing effect. This can effectively improve the anti-power side-channel attack capability of the VLIW processor in sensitive application scenarios and meet the scheduling requirements of security-sensitive scenarios such as cryptographic algorithms, privacy computing, and key processing.

[0013] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart of an instruction packet-level power balancing scheduling method according to an embodiment of this application. Detailed Implementation

[0015] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0016] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0017] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0018] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0019] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are some embodiments of this application, not all embodiments.

[0020] See Figure 1 , Figure 1 This is a flowchart of an instruction packet-level power balancing scheduling method provided in an embodiment of this application. The instruction packet-level power balancing scheduling method is applied to a very long instruction word (VLSI) compiler and includes, but is not limited to, steps S100 to S500: Step S100: Obtain the initial sensitive instruction packet; Step S200: Assess the resource consumption and power leakage risk of the initial sensitive instruction packet, and calculate the power leakage score; Step S300: If the power leakage score does not meet the preset equalization conditions, perform a power equalization operation on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Step S400: Generate security metadata based on the target instruction packet. The security metadata includes security attribute information, power leakage score, operation result information of power equalization operation, and preset transmission width. In step S500, the target instruction packet and security metadata are sent to the Very Long Instruction Word (VLTB) processor so that the VLTB ​​processor executes the target instruction packet based on the security metadata.

[0021] In this embodiment, by quantitatively assessing the power leakage risk of the initial sensitive instruction packet and adopting appropriate power balancing operations for different scoring conditions, the power consumption characteristic differences between instruction packets can be effectively reduced. This solves the problems of lack of instruction packet-level leakage protection, power fluctuations caused by empty slots, and insufficient granularity of conventional protection methods in the existing VLIW architecture. At the same time, by realizing the collaborative scheduling of the VLIW compiler and the VLIW processor through security metadata, it ensures that the power balancing constraints generated in the compilation stage are accurately implemented in the execution stage, avoiding the optimization processing in the execution stage from destroying the preset power balancing effect. This can effectively improve the anti-power side-channel attack capability of the VLIW processor in sensitive application scenarios and meet the scheduling requirements of security-sensitive scenarios such as cryptographic algorithms, privacy computing, and key processing.

[0022] In step S100 above, the initial sensitive instruction package is the instruction package corresponding to the sensitive application, and sensitive information can be identified in the following ways: (1) by user annotation; (2) by type marking; (3) by compiler data flow analysis to identify the propagation path of sensitive data such as keys, intermediate states, authentication codes, and random numbers; (4) by function whitelist to identify cryptographic algorithm functions, such as core calculation functions such as AES, SM4, SHA, ECC, and RSA.

[0023] After identification is complete, the VLIW compiler adds sensitive flags to the relevant variables, operations, and basic blocks for use in the subsequent VLIW instruction packet scheduling phase.

[0024] The embodiments of this application only enable power balancing operation for sensitive instruction packets, which can reduce overall performance loss while improving the resistance of sensitive instruction packets to power side-channel attacks.

[0025] In step S200 above, the constraint formula for the power leakage score is: ;Formula (1) in, For power consumption leakage scoring, Weights for operation types, Assigning weight to slot occupancy. For the activity weight of the functional unit, Weights for register read / write ports. Weighting of memory access behavior, As the bus activity weight, To estimate weights for data flipping, , , , , , and The preset weighting coefficients, , , , , , and This is calculated based on the resource usage of the initial sensitive instruction packet.

[0026] In some implementations, the operation type weight, slot occupancy weight, functional unit activity weight, register read / write port weight, memory access behavior weight, bus activity weight, and data flip estimation weight are obtained through the following steps: Analyze the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, and data changes of each instruction within the initial sensitive instruction packet; The raw overhead is calculated separately for operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission and data change. The raw overhead represents the resource usage. Divide the original overhead corresponding to each resource class by the preset overhead upper limit of the resource class in a single instruction packet to obtain the operation type weight, slot occupancy weight, functional unit activity weight, register read / write port weight, memory access behavior weight, bus activity weight, and data flip estimation weight. The resource class represents the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, or data change.

[0027] The raw overhead of the above operation types is calculated by statistically analyzing the operational complexity of each instruction itself. The raw overhead corresponding to different operation types is as follows: the raw overhead of the null instruction (NOP) is 0, the raw overhead of logical operation (AND / OR / XOR) is 1, the raw overhead of addition / subtraction operation (ADD / SUB) is 2, the raw overhead of shift operation (SHIFT) is 2, the raw overhead of comparison operation (CMP) is 2, the raw overhead of multiplication operation (MUL) is 4, the raw overhead of division operation (DIV) is 6, the raw overhead of memory access read operation (Load) is 3, the raw overhead of memory access write operation (Store) is 3, the raw overhead of branch / jump operation (Branch / Jump) is 2, and the raw overhead of special control instructions is 3~5.

[0028] It should be noted that the above-mentioned original cost values ​​can be adjusted according to the actual situation and should not be regarded as a limitation on this application.

[0029] The original overhead of the aforementioned execution slots is obtained by statistically analyzing how many execution slots the initial sensitive instruction packet occupies.

[0030] The original overhead of the above functional units is determined by statistically analyzing the types and number of activated functional units. The original overhead of different functional units is as follows: the original overhead of the logic unit (ALU) is 1, the original overhead of the shift unit (SHIFT) is 2, the original overhead of the multiplication unit (MUL) is 3, the original overhead of the division / special operation unit (DIV) is 4, the original overhead of the memory access unit (Load / Store) is 2, and the original overhead of the jump unit (Branch) is 1.

[0031] The original overhead of the above register reads and writes is determined by counting the number of times the source register is read and the number of times the destination register is written back.

[0032] The raw overhead of the aforementioned memory access behavior is determined by statistically analyzing data such as Load / Store counts, access width, and whether it is non-aligned. The constraint formula for the raw overhead of the memory access behavior is: ;Formula (2) ;Formula (3) in, The original overhead of memory access. Indicates the first in the initial sensitive instruction packet One instruction, This represents the raw memory access cost of a single instruction within the initial sensitive instruction packet. Based on the basic memory access overhead, the memory access behavior is 1 during Load and 1.2 during Store. This is the data width factor; when the access type is 32-bit Load. When the access type is 64-bit Load (for version 1.0) When it is version 2.0 and the access type is 32-bit Store When the access type is 64-bit Store (version 1.2) It is 2.4. This is the alignment factor; it is 1 for address alignment and 1.5 for non-alignment.

[0033] The raw overhead of the bus transfers described above is determined by statistically analyzing the amount of data transferred due to the initial sensitive instruction packets. Bus activity can be estimated from several sources: instruction fetch transfers, source operand read transfers, and result write-back transfers. The raw overhead of the bus transfers can be expressed as the sum of the number of instruction packet bytes, the number of source operand transfers, and the number of result write-backs.

[0034] The original overhead of the above data changes is determined by counting the number of bit changes. Dynamic power consumption is related to bit flips, so it depends on how many bits of data have changed from the previous state to the current state. It is estimated based on the average data flip rate, using the following formula: ;Formula (4) in, The original overhead for data changes. This represents the average toggle rate. For random data, a value of 0.5 is suitable; for address-incrementing data, a value of 0.1 to 0.2 is suitable; and for immediate values ​​or control fields, a value of 0.05 to 0.2 is suitable. Indicates the data bit width. This indicates the number of data transfers in the initial sensitive instruction packet.

[0035] After calculating the seven categories of raw overhead, each category is divided by the maximum possible overhead of that resource type in a single instruction packet to obtain the normalized operation type weight, slot occupancy weight, functional unit activity weight, register read / write port weight, memory access behavior weight, bus activity weight, and data flip estimation weight. After normalization, each weight typically falls between 0 and 1. The closer a weight is to 0, the less the initial sensitive instruction packet uses that resource type; the closer a weight is to 1, the closer the initial sensitive instruction packet's use of that resource type is to the maximum overhead allowed by the architecture.

[0036] The maximum possible overhead (i.e., the preset overhead limit) for the above seven types of resources in a single instruction packet are as follows: Operation type: The total cost of the operation type when all available slots within a single instruction packet execute the highest complexity operation; Execution slots: The total number of available execution slots within a single instruction package; Functional unit: The sum of the maximum costs of functional units that can be activated simultaneously within a single instruction packet; Register read / write: Maximum number of register read ports used within a single instruction packet; Memory access behavior: maximum number of memory accesses within a single instruction packet, maximum access width, and memory access overhead in the case of non-alignment; Bus transfer: The sum of the overhead of maximum instruction fetch transfer, operand transfer, and result write-back within a single instruction packet; Data change status: The maximum number of bits flipped when all relevant data bits in a single instruction packet are flipped.

[0037] In some implementations... , , , , , and The weights represent the contribution coefficients of various resource weights to the overall overhead of the instruction packet. Their magnitudes are determined jointly by chip structure parameters, simulation results, and power consumption test results. Each weight reflects the intensity of the current instruction packet's use of different resources. ~ This reflects the degree of impact of the normalized overhead of the corresponding resource unit on the power leakage score.

[0038] From a physical point of view, With the The equivalent switched capacitance, bit width, number of ports, interconnect length, access frequency, data toggle rate, operating voltage, and operating frequency of the corresponding hardware module for each resource type are related. According to the dynamic power consumption formula: ;Formula (5) in, Indicates dynamic power consumption. Indicates the flip rate. Indicates the equivalent load capacitance. Indicates the operating voltage. This represents the clock frequency. The larger the hardware scale, the larger the equivalent capacitance, and the more frequently the resources flip, the larger their corresponding coefficients usually are. In actual determination, initial coefficients can be given first based on chip design parameters, such as setting initial values ​​based on the area, bit width, number of ports, and estimated power consumption of modules like the ALU, multiplier, register file, memory access unit, and bus. Then, calibration is performed using RTL simulation, gate-level power consumption simulation, or measured power consumption data. The weight values ​​of each instruction packet or program segment are statistically analyzed, and the corresponding simulated or measured power consumption is obtained. Formula (1) is fitted using the least squares method, thus obtaining... ~ .

[0039] In some implementations, the insertion operation includes inserting a pseudo-operation, inserting a complementary operation, and inserting a fixed memory access operation; the instruction reordering operation includes adjusting slot allocation and reordering high-power operations; and the above step S300 includes, but is not limited to, steps S310 and S320: Step S310: If the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is lower than the preset target leakage threshold, perform at least one of the following operations on the initial sensitive instruction packet: insert a pseudo-operation, insert a complementary operation, and insert a fixed memory access operation to generate a target instruction packet that meets the preset balance condition. Step S320: If the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is higher than the preset target leakage threshold, perform at least one of the following operations on the initial sensitive instruction packet: adjust the slot allocation and rearrange the high power operation to generate a target instruction packet that meets the preset balance condition.

[0040] In step S310 above, when the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is lower than the preset target leakage threshold, it indicates that there are many empty slots or insufficient resource activity in the initial sensitive instruction packet. The overall power leakage level of the initial sensitive instruction packet is far below the preset equilibrium target, and the power consumption characteristics of different sensitive instruction packets differ significantly. This difference can be captured by attackers through power side-channel analysis, thereby extracting secret information such as keys and sensitive computation intermediate results. At this time, it is necessary to supplement resource overhead through insertion operations to raise the power leakage score to within the preset allowable deviation range of the preset target leakage threshold, so that the overall power consumption level of all sensitive instruction packets remains in a similar range, eliminating exploitable power consumption differences.

[0041] The aforementioned pseudo-operations can select pseudo-instructions with corresponding overhead to fill the empty slots in the instruction package, supplementing the resource overhead of the corresponding dimension, based on the size and missing dimension of the current scoring gap. For example, pseudo-operations such as XOR (dummy_xor) and addition (dummy_add) can be inserted into empty ALU slots, multiplication (dummy_mul) can be inserted into empty MUL slots, and memory access and load-safe pseudo-operations (dummy_load) can be inserted into empty MEM slots.

[0042] The following example illustrates the power compensation process for a single VLIW instruction packet.

[0043] Suppose a very long instruction word processor has four slots: ALU0, ALU1, MUL, and MEM. ALU0 and ALU1 are used to perform arithmetic logic operations, MUL is used to perform multiplication operations, and MEM is used to perform memory access operations.

[0044] The initial sensitive instruction packet is: [ALU0: XOR r10, r2, r3]; [ALU1: empty]; [MUL: empty]; [MEM: Load r11, r4]; In this context, XOR r10 is the destination register for the result of the XOR operation between r2 and r3. r2 and r3 can be sensitive data or intermediate values ​​derived from sensitive data. Load r11 is the destination register for storing the sensitive data retrieved from r4, where r4 is the memory access address register. This initial sensitive instruction packet only uses ALU0 and MEM slots, while ALU1 and MUL slots are empty. This results in a low number of active functional units, and the difference between the power leakage score and the preset target leakage threshold exceeds the preset allowable deviation. Furthermore, the power leakage score is higher than the preset target leakage threshold. Therefore, the VLTC compiler determines that the power activity of this instruction packet is too low and requires compensation padding. The adjusted target instruction packet is as follows: [ALU0: XOR r10, r2, r3]; [ALU1: dummy_xor rD0, c1, c2]; [MUL: dummy_mul rD1, c3, c4]; [MEM: Load r11, r4]; Among them, r10 and r11 are real program registers, rD0 and rD1 are dedicated pseudo-operation registers, c1, c2, c3, and c4 are fixed constants, mask values, or secure random values. dummy_xor and dummy_mul do not change the program's visible semantics. Pseudo-operations are only used to improve slot occupancy and the stability of functional unit activities.

[0045] After adjustment, operations are present in slots ALU0, ALU1, MUL, and MEM. The power leakage score is improved to the point where the difference between the score and the preset target leakage threshold is less than or equal to the preset allowable deviation, thereby reducing power side channel leakage caused by changes in the number of empty slots.

[0046] The aforementioned complementary insertion operation can generate a compensation operation that complements the flipped state based on the data flipping characteristics of the original instruction, so that the total data flipping rate is stabilized at the expected level while supplementing the corresponding resource overhead.

[0047] The following example illustrates how the VLTC compiler inserts complementary operations to reduce power leakage caused by data flipping differences when sensitive data is involved in real operations (the specific registers and data in the instructions are omitted below, and only the principle of inserting complementary operations is explained in detail).

[0048] Suppose a very long instruction word processor has four slots: ALU0, ALU1, MUL, and MEM. ALU0 and ALU1 are used to perform arithmetic logic operations, MUL is used to perform multiplication operations, and MEM is used to perform memory access operations.

[0049] The initial sensitive instruction packet is: [ALU0: XOR r20, r14, r15]; [ALU1: empty]; [MUL: empty]; [MEM: Load r21, r16]; Here, r14 and r15 can represent the encryption state and round key, respectively. Since XOR r20, r14, and r15 directly process sensitive data, their data inversion characteristics may be related to the sensitive values. After the VLTC compiler inserts complementary operations, the adjusted target instruction package is: [ALU0: XOR r20, r14, r15]; [ALU1:XOR_comp rD0, ~r14, ~r15]; [MUL: dummy_mul rD1, c1, c2]; [MEM: Load r21, r16]; Among them, XOR_comp rD0, ~r14, and ~r15 are complementary operations. ~r14 and ~r15 represent the inverse complement of the corresponding operand, or can be replaced by a mask value. The result of the complementary operation is written to the pseudo-operation register rD0. The complementary operation does not change the semantics of the real program. Its function is to make the ALU data flipping activity more balanced.

[0050] In other implementations, the complementary operation can also be in mask form: [ALU1: xor_comp rD0, r14] mask, R15 [mask], where mask is a fixed mask or a secure random mask.

[0051] The aforementioned fixed memory access operations can specifically supplement resource overhead in memory access and bus-related dimensions, and can quickly adjust the overall power consumption leakage score to within the target range. For example, a fixed memory access operation that accesses the isolation buffer is inserted into an empty MEM slot.

[0052] The following specific example illustrates how the VLTC compiler inserts fixed memory access operations when the initial sensitive instruction packet lacks memory access operations, in order to maintain stable memory access port and bus activity (the specific registers and data in the instructions are omitted below, and only the principle of inserting fixed memory access operations is explained in detail).

[0053] Suppose a very long instruction word processor has four slots: ALU0, ALU1, MUL, and MEM. ALU0 and ALU1 are used to perform arithmetic logic operations, MUL is used to perform multiplication operations, and MEM is used to perform memory access operations.

[0054] The initial sensitive instruction packet is: [ALU0: ADD r30, r22, r23]; [ALU1:XOR r31, r24, r25]; [MUL: MUL r32, r26, r27]; [MEM: empty]; The initial sensitive instruction packet did not use the MEM slot, which may result in lower memory access port and bus activity in this cycle compared to other cycles. The VLTC compiler inserts a fixed memory access operation in the MEM slot, and the adjusted target instruction packet is as follows: [ALU0: ADD r30, r22, r23]; [ALU1:XOR r31, r24, r25]; [MUL: MUL r32, r26, r27]; [MEM: dummy_load rD0, dummy_addr]; The dummy_addr is located in the isolation buffer or a dedicated pseudo-operation register area. This memory access operation does not access the actual data area and does not affect program semantics, but it can maintain the stability of memory access ports and bus activity.

[0055] In some implementations, resource overhead can be mitigated by writing the result to a dedicated pseudo-operation register.

[0056] In step S320 above, when the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is higher than the preset target leakage threshold, it indicates that the resource activity of the initial sensitive instruction packet is too concentrated. The overall power leakage level of this initial sensitive instruction packet is far higher than the preset equilibrium target. It will also create a significant power difference with other low-power sensitive instruction packets that can be captured by attackers, thereby leaking secret information such as keys and sensitive intermediate computation results. At this point, it is necessary to reduce the overall power leakage level through scheduling adjustments, lowering the power leakage score to within the preset allowable deviation range of the preset target leakage threshold, so that the overall power consumption level of all sensitive instruction packets remains within a similar range, eliminating power differences that can be exploited by side-channel analysis.

[0057] The aforementioned slot allocation adjustment includes, but is not limited to: adjusting the instruction to be adjusted from the current slot to another functionally compatible slot without changing the program semantics and execution cycle of the initial sensitive instruction package, so as to reduce the power consumption hotspots of a single slot, execution cluster, register port or local bus. The instruction to be adjusted is an instruction in the initial sensitive instruction package that belongs to the same execution cluster as the previous instruction or the next instruction and shares a register port.

[0058] As can be understood, adjusting slot allocation refers to moving certain operations from their current slot to other functionally compatible slots within the same instruction packet, without altering the program semantics or the instruction packet's execution cycle. This method differs from moving high-power operations to adjacent instruction packets, which involves cross-cycle scheduling; slot allocation adjustment is a spatial reallocation within the instruction packet. The goal of adjusting slot allocation is to achieve a more balanced use of hardware resources within the same cycle, while satisfying slot functional constraints, register port constraints, and data dependency constraints. This reduces power hotspots in individual slots, execution clusters, register ports, or local buses, thereby lowering the local peak power consumption of the instruction packet.

[0059] The following is a specific example illustrating the process of adjusting slot allocation (the specific registers and data in the instructions are omitted below, and only the principle of slot allocation is explained in detail).

[0060] Suppose a Very Long Instruction Word (VLTB) processor has four slots: Slot0, Slot1, Slot2, and Slot3.

[0061] The initial sensitive instruction packet is: [Slot0: ADD r30, r22, r23]; [Slot1: SUB r32, r26, r27]; [Slot2: MUL r28, r24, r25]; [Slot3: NOP]; If Slot0 and Slot1 belong to the same execution cluster and share a register read port, and Slot3 also supports simple ALU operations, the adjusted target instruction package is as follows: [Slot0: ADD r30, r22, r23]; [Slot1: NOP]; [Slot2: MUL r28, r24, r25]; [Slot3: SUB r32, r26, r27]; Before the adjustment, ADD and SUB were executed simultaneously in the same execution cluster. After the adjustment, SUB was assigned to another compatible slot. The instruction packet cycle number and semantics remained unchanged, but the activity of the register port and local data path was more dispersed, and the local power consumption peak was reduced.

[0062] It should be noted that for scenarios with high performance requirements, a sliding window approach can also be used to determine the preset equalization conditions: ;Formula (6) in, Indicates the first Power leakage score of each initial sensitive instruction packet. Indicates the number of instruction packets. This indicates the preset target leakage threshold. This represents the maximum allowable deviation value for the sliding window. This constraint requires continuity. The total power leakage score of the initial sensitive instruction packet and The difference between the target leakage threshold and the preset threshold does not exceed the allowable deviation. This ensures that the average power leakage level of adjacent consecutive initial sensitive instruction packets remains within a stable range, while also allowing for some flexibility in power scheduling of individual initial sensitive instruction packets, adapting to instruction scheduling constraints in high-performance scenarios. Since most current power side-channel analysis attacks are based on extracting secret information from multi-cycle power statistical features, this sliding window-style equilibrium constraint can effectively disrupt the statistical differences relied upon by attackers, achieving sufficient security protection while ensuring instruction execution performance.

[0063] The above-mentioned high-power rearrangement operation includes, but is not limited to: moving the instruction to be adjusted to the instruction packet adjacent to the initial sensitive instruction packet, and inserting compensation operations in the initial sensitive instruction packet and the instruction packet adjacent to the initial sensitive instruction packet respectively, wherein the instruction to be adjusted is the instruction in the initial sensitive instruction packet whose power consumption value is higher than a preset power consumption threshold.

[0064] The aforementioned high-power rearrangement operations also include, but are not limited to: moving the instruction to be adjusted to an instruction packet adjacent to the initial sensitive instruction packet, and inserting compensation operations into the initial sensitive instruction packet and the instruction packet adjacent to the initial sensitive instruction packet respectively, wherein the instruction to be adjusted is one of multiple multiplication operations or memory access operations in the same cycle of the initial sensitive instruction packet.

[0065] It's important to note that moving some high-power operations to adjacent instruction packets emphasizes cross-instruction packet rescheduling. It doesn't necessarily target only one type of operation, but rather moves excessively concentrated high-power instructions within the current instruction packet to the preceding or following instruction packet, thus dispersing power peaks. In contrast, splitting multiple multiplication and memory access operations within the same cycle emphasizes resolving concurrent conflicts for specific high-power resources. It primarily addresses the issue of high-power resources such as multipliers, memory access units, buses, and register ports being used simultaneously multiple times within the same cycle.

[0066] The following is a specific example illustrating the process of rearranging high-power operations (the specific registers and data in the instructions are omitted below, and only the principle of rearranging high-power operations is explained in detail).

[0067] Suppose a very long instruction word processor has four slots: ALU0, ALU1, MUL, and MEM. ALU0 and ALU1 are used to perform arithmetic logic operations, MUL is used to perform multiplication operations, and MEM is used to perform memory access operations.

[0068] The initial sensitive instruction packet is: [ALU0: ADD r10, r2, r3]; [ALU1: XOR r11, r4, r5]; [MUL: MUL r12, r6, r7]; [MEM: Load r13, r8]; The initial sensitive instruction packet simultaneously utilizes two logic operation slots, one multiplication slot, and one memory access slot, and includes two relatively high-power operations: multiplication and memory access. At this point, the difference between the calculated power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is higher than the preset target leakage threshold. This indicates that the power leakage score of the initial sensitive instruction packet is too high, with a significant power peak. The VLTC compiler moves the multiplication operation to an adjacent instruction packet and inserts compensation operations in both instruction packets. The adjusted target instruction packet is as follows: [ALU0: ADD r10, r2, r3]; [ALU1: XOR r11, r4, r5]; [MUL: dummy_mul rD0, c1, c2]; [MEM: Load r13, r8]; Adjacent instruction packets are: [ALU0: dummy_add rD1, c3, c4]; [ALU1: dummy_xor rD2, c5, c6]; [MUL: MUL r12, r6, r7]; [MEM: dummy_load rD3, dummy_addr]; Among them, MUL r12, r6, and r7 are the actual multiplication operations that are moved from the initial sensitive instruction packet to the adjacent instruction packet. dummy_mul is used to compensate for the activity of the multiplication slot in the initial sensitive instruction packet. dummy_add and dummy_xor are used to compensate for the activity of the ALU slot in the adjacent instruction packet. dummy_load accesses the fixed address dummy_addr in the isolation buffer. rD0, rD1, rD2, and rD3 are all pseudo-operation registers and do not affect the actual program result.

[0069] After adjustment, the power consumption activities of the two consecutive instruction packets are more similar, avoiding significant power consumption peaks in the initial sensitive instruction packet.

[0070] The aforementioned high-power rearrangement operations also include, but are not limited to, sliding window rearrangement of multiple consecutive instruction packets.

[0071] The following example illustrates the process of reordering multiple consecutive instruction packets using a sliding window when strict balancing of a single instruction packet would cause significant performance loss.

[0072] The window size is set to 4, meaning that every four consecutive VLIW instruction packets form a balanced window. : ;Formula (7) in, These represent four consecutive VLIW instruction packets. In the original window, The power leakage scores are 4, 9, 3, and 8 respectively. Assuming the target window's power leakage score is 24, and the current window's total score is also 24 (4+9+3+8=24), although the total window score meets the requirements, the individual instruction packets fluctuate significantly. The VLTC compiler can reduce some high-power operations from... and Move to and Furthermore, pseudo-operations are inserted into low-scoring instruction packages to make the instruction packages within the window smoother.

[0073] Assuming the adjustment The power leakage scores were 6, 7, 5, and 6, respectively. The adjusted total score for the window was still 24, but the power fluctuation within the window was reduced, which helps to suppress attackers from identifying sensitive operations based on short-term power peaks.

[0074] It should be noted that the goal of the above instruction reordering operation is not simply to increase the number of instructions, but to strike a balance between security and performance, making the activity pattern of instruction package resources in sensitive code areas more stable.

[0075] In step S400 above, the security metadata generation module is located in the backend of the VLIW compiler. After the instruction packet equalization scheduling is completed, it generates security metadata associated with the VLIW instruction packet based on sensitive flags, slot occupancy results, pseudo-operation insertion results, complementary operation insertion results, power leakage score, target power level, fixed transmit width, and pseudo-operation register allocation results. The security metadata includes security attribute information, power leakage score, operation result information of the power equalization operation, and preset transmit width. The security attribute information indicates whether the current instruction packet uses secure execution mode ("1" for enabled, "0" for disabled). Secure execution mode needs to be enabled when the instruction packet is a sensitive instruction packet; otherwise, normal execution mode is enabled. The operation result information of the power equalization operation includes slot usage information, indicating the purpose of each slot in the target instruction packet ("real" for real operations, "dummy" for pseudo-operations). The operation result information of the power equalization operation also includes operation authenticity information, indicating which slots in the target instruction packet are dummy. The operation results are categorized as follows: "1" represents a dummy operation, and "0" represents a real operation. The power balancing operation results also include power level information, indicating the target power level to which the target instruction packet is assigned: P0 for low power level, P1 for medium-low power level, P2 for target balanced power level, and P3 for high power level. When the power level information is P2, it indicates that the power leakage score of the target instruction packet meets the preset balancing conditions. The power balancing operation results also include pseudo-operation register allocation results, indicating which pseudo-operation registers are used in the target instruction packet. The preset transmit width indicates the number of fixed transmit slots required when the target instruction packet is executed.

[0076] In step S500 above, the VLTB ​​processor executes the target instruction packet based on security metadata, including but not limited to: if the security attribute information indicates that a secure execution mode needs to be enabled, and the power leakage score of the target instruction packet meets the preset equalization conditions, the target instruction packet is executed according to the preset transmit width based on the operation result information of the power equalization operation.

[0077] The "Execution of Target Instruction Package Based on Secure Metadata" is performed by a secure execution unit located on the VLIW processor side. This secure execution unit works with the VLIW compiler to generate secure VLIW machine code for execution. The secure execution unit may include: 1. Safe Mode Control Unit: Determines whether the target instruction packet needs to enter safe execution mode based on security metadata; 2. Fixed launch control unit: Ensures that each cycle is executed according to the preset launch width in safe execution mode, and does not reduce resource activity due to false operations or empty slots; 3. Pseudo-operation execution control unit: ensures that pseudo-operations are not discarded by the hardware as invalid operations; 4. Secure memory access control unit: Directs fixed memory access operations to a fixed address buffer or a secure pseudo-operation register area to avoid affecting real program data; 5. Security Metadata Verification Unit: Based on slot occupancy information, pseudo-operation identifiers, and target power consumption data, this unit checks whether the target instruction packet meets the security execution requirements. The judgment process includes slot consistency checks, pseudo-operation consistency checks, and target power consumption level checks. First, based on slot usage information, the number of real operation slots and pseudo-operation slots is counted, and their sum is checked to ensure it equals the preset issue width, guaranteeing that the processor executes at a fixed issue width. Second, the consistency between operation authenticity information and slot usage information is checked; slots marked "1" in the operation authenticity information must correspond to pseudo-operations, and unmarked slots cannot be incorrectly identified as pseudo-operations. Third, the legality of pseudo-operations is checked, requiring that pseudo-operation results can only be written to the pseudo-register or isolated region specified by the pseudo-operation register allocation result, and cannot modify real registers, real memory, or program-visible states. Based on this, the VLTC processor calculates a power leakage score based on both real and pseudo-operations, and classifies it into P0, P1, P2, or P3 according to a preset target leakage threshold. If the calculated power leakage score meets the preset equalization conditions, it indicates that the target instruction packet has reached the target power consumption level specified by the VLTC compiler. The target instruction packet is considered to meet the safe execution requirements only when the slot transmit width, pseudo-operation identifier, pseudo-operation side effects, functional unit activity, and target power consumption level all meet the requirements.

[0078] The beneficial effects of the embodiments of this application include, but are not limited to: 1. Reduce power leakage caused by changes in the number of empty slots in VLIW instruction packets; 2. Reduce side-channel characteristics caused by changes in the start / stop status of functional units; 3. Reduce the differences in activity between register read / write ports, memory access ports, and the bus; 4. Supports single-instruction packet-level equalization and sliding window-level equalization; 5. Supports enabling only on sensitive code sections, reducing overall performance loss; 6. By using secure metadata and secure execution mode, we ensure that pseudo-operations are not discarded by the long instruction word processor; 7. Compared to ordinary pseudo-operation instruction insertion, it is more compatible with VLIW multi-slot parallel execution architecture; 8. Improve the resistance of cryptographic algorithms, security authentication procedures, and key processing procedures to power side-channel attacks on very long instruction word processors.

[0079] This application also provides an instruction packet-level power balancing scheduling system, including a very long instruction word (VLSI) compiler and a VLSI processor, wherein: The Very Long Instruction Word (VLTB) compiler is used to obtain the initial sensitive instruction packet, assess the resource consumption and power leakage risk of the initial sensitive instruction packet, calculate the power leakage score, and if the power leakage score does not meet the preset equalization conditions, perform a power equalization operation on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Based on the target instruction packet, security metadata is generated. The security metadata includes security attribute information, power leakage score, operation result information of power equalization operation, and preset issue width. The target instruction packet and security metadata are sent to the VLTB ​​processor. Very Long Instruction Word (VLTB) processors are used to execute target instruction packages based on security metadata.

[0080] Since the instruction packet-level power balancing scheduling system of this application adopts all the technical solutions of the above-mentioned instruction packet-level power balancing scheduling method, it can obtain all the technical effects of the instruction packet-level power balancing scheduling method, which will not be repeated here.

[0081] It should be clarified that this application is not limited to the specific configurations and processes described above. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of this application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0082] The functional blocks described above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. The programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0083] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0084] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A packet-level power balancing scheduling method, applied to a very long instruction word compiler, characterized in that, The instruction packet-level power balancing scheduling method includes: Obtain the initial sensitive instruction packet; The resource consumption and power leakage risks of the initial sensitive instruction packet are assessed, and a power leakage score is calculated; the constraint formula for the power leakage score is: ； in, The power consumption leakage score is given. Weights for operation types, Assigning weight to slot occupancy. For the activity weight of the functional unit, Weights for register read / write ports. Weighting of memory access behavior, As the bus activity weight, To estimate weights for data flipping, , , , , , and The preset weighting coefficients, , , , , , and The weights are calculated based on the resource usage of the initial sensitive instruction package. The weights for operation type, slot usage, functional unit activity, register read / write port, memory access behavior, bus activity, and data flip estimation are obtained through the following steps: parsing the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, and data change of each instruction within the initial sensitive instruction package; calculating the original overhead for each operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, and data change, where the original overhead represents resource usage; dividing the original overhead corresponding to each resource class by the preset overhead upper limit of that resource class in a single instruction package to obtain the weights for operation type, slot usage, functional unit activity, register read / write port, memory access behavior, bus activity, and data flip estimation, where the resource class represents the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, or data change. If the power leakage score does not meet the preset equalization conditions, a power equalization operation is performed on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Security metadata is generated based on the target instruction packet. The security metadata includes security attribute information, power leakage score, operation result information of the power equalization operation, and preset transmit width. The target instruction packet and the security metadata are sent to a Very Long Instruction Word (VLE) processor, so that the VLE processor executes the target instruction packet based on the security metadata.

2. The instruction packet-level power balancing scheduling method according to claim 1, characterized in that, The insertion operation includes insertion pseudo-operation, insertion complementary operation, and insertion fixed memory access operation; If the power leakage score does not meet the preset equalization conditions, a power equalization operation is performed on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions, including: If the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is lower than the preset target leakage threshold, at least one of the following operations shall be performed on the initial sensitive instruction packet: inserting a pseudo-operation, inserting a complementary operation, and inserting a fixed memory access operation to generate the target instruction packet that satisfies the preset balancing condition.

3. The instruction packet-level power balancing scheduling method according to claim 1, characterized in that, The instruction reordering operation includes adjusting slot allocation and reordering high-power operations; If the power leakage score does not meet the preset equalization conditions, a power equalization operation is performed on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions, including: If the difference between the power leakage score and the preset target leakage threshold is greater than the preset allowable deviation, and the power leakage score is higher than the preset target leakage threshold, at least one of the following operations shall be performed on the initial sensitive instruction packet: adjust the slot allocation and rearrange the high power operation to generate the target instruction packet that meets the preset balance condition.

4. The instruction packet-level power balancing scheduling method according to claim 3, characterized in that, The adjustment of slot allocation includes: Without changing the program semantics and execution cycle of the initial sensitive instruction package, the instruction to be adjusted is moved from the current slot to another functionally compatible slot to reduce the power hotspots of a single slot, execution cluster, register port, or local bus. The instruction to be adjusted is an instruction in the initial sensitive instruction package that belongs to the same execution cluster as the previous or next instruction and shares a register port.

5. The instruction packet-level power balancing scheduling method according to claim 3, characterized in that, The high-power rearrangement operation includes: The instruction to be adjusted is moved to the instruction packet adjacent to the initial sensitive instruction packet, and compensation operations are inserted into the initial sensitive instruction packet and the instruction packet adjacent to the initial sensitive instruction packet respectively. The instruction to be adjusted is the instruction in the initial sensitive instruction packet whose power consumption value is higher than a preset power consumption threshold.

6. The instruction packet-level power balancing scheduling method according to claim 3, characterized in that, The high-power rearrangement operation includes: The instruction to be adjusted is moved to the instruction packet adjacent to the initial sensitive instruction packet, and a compensation operation is inserted into the initial sensitive instruction packet and the instruction packet adjacent to the initial sensitive instruction packet, respectively. The instruction to be adjusted is one of multiple multiplication operations or memory access operations in the same cycle in the initial sensitive instruction packet.

7. The instruction packet-level power balancing scheduling method according to claim 1, characterized in that, The Very Long Instruction Word processor executes the target instruction package based on the security metadata, including: If the security attribute information indicates that a secure execution mode needs to be enabled, and the power leakage score of the target instruction packet meets the preset equalization conditions, the target instruction packet is executed according to the preset transmit width based on the operation result information of the power equalization operation.

8. A packet-level power balancing scheduling system, characterized in that, This includes very long instruction word (VLSI) compilers and VLSI processors, among which: The Very Long Instruction Word (VLIW) compiler is used to obtain an initial sensitive instruction packet, assess the resource consumption and power leakage risk of the initial sensitive instruction packet, calculate a power leakage score, and if the power leakage score does not meet the preset equalization conditions, perform a power equalization operation on the initial sensitive instruction packet to generate a target instruction packet that meets the preset equalization conditions. The power equalization operation includes an insertion operation and an instruction reordering operation. The insertion operation is used to supplement resource overhead, and the instruction reordering operation is used to reduce resource overhead. Security metadata is generated based on the target instruction packet. The security metadata includes security attribute information, the power leakage score, the operation result information of the power equalization operation, and a preset transmit width. The target instruction packet and the security metadata are sent to the VLIW processor. The constraint formula for the power leakage score is: ； in, The power consumption leakage score is given. Weights for operation types, Assigning weight to slot occupancy. For the activity weight of the functional unit, Weights for register read / write ports. Weighting of memory access behavior, As the bus activity weight, To estimate weights for data flipping, , , , , , and The preset weighting coefficients, , , , , , and The weights are calculated based on the resource usage of the initial sensitive instruction package. The weights for operation type, slot usage, functional unit activity, register read / write port, memory access behavior, bus activity, and data flip estimation are obtained through the following steps: parsing the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, and data change of each instruction within the initial sensitive instruction package; calculating the original overhead for each operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, and data change, where the original overhead represents resource usage; dividing the original overhead corresponding to each resource class by the preset overhead upper limit of that resource class in a single instruction package to obtain the weights for operation type, slot usage, functional unit activity, register read / write port, memory access behavior, bus activity, and data flip estimation, where the resource class represents the operation type, execution slot, functional unit, register read / write, memory access behavior, bus transmission, or data change. The Very Long Instruction Word (VLTB) processor is used to execute the target instruction package based on the security metadata.

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