Unstructured mesh topology-aware dynamic scheduling method and system for cpu-gpu heterogeneous platform

Abstract

This invention discloses a topology-aware dynamic scheduling method and system for unstructured meshes on CPU-GPU heterogeneous platforms, belonging to the field of high-performance computing technology. The method includes: automatically constructing an enhanced physical topology dependency graph containing computation, data, and memory access weights through source code semantic parsing and mesh adjacency information; collecting device computing power and communication bandwidth profiles; dynamically allocating subdomains to CPUs or GPUs based on computational intensity indicators; optimizing virtual frame data transmission using collaborative memory management; and implementing local rescheduling under load drift through runtime monitoring. This invention requires no modification to the user solver source code, is compatible with unstructured mesh simulation frameworks such as SCHISM and OpenFOAM, significantly improves computational efficiency and resource utilization on heterogeneous platforms, reduces overall power consumption, is compatible with adaptive mesh refinement scenarios, and ensures numerical simulation accuracy and operational stability.

Description

Technical Field

[0001] This invention relates to the fields of high-performance computing and scientific simulation technology, and in particular to an unstructured mesh topology-aware dynamic scheduling method and system for CPU-GPU heterogeneous platforms. Background Technology

[0002] In the fields of meteorology and oceanography, unstructured grid models, represented by SCHISM, can flexibly fit complex coastal terrain and refine the grid in key areas, achieving higher accuracy and resolution, and more efficient variable simulation and solution compared to structured grid models. However, due to the lack of support for multi-GPU parallel computing and distributed computing, its computational efficiency is difficult to improve further.

[0003] In unstructured mesh simulations, the computational domain is usually divided into multiple subdomains and distributed to multiple computational units for parallel processing. Mainstream partitioning tools (such as ParMETIS and Zoltan) mainly partition based on the number of mesh cells or the balance of computational load, which has the following drawbacks: (1) Ignoring hardware heterogeneity: It does not consider the differences in floating-point computing power of different GPUs and the actual transmission bandwidth of links such as PCIe / NVLink; (2) Rigid partitioning granularity: It is divided in units of "cells", but the data volume and computational complexity of different cells are significantly different; (3) Inefficient management of ghost cells: Ghost cell data is stored in a scattered manner, and multiple small packet copies are required during transmission; (4) Lack of runtime adaptability: It cannot cope with dynamic load drift caused by adaptive mesh refinement (AMR); (5) Ignoring differences in computational modes: Existing solutions assume that all subdomains are suitable for GPU acceleration, but in reality, some subdomains (such as boundary layers and sparse physical field regions) have low computational intensity and severe branch divergence, and are more efficient on the CPU.

[0004] Chinese invention patent application CN120144275A discloses a dynamic partitioning and sharding method for CPU-GPU heterogeneous model computation. It allocates tasks across heterogeneous computing components using a 3D rule matrix, employing SIMD technology for instruction-level optimization to improve vector computation speed. Chinese invention patent CN120295803B discloses a GPU and parallel I / O collaborative optimization method based on pattern-based heterogeneous computing. It visualizes common instruction flow characteristics as adjacency features in physical space, achieving automatic source code mapping and topology extraction.

[0005] Therefore, existing related technologies are still limited to the optimization of regular matrices or general instruction streams, and have not achieved automated topology extraction and accurate heterogeneous matching for unstructured grid physical topology and Fortran source code characteristics, thus failing to solve the heterogeneous parallel performance bottleneck of unstructured grid patterns such as SCHISM. Summary of the Invention

[0006] The problem to be solved by this invention is to provide a method and system for topology-aware dynamic scheduling of unstructured grids for CPU-GPU heterogeneous platforms, which can reduce global memory contention caused by random access to unstructured grids and directly improve computational efficiency.

[0007] This invention adopts the following technical solution: a dynamic scheduling method for unstructured mesh topology awareness on CPU-GPU heterogeneous platforms, comprising the following steps:

[0008] Step 1: Based on the source code of the computation program and the grid adjacency list of unstructured grid data, perform source code semantic parsing and construct an enhanced physical topology dependency graph;

[0009] Step 2: Collect the device computing power of CPU and GPU, and the effective bandwidth between devices to form a device profile and communication cost matrix;

[0010] Step 3: Perform dynamic partitioning and heterogeneous allocation based on the enhanced physical topology dependency graph and device profile, and allocate subdomains to CPUs or GPUs according to the subdomain computing intensity index;

[0011] Step 4: Perform collaborative memory management for the GPU and CPU to optimize virtual frame data storage and cross-device data exchange;

[0012] Step 5: Perform runtime monitoring, monitor the equipment load at fixed time steps, and trigger local re-partitioning and re-scheduling when the load deviation rate exceeds the threshold.

[0013] As a preferred embodiment, in step 1, the enhanced physical topology dependency graph is constructed as follows:

[0014] Step 1.1: Traverse the source code using the abstract syntax tree to identify indirect array access statements that satisfy the following pattern: variable name [adjacent index array [loop variable j, i]];

[0015] Step 1.2: If the indirect array access statement appears in the main time step iteration loop, it is determined that there is a physical dependency between unit i and the adjacent index array;

[0016] Step 1.3: Construct an undirected graph ,vertex Represents a grid cell, edge This indicates that the two units are physically adjacent and exchange data.

[0017] Step 1.4, for each vertex Assigning computational weights Data volume weight Memory access weight And the corrected weights are run by sampling a small number of profiles.

[0018] As a preferred embodiment, in step 2, the device profile and communication cost matrix are formed using the following method:

[0019] Step 2.1: Obtain the GPU model through the CUDA Runtime API and look up the peak computing power in the preset performance table. ;

[0020] Step 2.2: Obtain the peak performance of CPU multi-core aggregation through OpenMP micro-benchmark testing. ;

[0021] Step 2.3: Use cudaMemcpyPeer to measure the effective bandwidth between GPUs and between CPUs and GPUs, and construct the communication cost matrix. .

[0022] As a preferred embodiment, in step 3, dynamic partitioning and heterogeneous allocation are performed, as follows:

[0023] Step 3.1: Divide the enhanced physical topology dependency graph into... Connected subfield A multi-level graph partitioning algorithm is used for partitioning, with cut edge weights of 1 / 2. ;

[0024] Step 3.2: For each subdomain Obtain computation / latency intensity metrics ;

[0025] Step 3.3: Set the intensity threshold Used for dynamic adaptation;

[0026] Step 3.4, if If the thread is not assigned to the GPU, it will be assigned to the CPU thread pool. This indicates the computational delay strength of the subdomain. Indicates the real-time intensity threshold;

[0027] Step 3.5: Ensure that subdomains on the same device remain connected in the enhanced physical topology dependency graph to reduce cross-device communication.

[0028] As a preferred embodiment, in step 4, the collaborative memory management method is as follows:

[0029] Step 4.1: Allocate the following for each GPU SM module: main compute memory area and virtual frame dedicated memory area;

[0030] Step 4.2: Allocate an independent memory area for the CPU to store its subdomain data;

[0031] Step 4.3: Perform cross-device virtual frame processing: If GPU subdomain A and CPU subdomain B are adjacent, reserve data slots for B in the virtual frame area of ​​A; and create a read-only mirror copy of the boundary unit of A in the CPU memory;

[0032] Step 4.4: Implement efficient bidirectional data exchange using pinned memory and asynchronous cudaMemcpy to avoid synchronous blocking.

[0033] As a preferred embodiment, the runtime monitoring and local rescheduling in step 5 are performed as follows:

[0034] Step 5.1, each The time step records the computation time of all CPU thread groups and GPU computing units. With communication time ;

[0035] Step 5.2: Calculate the normalized total device time. And obtain the load deviation rate. ;

[0036] Step 5.3, if , To preset the load bias, high / low bias subdomains and their enhanced physical topology dependency graph neighbors are extracted, a local subgraph is constructed, and lightweight repartitioning and redistribution are performed, migrating only the affected subdomains.

[0037] The present invention also provides: an unstructured mesh topology-aware dynamic scheduling system for CPU-GPU heterogeneous platforms, used to implement the aforementioned method, comprising:

[0038] The source code semantic parsing module is used to traverse the source code of the computing program, identify the physical dependencies of grid cells, and construct an enhanced physical topology dependency graph.

[0039] The device profiling module is used to acquire CPU and GPU computing power and inter-device communication bandwidth to form a device profile and communication cost matrix.

[0040] The dynamic partitioning and heterogeneous allocation module is used to perform multi-level graph partitioning on the enhanced physical topology dependency graph and allocate subdomains to CPUs or GPUs according to the computational intensity index.

[0041] The collaborative memory management module is used for GPU memory and CPU memory partition management, optimizing virtual frame data storage and cross-device data transfer;

[0042] The runtime monitoring and rescheduling module is used to monitor device load in real time and trigger local repartitioning and rescheduling.

[0043] The modules interact through message queues to form a closed-loop scheduling system.

[0044] As a preferred embodiment, the source code semantic parsing module traverses the source code through an abstract syntax tree, identifies indirect array access statements, and assigns and corrects computational, data, and memory access weights to the vertices of the enhanced physical topology dependency graph.

[0045] As a preferred embodiment, the collaborative memory management module configures a continuously aligned virtual frame memory area for the GPU and a pinned memory for the CPU to perform asynchronous cudaMemcpy cross-device data exchange.

[0046] As a preferred embodiment, the runtime monitoring and rescheduling module calculates the load deviation rate at fixed time steps, and performs local subgraph repartitioning and subdomain reallocation when the threshold is exceeded.

[0047] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0048] 1. Improved performance and energy efficiency: In the SCHISM nearshore model containing islands, the system of this invention reduces the total execution time by 4.9% compared to the pure GPU solution (ParMETIS partitioning + full GPU execution). Overall energy consumption is reduced by 18%, and performance / watt ratio is improved by 27%.

[0049] 2. Maximize source utilization: The average SM utilization of the GPU is 91%, and the average multi-core utilization of the CPU is 82%; it can effectively avoid SM idleness and branch divergence loss caused by low-intensity subdomains on the GPU.

[0050] 3. Strong compatibility: The method of this invention does not require modification of the user solver source code. It is injected in the form of a dynamic link library and supports mainstream simulation frameworks such as SCHISM v5.10 and OpenFOAM v2212.

[0051] 4. Dynamic Adaptability: The method of this invention can complete local redistribution within 5 time steps after AMR triggering, with a low load deviation rate. The L2 error decreased from 2.3 to 1.15, and remained < . Attached Figure Description

[0052] Figure 1 This is a structural diagram of the unstructured grid topology-aware dynamic scheduling system of the present invention;

[0053] Figure 2 This is a schematic diagram illustrating the construction and subdomain partitioning of the ePTDG in this invention;

[0054] Figure 3This is a layout diagram of the GPU memory and CPU memory collaboration in this invention;

[0055] Figure 4 This is a flowchart of the runtime rescheduling process of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0057] In one embodiment of the present invention, an unstructured grid topology-aware dynamic scheduling system for CPU-GPU heterogeneous platforms has the following structure: Figure 1 As shown, it includes: source code semantic parsing module, device profile collection module, dynamic partitioning and heterogeneous allocation module, collaborative memory management module, and runtime monitoring and rescheduling module. The modules interact through message queues to form a closed-loop scheduling system, realizing automated, dynamic adaptive, and topology-aware CPU-GPU heterogeneous scheduling.

[0058] The source code semantic parsing module is used to traverse the source code of the computing program, identify the physical dependencies of grid cells, and construct an enhanced physical topology dependency graph.

[0059] The device profiling module is used to acquire CPU and GPU computing power and inter-device communication bandwidth to form a device profile and communication cost matrix.

[0060] The dynamic partitioning and heterogeneous allocation module is used to perform multi-level graph partitioning on the enhanced physical topology dependency graph and allocate subdomains to CPUs or GPUs according to the computational intensity index.

[0061] The collaborative memory management module is used for GPU memory and CPU memory partition management, optimizing virtual frame data storage and cross-device data transfer;

[0062] The runtime monitoring and rescheduling module is used to monitor device load in real time and trigger local repartitioning and rescheduling.

[0063] Based on the above system, topology-aware dynamic scheduling of unstructured grids is performed. The input data used are the source code of the calculation program for unstructured grid data (such as a *.f90 file in Fortran) and the grid adjacency list (such as a *.gr3 file in SCHISM). The specific method is as follows:

[0064] Step 1: Construct the enhanced physical topology dependency graph (ePTDG).

[0065] (a) Traverse the source code by abstract syntax tree (AST) (using techniques such as LLVM) to identify indirect array access statements that satisfy the following pattern: variable name [adjacent index array [loop variable]], for example phi(nm(j,i)).

[0066] (b) If the statement appears in the main time step iteration loop, then it is determined that there is a physical dependency between unit i and unit nm(j,i).

[0067] (c) Constructing an undirected graph ;

[0068] Among them, vertex Represents a grid cell; edge This indicates that two cells are physically adjacent and exchange data (i.e., they share at least one mesh vertex or face, and there is cross-cell data reading in the source code).

[0069] (d) for each vertex Assign three types of weights:

[0070] Computational weight : Count the number of floating-point operations (FLOPs) involved in a single time step iteration of this unit, estimated by multiplying the number of floating-point operators (+, −, ×, ÷, sqrt, etc.) in the loop body by the loop expansion factor.

[0071] Data volume weight The total number of bytes is calculated based on the number and data types of the conserved variables contained in the unit. For example, if a triangular unit contains 6 double-type variables, then... byte.

[0072] Memory access weight : Count the number of times the indirect array is accessed (load / store) within the loop body. Bytes per access Cache miss penalty factor (default miss rate 0.7, a single penalty is equivalent to an additional 200 bytes of traffic).

[0073] To improve the accuracy of weights, this embodiment performs correction by combining a small amount of profile sampling (taking the actual execution time of 5-10 time steps) after the initial construction; the constructed ePTDG is cached in memory and only incrementally updated thereafter to avoid repeated full source code analysis.

[0074] In this embodiment, the ePTDG construction and subdomain partitioning process is as follows: Figure 2As shown, the figure includes vertex weight labels.

[0075] Step 2: Collect device profiles.

[0076] (a) Obtain the GPU model through the CUDA Runtime API and look up the peak computing power in the preset performance table. (Unit: TFLOPS)

[0077] (b) Obtain CPU multi-core aggregate peak performance through OpenMP micro-benchmark (STREAM Triad + DGEMM) ;

[0078] (c) Use cudaMemcpyPeer to measure the effective bandwidth between GPU and GPU and between CPU and GPU, and construct the communication cost matrix. .

[0079] Step 3: Perform dynamic partitioning and heterogeneous allocation.

[0080] (a) Divide ePTDG into Connected subdomains The multilevel graph partitioning algorithm (KaHIP) is used for partitioning, and the cut edge weights are:

[0081] ;

[0082] in, , For balance factor ( (Used to illustrate how memory latency amplifies the communication cost) For the target device.

[0083] (b) For each subdomain Calculate the computational / delay intensity index The unit is :

[0084] ;

[0085] (c) Set intensity threshold (Dynamic Adaptive):

[0086] ;

[0087] in, This is an empirical coefficient (default 2.0). The measured roofline inflection point for the CPU (obtained from STREAM testing, approximately 4 FLOPs / Byte by default).

[0088] (d) If If the thread is not assigned to the GPU, it will be assigned to the CPU thread pool.

[0089] (e) Ensure that subdomains on the same device remain connected in the ePTDG to reduce cross-device communication.

[0090] Step 4: Cooperative memory management.

[0091] In this embodiment, the GPU memory and CPU memory collaborative layout process is as follows: Figure 3 As shown, the specific steps include the following:

[0092] (a) Allocate to each SM module within the GPU, including:

[0093] Main compute memory area (stores its subdomain data);

[0094] Dedicated video memory area with virtual frame (contiguous, block-based by source subdomain ID, 128-byte aligned, supports) - Layer Halo extension, default ).

[0095] (b) Allocate a separate memory area (using pinned memory) for the CPU to store its subdomain data.

[0096] (c) Cross-device dashed frame processing:

[0097] If subdomain A (GPU) and subdomain B (CPU) are adjacent, then a data slot for B is reserved in the dashed frame area of ​​A;

[0098] Create a read-only mirror copy of the boundary cell of A in CPU memory;

[0099] Efficient bidirectional data exchange is achieved through pinned memory and asynchronous cudaMemcpy, avoiding synchronous blocking.

[0100] Step 5: Runtime monitoring and local rescheduling.

[0101] (a) each Time step (default) Record the computation time of all computing units (CPU thread groups, GPU). With communication time .

[0102] (b) Calculate the normalized total equipment time and obtain the load deviation rate:

[0103] ;

[0104] ;

[0105] in, For all active devices.

[0106] (c) If (In this embodiment, the default value is 1.5, which can be dynamically adjusted based on historical statistics.) Then, high / low deviation subdomains and their ePTDG neighbors are extracted, a local subgraph is constructed, and lightweight repartitioning and redistribution are performed, migrating only the affected subdomains. The migration amount is usually <5% of the total cells.

[0107] In this embodiment, the runtime rescheduling process is as follows: Figure 4 As shown, it includes Logic for computation and local subgraph extraction.

[0108] Furthermore, taking the SCHISM v5.10 nearshore model (including islands) as an example, the input is an unstructured triangular mesh (8.2 million elements) with a complex coastline; the source code is in Fortran 90 format; the hardware configuration is one server (2×IntelXeon Gold 6348 CPU + 4×NVIDIA A100 80GB GPU, NVLink interconnect).

[0109] In use, scheduling is performed using the unstructured grid topology-aware dynamic scheduling method of this invention, as follows:

[0110] 1. Source code analysis to construct ePTDG: Identifying indirect accesses such as eta(nm(j,i)) to obtain typical cells. FLOPs byte.

[0111] 2. Equipment Profile: TFLOPS TFLOPS GB / s;

[0112] 3. Dynamic partitioning generates 16 subdomains; strength analysis is performed on 10 subdomains. → Allocate to GPU; 6 (sparse regions at the edge of islands) → Assigned to CPU;

[0113] 4. Collaborative memory management: GPU Ghost areas are allocated contiguously, while the CPU uses pinned memory; cross-device Ghost swap latency is < 15 μs;

[0114] 5. Execution time: 4320 time steps, total time: 6.8 hours, L2 error: < ;

[0115] 6. Step 2000 AMR is triggered (120,000 new units are added), and local redistribution is completed within 5 steps with no significant fluctuations in system throughput.

[0116] In summary, this invention provides an automated, dynamically adaptive scheduling method and system for heterogeneous unstructured grids, which can achieve: (1) accurate modeling: automatically constructing an enhanced physical topology dependency graph (ePTDG) with weights for computational and data volume from the source code; (2) heterogeneous matching: dynamically allocating computational tasks to CPU or GPU based on subdomain computational intensity index; (3) collaborative management: allocating continuous GPU memory areas for virtual frames and establishing independent memory areas for tasks allocated to CPU; (4) closed-loop adaptation: monitoring system load deviation in real time during runtime and dynamically triggering local repartitioning and reassignment.

[0117] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A topology-aware dynamic scheduling method for unstructured meshes on CPU-GPU heterogeneous platforms, characterized in that, Includes the following steps: Step 1: Based on the source code of the computation program and the grid adjacency list of unstructured grid data, perform source code semantic parsing and construct an enhanced physical topology dependency graph; Step 2: Collect the device computing power of CPU and GPU, and the effective bandwidth between devices to form a device profile and communication cost matrix; Step 3: Perform dynamic partitioning and heterogeneous allocation based on the enhanced physical topology dependency graph and device profile, and allocate subdomains to CPUs or GPUs according to the subdomain computing intensity index; Step 4: Perform collaborative memory management for the GPU and CPU to optimize virtual frame data storage and cross-device data exchange; Step 5: Perform runtime monitoring, monitor the equipment load at fixed time steps, and trigger local re-partitioning and re-scheduling when the load deviation rate exceeds the threshold.

2. The unstructured grid topology-aware dynamic scheduling method according to claim 1, characterized in that, In step 1, the enhanced physical topology dependency graph is constructed as follows: Step 1.1: Traverse the source code using the abstract syntax tree to identify indirect array access statements that satisfy the following pattern: variable name [adjacent index array [loop variable j, i]]; Step 1.2: If the indirect array access statement appears in the main time step iteration loop, it is determined that there is a physical dependency between unit i and the adjacent index array; Step 1.3: Construct an undirected graph ,vertex Represents a grid cell, edge This indicates that the two units are physically adjacent and exchange data. Step 1.4, for each vertex Assigning computational weights Data volume weight Memory access weight And the corrected weights are run by sampling a small number of profiles.

3. The unstructured grid topology-aware dynamic scheduling method according to claim 2, characterized in that, The computational weight is used to count the number of floating-point operations involved in a single time step iteration of the unit, and is estimated by multiplying the number of floating-point operators in the loop body by the loop expansion factor. The data volume weight is calculated based on the number of conserved variables contained in the unit and their data types, totaling the number of bytes. The memory access weight is determined by counting the number of indirect array accesses within the loop body. Bytes per access Calculation of cache miss penalty coefficient.

4. The unstructured grid topology-aware dynamic scheduling method according to claim 2, characterized in that, In step 2, the device profile and communication cost matrix are formed, as follows: Step 2.1: Obtain the GPU model through the CUDA Runtime API and look up the peak computing power in the preset performance table. ; Step 2.2: Obtain the peak performance of CPU multi-core aggregation through OpenMP micro-benchmark testing. ; Step 2.3: Use cudaMemcpyPeer to measure the effective bandwidth between GPUs and between CPUs and GPUs, and construct the communication cost matrix. .

5. The unstructured grid topology-aware dynamic scheduling method according to claim 4, characterized in that, In step 3, dynamic partitioning and heterogeneous allocation are performed as follows: Step 3.1: Divide the enhanced physical topology dependency graph into... Connected subfield A multi-level graph partitioning algorithm is used for partitioning, with cut edge weights of 1 / 2. ; ； in, , As a balance factor, For the target device; Step 3.2: For each subdomain Obtain computation / latency intensity metrics : ； Step 3.3: Set the intensity threshold Used for dynamic adaptation: ； in, This is an empirical coefficient. This refers to the measured inflection point of the CPU's roofline. Step 3.4, if If the thread is not assigned to the GPU, it will be assigned to the CPU thread pool. This indicates the computational delay strength of the subdomain. Indicates the real-time intensity threshold; Step 3.5: Ensure that subdomains on the same device remain connected in the enhanced physical topology dependency graph to reduce cross-device communication.

6. The unstructured grid topology-aware dynamic scheduling method according to claim 4, characterized in that, In step 4, collaborative memory management is implemented as follows: Step 4.1: Allocate the following for each GPU SM module: main compute memory area and virtual frame dedicated memory area; Step 4.2: Allocate an independent memory area for the CPU to store its subdomain data; Step 4.3: Perform cross-device virtual frame processing: If GPU subdomain A and CPU subdomain B are adjacent, reserve data slots for B in the virtual frame area of ​​A; and create a read-only mirror copy of the boundary unit of A in the CPU memory; Step 4.4: Implement efficient bidirectional data exchange using pinned memory and asynchronous cudaMemcpy to avoid synchronous blocking.

7. The unstructured grid topology-aware dynamic scheduling method according to claim 4, characterized in that, In step 5, runtime monitoring and local rescheduling are performed as follows: Step 5.1, each The time step records the computation time of all CPU thread groups and GPU computing units. With communication time ; Step 5.2: Calculate the normalized total device time. And obtain the load deviation rate. ; Step 5.3, if , To preset the load bias, high / low bias subdomains and their enhanced physical topology dependency graph neighbors are extracted, a local subgraph is constructed, and lightweight repartitioning and redistribution are performed, migrating only the affected subdomains.

8. The unstructured grid topology-aware dynamic scheduling method according to claim 7, characterized in that, The normalized device total time The formula is: ； The load deviation rate The formula is: ； in, For all active devices.

9. A topology-aware dynamic scheduling system for unstructured meshes on CPU-GPU heterogeneous platforms, used to implement the method described in any one of claims 1 to 8, characterized in that, include: The source code semantic parsing module is used to traverse the source code of the computing program, identify the physical dependencies of grid cells, and construct an enhanced physical topology dependency graph. The device profiling module is used to acquire CPU and GPU computing power and inter-device communication bandwidth to form a device profile and communication cost matrix. The dynamic partitioning and heterogeneous allocation module is used to perform multi-level graph partitioning on the enhanced physical topology dependency graph and allocate subdomains to CPUs or GPUs according to the computational intensity index. The collaborative memory management module is used for GPU memory and CPU memory partition management, optimizing virtual frame data storage and cross-device data transfer; The runtime monitoring and rescheduling module is used to monitor device load in real time and trigger local repartitioning and rescheduling. The modules interact through message queues to form a closed-loop scheduling system.

10. The unstructured grid topology-aware dynamic scheduling system according to claim 9, characterized in that, The source code semantic parsing module traverses the source code through an abstract syntax tree, identifies indirect array access statements, and assigns and corrects computational, data, and memory access weights to the vertices of the enhanced physical topology dependency graph. The collaborative memory management module configures a continuously aligned virtual frame memory area for the GPU and a pinned memory for the CPU to perform asynchronous cudaMemcpy cross-device data exchange. The runtime monitoring and rescheduling module calculates the load deviation rate at fixed time steps, and performs local subgraph repartitioning and subdomain reallocation when the threshold is exceeded.

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