An AI and multi-parameter fusion-based flash memory particle screening method and system

Abstract

This invention relates to the field of semiconductor storage technology, specifically a flash memory chip screening method and system based on AI and multi-parameter fusion. The method includes the following steps: S1, initial grading test: screening A-grade and B-grade chips based on a preset basic threshold T0; S2, defect feature extraction: analyzing the defect features of B-grade chips; S3, calculating the reactivation threshold T1 based on the extracted defect features, and optimizing T1 by combining the fill rate risk coefficient, data retention decay rate, and cumulative erase / write cycles to obtain the final dynamic threshold T2; S4, secondary screening; S5, adaptive adjustment. Compared with existing technologies, this significantly improves yield, ensures reliability throughout the entire lifecycle, and enhances scenario adaptability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, specifically to a flash memory chip screening method and system based on AI and multi-parameter fusion. Background Technology

[0002] In the NAND flash memory manufacturing process, RDT (Reliability Detection and Testing) is a crucial step in ensuring product reliability. It primarily filters out defective chips by setting a fixed error bit threshold, such as a common threshold of 200 bits of error per 4KB data page. However, this traditional fixed threshold screening method has gradually revealed the following significant problems in practical applications: First, there is the issue of yield loss. Fixed thresholds lack the ability to distinguish the types of particle defects. Some particles, although their initial number of error bits is slightly higher than the threshold, but whose defects are repairable and can be effectively corrected by strong error correction algorithms such as LDPC, are misjudged as failures. This directly leads to a reduction in effective yield, typically causing a potential yield loss of 5%-10%.

[0003] Secondly, there is the issue of insufficient reliability adaptation. Different NAND flash memory chips exhibit significant differences in defect characteristics, such as random errors, consecutive errors, and errors caused by write / erase fatigue. Their reliability performance varies greatly across different application scenarios. Fixed thresholds cannot dynamically adapt to these differences, especially in high-fill-rate scenarios, such as data storage scenarios with over 90% data storage. Some chips deemed acceptable (Grade B), meaning those with slightly lower performance or reliability than Grade A, may face the risk of rapidly declining data retention capabilities. Traditional methods struggle to accurately assess their long-term reliability.

[0004] Finally, there is a lack of dynamic optimization mechanisms. Existing screening methods are mostly one-time tests, failing to consider real-time changes in the state of the chips during subsequent use, such as temperature fluctuations, increases in the cumulative number of erase / write cycles, and changes in IO response time. This makes it impossible for the screening strategy to be dynamically adjusted according to the actual usage of the chips, easily leading to over-screening by misjudging potentially usable chips as invalid, and under-screening by misjudging potentially risky chips as qualified. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a flash memory chip screening method and system based on AI and multi-parameter fusion. This method can dynamically adjust dynamic thresholds according to chip characteristics, application scenarios, and real-time status, thereby improving the utilization rate of NAND chips and ensuring the long-term reliability of the storage system.

[0006] To achieve the above objectives, a flash memory chip screening method based on AI and multi-parameter fusion is designed, including the following methods: S1, Initial grading test: Perform reliability verification test on the NAND particles to be screened, and screen out A-grade particles and B-grade particles based on the preset basic threshold T0. The number of error bits of the A-grade particles is ≤ T0, and the number of error bits of the B-grade particles is > T0. S2, Defect feature extraction: Perform defect feature analysis on B-level particles. The defect features include error type, LDPC error correction code margin, and error bit spatial distribution characteristics. S3, obtain the resurrection threshold T1: calculate the resurrection threshold T1 based on the extracted defect features, and optimize T1 by combining the fill rate risk coefficient, data retention decay rate and cumulative erase / write count to obtain the final dynamic threshold T2; S4, Secondary screening: Use T2 to perform a secondary screening test on the B-level particles to determine whether they are reusable B+ level particles; if the number of error bits of the B-level particles is ≤ T2, then mark them as reusable B+ level particles; otherwise, mark them as B- level particles. S5, Adaptive Adjustment: After the B+ level particles are put into actual use, the number of error bits in operation is monitored in real time by inputting the particles through the LSTM neural network model, the number of error bits in a specific future time period is predicted, and T2 is dynamically adjusted up / down according to the prediction results. When the predicted number of error bits in the future exceeds the safety threshold, the minimum safety margin in S3 is corrected in reverse, and S3 to S5 are re-executed to form a closed-loop feedback optimization.

[0007] In step S2, the error type includes the ratio of correctable errors to uncorrectable errors, and the spatial distribution characteristics of error bits are characterized by the relative proportions of continuous errors and random errors.

[0008] In step S3, the resurrection threshold T1 is: T1 = T0 + k × (LDPC margin - minimum safety margin), where, k is a correction factor, with a value of 0.5-0.8, and the minimum safety margin is 30-50 bits. The dynamic threshold T2 = T1 × (1 – α × P - β × R - γ × E), where, P is the risk coefficient for the fill rate, P = 0.1 × (fill rate - 50%); R is the data retention decay rate, R = (number of erroneous bits after aging - number of initial erroneous bits) / number of initial erroneous bits; E is the normalized value of the cumulative erase / write count. When the cumulative erase / write count > the preset erase / write lifespan baseline value, E = 1. When the cumulative erase / write count ≤ the preset erase / write lifespan baseline value, E = current cumulative erase / write count / preset erase / write lifespan baseline value. α, β, and γ are the weighting coefficients for the fill rate risk coefficient, the data retention decay rate, and the normalized value of the cumulative number of erase / write cycles, respectively, and satisfy α+β+γ=1.

[0009] In step S3, the weighting coefficients of the fill rate risk coefficient, data retention decay rate, and cumulative erase / write count are dynamically adjusted based on the error type and the relative magnitudes of the proportion of continuous errors and the proportion of random errors. Specifically, the method is as follows: When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of correctable errors is higher than the preset threshold, the weight of the fill rate risk coefficient is increased, and the weight of the cumulative number of erase / write cycles is decreased accordingly. When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of uncorrectable errors is higher than a preset threshold, the weight of the data retention decay rate is increased, and the weight of the fill rate risk coefficient is decreased accordingly. When the proportion of random errors is greater than the proportion of consecutive errors, the weight of the fill rate risk coefficient is reduced, and the weight of the cumulative number of erase / write cycles is increased accordingly. The value of the weight adjustment step size Δ, which is increased or decreased, ranges from 0.05 to 0.15.

[0010] In step S4, during the secondary screening, if the number of error bits of a grade B particle is greater than T2 but less than 1.2 times T2, it is marked as a grade B particle to be observed, and the process is repeated in step S2 to extract defect features and calculate T2 again.

[0011] In step S5, the dynamic upward / downward adjustment ratio range based on the prediction result is 5-10%.

[0012] In step S5, the security threshold is the theoretical upper limit of LDPC error correction code multiplied by a preset security coefficient, and the security coefficient ranges from 0.7 to 0.9.

[0013] In step S5, the specific method for reverse correction is as follows: the minimum safety margin is increased according to the formula M_new = M_old × (1 + δ), where δ is the adaptive step size between 0.05 and 0.15, M_new is the corrected minimum safety margin, and M_old is the current minimum safety margin.

[0014] To achieve the above objectives, a flash memory chip screening system based on AI and multi-parameter fusion is designed to implement the aforementioned flash memory chip screening method based on AI and multi-parameter fusion, including: Reliability verification test module: used to perform reliability verification tests and secondary screening tests on NAND flash memory chips, supports high temperature aging tests, erase and write cycle tests, and generates error bit growth curves; Particle grading module: Used to grade particles into A, B, B+, and B- grades; Multi-parameter decision module: used to collect multi-dimensional parameters in real time and calculate the dynamic threshold T2 through a preset algorithm; AI Prediction Module: Used to deploy a trained LSTM neural network model, receive real-time monitoring data of particles, output the predicted number of error bits within a specific future time period, and provide suggestions for adjusting the dynamic threshold T2. Storage controller: Based on the grading results of the granularity grading module, it allocates granules of different grades to different storage task scenarios.

[0015] The input features of the LSTM neural network model include: the current number of error bits, the cumulative number of erase / write cycles, the operating temperature, and the previous prediction error value. The output is the number of predicted error bits for the next 24 hours. The real-time particle monitoring data includes the number of error bits, IO response latency, and temperature change rate. The AI ​​prediction module includes a model update unit, which iteratively trains the LSTM model every quarter using newly added particle data.

[0016] Compared with the prior art, the present invention has the following advantages: 1. Significantly improve yield: Through a dual-layer screening mechanism of basic threshold + revival threshold, a large number of repairable B-grade particles that would otherwise be eliminated by fixed threshold screening can be effectively revived, improving the overall yield of NAND particles by 15%-20%, thereby significantly reducing the production cost per 10,000 wafers, which is expected to be reduced by 8%-12%.

[0017] 2. Ensure reliability throughout the entire lifecycle: The multi-parameter fusion decision model incorporates key factors such as fill rate, data retention decay, and number of erase / write cycles into threshold calculations. Combined with the AI ​​model's accurate prediction of the long-term reliability of the particles, it ensures that the number of error bits of the selected particles throughout their entire lifecycle is always lower than the error correction limit of error correction algorithms such as LDPC, reducing the risk of data loss by more than 90%.

[0018] 3. Enhanced scenario adaptability: Through fine-grained granular classification, differentiated and scenario-specific reuse of granules of different quality levels is achieved. This not only meets the diverse reliability and cost requirements of different markets such as enterprise and consumer, but also adapts to application scenarios in multiple fields such as cloud computing, mobile terminals, and the Internet of Things. Detailed Implementation

[0019] The present invention will now be further described.

[0020] The flash memory chip screening method based on AI and multi-parameter fusion in this embodiment includes the following methods: S1, Initial Grading Test: The initial grading test performs a reliability verification test on the NAND flash memory chips to be screened. Based on a preset basic threshold T0, A-grade and B-grade chips are selected. The number of error bits in the A-grade chips is ≤ T0, and the number of error bits in the B-grade chips is > T0. The B-grade chips are not directly eliminated but enter a subsequent secondary revival test process. In this embodiment, the basic threshold T0 is 200 bit errors / 4KB data page. S2, Defect feature extraction: Perform defect feature analysis on B-level particles. The defect features include error type, LDPC error correction code margin, and error bit spatial distribution characteristics. S3, obtain the resurrection threshold T1: calculate the resurrection threshold T1 based on the extracted defect features, and optimize T1 by combining the fill rate risk coefficient, data retention decay rate and cumulative erase / write count to obtain the final dynamic threshold T2; S4, Secondary screening: Use T2 to perform a secondary screening test on the B-level particles to determine whether they are reusable B+ level particles; if the number of error bits of the B-level particles is ≤ T2, then mark them as reusable B+ level particles; otherwise, mark them as B- level particles. S5, Adaptive Adjustment: After the B+ level particles are put into actual use, the number of error bits in operation is monitored in real time by inputting the particles through the LSTM neural network model, the number of error bits in a specific future time period is predicted, and T2 is dynamically adjusted up / down according to the prediction results. When the predicted number of error bits in the future exceeds the safety threshold, the minimum safety margin in S3 is corrected in reverse, and S3 to S5 are re-executed to form a closed-loop feedback optimization.

[0021] In step S2, the error type includes the ratio of correctable errors to uncorrectable errors, and the spatial distribution characteristics of error bits are characterized by the relative proportions of consecutive errors and random errors. The error types are divided into consecutive errors and random errors. A consecutive error refers to an error pattern where adjacent memory cells fail consecutively. Specifically, the criteria are: if three or more consecutive adjacent memory cells within a physical page contain error bits, it is considered a consecutive error; error bits that do not meet the criteria for consecutive errors are classified as random errors.

[0022] Assuming the total number of error bits extracted from the Class B particles is N_total, the number of consecutive error bits is N_burst, and the number of random error bits is N_random, then: Percentage of consecutive errors R_burst = N_burst / N_total The percentage of random errors R_random = N_random / N_total And it satisfies R_burst + R_random = 1.

[0023] For Class B particles with extracted defect features, this invention introduces the concepts of a resurrection threshold T1 and a dynamic threshold T2. Particles that, although initially exceeding the error limit, have defect types that can be effectively corrected and possess sufficient error correction redundancy, are given a chance to be resurrected.

[0024] In step S3, the resurrection threshold T1 is: T1 = T0 + k × (LDPC margin - minimum safety margin), where, k is a correction factor, ranging from 0.5 to 0.8. The LDPC margin is calculated in real time using ECC logs. The minimum safety margin is a redundancy reserved to ensure that the particle still has sufficient error correction capabilities during long-term use, with a value of 30-50 bits. In actual use, the minimum safety margin is dynamically adjusted according to the particle's application scenario; for example, it is set to 50 bits for enterprise-level scenarios and 30 bits for consumer-level scenarios.

[0025] To further ensure the reliability of the screened particles in practical application scenarios, this invention integrates the calculation of the dynamic threshold with multiple key influencing parameters to form a more comprehensive decision-making model. The dynamic threshold T2 = T1 × (1 – α × P - β × R - γ × E), where, P represents the fill rate risk coefficient, P = 0.1 × (fill rate - 50%), where the fill rate can be obtained through real-time statistics from the storage controller or preset according to the target application scenario. The data fill rate of the storage device is a significant factor affecting the error rate of NAND flash memory. A high fill rate exacerbates interference between different storage cells within the flash memory, leading to an increase in the error rate. Therefore, when the fill rate increases, the dynamic threshold T2 will be lowered accordingly.

[0026] R represents the data retention decay rate, calculated as: R = (Number of erroneous bits after aging - Initial number of erroneous bits) / Initial number of erroneous bits. The data retention decay rate R is obtained by calculating the increase in the number of erroneous bits after high-temperature aging testing of the particles. If the R value is too high, it indicates poor data retention capability of the particle, and T2 will be adjusted accordingly.

[0027] E is the normalized value of the cumulative erase / write cycles. When the cumulative erase / write cycles > the preset erase / write lifetime baseline value, E = 1. When the cumulative erase / write cycles ≤ the preset erase / write lifetime baseline value, E = current cumulative erase / write cycles / preset erase / write lifetime baseline value. The preset erase / write lifetime baseline value is adjusted according to the type of flash memory chip and the manufacturing process. In this embodiment, the preset erase / write lifetime baseline value is 1000 cycles. The number of erase / write cycles of NAND chips directly affects their lifespan and reliability. If the chip has undergone a large number of PE cycles before screening, i.e., a large number of erase / write cycles, its dynamic threshold T2 also needs to be lowered accordingly.

[0028] α, β, and γ are the weighting coefficients for the fill rate risk coefficient, the data retention decay rate, and the normalized value of the cumulative erase / write cycles, respectively, and satisfy α + β + γ = 1. In this embodiment, α = 0.4, β = 0.3, and γ = 0.3.

[0029] In step S3, the weighting coefficients of the fill rate risk coefficient, data retention decay rate, and cumulative erase / write count are dynamically adjusted based on the error type and the relative magnitudes of the proportion of continuous errors and the proportion of random errors. Specifically, the method is as follows: When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of correctable errors is higher than the preset threshold, the weight of the fill rate risk coefficient is increased, and the weight of the cumulative number of erase / write cycles is decreased accordingly. When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of uncorrectable errors is higher than a preset threshold, the weight of the data retention decay rate is increased, and the weight of the fill rate risk coefficient is decreased accordingly. When the proportion of random errors is greater than the proportion of consecutive errors, the weight of the fill rate risk coefficient is reduced, and the weight of the cumulative number of erase / write cycles is increased accordingly. The step size Δ for increasing or decreasing the weights ranges from 0.05 to 0.15. In this embodiment, Δ = 0.1. That is, when R_burst>R_random: (α, β, γ) = (α0 + Δ, β0, γ0 - Δ); When R_random>R_burst: (α, β, γ) = (α0 - Δ, β0, γ0 + Δ); When R_burst = R_random: (α, β, γ) = (α0, β0, γ0); Where Δ is the weight adjustment step size, R_burst is the proportion of continuous errors, and R_random is the proportion of random errors.

[0030] In one embodiment of the present invention, the proportion of continuous errors R_burst = 0.7 and the proportion of random errors R_random = 0.3 for a certain B-grade particle. Since R_burst > R_random, it indicates that the defects of this particle are mainly continuous errors. Such defects are more strongly associated with the fill rate risk. Therefore, the weight of the fill rate risk coefficient is increased. The adjusted weight coefficient is (α, β, γ) = (0.4 + 0.1, 0.3, 0.3 - 0.1) = (0.5, 0.3, 0.2). In one embodiment of the present invention, the random error ratio R_random = 0.7 and the continuous error ratio R_burst = 0.3 for another B-grade particle. Since R_random > R_burst, it indicates that the defects of this particle are mainly random errors. Such defects are more strongly associated with erase and write fatigue. Therefore, the weight of the cumulative erase and write times is increased. The adjusted weight coefficient is: (α, β, γ) = (0.4 - 0.1, 0.3, 0.3 + 0.1) = (0.3, 0.3, 0.4); The test experiment based on 1,000 B-grade particles showed that after adopting the above dynamic adjustment mechanism, the screening accuracy of B+ grade particles, that is, the proportion of particles marked as B+ grade that did not experience early failure in actual use, reached 87.3%, which is about 12.2 percentage points higher than the 75.1% of the fixed weight scheme.

[0031] In one embodiment of the present invention, if a Class B particle has an error bit count greater than T2 but less than 1.2 times T2 during the secondary screening in S4, it is marked as a Class B particle to be observed. For the Class B particles to be observed, the process proceeds to S2 to re-extract defect features, and S3 is executed again to calculate T2, and secondary screening is performed using the new T2. If the error bit count of the particle after re-screening is ≤ T2, it is upgraded to a Class B+ particle; if it is still greater than T2 but less than 1.2 times T2, it remains in the observation state and an observation period is set, for example, re-evaluation after every 100 erase / write cycles. If the error bit count is ≥ 1.2 times T2, it is downgraded to a Class B- particle and discarded.

[0032] In step S5, the dynamic upward / downward adjustment ratio ranges from 5% to 10% based on the prediction results.

[0033] In step S5, the security threshold is the theoretical upper limit of LDPC error correction code multiplied by a preset security factor, where the security factor ranges from 0.7 to 0.9. For example, if the upper limit of LDPC error correction for a certain flash memory chip is 320 bits, and the security factor η = 0.8, then the security threshold S_threshold = 320 × 0.8 = 256 bits. When the number of future error bits predicted by LSTM exceeds 256 bits, a reverse correction operation is triggered. The value of the security factor η is determined by comprehensively considering factors such as the type of flash memory chip and the reliability level of the application scenario: for high-reliability scenarios such as enterprise-level SSDs, the value of η is relatively small, such as 0.7, to reserve a larger safety margin. For consumer-grade products, the value of η can be appropriately relaxed, such as 0.9.

[0034] In step S5, the specific method for reverse correction is as follows: the minimum safety margin is increased according to the formula M_new = M_old ×(1 + δ), where M_new is the corrected minimum safety margin, M_old is the current minimum safety margin, and δ is an adaptive step size between 0.05 and 0.15. The value of δ is positively correlated with the excess ratio, and the mapping relationship is as follows: When the excess proportion is ≤ 5%, δ = 0.05; When 5% < the excess proportion ≤ 10%, δ = 0.08; When 10% < the excess proportion ≤ 15%, δ = 0.12; When the excess ratio is greater than 15%, δ = 0.15.

[0035] In one embodiment of the present invention, the initial value of the minimum safety margin M_old is 40 bits. If the number of prediction error bits is 280 and the safety threshold is 256, the excess ratio is (280-256) / 256 ≈ 9.4%, then δ = 0.08 is taken, and M_new = 40 × 1.08 = 43.2 bits is calculated. Substituting M_new into S3, the resurrection threshold T1 is recalculated to achieve closed-loop feedback optimization.

[0036] To achieve precise control over the reliability of NAND flash memory throughout its entire lifecycle and to dynamically adjust the screening strategy based on its actual state, this embodiment employs an artificial intelligence-based prediction model. The specific training method for the LSTM neural network model in step S5 is as follows: S51, Dataset Construction: Collect full lifecycle operation data of NAND chips of different types and batches, including the growth curve of the number of error bits over time, performance at different fill rates, data retention test decay records, and the impact of temperature changes on the error rate; in this embodiment, data of more than 100,000 NAND chips are collected.

[0037] S52, Model Training: An LSTM neural network is used as the prediction model. This model can effectively process time series data and is suitable for predicting the trend of particle error bit count over time. The input features of the model include the real-time error bit count of the particle, IO read / write operation response latency, current operating temperature and temperature change rate, particle production batch, and wafer location information. The output feature is the predicted error bit count of the particle within a future set time period. In this embodiment, the future set time period is 1 year / 3 years. The particle production batch is obtained by reading the laser marking on the particle surface or the manufacturer information in the internal register. The wafer location information is obtained by recording the physical coordinates (X,Y) of each particle on the wafer during the wafer testing stage and burning these coordinates into the one-time programmable area of ​​the particle or writing them into the metadata area of ​​the particle by the packaging plant.

[0038] In one specific embodiment, a two-layer LSTM structure is used, with a hidden layer dimension of 128, followed by a fully connected layer to output the predicted value. The model's input features are multi-dimensional vectors within a time window (taking monitoring data from the previous 24 hours, with a sampling interval of 1 hour), including the current number of error bits, cumulative erase / write cycles, operating temperature, and the previous prediction error value. Training uses the Adam optimizer with an initial learning rate of 0.001, a batch size of 64, and 200 training epochs. The loss function is the mean squared error (MSE), and the training objective is for the MSE on the validation set to be less than 0.001. An early stopping strategy is employed during training; training stops when the validation set loss does not decrease for 10 consecutive epochs to prevent overfitting.

[0039] S53, Model Optimization: Continuously adjust the LSTM neural network structure and hyperparameters, and use historical data for training and validation to minimize the mean square error (MSE) between the predicted and actual values, so that the prediction accuracy of the model reaches the set level. In this embodiment, the prediction accuracy is set to be above 92%.

[0040] The system for implementing the above-mentioned flash memory chip screening method based on AI and multi-parameter fusion includes: Reliability verification test module: used to perform reliability verification tests and secondary screening tests on NAND flash memory chips, supports high temperature aging tests, erase and write cycle tests, and generates error bit growth curves; Particle grading module: Used to grade particles into A, B, B+, and B- grades; Multi-parameter decision module: used to collect multi-dimensional parameters in real time and calculate the dynamic threshold T2 through a preset algorithm; AI Prediction Module: Used to deploy a trained LSTM neural network model, receive real-time monitoring data of particles, output the predicted number of error bits within a specific future time period, and provide suggestions for adjusting the dynamic threshold T2. Storage Controller: Based on the grading results from the granularity grading module, different grades of granules are allocated to different storage task scenarios. In this embodiment, Grade A granules are allocated to enterprise-level high-load storage tasks, and Grade B+ granules are allocated to consumer-level read-only storage tasks.

[0041] The input features of the LSTM neural network model include: the current number of error bits, the cumulative number of erase / write cycles, the operating temperature, and the previous prediction error value. The output is the number of predicted error bits for the next 24 hours. The real-time particle monitoring data includes the number of error bits, IO response latency, and temperature change rate. The AI ​​prediction module includes a model update unit, which iteratively trains the LSTM model every quarter using newly added particle data.

[0042] This invention overcomes the limitations of fixed thresholds in existing NAND flash memory RDT screening technologies by introducing a flash memory grading mechanism, multi-dimensional parameter fusion decision-making, and AI prediction models. Through intelligent and dynamic screening strategies, it achieves accurate identification and graded reuse of NAND flash memory defects. This significantly improves the yield of NAND flash memory and reduces the overall cost of storage devices while effectively ensuring the reliability of the storage system throughout its entire lifecycle, thus balancing the yield, cost, and reliability of storage products.

Claims

1. A flash memory chip screening method based on AI and multi-parameter fusion, characterized in that: Including the following methods: S1, Initial grading test: Perform reliability verification test on the NAND particles to be screened, and screen out A-grade particles and B-grade particles based on the preset basic threshold T0. The number of error bits of the A-grade particles is ≤ T0, and the number of error bits of the B-grade particles is > T0. S2, Defect feature extraction: Perform defect feature analysis on B-level particles. The defect features include error type, LDPC error correction code margin, and error bit spatial distribution characteristics. S3, obtain the resurrection threshold T1: calculate the resurrection threshold T1 based on the extracted defect features, and optimize T1 by combining the fill rate risk coefficient, data retention decay rate and cumulative erase / write count to obtain the final dynamic threshold T2; S4, Secondary screening: Use T2 to perform a secondary screening test on the B-level particles to determine whether they are reusable B+ level particles; if the number of error bits of the B-level particles is ≤ T2, then mark them as reusable B+ level particles; otherwise, mark them as B- level particles. S5, Adaptive Adjustment: After the B+ level particles are put into actual use, the number of error bits in operation is monitored in real time by inputting the particles through the LSTM neural network model, the number of error bits in a specific future time period is predicted, and T2 is dynamically adjusted up / down according to the prediction results. When the predicted number of error bits in the future exceeds the safety threshold, the minimum safety margin in S3 is corrected in reverse, and S3 to S5 are re-executed to form a closed-loop feedback optimization.

2. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S2, the error type includes the ratio of correctable errors to uncorrectable errors, and the spatial distribution characteristics of error bits are characterized by the relative proportions of continuous errors and random errors.

3. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S3, the resurrection threshold T1 is: T1 = T0 + k × (LDPC margin - minimum safety margin), where, k is a correction factor, with a value of 0.5-0.8, and the minimum safety margin is 30-50 bits. The dynamic threshold T2 = T1 × (1 – α × P - β × R - γ × E), where, P is the risk coefficient for the fill rate, P = 0.1 × (fill rate - 50%); R is the data retention decay rate, R = (number of erroneous bits after aging - number of initial erroneous bits) / number of initial erroneous bits; E is the normalized value of the cumulative erase / write count. When the cumulative erase / write count > the preset erase / write lifespan baseline value, E = 1. When the cumulative erase / write count ≤ the preset erase / write lifespan baseline value, E = current cumulative erase / write count / preset erase / write lifespan baseline value. α, β, and γ are the weighting coefficients for the fill rate risk coefficient, the data retention decay rate, and the normalized value of the cumulative number of erase / write cycles, respectively, and satisfy α+β+γ=1.

4. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S3, the weighting coefficients of the fill rate risk coefficient, data retention decay rate, and cumulative erase / write count are dynamically adjusted based on the error type and the relative magnitudes of the proportion of continuous errors and the proportion of random errors. Specifically, the method is as follows: When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of correctable errors is higher than the preset threshold, the weight of the fill rate risk coefficient is increased, and the weight of the cumulative number of erase / write cycles is decreased accordingly. When the proportion of continuous errors is greater than the proportion of random errors, and the proportion of uncorrectable errors is higher than a preset threshold, the weight of the data retention decay rate is increased, and the weight of the fill rate risk coefficient is decreased accordingly. When the proportion of random errors is greater than the proportion of consecutive errors, the weight of the fill rate risk coefficient is reduced, and the weight of the cumulative number of erase / write cycles is increased accordingly. The value of the weight adjustment step size Δ, which is increased or decreased, ranges from 0.05 to 0.

15.

5. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S4, during the secondary screening, if the number of error bits of a grade B particle is greater than T2 but less than 1.2 times T2, it is marked as a grade B particle to be observed, and the process is repeated in step S2 to extract defect features and calculate T2 again.

6. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S5, the dynamic upward / downward adjustment ratio range based on the prediction result is 5-10%.

7. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S5, the security threshold is the theoretical upper limit of LDPC error correction code multiplied by a preset security coefficient, and the security coefficient ranges from 0.7 to 0.

9.

8. The flash memory chip screening method based on AI and multi-parameter fusion according to claim 1, characterized in that: In step S5, the specific method for reverse correction is as follows: the minimum safety margin is increased according to the formula M_new = M_old × (1+ δ), where δ is the adaptive step size between 0.05 and 0.15, M_new is the corrected minimum safety margin, and M_old is the current minimum safety margin.

9. A flash memory chip screening system based on AI and multi-parameter fusion, used to implement the flash memory chip screening method based on AI and multi-parameter fusion as described in any one of claims 1-8, characterized in that, include: Reliability verification test module: used to perform reliability verification tests and secondary screening tests on NAND flash memory chips, supports high temperature aging tests, erase and write cycle tests, and generates error bit growth curves; Particle grading module: Used to grade particles into A, B, B+, and B- grades; Multi-parameter decision module: used to collect multi-dimensional parameters in real time and calculate the dynamic threshold T2 through a preset algorithm; AI Prediction Module: Used to deploy a trained LSTM neural network model, receive real-time monitoring data of particles, output the predicted number of error bits within a specific future time period, and provide suggestions for adjusting the dynamic threshold T2. Storage controller: Based on the grading results of the granularity grading module, it allocates granules of different grades to different storage task scenarios.

10. A flash memory chip screening system based on AI and multi-parameter fusion according to claim 9, characterized in that: The input features of the LSTM neural network model include: the current number of error bits, the cumulative number of erase / write cycles, the operating temperature, and the previous prediction error value. The output is the number of predicted error bits for the next 24 hours. The real-time particle monitoring data includes the number of error bits, IO response latency, and temperature change rate. The AI ​​prediction module includes a model update unit, which iteratively trains the LSTM model every quarter using newly added particle data.