A programmable logic device software power analysis apparatus and method of using the same

Abstract

This application discloses a power consumption analysis device for programmable logic devices (PLDs) and its usage method, relating to the field of PLD software verification technology. The device includes a PLD core baseboard and peripheral device boards. The PLD core baseboard includes a FLASH module, a PLD chip, a first power supply module, a JTAG interface, and a first FMC interface. The peripheral device boards include peripheral device board chips, a second power supply module, and a second FMC interface. The FLASH module includes a FLASH power supply chip and a FLASH chip. Based on the configured power consumption analysis device and a specific analysis process, this application achieves widely applicable power consumption analysis through physical testing, enriching the software testing capabilities of PLDs.

Description

Technical Field

[0001] This application relates to the field of programmable logic device software verification technology, specifically to a programmable logic device software power consumption analysis device and its usage method. Background Technology

[0002] With the development of digital electronics technology and chips, programmable logic devices are increasingly widely used in digital circuits. Power consumption analysis is one of the important test types for programmable logic device software, and commonly used test methods include design checks, gate-level simulation, and timing simulation. However, the above power consumption analyses are all deductions based on statistical data and mathematical models, which differ significantly from the actual power consumption under physical conditions. The difference is similar to the difference between computer simulation and wind tunnel testing in fluid mechanics. Obviously, the results of physical testing under real-world conditions are the most realistic and reliable.

[0003] Therefore, to address the above problems and meet practical needs, a software power consumption analysis technique for programmable logic devices is proposed. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a power consumption analysis device for programmable logic devices and a method for using the same. Based on the configured power consumption analysis device and in conjunction with a specific analysis process, power consumption analysis with broad applicability and implemented through physical testing can be achieved, thereby enriching the software testing capabilities of programmable logic devices.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a software power consumption analysis device for a programmable logic device, the device comprising a core baseboard of a programmable logic device and peripheral device boards; The core baseboard of the programmable logic device includes a FLASH module, a programmable logic device chip, a first power module, a JTAG interface, and a first FMC interface; The peripheral device board includes peripheral device board chip, second power module and second FMC interface; The FLASH module includes a FLASH power supply chip and a FLASH chip; The first power module includes a kernel power module, an I / O power module, and a BRAM power module. The kernel power module is equipped with a kernel voltage adjustment resistor, the I / O power module is equipped with an I / O voltage adjustment resistor, and the BRAM power module is equipped with a BRAM voltage adjustment resistor. The core baseboard of the programmable logic device is equipped with breakpoints 1, 2, 3, 4, 5 and 6. The programmable logic device chip is connected to the FLASH chip, the JTAG interface, and the first FMC interface; The output terminal of the kernel power module is connected to the breakpoint 4; The input terminal of the core power supply of the programmable logic device chip is connected to the breakpoint 1. The output terminal of the IO power module is connected to the breakpoint 5. The input terminal of the I / O power supply of the programmable logic device chip is connected to the breakpoint 2; The output terminal of the BRAM power module is connected to the breakpoint 6. The input terminal of the BRAM power supply of the programmable logic device chip is connected to the breakpoint 3. The first FMC interface is connected to the second FMC interface; The peripheral device board chip is connected to the second power module and the second FMC interface, respectively.

[0006] Based on the above technical solution, the peripheral device board is configured to be replaceable to simulate the peripheral device composition of the programmable logic device under test.

[0007] Based on the above technical solution, the JTAG interface is a resistor and connector used to burn and solidify the program under test into the FLASH module.

[0008] Based on the above technical solution, the FLASH module is equipped with an independent power supply chip.

[0009] Based on the above technical solution, the core voltage adjustment resistor is used to adjust the output voltage of the core power module by changing its own resistance value.

[0010] Based on the above technical solution, the IO voltage adjustment resistor is used to adjust the output voltage of the IO power module by changing its own resistance value.

[0011] Based on the above technical solution, the BRAM voltage adjustment resistor is used to adjust the output voltage of the BRAM power module by changing its own resistance value.

[0012] Secondly, this application provides a method for using the programmable logic device software power consumption analysis device mentioned in the first aspect, the method comprising the following steps: The device composition and inter-device connection method of the peripheral device board are configured to be consistent with the programmable logic device under test, thereby connecting the core baseboard of the programmable logic device and the peripheral device board. The program under test is burned and solidified into the FLASH module via the JTAG interface. Using programmable logic device chips to drive peripheral device boards and device chips to run the program under test; Select three multimeters and set them all to current measurement mode to measure the current of the kernel power module, IO power module and BRAM power module respectively. Select three multimeters and set them all to voltage measurement mode to measure the voltage of the kernel power module, IO power module and BRAM power module respectively. The total power consumption is calculated based on the operating current and operating voltage of the kernel power module, IO power module, and BRAM power module.

[0013] Based on the above technical solution, the method is configured with a total power consumption calculation formula, which is as follows: P = U1×I1 + U2×I2 + U3×I3; where... P represents total power consumption, U1 represents the operating voltage of the core power module, I1 represents the operating current of the core power module, U2 represents the operating voltage of the IO power module, I2 represents the operating current of the IO power module, U3 represents the operating current of the BRAM power module, and I3 represents the operating voltage of the BRAM power module.

[0014] Compared with the prior art, the advantages of this application are: This application, based on a configured power consumption analysis device and in conjunction with a specific analysis process, enables power consumption analysis with broad applicability and implemented through physical testing, thereby enriching the software testing capabilities of programmable logic devices. Attached Figure Description

[0015] Terminology Explanation: JTAG: Joint Test Action Group, is an international standard test protocol primarily used for internal chip testing. Most advanced devices now support the JTAG protocol, such as programmable logic devices. FMC: FPGA Mezzanine Card, is a standardized FPGA expansion interface specification developed by VITA (VMEbus International Trade Association). Its core standard number is VITA 57.1, and it is mainly used to enable rapid connection between FPGA boards and various functional expansion modules. FPGA: Field Programmable Gate Array; IO: Input / Output; BRAM: Block RAM, Block Random Access Memory.

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of a programmable logic device software power consumption analysis device according to an embodiment of this application; Figure 2 This is a structural block diagram of the core baseboard of the programmable logic device in the programmable logic device software power consumption analysis device according to an embodiment of this application; Figure 3 This is a structural block diagram of the peripheral device board in the programmable logic device software power consumption analysis device according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0020] This application provides a power consumption analysis device for programmable logic devices and a method for using the same. Based on the configured power consumption analysis device and in conjunction with a specific analysis process, power consumption analysis with wide applicability and implemented through physical testing can be achieved, thereby enriching the software testing capabilities of programmable logic devices.

[0021] To achieve the aforementioned technical effects, the overall concept of this application is as follows: A software power consumption analysis device for a programmable logic device, the device comprising a core baseboard of the programmable logic device and peripheral device boards; The core baseboard of the programmable logic device includes a FLASH module, a programmable logic device chip, a first power module, a JTAG interface, and a first FMC interface; The peripheral device board includes peripheral device board chip, second power module and second FMC interface; The FLASH module includes a FLASH power supply chip and a FLASH chip; The first power module includes a kernel power module, an I / O power module, and a BRAM power module. The kernel power module is equipped with a kernel voltage adjustment resistor, the I / O power module is equipped with an I / O voltage adjustment resistor, and the BRAM power module is equipped with a BRAM voltage adjustment resistor. The core baseboard of the programmable logic device is equipped with breakpoints 1, 2, 3, 4, 5 and 6. The programmable logic device chip is connected to the FLASH chip, the JTAG interface, and the first FMC interface; The output terminal of the kernel power module is connected to the breakpoint 4; The input terminal of the core power supply of the programmable logic device chip is connected to the breakpoint 1. The output terminal of the IO power module is connected to the breakpoint 5. The input terminal of the I / O power supply of the programmable logic device chip is connected to the breakpoint 2; The output terminal of the BRAM power module is connected to the breakpoint 6. The input terminal of the BRAM power supply of the programmable logic device chip is connected to the breakpoint 3. The first FMC interface is connected to the second FMC interface; The peripheral device board chip is connected to the second power module and the second FMC interface, respectively.

[0022] The embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0023] Firstly, see [the following] Figures 1-3 As shown, this application provides a software power consumption analysis device for a programmable logic device, which includes a core baseboard of the programmable logic device and peripheral device boards; The core baseboard of the programmable logic device includes a FLASH module, a programmable logic device chip, a first power module, a JTAG interface, and a first FMC interface; The peripheral device board includes peripheral device board chip, second power module and second FMC interface; The FLASH module includes a FLASH power supply chip and a FLASH chip; The first power module includes a kernel power module, an I / O power module, and a BRAM power module. The kernel power module is equipped with a kernel voltage adjustment resistor, the I / O power module is equipped with an I / O voltage adjustment resistor, and the BRAM power module is equipped with a BRAM voltage adjustment resistor. The core baseboard of the programmable logic device is equipped with breakpoints 1, 2, 3, 4, 5 and 6. The programmable logic device chip is connected to the FLASH chip, the JTAG interface, and the first FMC interface; The output terminal of the kernel power module is connected to the breakpoint 4; The input terminal of the core power supply of the programmable logic device chip is connected to the breakpoint 1. The output terminal of the IO power module is connected to the breakpoint 5. The input terminal of the I / O power supply of the programmable logic device chip is connected to the breakpoint 2; The output terminal of the BRAM power module is connected to the breakpoint 6. The input terminal of the BRAM power supply of the programmable logic device chip is connected to the breakpoint 3. The first FMC interface is connected to the second FMC interface; The peripheral device board chip is connected to the second power module and the second FMC interface, respectively.

[0024] In this embodiment of the application, based on the configured power consumption analysis device and in conjunction with a specific analysis process, power consumption analysis with wide applicability and implemented through physical testing is realized, which is used to enrich the software testing capabilities of programmable logic devices.

[0025] Furthermore, the peripheral device board is configured to be replaceable to simulate the peripheral device composition of the programmable logic device under test.

[0026] Furthermore, the JTAG interface consists of resistors and connectors, used to burn and solidify the program under test into the FLASH module.

[0027] Furthermore, the FLASH module is equipped with an independent power supply chip.

[0028] Furthermore, the core voltage adjustment resistor is used to adjust the output voltage of the core power module by changing its own resistance value.

[0029] Furthermore, the IO voltage adjustment resistor is used to adjust the output voltage of the IO power module by changing its own resistance value.

[0030] Furthermore, the BRAM voltage adjustment resistor is used to adjust the output voltage of the BRAM power module by changing its own resistance value.

[0031] It should be noted that, in the technical solution of this application embodiment, the core baseboard of the programmable logic device is specifically designed as follows: 1. The core baseboard of the programmable logic device includes the programmable logic device chip and the peripheral filter circuit of the programmable logic device (i.e., the voltage stabilizing capacitor configured at the power input terminal of the programmable logic device).

[0032] 2. The core baseboard includes a power supply module for the programmable logic device (PLD). This power supply module is selected for its high current output and adjustable voltage, such as the LTM4633, and its voltage adjustment resistor is also adjustable. Since common PLDs include multiple power supplies such as core power, I / O power, and BRAM power modules, multiple power supply modules are required to ensure proper power supply to the PLD. However, none of the power supply modules are directly connected to the PLD; all are connected via breakpoints (see attached diagram in the manual). Figure 2 In this setup, the core power module output is breakpoint 4, the core power input of the programmable logic device (PLD) is breakpoint 1, the IO power module output is breakpoint 5, the PLD power input of the PLD is breakpoint 2, the BRAM power module output is breakpoint 6, and the BRAM power input of the PLD is breakpoint 3. This ensures that each output power supply is disconnected from the power input of the PLD (the core baseboards of different PLD models are not the same; for example, if a certain PLD model has n voltages, the number of breakpoints is 2×n, meaning each power supply has 2 breakpoints). Simultaneously, the power supply ground needs to be reserved as a measurable point (i.e., a location convenient for voltage testing equipment such as a multimeter to measure voltage).

[0033] 3. The core baseboard is equipped with a JTAG interface. The JTAG interface is used to write programs into the programmable logic device. The actual components of the JTAG interface on the circuit board are only resistors and connectors. It is only used when writing programs and will not affect the power consumption of the programmable logic device during program execution.

[0034] 4. FLASH module: The programmable logic device's operating program needs to be stored in the FLASH module to ensure that the program can start automatically upon power-up. FLASH is a power-consuming chip, so to ensure the accuracy of the measurement data, the power supply for the FLASH module needs to be set up separately.

[0035] 5. FMC Interface: Because programmable logic devices generally have a large number of pins (IO ports), to improve the flexibility of this method and to consider reuse to reduce economic costs, the pins of programmable logic devices are connected to the FMC interface via equal-length wiring (the FMC interface connector has up to 400 IO ports). Peripheral device boards with different chips can be designed according to different project needs.

[0036] It should be noted that, in the technical solution of this application embodiment, the peripheral device board is specifically designed as follows: 1. In order to achieve the connection with the core baseboard of the programmable logic device, the peripheral device board adopts the FMC interface to realize the communication between the peripheral device and the programmable logic device. To ensure the communication quality, the chips on the peripheral device board and the FMC interface need to be wired with the same length.

[0037] 2. The components on the peripheral device board must be consistent with the actual peripheral components of the programmable logic device under test (e.g., if the function of a programmable logic device is to implement the AD7606 data acquisition function, then the components on the peripheral device board should be AD7606 chips, and the data lines, control lines, etc. of AD7606 should be connected to the programmable logic device using FMC interfaces).

[0038] 3. Power modules on peripheral device boards: To ensure more accurate power consumption analysis of programmable logic devices, the power supply for the programmable logic devices must be separated from that of the peripheral devices. The power modules on the peripheral device boards should only supply power to the peripheral devices.

[0039] Based on the technical solution of the embodiments of this application, the actual usage steps of this device are as follows: The first step involves the tester connecting the core backplane of the programmable logic device and the peripheral device boards via the FMC interface, as shown in the attached diagram in the manual. Figure 1 As shown.

[0040] The second step involves the testers setting up several multimeters in current measurement mode, and connecting the probes of multimeter 1 to breakpoints 1 and 4; connecting the probes of multimeter 2 to breakpoints 2 and 5; and connecting the probes of multimeter 3 to breakpoints 3 and 6. This enables the connection of power modules such as the core power supply, IO power supply, and BRAM power supply to the programmable logic device on the core baseboard, thereby ensuring the power supply to the programmable logic device.

[0041] The third step involves the tester burning the program under test into the FLASH module via the JTAG interface.

[0042] The fourth step involves the testers setting the remaining multimeters (several) to voltage measurement mode. They then use the multimeter probes to measure the voltage of the core power supply (i.e., the voltage between breakpoint 1 and ground), IO power supply (i.e., the voltage between breakpoint 2 and ground), and BRAM power module (i.e., the voltage between breakpoint 3 and ground) on the core backplane of the programmable logic device.

[0043] Fifth, the tester powers all the boards back on. At this time, the program under test will be automatically loaded from the FLASH module into the programmable logic device chip, and the device driver on the peripheral device board will be implemented through the FMC interface, and the program can run normally.

[0044] The sixth step is for the tester to read the voltage and current on the multimeter after the multimeter data stabilizes. This will allow them to obtain the voltage U1 and current I1 of the core power supply of the programmable logic device chip under normal operating conditions; the voltage U2 and current I2 of the IO power supply; and the voltage U3 and current I3 of the BRAM power supply.

[0045] The seventh step involves the tester calculating the power consumption of the programmable logic device chip at this point using the power formula based on the data obtained in the sixth step. The total power consumption at this point is P = U1×I1 + U2×I2 + U3×I3 (the power consumption of different models of programmable logic devices may vary. For example, if a certain model of programmable logic device has n voltages, then the total power consumption is P = U1×I1 + U2×I2 + U3×I3 + … + Un×In).

[0046] This completes the software power consumption analysis of programmable logic devices.

[0047] Based on the above technical solution, power consumption analysis and testing are performed using programmable logic device software in a physical testing environment, which has the following advantages: The testing method is based on the real-world environment and is characterized by its practicality and accurate data. The FMC interface is used to connect the programmable logic device (PLD) to peripheral devices. The peripheral devices used on the peripheral device board are consistent with those used in the actual test project, and the PLD core board uses the same PLD as the actual test project. This allows for flexible replacement of different peripheral devices or PLDs when there are changes in the device chips, which is economical. Based on a self-built physical environment, it does not rely on the test environment provided by the designer, making it more flexible and mobile for testing; The power supply module of the programmable logic device chip has an adjustable output voltage to adapt to different peripheral devices (e.g., some peripheral devices have an interface voltage of 2.5V, while others have an interface voltage of 3.3V, so the I / O port voltage of the programmable logic device needs to be adjusted; in this method, the voltage adjustment resistor of the power supply module can be adjusted).

[0048] In summary, the key technical points and technical protection points of the technical solutions in this application are as follows: Power consumption analysis and testing of programmable logic device (PLD) software were conducted using a physical testing environment. The testing methods primarily included the PLD core board, peripheral device boards, and a multimeter (a general-purpose device). The PLD core board comprises the PLD chip, PLD power supply module, FLASH module, JTAG interface, and FMC interface. The peripheral device boards comprise peripheral device chips, power supply modules, and FMC interfaces.

[0049] The FMC interface enables the connection between programmable logic device chips and peripheral devices, allowing the program to run completely.

[0050] By using a separately powered FLASH module, the power consumption of the programmable logic device can be separated from that of the FLASH, effectively ensuring the accuracy of the test data.

[0051] By using power supply modules on the peripheral device boards, the power consumption of programmable logic devices can be separated from that of peripheral devices, effectively ensuring the accuracy of test data. Through the unique breakpoint design on the core baseboard of the programmable logic device, the current during operation of the programmable logic device can be accurately measured using a multimeter, and the voltage can also be measured using a multimeter. Thus, the software power consumption of the programmable logic device can be accurately measured through the power calculation formula.

[0052] The power supply module of the programmable logic device chip has an adjustable output voltage to adapt to different peripheral devices (e.g., some peripheral devices have an interface voltage of 2.5V, while others have an interface voltage of 3.3V, so the I / O port voltage of the programmable logic device needs to be adjusted; in this method, the voltage adjustment resistor of the power supply module can be adjusted). Secondly, embodiments of this application provide a method for using the programmable logic device software power consumption analysis device mentioned in the first aspect, the method comprising the following steps; S1. The device composition and inter-device connection method of the peripheral device board are configured to be consistent with the programmable logic device under test, and then the core baseboard of the programmable logic device and the peripheral device board are connected. S2. Burn and solidify the program under test into the FLASH module via the JTAG interface; S3. Use programmable logic device chips to drive peripheral device board chips to run the program under test; S4. Select three multimeters and set them all to current measurement mode. Measure the current of the kernel power module, IO power module, and BRAM power module respectively. S5. Select three multimeters and set them all to voltage measurement mode to measure the voltage of the kernel power module, IO power module and BRAM power module respectively. S6. Calculate the total power consumption based on the operating current and operating voltage of the kernel power module, IO power module, and BRAM power module.

[0053] In this embodiment of the application, based on the configured power consumption analysis device and in conjunction with a specific analysis process, power consumption analysis with wide applicability and implemented through physical testing is realized, which is used to enrich the software testing capabilities of programmable logic devices.

[0054] Furthermore, the method is configured with a total power consumption calculation formula, which is: P = U1×I1 + U2×I2 + U3×I3; where... P represents total power consumption, U1 represents the operating voltage of the core power module, I1 represents the operating current of the core power module, U2 represents the operating voltage of the IO power module, I2 represents the operating current of the IO power module, U3 represents the operating current of the BRAM power module, and I3 represents the operating voltage of the BRAM power module.

[0055] In summary, the method of using the programmable logic device software power consumption analysis device provided in this application embodiment is the same as the programmable logic device software power consumption analysis device provided in the first aspect in terms of technical problems, technical solutions and technical effects, so it will not be described again here.

[0056] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the system or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0057] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A software power consumption analysis device for a programmable logic device, characterized in that, The device includes a programmable logic device core baseboard and peripheral device boards; The core baseboard of the programmable logic device includes a FLASH module, a programmable logic device chip, a first power module, a JTAG interface, and a first FMC interface; The peripheral device board includes peripheral device board chip, second power module and second FMC interface; The FLASH module includes a FLASH power supply chip and a FLASH chip; The first power module includes a kernel power module, an I / O power module, and a BRAM power module. The kernel power module is equipped with a kernel voltage adjustment resistor, the I / O power module is equipped with an I / O voltage adjustment resistor, and the BRAM power module is equipped with a BRAM voltage adjustment resistor. The core baseboard of the programmable logic device is equipped with breakpoints 1, 2, 3, 4, 5 and 6. The programmable logic device chip is connected to the FLASH chip, the JTAG interface, and the first FMC interface; The output terminal of the kernel power module is connected to the breakpoint 4; The input terminal of the core power supply of the programmable logic device chip is connected to the breakpoint 1. The output terminal of the IO power module is connected to the breakpoint 5. The input terminal of the I / O power supply of the programmable logic device chip is connected to the breakpoint 2; The output terminal of the BRAM power module is connected to the breakpoint 6. The input terminal of the BRAM power supply of the programmable logic device chip is connected to the breakpoint 3. The first FMC interface is connected to the second FMC interface; The peripheral device board chip is connected to the second power module and the second FMC interface, respectively.

2. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The peripheral device board is configured to be replaceable and is used to simulate the peripheral device composition of the programmable logic device under test.

3. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The JTAG interface consists of resistors and connectors, used to burn and solidify the program under test into the FLASH module.

4. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The FLASH module is equipped with an independent power supply chip.

5. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The core voltage adjustment resistor is used to adjust the output voltage of the core power module by changing its own resistance value.

6. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The IO voltage adjustment resistor is used to adjust the output voltage of the IO power module by changing its own resistance value.

7. The programmable logic device software power consumption analysis device as described in claim 1, characterized in that: The BRAM voltage adjustment resistor is used to adjust the output voltage of the BRAM power module by changing its own resistance value.

8. A method of using a programmable logic device software power consumption analysis device as described in any one of claims 1 to 7, characterized in that, The method includes the following steps; The device composition and inter-device connection method of the peripheral device board are configured to be consistent with the programmable logic device under test, thereby connecting the core baseboard of the programmable logic device and the peripheral device board. The program under test is burned and solidified into the FLASH module via the JTAG interface. Using programmable logic device chips to drive peripheral device boards and device chips to run the program under test; Select three multimeters and set them all to current measurement mode to measure the current of the kernel power module, IO power module and BRAM power module respectively. Select three multimeters and set them all to voltage measurement mode to measure the voltage of the kernel power module, IO power module and BRAM power module respectively. The total power consumption is calculated based on the operating current and operating voltage of the kernel power module, IO power module, and BRAM power module.

9. The method of using the programmable logic device software power consumption analysis device as described in claim 8, characterized in that, The method includes a total power consumption calculation formula, which is: P = U1×I1 + U2×I2 + U3×I3; where... P represents total power consumption, U1 represents the operating voltage of the core power module, I1 represents the operating current of the core power module, U2 represents the operating voltage of the IO power module, I2 represents the operating current of the IO power module, U3 represents the operating current of the BRAM power module, and I3 represents the operating voltage of the BRAM power module.

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