Address acquisition apparatus, address acquisition method, processor, and electronic device

Abstract

The present disclosure provides an address acquisition device, an address acquisition method, a processor and an electronic device. The address acquisition device comprises an address acquisition unit, a page size storage unit and a multi-level storage unit. The address acquisition unit is configured to acquire a first page size corresponding to a first virtual address in a data processing instruction from the page size storage unit, generate a first address query request according to the first virtual address and the first page size, and send the first address query request to a target storage unit in the multi-level storage unit. The target storage unit is configured to determine a first page identifier corresponding to the first address query request, determine a second page identifier corresponding to a second address query request currently performing a page table query operation, and in a case where the first page identifier and the second page identifier are the same, determine a first physical address corresponding to the first virtual address according to a page table query result corresponding to the second address query request, and send the first physical address to the address acquisition unit. According to the embodiments of the present disclosure, the query efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an address acquisition device, an address acquisition method, a processor, and an electronic device. Background Technology

[0002] With the continuous development of computer technology, computers can use storage units to store virtual addresses and corresponding physical addresses during the execution of data processing tasks, and use retrieval units to retrieve the required physical address from the storage unit when the physical address is needed.

[0003] In related technologies, when a storage unit receives multiple address retrieval requests from an acquisition unit but does not store the corresponding physical addresses, it performs a query operation for each request to obtain the physical addresses corresponding to the multiple address retrieval requests. However, multiple query operations lead to a waste of computing resources and low query efficiency. Therefore, how to improve query efficiency and save computing resources has become an urgent technical problem to be solved. Summary of the Invention

[0004] This disclosure provides an address acquisition device, an address acquisition method, a processor, and an electronic device.

[0005] In a first aspect, this disclosure provides an address acquisition device, which includes an address acquisition unit, a page-size storage unit, and a multi-level storage unit.

[0006] The address acquisition unit is configured to: upon receiving a data processing instruction, acquire a first page size corresponding to a first virtual address in the data processing instruction from the page size storage unit; generate a first address query request based on the first virtual address and the first page size and send it to the target storage unit in the multi-level storage unit.

[0007] The target storage unit is configured to: determine the first page identifier corresponding to the first address query request based on the first virtual address and the first page size when the first physical address corresponding to the first virtual address is not stored; determine the second page identifier corresponding to the second address query request currently performing a page table query operation; wait for the parent storage unit of the target storage unit to return the page table query result corresponding to the second address query request when the first page identifier and the second page identifier are the same; determine the first physical address corresponding to the first virtual address based on the page table query result, and send the first physical address to the address acquisition unit.

[0008] Secondly, this disclosure provides an address acquisition method, which includes: upon receiving a data processing instruction, acquiring a first page size corresponding to a first virtual address in the data processing instruction, and generating a first address query request based on the first virtual address and the first page size; if the first physical address corresponding to the first virtual address is not stored, determining a first page identifier corresponding to the first address query request based on the first virtual address and the first page size, and determining a second page identifier corresponding to a second address query request currently performing a page table query operation; if the first page identifier and the second page identifier are the same, waiting for the page table query result corresponding to the second address query request, and determining the first physical address corresponding to the first virtual address based on the page table query result.

[0009] Thirdly, this disclosure provides a processor that includes the address acquisition device described above.

[0010] Fourthly, this disclosure provides an electronic device that includes the processor described above.

[0011] The address acquisition device provided in this embodiment includes an address acquisition unit, a page size storage unit, and a multi-level storage unit. When the address acquisition unit receives a data processing instruction, in order to perform address lookup accurately and quickly and improve address lookup efficiency, it can obtain the first page size corresponding to the first virtual address from the page size storage unit, generate a first address lookup request based on the first virtual address and the first page size, and send it to the target storage unit in the multi-level storage unit for lookup.

[0012] The target storage unit in this multi-level storage unit accurately determines the first page identifier of the first virtual page corresponding to the first virtual address based on the first virtual address and the first page size, and determines the second page identifier corresponding to the second address query request currently performing a page table lookup operation. By comparing whether the first page identifier and the second page identifier are the same, it accurately and quickly determines whether the first address query request and the second address query request are requests for the same virtual page. If the first page identifier and the second page identifier are the same, it can be determined that the two requests are requests for the same virtual page. Therefore, the target storage unit can wait for the upper-level storage unit to return the page table lookup result corresponding to the second address query request; there is no need to perform the page table lookup operation of the first address query request, thereby avoiding the waste of computing resources.

[0013] After the page table lookup result is returned by the previous level storage unit, the first physical address corresponding to the first virtual address in the first address lookup request can also be determined based on the page table lookup result corresponding to the second address lookup request, thereby improving lookup efficiency and saving computing resources.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 This is a flowchart illustrating the handling of missing TLBs in a GPU, as provided in an embodiment of this disclosure.

[0017] Figure 2 This is a flowchart illustrating a page table translation process provided in an embodiment of the present disclosure.

[0018] Figure 3 This is a flowchart illustrating the translation process of a 64K page table, as provided in an embodiment of this disclosure.

[0019] Figure 4 A flowchart illustrating the translation process of a 2M page table provided in this embodiment of the disclosure.

[0020] Figure 5 This is a schematic diagram of the structure of a TLB provided in an embodiment of this disclosure.

[0021] Figure 6 This is a block diagram of an address acquisition device provided in an embodiment of the present disclosure.

[0022] Figure 7 This is a schematic diagram illustrating the application of an address acquisition device provided in an embodiment of this disclosure.

[0023] Figure 8 This is a flowchart of an address acquisition method provided in an embodiment of the present disclosure. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0025] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0026] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0028] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0029] The technical terms used in the embodiments of this disclosure are explained below.

[0030] TLB (Translation Lookaside Buffer): This is a high-speed cache inside the GPU used to cache recently used PTEs.

[0031] PTE (Page Table Entry): is a page table entry, specifically a row in the page table. Each row in the page table records a mapping relationship from VA to PA.

[0032] VA (Virtual Address): refers to a virtual address.

[0033] PA (Physical Address): refers to the physical address.

[0034] MMU (Memory Management Unit): This refers to the memory management unit; the MMU is a hardware module in the GPU (or CPU) specifically responsible for translating virtual addresses (VA) into physical addresses (PA). The task of the MMU is to accurately translate the "virtual address" accessed by the program into a "physical address" that the hardware can process.

[0035] The LSU (Load / Store Unit) is a component in the GPU responsible for reading (Load) and writing (Store) data. It cannot directly retrieve data from memory using virtual addresses; it must first know the physical address.

[0036] PTW (Page Table Walk): This refers to the MMU looking up the page table step by step according to the VA (e.g., L4-L3-L2-L1-L0) to finally find the PA.

[0037] Base Register: This is a special register of the CPU that stores the starting address of the highest-level page table (such as L4PT) in memory.

[0038] LLC (Last-Level Cache): It is the largest, relatively slow (but still much faster than memory) cache layer inside the CPU or GPU chip, which is closest to memory.

[0039] HBM (High Bandwidth Memory): It is a new type of video memory specifically designed for high-performance computing (such as GPUs and AI chips).

[0040] SRAM (Static Random-Access Memory): A type of semiconductor memory based on bistable flip-flops, used as internal cache for CPUs / GPUs (such as TLB).

[0041] Status (STATUS): Indicates whether this TLB record is currently available; READY: means the translation is complete, the ENTRY (i.e., a TLB record) is valid, and it can be used directly. WAIT_RESPONSE: means it is waiting for the MMU to return a result, and it is not yet available, but it may be reused in subsequent requests.

[0042] Page size: Indicates the size of the physical page corresponding to this virtual page (VPAGE); for example, if the page size = 4KB = 2¹² bytes, then the virtual page requires 12 bits to represent the offset within the page.

[0043] Virtual page number (also known as virtual page number) = virtual address ÷ page size (rounded down); for example, virtual address 0x12345, page size 4KB (=4096=0x1000), therefore virtual page number = 0x12345>>12=0x12 (i.e., the 18th virtual page).

[0044] With the continuous development of computer technology, computers can utilize storage units (such as TLB and MMU) to store virtual addresses and their corresponding physical addresses during data processing tasks. When a physical address is needed, an acquisition unit (such as LSU) retrieves the required physical address from the storage unit. In related technologies, when a storage unit receives multiple address retrieval requests from the acquisition unit and does not store the corresponding physical address, it will perform a corresponding query operation for each request to obtain the physical address corresponding to the multiple address retrieval requests. However, multiple query operations lead to a waste of computing resources and low query efficiency.

[0045] For example, in the technical field of TLB and MMU, regarding the above problem, when a preceding TLB request misses, a page table entry needs to be retrieved from the MMU. If a subsequent TLB request and the preceding request belong to the same page before the preceding request returns from the MMU, a HIT_ON_MISS occurs. In this case, the subsequent request does not need to send a request to the MMU; it only needs to wait for the preceding request to return, thus reducing the pressure on the MMU. However, in the case of HIT_ON_MISS, the storage unit may not know the virtual page sizes of the preceding and subsequent TLB requests, and therefore can only assume, using the most conservative approach, that both virtual page sizes are 4KB. In scenarios with poor address locality, the coverage is limited to 4KB, which cannot reduce HIT_ON_MISS and increases the pressure on the MMU.

[0046] Specifically Figure 1 This disclosure provides a flowchart for handling TLB missing values ​​in a GPU. In the GPU architecture, the Load Storage Unit (LSU) needs to obtain the Physical Address (PA) corresponding to the Virtual Address (VA) with the help of the TLB and the Memory Management Unit (MMU) before it can access memory. The MMU is responsible for converting the VA to the PA, and the TLB caches the conversion result. A hierarchical structure of a GPU architecture is shown below. Figure 1As shown, the GPU_CORE (GPU core) can include the SM, LSU, TLB, and MMU; specifically, the GPU core includes smaller and faster TLB_L1, larger and slower TLB_L2, and the MMU. When a TLB_L1 miss occurs, it initiates a lookup request to TLB_L2. If TLB_L2 hits, it directly returns the translation result. If TLB_L2 also misses, it needs to initiate a request to the downstream MMU. The MMU performs a Page Table Walk (PTW) through LLC and HBM to obtain the Page Table Entry (PTE), thereby translating the VA into a Page Appearance (PA). The MMU then returns the PTE. After receiving the PTE, TLB_L2 refills its internal cache and then returns the PTE to TLB_L1. After receiving the PTE, TLB_L1 refills its internal SRAM and then returns the PA from the PTE to the LSU. The LSU can then use the PA to access memory.

[0047] Figure 2 A flowchart illustrating a page table translation process provided in this disclosure embodiment; based on Figure 2 It is known that during the MMU's PTW (page table translation or page table traversal) process, the Base Register provides the base address of L4PT (Level 4 Page Table), and page tables such as L4PTE (Level 4 Page Table Entry), L3PTE (Level 3 Page Table Entry), L2PTE (Level 2 Page Table Entry), and L1PTE (Level 1 Page Table Entry) provide the base addresses of the next level L3PT (Level 3 Page Table), L2PT (Level 2 Page Table), L1PT (Level 1 Page Table), and L0PT (Level 0 Page Table). L0PTE (Level 0 Page Table Entry) provides the base address (PPAGE_BITS) of the Physical Page. Based on this base address and the Physical Page Offset, the PA (Parent Page) within the physical page can be accessed.

[0048] VPN[4] / VPN[3] / VPN[2] / VPN[1] / VPN[0] are used to index L4PTE / L3PTE / L2PTE / L1PTE / L0PTE respectively. Among them, L2PTE(2m_flag=0) and L1PTE(64K_flag=0) indicate that the page size of the virtual page of all L0PTEs in L0PT is 4K ( Figure 2 The L0PT in the middle has 512 L0PTEs.

[0049] Figure 3 A flowchart illustrating the translation process of a 64K page table is provided for embodiments of this disclosure; the translation process for a 64K page table is as follows: Figure 3 As shown. Based on Figure 3 It can be seen that L2PTE(2m_flag=0) and L1PTE(64K_flag=1) indicate that the page size of the virtual pages of all L0PTEs in L0PT is 64K (in Figure 3 The LOPTE shown in the figure has 128 LOPTEs.

[0050] Figure 4 A flowchart illustrating the translation process of a 2M page table is provided for embodiments of this disclosure; the translation process for a 2M page table is as follows: Figure 4 As shown. Based on Figure 4 It can be seen that, in the case of L2PTE(2m_flag=1), the base address of the Physical Page is provided by L1PTE. Furthermore, L2PTE(2m_flag=1) and L1PTE(64K_flag=0) indicate that the page size of the virtual pages of all L1PTEs in L1PT is 2M (in... Figure 4 The diagram shows that L1PT has 512 L1PTEs.

[0051] Figure 5 This is a schematic diagram of the structure of a TLB provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the TLB can interact with the LSU. During the TLB hit check, the TLB can include TAG_SRAM (SRAM for storing TAGs) and ENTRY_SRAM (SRAM for storing Page Table Entry). The Page Table Entry included in ENTRY_SRAM refers to the address information of the physical page corresponding to the virtual address. Through this Page Table Entry, the LSU can query the physical address corresponding to the virtual address when needed; therefore, this Page Table Entry can also be understood as a Page Table Entry.

[0052] The TAG in TAG_SRAM can consist of VPAGE, STATUS, and SIZE. VPAGE in TAG_SRAM represents the virtual page address aligned to 4K; STATUS represents status bits (e.g., READY indicates the ENTRY has been retrieved from the MMU, WAIT_RESPONSE indicates waiting for the MMU to return); and SIZE represents the page size of the virtual page. When the TLB receives a translation request, it matches the VPAGE of the translation request with each VPAGE in the TAG, using the calculation method described in Formula 1 below.

[0053] Formula 1.

[0054] Here, >> indicates a right shift, REQ.VPAGE represents the VPAGE of the translation request, and TAG.VPAGE is the VPAGE in TAG_SRAM; GET_OFFSET() is a function used to calculate the address offset relative to 4K pages. If TAG.SIZE (i.e., SIZE in TAG_SRAM) is 4K, then the OFFSET result is 0. If TAG.SIZE is 64K, then the OFFSET result is 2. If TAG.SIZE is 2M, then the OFFSET result is 9.

[0055] If HIT equals 0 (i.e., a miss), the request needs to be sent to the MMU (this is called a MISS). If HIT equals 1 (i.e., a hit), the request can use the data from ENTRY_SRAM (when STATUS is READYS, this is called TRUE_HIT). Alternatively, it can wait for the MMU to return before using the data from ENTRY_SRAM (when STATUS is WAIT_RESPONSE, this is called HIT_ON_MISS). There is a significant performance issue here: requests in the TAG before the MMU returns cannot know the page size and can only perform HIT checks based on 4K page sizes. For 4K and 64K virtual pages, this puts greater pressure on the downstream MMU.

[0056] Based on this, the present disclosure provides an address acquisition device, an address acquisition method, a processor, and an electronic device, as detailed in the following embodiments.

[0057] Figure 6 This is a block diagram of an address acquisition device provided in an embodiment of the present disclosure. (Refer to...) Figure 6 The address acquisition device includes an address acquisition unit 61, a page-size storage unit 62, and a multi-level storage unit 63.

[0058] In this embodiment, the address acquisition unit 61 can be understood as a unit for acquiring physical addresses from the multi-level storage unit 63; for example, the address acquisition unit 61 may be an LSU. The page size storage unit 62 can be understood as a unit for storing page sizes; the page size storage unit 62 may be a cache in the address acquisition device; for example, the page size storage unit 62 may be a PAGE_SIZE_CACHE (PSC). In some embodiments, there may be multiple address acquisition units 61 in the address acquisition device, and one page size storage unit 62; multiple address acquisition units 61 acquire page sizes from the page size storage unit 62. In some embodiments, there may be multiple address acquisition units 61 in the address acquisition device, and multiple page size storage units 62; one page size storage unit 62 may correspond to one or at least two address acquisition units 61, and is used to provide page sizes to the one or at least two address acquisition units 61.

[0059] The multi-level storage unit 63 may include multiple storage units at different levels, with at least one storage unit in each level. The target storage unit may be one of the storage units in the multi-level storage unit 63. The target storage unit may determine the first physical address corresponding to the first address query request and send the first physical address to the address acquisition unit 61 directly or indirectly. A direct method refers to returning the first physical address to the address acquisition unit 61 when the target storage unit is directly connected to the address acquisition unit 61. An indirect method refers to using other storage units between the target storage unit and the address acquisition unit 61 to return the first physical address to the address acquisition unit 61. For example, the multi-level storage unit 63 may be an MMU and a multi-level TLB.

[0060] The address acquisition unit 61 is configured to: upon receiving a data processing instruction, acquire a first page size corresponding to the first virtual address in the data processing instruction from the page size storage unit 62; generate a first address query request based on the first virtual address and the first page size and send it to the target storage unit in the multi-level storage unit 63.

[0061] The data processing instructions can be set according to the actual application scenario. For example, the data processing instructions can be data deletion instructions, data update instructions, data read instructions, data write instructions, etc.

[0062] An address lookup request can be understood as a request to obtain the physical address corresponding to a virtual address from the multi-level storage unit 63.

[0063] The target storage unit is configured to: determine the first page identifier corresponding to the first address query request based on the first virtual address and the first page size when the first physical address corresponding to the first virtual address is not stored; determine the second page identifier corresponding to the second address query request currently performing a page table query operation; wait for the parent storage unit of the target storage unit to return the page table query result corresponding to the second address query request when the first page identifier and the second page identifier are the same; determine the first physical address corresponding to the first virtual address based on the page table query result, and send the first physical address to the address acquisition unit 61.

[0064] The page table query result can be understood as the result obtained by performing a page table query operation. For example, the page table query result can be the physical address corresponding to the virtual address, or the page table query result can be the page table or a page table entry in the page table.

[0065] A page identifier can be understood as an identifier for a page table. For example, the page identifier can be a virtual page number (VPAGE), a virtual page name, a virtual page ID, etc.

[0066] Taking the application of the address acquisition device provided in this disclosure in the HIT_ON_MISS scenario as an example, the address acquisition device will be described. The address acquisition device can be a GPU core; the address acquisition unit 61 is an LSU; the target storage unit can be a TLB; and the page size storage unit 62 can be a PAGE_SIZE_CACHE (PSC).

[0067] Based on this, when the LSU receives a data processing instruction from the SM, it needs to access the TLB according to the virtual address (i.e., the first virtual address) in the data processing instruction and obtain the corresponding physical address (i.e., the first physical address) from the TLB. This disclosure sets up a PAGE_SIZE_CACHE (PSC) between the LSU and the TLB. Before accessing the TLB, the LSU needs to access the PSC to obtain the page size (i.e., the first page size) corresponding to the virtual address; it then generates an address lookup request (i.e., the first address lookup request) based on the page size corresponding to the virtual address and sends it to the LSU.

[0068] After receiving an address query request, if the TLB determines that the first physical address corresponding to the first virtual address is not stored in its local cache, it needs to request the corresponding first physical address from the next higher-level TLB. During this process, it needs to determine whether a HIT_ON_MISS has occurred. Specifically, this determination involves: calculating the first virtual page number (i.e., the first page identifier) ​​corresponding to the first address query request based on the first virtual address and the first page size; and determining the second virtual page number (i.e., the second page identifier) ​​corresponding to the second address query request currently performing a page table lookup operation.

[0069] It should be noted that, according to Figure 5 As can be seen, the TAG_SRAM includes a STATUS bit (e.g., READY indicates that the ENTRY has been retrieved from the MMU, and WAIT_RESPONSE indicates waiting for the MMU to return). Based on this, when the status bit corresponding to an address query request is "WAIT_RESPONSE", it is identified as the second address query request currently performing a page table query operation. In other words, this disclosure can determine the second address query request currently performing a page table query operation based on the status bit.

[0070] If the first virtual page number and the second virtual page number are the same, it can be determined that the first address query request and the second address query request are requests for the same virtual page; therefore, the TLB can wait for the PTE information (i.e., page table query result) returned by the parent TLB.

[0071] The first physical address corresponding to the first virtual address is calculated based on the PTE information, and the first physical address is sent to the LSU.

[0072] As can be seen from the above embodiments, this disclosure adds a pagesize_cache before TLB access to record the page size (i.e., page size) of each VPAGE (virtual page), so that preceding TLB requests and subsequent TLB requests can determine HIT_ON_MISS according to the real page size, thereby minimizing the pressure on MMU access.

[0073] In some embodiments, the target storage unit is further configured to: obtain the first virtual address and the first page size from the received first address query request; extract the first page identifier to be processed from the first virtual address, and obtain a first displacement parameter of the first page identifier to be processed based on the first page size; and shift the first page identifier to be processed based on the first displacement parameter to obtain the first page identifier.

[0074] The page identifier to be processed can be understood as the default page identifier carried in the first virtual address; for example, the page identifier to be processed can be the virtual page number in the virtual address, and the virtual page number can be binary encoded.

[0075] The first displacement parameter can be understood as a parameter for displacing the first page identifier to be processed. For example, the first displacement parameter can be OFFSET, which can be 0, 9, etc.

[0076] The displacement can be set according to the actual application scenario; for example, the displacement can be a leftward or rightward shift.

[0077] Following the previous example, in the process of comparing the virtual page numbers requested by the two addresses, it is necessary to calculate the first displacement parameter based on the first page size (REQ.SIZE), and then, based on the first displacement parameter, to shift the default page identifier (REQ.VPAGE) extracted from the first virtual address, thereby obtaining the processed page identifier.

[0078] As can be seen from the above embodiments, this disclosure achieves a unified approach to memory pages of different sizes, facilitating rapid subsequent comparisons, thereby enabling efficient and flexible determination of virtual pages at address ownership.

[0079] In some embodiments, the first displacement parameter includes a first right shift bit; the target storage unit is further configured to: determine the size of a third page in local storage; if the third page size is greater than or equal to the first page size, determine the third page size as the target page size; if the first page size is greater than the third page size, determine the first page size as the target page size; based on the target page size, obtain the first right shift bit corresponding to the first page identifier to be processed; and right-shift the first page identifier to be processed based on the first right shift bit to obtain the first page identifier.

[0080] The third page size can be understood as the page size of the local storage of the target storage unit; for example, when the target storage unit is a TLB, based on Figure 5 It can be seen that the TAG_SRAM in the TLB stores the page size (SIZE), which can be the size of the third page.

[0081] Continuing with the previous example, during the process of an LSU accessing the TLB, the LSU can use REQ.VPAGE (the default virtual page number) and REQ.SIZE (the page size) to access the TLB. That is, after obtaining REQ.SIZE from the PSC, the LSU can generate an address lookup request based on REQ.VPAGE (the default virtual page number contained in the virtual address) and REQ.SIZE, and send the address lookup request to the TLB.

[0082] After receiving an address query request, the TLB will obtain the default REQ.VPAGE and REQ.SIZE from the virtual address. Meanwhile, considering that the PSC may not be updated in a timely manner, when the TLB performs a HIT check, whether to use REQ.SIZE or TAG.SIZE depends on the size relationship between the two, which is determined according to the following formula 2.

[0083] SEL.SIZE = MAX(TAG.SIZE ≥ REQ.SIZE) Formula 2.

[0084] MAX(TAG.SIZE ≥ REQ.SIZE) means that if TAG.SIZE is greater than or equal to REQ.SIZE, then TAG.SIZE is used; otherwise, if TAG.SIZE is less than REQ.SIZE, then REQ.SIZE is used.

[0085] After obtaining SEL.SIZE, the first right shift bit (GET_OFFSET) corresponding to REQ.VPAGE is calculated based on the formula "REQ.VPAGE>>GET_OFFSET(SEL.SIZE)". Here, PSC_GET_OFFSET can be understood as a function that, given an input SEL.SIZE (e.g., 64K, 2M), outputs the number of right shift bits (including but not limited to 0, 2, 9).

[0086] The REQ.VPAGE is right-shifted based on the first right shift bit to obtain the right-shifted REQ.VPAGE (i.e., the first page identifier).

[0087] It should be noted that `REQ.VPAGE >> GET_OFFSET` means shifting the binary representation of `REQ.VPAGE` to the right by `GET_OFFSET` bits (e.g., 0, 2, 9). Its effect is equivalent to integer division, i.e., `REQ.VPAGE ÷ 2_GET_OFFSET`.

[0088] The purpose of the right-shift operation in this disclosure is that, since virtual pages (VPAGE) of different sizes have different "granularity", the right-shift operation can "align" the VPAGE to the actual page size before comparison; ignore the finer numerical division of the VPAGE, and only look at whether the starting numbers of the larger pages are the same; thus, the comparison can be performed efficiently.

[0089] As can be seen from the above embodiments, by adopting the strategy of "taking the largest granularity first" (SEL.SIZE = MAX(TAG.SIZE,REQ.SIZE)) and shifting operations, the problem of inconsistent page size information between PSC and TLB is solved, ensuring that the TLB query request issued by LSU can obtain the correct HIT_ON_MISS judgment even if the PSC information is inaccurate, which significantly improves the effective utilization and hit rate of TLB.

[0090] In some embodiments, the target storage unit is further configured to: obtain a second virtual address from the second address query request currently performing a page table query operation; extract a second page identifier to be processed from the second virtual address, and obtain a second displacement parameter of the second page identifier to be processed based on the first page size; and shift the second page identifier to be processed based on the second displacement parameter to obtain the second page identifier.

[0091] The second displacement parameter can be understood as a parameter for displacing the second page identifier to be processed. For example, the second displacement parameter can be OFFSET, which can be 0, 2, 9, etc.

[0092] Following the previous example, in the process of comparing the virtual page numbers of the two address retrieval requests, for the preceding request (i.e. the second address retrieval request), it is necessary to calculate the second displacement parameter based on the first page size (REQ.SIZE), and then, based on the second displacement parameter, to shift the default page identifier (REQ.VPAGE) extracted from the second virtual address, thereby obtaining the processed page identifier.

[0093] As can be seen from the above embodiments, this disclosure achieves a unified approach to virtual pages of different sizes, facilitating rapid subsequent comparisons, thereby enabling efficient and flexible determination of the virtual page's address attribution.

[0094] In some embodiments, the second displacement parameter includes a second right shift bit; the target storage unit is further configured to: determine the size of a third page in local storage; if the third page size is greater than or equal to the first page size, determine the third page size as the target page size; if the first page size is greater than the third page size, determine the first page size as the target page size; based on the target page size, obtain the second right shift bit corresponding to the second page identifier to be processed; and right-shift the second page identifier to be processed based on the second right shift bit to obtain the second page identifier.

[0095] Following the previous example, this TLB also needs to obtain the default REQ.VPAGE from the virtual address of the preceding request for the preceding request. At the same time, considering that the PSC may not be updated in time, when the TLB performs the HIT check, whether to use REQ.SIZE or TAG.SIZE depends on the size relationship between the two, which is determined according to Formula 2 above.

[0096] After obtaining SEL.SIZE, the second right shift bit (right shift number) corresponding to TAG.VPAGE is calculated based on the formula "TAG.VPAGE>>GET_OFFSET(SEL.SIZE)". Here, PSC_GET_OFFSET can be understood as a function that, by taking SEL.SIZE (e.g., 64K, 2M) as input, outputs the right shift number (including but not limited to 0, 2, 9).

[0097] The TAG.VPAGE is right-shifted based on the second right shift bit to obtain the right-shifted TAG.VPAGE (i.e., the second page identifier).

[0098] As can be seen from the above embodiments, the "largest granularity priority" strategy (SEL.SIZE = MAX(TAG.SIZE,REQ.SIZE)) and shift operations solve the problem of inconsistent page size information between PSC and TLB, ensuring that TLB query requests issued by LSU can obtain correct HIT_ON_MISS judgments even when PSC information is inaccurate, significantly improving the effective utilization and hit rate of TLB. For example, the TLB HIT can be calculated using the following formula 3.

[0099] HIT=REQ.VPAGE>>GET_OFFSET(SEL.SIZE)==TAG.VPAGE>>GET_OFFSET(SEL.SIZE) Formula 3.

[0100] In some embodiments, the page size storage unit is configured to: upon receiving a size acquisition request sent by the address acquisition unit, extract a first page identifier to be processed from the first virtual address carried in the size acquisition request; determine a candidate page identifier corresponding to the first page identifier to be processed from a plurality of currently stored page identifiers, wherein the candidate page identifier is any one of the plurality of currently stored page identifiers; if it is determined that the first page identifier to be processed matches the candidate page identifier, determine the candidate page size corresponding to the candidate page identifier as the first page size corresponding to the first virtual address, and send the first page size to the address acquisition unit.

[0101] Using the previous example, before the LSU sends an address retrieval request to the TLB, it needs to access the PSC first. The PSC can query the page size corresponding to the virtual address and return it to the LSU. The specific method for querying the page size is as follows.

[0102] 1. Extract the page identifier (REQ.VPAGE) from the first virtual address.

[0103] 2. Compare the virtual page number (REQ.VPAGE) with the locally cached virtual page number (PSC.VPAGE).

[0104] 3. If a match is found, the page size (PSC.SIZE, e.g., 64K) corresponding to the virtual page number (PSC.VPAGE) is determined as the selected page size and sent to the LSU.

[0105] As can be seen from the above embodiments, this disclosure introduces a page size cache (PSC) to quickly predict the page size before TLB queries, effectively improving address translation efficiency and system performance in huge page scenarios with minimal hardware overhead. This allows TLB queries to directly use the correct page granularity for matching, eliminating the need to try multiple page sizes or fall back to slow page table traversal, significantly reducing memory access latency, especially in huge page scenarios.

[0106] In some embodiments, the page size storage unit is further configured to: obtain a third right shift bit of the first page identifier to be processed based on the candidate page size, and perform a right shift operation on the first page identifier to be processed using the third right shift bit to obtain a third page identifier; obtain a fourth right shift bit of the candidate page identifier based on the candidate page size, and perform a right shift operation on the candidate page identifier using the fourth right shift bit to obtain a fourth page identifier; and determine that the first page identifier to be processed matches the candidate page identifier if the third page identifier and the fourth page identifier are the same.

[0107] Following the previous example, this disclosure employs two design approaches in providing page size information to the LSU: 1. Since 4k_flag is stored in the L1PTE, if a PTE is 64K, then within a 2M range, all PTEs are 64K. 2. Since 2m_flag is stored in the L2PTE, if a PTE is 2M, then within a 512M range, all PTEs are 2M.

[0108] Based on this, this disclosure inserts PAGE_SIZE_CACHE (PSC) between LSU and TLB. LSU needs to access PSC before accessing TLB. Each cache line of PSC contains the following information: 1. V indicates valid, 2. VPAGE is the virtual page address aligned to 2M, and 3. SIZE indicates the page size (since 4K virtual pages will not be stored in PSC, SIZE will not be 4K).

[0109] During the process of LSU accessing PSC, LSU sends a size acquisition request to PSC. After receiving the size acquisition request, PSC extracts REQ.VPAGE from the virtual address carried in the address acquisition request and determines whether it is HIT using the following formula 4.

[0110] Formula 4.

[0111] Where PSC.SIZE is the page size (i.e., candidate page size) cached in the PSC, and PSC.VPAGE is the virtual page number cached in the PSC.

[0112] If the two virtual page numbers after the right shift (i.e., >>) are the same (i.e., the first pending page identifier and the candidate page identifier), then a hit can be determined. If the hit is true, then REQ.SIZE = PSC.SIZE, and this PSC.SIZE is returned to the LSU.

[0113] As can be seen from the above embodiments, this disclosure can hit the target address by determining that the address falls within the 2M (or larger) alignment area of ​​the large page recorded by the PSC, thus avoiding missed detections caused by excessively high VPAGE precision; it also avoids trying multiple granularities or triggering unnecessary full page table traversal (Page Walk) due to unknown page size, thus significantly improving memory system efficiency.

[0114] In some embodiments, the page size storage unit is further configured to: send a size query failure notification to the address acquisition unit when it is determined that the first page identifier to be processed is different from the candidate page identifier; the address acquisition unit is further configured to: determine the locally stored preset page size as the first page size corresponding to the first virtual address when it receives the size query failure notification.

[0115] The dimension query failure notification can be understood as a notification that the dimension query failed. The dimension query failure notification can be an electrical signal or an instruction.

[0116] Continuing with the previous example, if HIT is true, then REQ.SIZE = PSC.SIZE, and PSC.SIZE is returned; otherwise, a failure notification is returned. The LSU queries the failure notification based on the size and selects the default page size of local storage (e.g., 4K) as the page size for accessing the TLB. That is, REQ.SIZE = HIT ? PSC.SIZE : 4K.

[0117] As can be seen from the above embodiments, this disclosure achieves both the performance benefits of big pages and the compatibility guarantee of small pages by using the mechanism of "using big pages when PSC is hit and safely falling back to the default small pages when it is not hit" without increasing hardware overhead. Even if the PSC has not cached the page size, the system can still work correctly and is fully backward compatible with the traditional memory management model.

[0118] In some embodiments, the target storage unit is further configured to: send the page identifier and the page size in the page table query result to the page size storage unit when the page size in the page table query result is greater than a preset size threshold; the page size storage unit is further configured to: store the page size and the page identifier in the page table query result.

[0119] Continuing with the previous example, after the TLB receives the PTE information returned by the MMU, it determines whether the PTE is a large page. If the page size carried in the PTE information is greater than a preset threshold (such as 4K), it determines whether the PTE is a large page. If it is a large page, then the page size and virtual page number in the PTE information are passed (updated) to the PSC for storage.

[0120] As can be seen from the above embodiments, this disclosure enables PSC to automatically, accurately, and efficiently cache big page information, providing fast page size hints for subsequent memory accesses, thereby significantly improving address translation performance and system throughput in big page scenarios without increasing significant hardware complexity.

[0121] In some embodiments, the page size storage unit is further configured to: determine the page size and the page identifier in the page table query result as the page size and the page identifier to be stored; determine, from a plurality of currently stored page identifiers, a verification page identifier corresponding to the page size to be stored, and a verification page size corresponding to the verification page identifier, wherein the verification page identifier is any one of the plurality of currently stored page identifiers; if the page identifier to be stored does not match the verification page identifier and the page size to be stored is different from the verification page size, store the page size to be stored and the page identifier to be stored; if the page identifier to be stored matches the verification page identifier and the page size to be stored is different from the verification page size, delete the verification page identifier and the verification page size, and store the page size to be stored and the page identifier to be stored.

[0122] Continuing with the previous example, during the TLB update of the PSC, after receiving the PTE information returned by the MMU, the TLB determines whether the PTE is a large page. If it is a large page, it passes the page table information to the PSC. After receiving this information, the PSC needs to perform a HIT test.

[0123] If the signal is hit, discard the UPDATE signal; otherwise, store the UPDATE signal in the PSC. Only 2M alignment is needed during storage, i.e.: PSC.VPAGE = UPDATE.VPAGE >> 9; PSC.SIZE = UPDATE.SIZE.

[0124] In other words, after receiving the information, the PSC needs to perform a HIT test: if HIT (i.e., the page identifier matches and the page size matches), it means that the same information has been stored, so the UPDATE signal is discarded; if the page identifier does not match and the page size does not match, the UPDATE is stored in the PSC; if the page identifier matches and the page size does not match, the UPDATE is stored in the PSC and the error message is deleted.

[0125] As can be seen from the above embodiments, this disclosure only writes when a new entry actually provides new information (different VPAGE or updated SIZE). This avoids duplicate or conflicting entries occupying limited PSC capacity and improves the effective hit rate, which is especially important in small-core or embedded scenarios where PSC capacity is limited.

[0126] In some embodiments, the page size storage unit is further configured to: obtain a fifth right-shifted bit of the page identifier to be stored based on the page size to be stored, and perform a right-shifting operation on the page identifier to be stored using the fifth right-shifted bit to obtain a fifth page identifier; obtain a sixth right-shifted bit of the verification page identifier based on the verification page size, and perform a right-shifting operation on the verification page identifier using the sixth right-shifted bit to obtain a sixth page identifier; determine that the page identifier to be stored matches the verification page identifier if the fifth page identifier and the sixth page identifier are the same; and determine that the page identifier to be stored does not match the verification page identifier if the fifth page identifier and the sixth page identifier are different.

[0127] Following the previous example, after receiving the page size and virtual page number from the PTE information, the PSC needs to perform a HIT test using the following formula 5.

[0128] Formula 5.

[0129] PSC_GET_OFFSET is used to calculate the range represented by PSC.SIZE. If PSC.SIZE is 64K, then the result of PSC_GET_OFFSET is 0 (pages within the 2M range are all 64K, and PSC.VPAGE is already aligned to 2M, so it only needs to be shifted right by 0 bits). If PSC.SIZE is 2M, then the result of PSC_GET_OFFSET is 9 (pages within the 1G range are all 2M).

[0130] If HIT occurs, the UPDATE signal is discarded; otherwise, the UPDATE signal is stored in PSC. Only 2M alignment is needed during storage: PSC.VPAGE = UPDATE.VPAGE >> 9; PSC.SIZE = UPDATE.SIZE.

[0131] As can be seen from the above embodiments, the PSC disclosed herein only needs to store the high-order address bits (the low-order 9 bits are implicitly 0), reducing the bit width of each entry. With a limited number of cache entries, a larger virtual address space can be covered, which is especially beneficial for sparse big-page applications.

[0132] In some embodiments, the address acquisition device further includes a data storage unit; the address acquisition unit is further configured to:

[0133] Based on the first physical address, access the first storage location in the data storage unit, and execute the data processing operation corresponding to the data processing instruction for the first storage location, wherein the first physical address corresponds to the first storage location.

[0134] The data storage unit can be understood as a unit used to store data, and the data storage unit can be memory or video memory; the first storage location can be the storage location in the data storage unit corresponding to the first physical address.

[0135] Following the previous example, after obtaining the first physical address, the LSU determines the corresponding first storage location from memory based on the first physical address, and performs operations such as data deletion, data update, data reading, and data writing for the first storage location; ensuring the stability and reliability of data processing.

[0136] The address acquisition device provided in this embodiment includes an address acquisition unit, a page size storage unit, and a multi-level storage unit. When the address acquisition unit receives a data processing instruction, in order to perform address lookup accurately and quickly and improve address lookup efficiency, it can obtain the first page size corresponding to the first virtual address from the page size storage unit, generate a first address lookup request based on the first virtual address and the first page size, and send it to the target storage unit in the multi-level storage unit for lookup.

[0137] The target storage unit in this multi-level storage unit accurately determines the first page identifier of the first virtual page corresponding to the first virtual address based on the first virtual address and the first page size, and determines the second page identifier corresponding to the second address query request currently performing a page table lookup operation. By comparing whether the first page identifier and the second page identifier are the same, it accurately and quickly determines whether the first address query request and the second address query request are requests for the same virtual page. If the first page identifier and the second page identifier are the same, it can be determined that the two requests are requests for the same virtual page. Therefore, the target storage unit can wait for the upper-level storage unit to return the page table lookup result corresponding to the second address query request; there is no need to perform the page table lookup operation of the first address query request, thereby avoiding the waste of computing resources.

[0138] After the page table lookup result is returned by the previous level storage unit, the first physical address corresponding to the first virtual address in the first address lookup request can also be determined based on the page table lookup result corresponding to the second address lookup request, thereby improving lookup efficiency and saving computing resources.

[0139] Taking the application of the address acquisition device provided in this disclosure in the HIT_ON_MISS scenario as an example, the address acquisition device is described. The address acquisition device can be a GPU core, the address acquisition unit is an LSU, the target storage unit can be a TLB, and the page size storage unit can be a PAGE_SIZE_CACHE (PSC). Figure 7 This is an application diagram of an address acquisition device provided in an embodiment of the present disclosure, based on... Figure 7As can be seen, this disclosure inserts PAGE_SIZE_CACHE (PSC) between LSU and TLB. LSU needs to access PSC before accessing TLB. Each cache line of PSC contains the following information: 1. V indicates valid; 2. VPAGE is the virtual page address aligned to 2M; 3. SIZE indicates the page size of the virtual page (since 4K pages will not be stored in PSC, SIZE will not be 4K).

[0140] The address acquisition device disclosed herein mainly includes three steps.

[0141] Step 1: Update PSC via TLB.

[0142] After receiving the Page Entrance (PTE) information returned by the MMU, the TLB determines whether the PTE is a large page. If the page size carried in the PTE information is greater than a preset threshold (e.g., 4K), the TLB determines whether the PTE is a large page. If it is a large page, the page size and virtual page number in the PTE information are updated and passed to the PSC for storage.

[0143] After receiving the page size and virtual page number, the PSC needs to perform a HIT test. For details on the HIT test method, please refer to Formula 5.

[0144] If HIT occurs, the UPDATE signal is discarded; otherwise, the UPDATE signal is stored in PSC. Only 2M alignment is needed during storage: PSC.VPAGE = UPDATE.VPAGE >> 9; PSC.SIZE = UPDATE.SIZE.

[0145] In other words, after receiving the information, the PSC needs to perform a HIT test: if HIT (i.e., the page identifier matches and the page size matches), it means that the same information has been stored, so the UPDATE signal is discarded; if the page identifier does not match and the page size does not match, the UPDATE is stored in the PSC; if the page identifier matches and the page size does not match, the UPDATE is stored in the PSC and the error message is deleted.

[0146] Step 2: LSU accesses PSC.

[0147] During the process of LSU accessing PSC, LSU sends a size acquisition request to PSC. After receiving the size acquisition request, PSC extracts REQ.VPAGE from the virtual address carried in the address acquisition request and determines whether it is HIT using Formula 4.

[0148] If the two virtual page numbers after the right shift (i.e., >>) are the same, then a hit can be determined. If the hit is true, then REQ.SIZE = PSC.SIZE, and this PSC.SIZE is returned to the LSU. Otherwise, a failure notification is returned; the LSU queries the failure notification based on the size and selects the default page size of the local storage (e.g., 4K) as the page size for accessing the TLB.

[0149] Step 3: LSU accesses TLB.

[0150] After obtaining REQ.SIZE from PSC, the LSU can generate an address lookup request based on REQ.VPAGE (the default virtual page number contained in the virtual address) and REQ.SIZE, and send the address lookup request to TLB.

[0151] After receiving an address query request, the TLB will obtain the default REQ.VPAGE and REQ.SIZE from the virtual address. Meanwhile, considering that the PSC may not be updated in a timely manner, when the TLB performs a HIT check, whether to use REQ.SIZE or TAG.SIZE depends on the size relationship between the two, which is determined according to Formula 2.

[0152] After obtaining SEL.SIZE, the HIT of TLB is determined by Equation 3.

[0153] Specifically, it is necessary to extract the default page identifier (REQ.VPAGE) from the virtual address, and to determine the default page identifier (TAG.VPAGE) in the preceding request.

[0154] Based on "REQ.VPAGE>>GET_OFFSET(SEL.SIZE)", the right shift bit (GET_OFFSET) corresponding to REQ.VPAGE is calculated. The REQ.VPAGE is then right-shifted according to this right shift bit to obtain the right-shifted REQ.VPAGE.

[0155] It should be noted that `REQ.VPAGE >> GET_OFFSET` means shifting the binary representation of `REQ.VPAGE` to the right by `GET_OFFSET` binary bits (e.g., 0, 2, 9). Its effect is equivalent to integer division, that is: `REQ.VPAGE ÷ 2_GET_OFFSET`.

[0156] This disclosure calculates the right shift bits corresponding to the TAG.VPAGE based on "TAG.VPAGE>>GET_OFFSET(SEL.SIZE)". The TAG.VPAGE is then right-shifted according to these right shift bits to obtain the right-shifted TAG.VPAGE (i.e., the second page identifier).

[0157] If the right-shifted REQ.VPAGE and the right-shifted TAG.VPAGE are the same, then HIT is determined. That is, HIT_ON_MISS has occurred. At this time, subsequent address acquisition requests do not need to send a request to the MMU. They only need to wait for the PTE returned by the previous request to obtain the corresponding physical address.

[0158] Based on the above steps, it can be seen that the address acquisition device of this disclosure provides a method to improve the HIT_ON_MISS rate of TLB; this disclosure adds a PSC hardware unit to the address acquisition device (that is, inserts a new cache structure - page size cache (PSC) between LSU and TLB, which is specifically used to store the size information of large pages).

[0159] The PSC update mechanism enables the TLB to proactively and asynchronously update the PSC upon receiving a large-page PTE from the MMU. Range-based deduplication logic is used during the update to ensure the validity of the PSC content.

[0160] The PSC query mechanism allows the LSU to query the PSC before initiating a TLB request, and dynamically append a predicted page size (REQ.SIZE) to the request using the information provided by the PSC.

[0161] By enhancing the TLB hit-checking logic, the TLB, upon receiving a request with a predicted page size, adopts a "take the larger value" strategy (SEL.SIZE = MAX(TAG.SIZE, REQ.SIZE)) to determine the address alignment range for the hit check. This gracefully handles situations where PSC predictions may be inaccurate, ensuring both functional correctness and performance robustness.

[0162] Therefore, the technical effects achieved by the address acquisition device provided in this disclosure include, but are not limited to:

[0163] 1. Significantly expand the coverage of HIT_ON_MISS: By using big page information provided by PSC, subsequent requests can identify cases where they belong to the same big page (64KB or 2MB) as the previous request, thereby triggering HIT_ON_MISS and expanding the optimization scope from a fixed 4KB to a dynamic big page level.

[0164] 2. Effectively reduce MMU access pressure: More HIT_ON_MISS means fewer MMU accesses, reducing bandwidth pressure and power consumption of system bus and page table traversal components.

[0165] 3. Simple implementation and low overhead: The PSC itself is a very small cache, storing only the aligned VPAGE and SIZE, resulting in low hardware overhead. Its update and query logic is clear, requiring minimal modification to existing TLBs and LSUs, and is easy to integrate into existing processor pipelines.

[0166] 4. Strong robustness: By adopting the "take the larger value" strategy during TLB hit checks, the potential delays or inaccuracies in PSC information are effectively addressed, ensuring that even if a PSC miss occurs, it will not lead to incorrect address translations, thus guaranteeing the correctness of the system.

[0167] Figure 8 A flowchart illustrating an address acquisition method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The method includes steps S81 to S83.

[0168] Step S81: Upon receiving a data processing instruction, obtain the first page size corresponding to the first virtual address in the data processing instruction, and generate a first address query request based on the first virtual address and the first page size.

[0169] Step S82: If the first physical address corresponding to the first virtual address is not stored, determine the first page identifier corresponding to the first address query request based on the first virtual address and the first page size, and determine the second page identifier corresponding to the second address query request currently performing the page table query operation.

[0170] Step S83: If the first page identifier and the second page identifier are the same, wait for the page table query result corresponding to the second address query request, and determine the first physical address corresponding to the first virtual address based on the page table query result.

[0171] It should be noted that the explanations of the technical terms in steps S81 to S83 above can be found in the corresponding explanations in the embodiments of the address acquisition device described above, and will not be repeated here.

[0172] The address acquisition method provided in this disclosure can be applied to different devices or equipment according to the needs of actual application scenarios. For example, the address acquisition method of this disclosure can be applied to the address acquisition device of the above embodiments, or the address acquisition method of this disclosure can also be applied to devices such as CPU architecture, GPU architecture, and on-chip chips.

[0173] Specifically, the address acquisition method provided in this embodiment can, upon receiving a data processing instruction, obtain a first virtual address from the data processing instruction and obtain a first page size corresponding to the first virtual address; then, generate a first address query request based on the first virtual address and the first page size, the first address query request being used to query a first physical address corresponding to the first virtual address.

[0174] After generating the first address query request, a query operation for the first physical address is triggered. This method first needs to determine whether the first physical address corresponding to the first virtual address is stored locally. If it is determined that the first physical address corresponding to the first virtual address is not stored, then it is necessary to further query the first physical address corresponding to the first virtual address.

[0175] In order to achieve accurate and fast address lookup, improve address lookup efficiency, and avoid wasting computing resources during the query of the first physical address, this method can determine the first page identifier of the first virtual page corresponding to the first address query request based on the first virtual address and the first page size corresponding to the first virtual address, and determine the second page identifier corresponding to the second address query request currently performing page table query operation. Then, the first page identifier and the second page identifier are compared.

[0176] If the first page identifier and the second page identifier are determined to be the same, it indicates that the second address query request currently executing the page table query operation and the first address query request are requests for the same virtual page. Therefore, this method can skip executing the first address query request and instead wait for the page table query result corresponding to the second address query request. After obtaining the page table query result corresponding to the second address query request, the first physical address corresponding to the first virtual address can be determined based on the page table query result. This first physical address is used to access the first storage location in the data storage unit and to execute the data processing operation corresponding to the data processing instruction for the first storage location.

[0177] Based on the above embodiments, the address acquisition method provided in this disclosure can accurately and quickly determine whether the first address query request and the second address query request are requests for the same virtual page by comparing whether the first page identifier and the second page identifier are the same during the address acquisition process. If the first page identifier and the second page identifier are the same, it can be determined that the two requests are requests for the same virtual page. Therefore, the page table query result corresponding to the second address query request can be waited for, and the page table query operation of the first address query request does not need to be performed, thereby avoiding the waste of computing resources. After obtaining the page table query result, the first physical address corresponding to the first virtual address in the first address query request can also be determined based on the page table query result corresponding to the second address query request, thereby achieving the purpose of improving query efficiency and saving computing resources.

[0178] It is understood that the above-mentioned method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0179] The above is an illustrative scheme of an address acquisition method according to this embodiment. It should be noted that the technical solution of this address acquisition method and the technical solution of the address acquisition device described above belong to the same concept. For details not described in detail in the technical solution of the address acquisition method, please refer to the description of the technical solution of the address acquisition device described above.

[0180] In addition, this disclosure also provides a processor and an electronic device, the corresponding technical solutions and descriptions of which are described in the method section and will not be repeated here.

[0181] This disclosure also provides a processor, which includes the address acquisition device described above.

[0182] This disclosure also provides an electronic device including the processor described above. For example, the electronic device includes: at least one processor; at least one memory; and one or more I / O interfaces connected between the processor and the memory; wherein the memory stores one or more computer programs executable by at least one processor.

[0183] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0184] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0185] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0186] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0187] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0188] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0189] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0190] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0191] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0192] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. An address acquisition device, characterized in that, The address acquisition device includes an address acquisition unit, a page-size storage unit, and a multi-level storage unit; The address acquisition unit is used for: Upon receiving a data processing instruction, the system retrieves the first page size corresponding to the first virtual address in the data processing instruction from the page size storage unit; generates a first address query request based on the first virtual address and the first page size, and sends it to the target storage unit in the multi-level storage unit. The target storage unit is used for: If the first physical address corresponding to the first virtual address is not stored, the first page identifier corresponding to the first address query request is determined based on the first virtual address and the first page size. Determine the second page identifier corresponding to the second address query request currently executing the page table query operation; If the first page identifier and the second page identifier are the same, wait for the parent storage unit of the target storage unit to return the page table query result corresponding to the second address query request; Based on the page table query results, the first physical address corresponding to the first virtual address is determined, and the first physical address is sent to the address acquisition unit.

2. The address acquisition device according to claim 1, characterized in that, The target storage unit is further used for: Obtain the first virtual address and the first page size from the received first address query request; Extract the first page identifier to be processed from the first virtual address, and obtain the first displacement parameter of the first page identifier based on the first page size; The first page identifier is obtained by shifting the first page identifier based on the first displacement parameter.

3. The address acquisition device according to claim 2, characterized in that, The first displacement parameter includes a first right shift bit; the target storage unit is further configured to: Determine the size of the third page in local storage; If the size of the third page is greater than or equal to the size of the first page, the size of the third page is determined as the target page size; If the size of the first page is larger than the size of the third page, the size of the first page shall be determined as the target page size; Based on the target page size, the first right shift bit corresponding to the first page identifier to be processed is obtained; The first page identifier is obtained by right-shifting the first page identifier based on the first right-shift bit.

4. The address acquisition device according to claim 1, characterized in that, The target storage unit is further used for: Obtain the second virtual address from the second address query request currently performing a page table query operation; Extract the second page identifier to be processed from the second virtual address, and obtain the second displacement parameter of the second page identifier based on the first page size; The second page identifier is shifted based on the second displacement parameter to obtain the second page identifier.

5. The address acquisition device according to claim 4, characterized in that, The second displacement parameter includes a second right shift bit; the target storage unit is further used for: Determine the size of the third page in local storage; If the size of the third page is greater than or equal to the size of the first page, the size of the third page is determined as the target page size; If the size of the first page is larger than the size of the third page, the size of the first page is determined as the target page size; Based on the target page size, the second right shift bit corresponding to the second page identifier to be processed is obtained; The second page identifier is obtained by right-shifting the second page identifier based on the second right-shift bit.

6. The address acquisition device according to claim 1, characterized in that, The page-size storage unit is used for: Upon receiving a size acquisition request sent by the address acquisition unit, the first page identifier to be processed is extracted from the first virtual address carried in the size acquisition request; From the multiple page identifiers currently stored, determine the candidate page identifier corresponding to the first page identifier to be processed, wherein the candidate page identifier is any one of the multiple page identifiers currently stored; If it is determined that the first page identifier to be processed matches the candidate page identifier, the candidate page size corresponding to the candidate page identifier is determined as the first page size corresponding to the first virtual address, and the first page size is sent to the address acquisition unit.

7. The address acquisition device according to claim 6, characterized in that, The page-size storage unit is also used for: Based on the candidate page size, the third right shift number of the first page identifier to be processed is obtained, and the first page identifier to be processed is right-shifted using the third right shift number to obtain the third page identifier; Based on the candidate page size, the fourth right shift number of the candidate page identifier is obtained, and the candidate page identifier is shifted to the right using the fourth right shift number to obtain the fourth page identifier; If the third page identifier is the same as the fourth page identifier, it is determined that the first page identifier to be processed matches the candidate page identifier.

8. The address acquisition device according to claim 6, characterized in that, The page size storage unit is further configured to: send a size query failure notification to the address acquisition unit when it is determined that the first page identifier to be processed is different from the candidate page identifier; The address acquisition unit is further configured to: upon receiving the size query failure notification, determine the locally stored preset page size as the first page size corresponding to the first virtual address.

9. The address acquisition device according to claim 1, characterized in that, The target storage unit is further configured to: send the page identifier and the page size in the page table query result to the page size storage unit when the page size in the page table query result is greater than a preset size threshold; The page size storage unit is also used to store the page size and the page identifier in the page table query result.

10. The address acquisition device according to claim 9, characterized in that, The page-size storage unit is also used for: The page size and page identifier in the page table query result are determined as the page size and page identifier to be stored; From the multiple page identifiers currently stored, determine the verification page identifier corresponding to the page size to be stored, and the verification page size corresponding to the verification page identifier, wherein the verification page identifier is any one of the multiple page identifiers currently stored; If the page identifier to be stored does not match the verification page identifier, and the page size to be stored is different from the verification page size, then the page size to be stored and the page identifier to be stored are stored. If the page identifier to be stored matches the verification page identifier and the page size to be stored is different from the verification page size, delete the verification page identifier and the verification page size, and store the page size to be stored and the page identifier to be stored.

11. The address acquisition device according to claim 10, characterized in that, The page-size storage unit is also used for: Based on the page size to be stored, the fifth right shift number of the page identifier to be stored is obtained, and the page identifier to be stored is shifted to the right using the fifth right shift number to obtain the fifth page identifier; Based on the verification page size, the sixth right shift number of the verification page identifier is obtained, and the verification page identifier is shifted to the right using the sixth right shift number to obtain the sixth page identifier; If the fifth page identifier is the same as the sixth page identifier, it is determined that the page identifier to be stored matches the verification page identifier; If the fifth page identifier is different from the sixth page identifier, it is determined that the page identifier to be stored does not match the verification page identifier.

12. The address acquisition device according to claim 1, characterized in that, The address acquisition device further includes a data storage unit; the address acquisition unit is also used for: Based on the first physical address, access the first storage location in the data storage unit, and execute the data processing operation corresponding to the data processing instruction for the first storage location, wherein the first physical address corresponds to the first storage location.

13. A method for obtaining an address, characterized in that, include: Upon receiving a data processing instruction, the system obtains the first page size corresponding to the first virtual address in the data processing instruction, and generates a first address query request based on the first virtual address and the first page size. In the absence of storing the first physical address corresponding to the first virtual address, the first page identifier corresponding to the first address query request is determined based on the first virtual address and the first page size, and the second page identifier corresponding to the second address query request currently performing the page table query operation is determined. If the first page identifier and the second page identifier are the same, wait for the page table query result corresponding to the second address query request, and determine the first physical address corresponding to the first virtual address based on the page table query result.

14. A processor, characterized in that, The processor includes the apparatus as described in any one of claims 1 to 12.

15. An electronic device, characterized in that, The electronic device includes the processor as described in claim 14.

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