PCIe reset signal processing circuit, chip, and PCIe system

Abstract

This application relates to the field of high-speed serial bus technology, and discloses a PCIe reset signal processing circuit, chip, and PCIe system. The processing circuit includes an external signal port, an input gating module, a reset generation module, and an output control module. The input gating module outputs a first PCIe reset signal from the external signal port in EP mode and disables the output of the first PCIe reset signal in RC mode, based on a mode indication signal. The reset generation module generates a second PCIe reset signal based on multiple reset source inputs and outputs it to the local PCIe controller and the output control module. The output control module disables the output of the second PCIe reset signal in EP mode and outputs the second PCIe reset signal in RC mode, based on the mode indication signal. This application adapts to both RC and EP operating modes with a single circuit structure, saving chip area and reducing hardware costs.

Description

Technical Field

[0001] This application relates to the field of high-speed serial bus technology, and in particular to a PCIe reset signal processing circuit, chip, and PCIe system. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe), as a high-speed serial bus standard, has been widely used in servers, embedded systems, and automotive-grade SoCs. In PCIe systems, the PERST# signal (PCIe Reset) is the core signal for controlling endpoint devices to initialize and reset links. Its timing management and control strategy directly affect the system's startup reliability and operational stability.

[0003] With the development of semiconductor technology, more and more system-on-a-chip (SoC) devices are designed to support both Root Complex (RC) mode and Endpoint (EP) mode, i.e., they have dual-role capabilities. In such dual-role chips, the processing logic for the PCIe reset signal varies significantly depending on the operating mode: when the chip operates in RC mode, it needs to actively generate a PCIe reset signal and provide it to downstream endpoint devices; when the chip operates in EP mode, it cannot independently determine whether the system is power-on ready and needs to receive and process the PCIe reset signal from the upstream Root Complex.

[0004] In existing technologies, the PCIe reset signal processing of the aforementioned dual-role chips typically employs two independent processing circuits: one adapted to RC mode, capable only of actively outputting PCIe reset signals; and the other adapted to EP mode, capable only of passively receiving PCIe reset signals. Signal processing in each mode is performed by its respective circuit. While this approach can achieve the reset function in each mode, the two independent circuits occupy a large chip area, increasing hardware resources and manufacturing costs. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted in this application is as follows: In a first aspect, embodiments of this application provide a PCIe reset signal processing circuit, applied to a PCIe dual-role chip, the processing circuit comprising: External signal ports; An input gating module is provided, wherein the first input terminal of the input gating module is connected to the external signal port to receive a first PCIe reset signal from the external source; the mode configuration terminal of the input gating module is used to receive a mode indication signal; and the input gating module outputs or disables the output of the first PCIe reset signal based on the mode indication signal. A reset generation module includes a first reset source input terminal and at least one second reset source input terminal. The first reset source input terminal is connected to the output terminal of the input gating module, and the second reset source input terminal is used to receive a local reset control signal. The reset generation module is used to generate a second PCIe reset signal when any input signal is valid. The output terminal of the reset generation module is connected to a local PCIe controller. An output control module is provided, wherein the input terminal of the output control module is connected to the output terminal of the reset generation module, and the output terminal of the output control module is connected to the external signal port; the control terminal of the output control module is used to receive the mode indication signal, and the output control module outputs or disables the output of the second PCIe reset signal based on the mode indication signal. Specifically, when the input gating module outputs the first PCIe reset signal, the output control module disables the output of the second PCIe reset signal; when the input gating module disables the output of the first PCIe reset signal, the output control module outputs the second PCIe reset signal.

[0006] In one alternative embodiment, the chip includes a local processor; the processing circuit further includes a notification module, the input of which is connected to the output of the input gating module, for providing the local processor with the state change of the first PCIe reset signal according to the signal output by the input gating module.

[0007] The PCIe controller is triggered to perform a hardware reset by the first PCIe reset signal. The software is notified by the notification module to automatically complete operations such as PCIe enumeration, link training, and cache channel initialization after the reset is released. The hardware reset and software notification are based on the same first PCIe reset signal to ensure timing synchronization, enabling the local PCIe controller to quickly synchronize the link status with the upstream root complex, and the PCIe link quickly enters the active state.

[0008] In one alternative embodiment, the notification module includes an interrupt generation module for generating an interrupt signal when an edge transition of the first PCIe reset signal is detected, in order to notify the local processor.

[0009] The interrupt generation module monitors the state transition of the externally input first PCIe reset signal in real time and generates an interrupt signal to immediately notify the local processor, thereby quickly executing link initialization or recovery operations. This interrupt scheme only triggers notification when the first PCIe reset signal changes state, saving processor resources, reducing system power consumption, and improving response speed.

[0010] Secondly, embodiments of this application provide a chip, including the PCIe reset signal processing circuit and PCIe controller mentioned in the first aspect.

[0011] Thirdly, embodiments of this application provide a PCIe system, including a root complex device and an endpoint device; The root complex device includes a PCIe reset signal processing circuit as described in the first aspect, wherein the PCIe reset signal processing circuit in the root complex device operates in RC mode; in the root complex device: the mode indication signal indicates that the current operating mode is RC mode; the input gating module, based on the mode indication signal, disables the output of the first PCIe reset signal; and the output control module, based on the mode indication signal, outputs the second PCIe reset signal. The endpoint device includes a PCIe reset signal processing circuit as described in the first aspect, wherein the PCIe reset signal processing circuit in the endpoint device operates in EP mode; in the endpoint device: the mode indication signal indicates that the current operating mode is EP mode; the input gating module outputs the first PCIe reset signal based on the mode indication signal; and the output control module disables the output of the second PCIe reset signal based on the mode indication signal. Wherein, the second PCIe reset signal of the root complex device is the first PCIe reset signal of the endpoint device.

[0012] The technical solution provided in this application embodiment controls whether to send the first PCIe reset signal from outside the chip to the reset generation module according to the mode indication signal through the input gating module, and controls whether to output the second PCIe reset signal generated by the reset generation module to outside the chip according to the same mode indication signal through the output control module.

[0013] In RC mode, the input gating module blocks the input of the external PCIe reset signal, the reset generation module generates a second PCIe reset signal based on the local reset control signal, and the output control module outputs the second PCIe reset signal. The second PCIe reset signal serves as an external reset signal, enabling the PCIe reset signal processing circuit to actively generate and output a reset signal as a root complex. In EP mode, the input gating module allows the input of the first PCIe reset signal from outside the chip, the reset generation module generates a second PCIe reset signal based on the first PCIe reset signal, the second PCIe reset signal is used as the on-chip reset signal, and the output control module blocks the output of the second PCIe reset signal generated inside the chip to outside the chip. Therefore, the same set of PCIe reset signal processing circuits can both act as a root complex to actively generate and output PCIe reset signals, and also act as an endpoint to receive and respond to PCIe reset signals input from outside the chip.

[0014] Therefore, this application utilizes a single circuit structure to adapt to the reset signal processing requirements of RC and EP modes under different operating conditions, eliminating the need to design two separate processing circuits for each mode. This saves chip area and reduces hardware resources and manufacturing costs. Furthermore, the input gating module and output control module are linked and controlled by the same mode indicator signal, ensuring the synchronization of signal source selection and signal flow control during mode switching. In addition, the mode indicator signal is dynamically configured by software, allowing the chip to switch modes during operation according to actual application requirements, improving the system's flexibility and applicability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a PCIe reset signal processing circuit provided in an embodiment of this application; Figure 2 A schematic diagram of a PCIe reset signal processing circuit including a notification module provided in an embodiment of this application; Figure 3 A schematic diagram of a PCIe reset signal processing circuit including a filtering logic module provided in an embodiment of this application; Figure 4 A schematic diagram of a PCIe reset signal processing circuit including a notification module and a filtering logic module provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a PCIe system provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a reset generation module provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation steps as shown in the following embodiments or drawings, the method may include more or fewer operation steps based on conventional or non-inventive effort. For steps that do not logically have a necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0018] The PCIe controller is a hardware module inside the chip used to implement the PCIe protocol stack. Its functions typically include handling the protocol logic of the PCIe transaction layer, data link layer, and physical layer. The PCIe controller needs to be initialized and switch states under the control of the PCIe reset signal to ensure the normal establishment and reliable operation of the PCIe link.

[0019] Depending on the chip's operating mode configuration, the PCIe controller can operate in RC mode or EP mode. When operating in RC mode, the PCIe controller acts as the root node of the PCIe bus hierarchy, responsible for initiating bus enumeration, configuration space access, and managing downstream endpoint devices. When operating in EP mode, the PCIe controller acts as a leaf node of the PCIe bus hierarchy, responding to configuration requests and data transfers from the upstream RC.

[0020] This embodiment provides a PCIe reset signal processing circuit. This circuit is applied to a PCIe dual-role chip and can generate and receive PCIe reset signals in RC and EP modes respectively. Figure 1 As shown, the chip also includes a local processor 900, a mode configuration module 800, and a PCIe controller 700. The mode configuration module 800 provides a mode indication signal MODE, which indicates whether the current operating mode is RC mode or EP mode. The local processor 900 runs software programs, such as performing link initialization or reset operations. The PCIe controller 700 performs PCIe protocol-related data link layer and physical layer operations, and its reset operation is controlled by a second PCIe reset signal PERST_OUT output by the reset generation module 300.

[0021] refer to Figure 1 The PCIe reset signal processing circuit includes an external signal port 100, an input gating module 200, a reset generation module 300, and an output control module 400.

[0022] External signal port 100 is used to receive or output PCIe reset signals from outside the chip. This external signal port 100 is a physical pin or pad of the chip. When the chip is in RC mode, the PCIe reset signal generated internally is output to the downstream endpoint device outside the chip via external signal port 100; when the chip is in EP mode, the PCIe reset signal from the upstream root complex device outside the chip is input to the chip internally via external signal port 100.

[0023] For ease of description and distinction, in this embodiment, the PCIe reset signal received from the external chip through the external signal port 100 is referred to as the first PCIe reset signal, and the PCIe reset signal generated by the reset generation module 300 is referred to as the second PCIe reset signal.

[0024] The input gating module 200 has a first input terminal 201, a mode configuration terminal 203, and an output terminal 204. The first input terminal 201 is connected to the external signal port 100 and is used to receive a first PCIe reset signal PERST_IN from outside the chip. The mode configuration terminal 203 is used to receive a mode indication signal MODE, which indicates whether the current operating mode is RC mode or EP mode. The input gating module 200 controls whether to output the first PCIe reset signal PERST_IN received by the first input terminal 201 through the output terminal 204 according to the mode indication signal MODE. Specifically, when the mode indication signal MODE indicates EP mode, the output terminal 204 of the input gating module 200 outputs the first PCIe reset signal PERST_IN; when the mode indication signal MODE indicates RC mode, the input gating module 200 disables the output terminal 204 from outputting the first PCIe reset signal PERST_IN.

[0025] The reset generation module 300 includes a first reset source input terminal 301, at least one second reset source input terminal (e.g., 302, 303), and an output terminal 304. The first reset source input terminal 301 receives signals output by the input gating module 200. Each second reset source input terminal receives one local reset control signal (e.g., RST1, RST2). Based on the signals received from the first reset source input terminal 301 and the second reset source input terminals 302, 303, the reset generation module 300 outputs a second PCIe reset signal PERST_OUT from its output terminal 304. The output terminal 304 of the reset generation module 300 is connected to the local PCIe controller 700 and the input terminal 401 of the output control module 400.

[0026] The output control module 400 includes an input terminal 401, an output terminal 402, and a control terminal 403. The input terminal 401 is connected to the output terminal 304 of the reset generation module 300 and is used to receive the second PCIe reset signal PERST_OUT output by the reset generation module 300. The output terminal 402 is connected to the external signal port 100. The control terminal 403 is used to receive the mode indication signal MODE. The output control module 400 controls whether to output the signal received by the input terminal 401 through the output terminal 402 according to the mode indication signal MODE. Specifically, when the mode indication signal indicates EP mode, the output control module 400 disables signal output, and the external signal port 100 is released to receive the first PCIe reset signal PERST_IN from outside the chip; when the mode indication signal indicates RC mode, the output control module 400 outputs the second PCIe reset signal PERST_OUT, which is output to the external chip via the external signal port 100.

[0027] The working principle of the above PCIe reset signal processing circuit is as follows: When the chip is configured in RC mode, the mode configuration module 800 outputs a mode indication signal representing the RC mode. The input gating module 200 disables the output of the first PCIe reset signal PERST_IN based on this mode indication signal. At this time, the external signal port 100 is used for external signal output. The reset generation module 300 outputs the second PCIe reset signal PERST_OUT from its output terminal 304 based on local reset control signals (e.g., RST1, RST2). The output control module 400 outputs PERST_OUT based on the mode indication signal MODE. PERST_OUT is output to the downstream endpoint device via the external signal port 100. PERST_OUT serves as the PCIe reset signal for the downstream endpoint device, controlling it to complete reset initialization. Simultaneously, the PERST_OUT output by the reset generation module 300 is also output to the local PCIe controller 700 to control the local PCIe controller 700 to perform corresponding reset or initialization operations, ensuring that the local PCIe controller 700 is synchronized with the state of the downstream endpoint device.

[0028] When the chip is configured in EP mode, the mode configuration module 800 outputs a mode indication signal representing the EP mode. The input gating module 200 selects the first input terminal 201 according to this mode indication signal and outputs the first PCIe reset signal PERST_IN received through the external signal port 100 to the reset generation module 300. The reset generation module 300 receives PERST_IN and outputs the second PCIe reset signal PERST_OUT from its output terminal 304 according to PERST_IN. The output control module 400 disables the output signal according to the mode indication signal, and the second PCIe reset signal output by the reset generation module 300 is blocked, preventing it from being output to the external circuitry through the external signal port 100. This avoids signal conflict with the first PCIe reset signal PERST_IN output by the upstream RC device on the board-level traces; at this time, the external signal port 100 is used to receive the first PCIe reset signal from the external circuitry. Meanwhile, the PERST_OUT output by the reset generation module 300 is also output to the local PCIe controller 700 to control the local PCIe controller 700 to perform a reset or release reset operation according to the state of PERST_OUT.

[0029] It should be noted that when the chip is configured in EP mode, the second reset source input terminals (such as 302 and 303) of the reset generation module 300 can be flexibly configured according to the actual chip design requirements. In some embodiments, all second reset source input terminals can be in an unconnected state or maintain a default level (e.g., high level). In this case, the reset generation module 300 only outputs the second PCIe reset signal PERST_OUT based on the first PCIe reset signal PERST_IN from outside the chip. In other embodiments, all or part of the second reset source input terminals can receive local reset control signals (e.g., SOC reset, subsystem reset, software triggered reset, or test mode reset, etc.), which, together with PERST_IN from outside the chip, serve as reset sources. PERST_OUT is output when any reset source is valid.

[0030] The PCIe reset signal processing circuit provided in this embodiment controls whether the first PCIe reset signal is output to the reset generation module 300 based on the mode indication signal via the input gating module 200. Simultaneously, the output control module 400 controls whether the second PCIe reset signal generated by the reset generation module 300 is output to an external chip based on the same mode indication signal. This achieves simultaneous adaptation of reset signal processing requirements in both RC and EP modes using a single circuit structure. This processing circuit eliminates the need to design two separate processing circuits for each mode, saving chip area and reducing hardware resources and manufacturing costs. Furthermore, the input gating module 200 and the output control module 400 are linked and controlled by the same mode indication signal, ensuring synchronization of signal source selection and signal flow control during mode switching. In addition, the mode indication signal is dynamically configured by software, allowing the chip to switch modes according to actual application requirements, improving the system's flexibility and applicability.

[0031] The mode indicator signal MODE can be generated by Figure 1 The mode configuration module 800 is provided in the local processor 900. Software running on the local processor 900 sets the state of the mode configuration module 800 through register configuration to generate mode indication signals corresponding to the operating mode. When the mode indication signal is at a first level (e.g., high level), it indicates that the current mode is RC; when the mode indication signal is at a second level (e.g., low level), it indicates that the current mode is EP. It should be noted that the correspondence between level and mode is only an example; in actual implementation, it can be flexibly configured. For example, a high level can represent EP mode, a low level can represent RC mode, or a multi-bit digital code can be used to indicate more operating modes. This embodiment does not limit this.

[0032] In this application, the specific implementation of the input gating module 200 is not limited, as long as it can selectively output the signal from the first input terminal 201 from its output terminal 204 under the control of the mode indication signal. Those skilled in the art can choose a suitable implementation method according to the chip design requirements. Some structural examples of the input gating module 200 are given below.

[0033] In some alternative embodiments, the input gating module 200 further has a second input terminal 202. (See reference...) Figure 2The second input terminal 202 is connected to a high-level signal (e.g., power supply voltage VDD). Since the PCIe reset signal is active low (low level indicates reset triggering, high level indicates an invalid reset state, meaning there is no valid external reset request), the high-level signal at the second input terminal 202 is used to make the input gating module 200 output an invalid level in RC mode. Therefore, when the input gating module 200 selects the second input terminal 202 in RC mode and outputs a high-level signal to the reset generation module 300, the reset generation module 300 will not trigger the output of the reset signal due to this input signal.

[0034] The input gating module 200 is specifically used to select, according to the mode indication signal, to output the first PCIe reset signal received at the first input terminal 201 from its output terminal 204 in EP mode, and to select to output the high-level signal received at the second input terminal 202 from its output terminal 204 in RC mode. That is, in EP mode, the input gating module 200 opens the signal path from the first input terminal 201 to the output terminal 204, and sends the first PCIe reset signal from outside the chip to the reset generation module 300; in RC mode, it opens the signal path from the second input terminal 202 to the output terminal 204, and sends the high-level signal to the reset generation module 300.

[0035] It should be noted that the high-level signal connected to the second input terminal 202 serves as a substitute input source for the first input terminal 201, ensuring that the input gating module 200 can still provide a definite level signal to the reset generation module 300 in RC mode, without the input terminal being left floating, thus preventing the input state of the reset generation module 300 from becoming uncertain. A high-level signal represents an invalid reset state and will not trigger the reset generation module 300 to generate a reset output, thereby ensuring that in RC mode, the reset generation module 300 generates a reset output solely based on the local reset control signal.

[0036] By providing a second input terminal 202 to the input gating module 200 and connecting it to a high-level signal, the input gating module 200 can provide a definite invalid reset state to the reset generation module 300 in RC mode, avoiding the state uncertainty problem caused by a floating input terminal and improving the reliability of the circuit. Simultaneously, the input gating module 200 selects the first input terminal 201 in EP mode and the second input terminal 202 in RC mode, achieving signal source switching between the two modes through the same module without the need for additional circuitry.

[0037] As an example, the input gating module 200 can be implemented using a 2-to-1 multiplexer, with its two data input terminals serving as the first input terminal 201 and the second input terminal 202, and its selection control terminal serving as the mode configuration terminal 203.

[0038] In some alternative embodiments, the input gating module 200 can also be implemented using a controllable switch (such as a three-state buffer): in EP mode, the switch is closed, and the signal of the first input terminal 201 is output to the reset generation module 300; in RC mode, the switch is open, blocking the signal transmission of the first input terminal 201 to the reset generation module 300, at which time the output terminal is in a high impedance state or outputs a high-level signal (depending on the switch type).

[0039] In some optional embodiments, the local reset control signal received by the second reset source input terminal of the reset generation module 300 can come from multiple reset sources within the chip. For example, the system-on-chip (SoC) reset signal is generated by the reset controller within the SoC and connected to one of the second reset source input terminals of the reset generation module 300 via internal chip wiring; the subsystem reset signal is generated by the reset logic within the PCIe subsystem and connected to another second reset source input terminal of the reset generation module 300; the software-triggered reset signal is generated by software through writing to a register, and the register output terminal is connected to the corresponding second reset source input terminal of the reset generation module 300; the reset signal in test mode is provided by a chip test interface (such as JTAG) and connected to the corresponding second reset source input terminal of the reset generation module 300. Those skilled in the art can flexibly configure the number of second reset source input terminals of the reset generation module 300 and the type of local reset control signal received by each second reset source input terminal according to chip design requirements.

[0040] In this embodiment, the reset generation module 300 can be implemented by combinational logic circuits. These combinational logic circuits perform logical synthesis processing on the signals at each reset source input terminal and output a second PCIe reset signal. When any input signal (such as the external first PCIe reset signal PERST_IN, SOC total reset, or software register reset) is at a valid level (0), the output of the logic merging unit is at a valid level (0). When all input signals are at an invalid level (1), the output of the logic merging unit is at an invalid level (1), thereby generating the second PCIe reset signal PERST_OUT.

[0041] like Figure 6As shown, in some embodiments, multiple reset source input signals (including signals output by the input gating module 200 and local reset control signals) are input to a multi-input AND gate 305 through their respective corresponding input terminals (e.g., 301, 302, 303). The AND gate 305 performs a logical AND operation on each reset source input signal: when any reset source input is at a valid level (low level), the AND gate 305 outputs a low level, i.e., outputs a valid reset signal; when all reset source inputs are at an invalid level (high level), the AND gate 305 outputs a high level, releasing the reset. This logic ensures that the first PCIe reset signal from outside the chip and the local reset control signal jointly participate in the reset determination.

[0042] Because the first PCIe reset signal comes from an external source and is asynchronous to the local PCIe clock, the output of AND gate 305 is synchronized to the local PCIe clock via reset signal synchronization logic 306, and then output as the second PCIe reset signal from output terminal 304. The reset signal synchronization logic 306 can be a synchronizer, etc. In some embodiments, when all reset sources are already in the same clock domain, or when the PCIe controller is not sensitive to the reset release timing, the reset generation module 300 may include AND gate 305 but not the reset signal synchronization logic 306.

[0043] It should be noted that, among the aforementioned multiple reset sources, the reset generation module 300 can use different combinations of reset sources to generate reset outputs in different operating modes. For example, in RC mode, the reset generation module 300 can receive one or more local reset control signals, and a reset output is generated when any local reset control signal is valid; in EP mode, the reset generation module 300 uses the externally input first PCIe reset signal as one of the reset sources; when a local reset control signal is connected to the second reset source input, the local reset control signal also participates in the reset determination as a reset source, and a reset output is triggered when any valid reset source input is received; when a local reset control signal is not connected to the second reset source input, the reset generation module 300 generates a reset output only based on the externally input first PCIe reset signal.

[0044] In some alternative embodiments, the output control module 400 can be implemented using a controllable switch. The controllable switch closes or opens under the control of the control terminal 403 to enable or disable the transmission of the internal second PCIe reset signal to the external signal port 100. As an example, the controllable switch can be implemented using a tri-state buffer, where the control terminal 403 is the output enable terminal (OE terminal) of the tri-state buffer, and the mode indication signal is connected directly or after inversion to this output enable terminal. As another example, the controllable switch can also be implemented using a tri-state inverter, a transmission gate, or an output enable buffer. Those skilled in the art will understand that the above devices all belong to the controllable switch implementation methods of the output control module of this application.

[0045] refer to Figure 2 This embodiment provides a PCIe reset signal processing circuit. Based on the aforementioned embodiment, the processing circuit further includes a notification module 500.

[0046] The input terminal 501 of the notification module 500 is connected to the output terminal 204 of the input gating module 200, and is used to receive the signal output by the input gating module 200. The notification module 500 is used to provide the local processor 900 with the status change of the first PCIe reset signal based on the first PCIe reset signal PERST_IN output by the input gating module 200. After sensing the status change of the first PCIe reset signal, the local processor 900 immediately calls or starts the PCIe driver to perform software initialization work such as protocol stack configuration and resource allocation.

[0047] When the first PCIe reset signal output by the input gating module 200 undergoes a state change (e.g., transitioning from high to low or vice versa), the notification module 500 notifies the local processor 900 of this state change. This allows the local processor 900 to promptly detect the state change of the externally input first PCIe reset signal PERST_IN, and thus, in EP mode, perform corresponding link initialization or reset operations based on the change in PERST_IN, improving the system's response speed. Simultaneously, the notification module 500 transforms the hardware-level reset signal change into processor-perceptible notification information, providing a mechanism to support software-level link management and exception handling.

[0048] In this application, a hardware reset of the PCIe controller is triggered by a first PCIe reset signal. The notification module 500 then notifies the software to automatically complete PCIe enumeration, link training, and cache channel initialization operations after the reset is released. The hardware reset and software notification are based on the same first PCIe reset signal, ensuring timing synchronization. This allows the local PCIe controller 700 to quickly synchronize the link status with the upstream root complex, and the PCIe link rapidly enters the active state. After the link is established, the local PCIe controller 700 responds to the root complex's configuration space read / write requests, opening the data transmission channel to ensure the rapid and reliable establishment of the PCIe link.

[0049] It should be noted that the notification module 500 can be implemented in different ways.

[0050] As an example, such as Figure 2As shown, the notification module 500 may include a status register 504. The status value of the status register 504 is updated according to the first PCIe reset signal for querying by the local processor 900. Specifically, when the first PCIe reset signal is at a valid level (low level), the status register is updated to a first status value; when the first PCIe reset signal is at an invalid level (high level), the status register is updated to a second status value. By periodically reading the current status value of the status register, the local processor 900 enables the software to obtain the current status of the PCIe reset signal as needed.

[0051] As another example, such as Figure 4 As shown, the notification module 500 may include an interrupt generation module 505, which generates an interrupt signal IRQ based on the first PCIe reset signal output by the input strobe module 200. The notification module 500 sends the interrupt signal IRQ to the local processor 900. Upon receiving the interrupt signal IRQ, the local processor 900 immediately calls or starts the PCIe driver to perform software initialization tasks such as protocol stack configuration and resource allocation. Specifically, the interrupt generation module 505 detects the rising edge and / or falling edge of the first PCIe reset signal output by the input strobe module 200 and generates an interrupt signal when the corresponding edge transition is detected. The interrupt generation module 505 can be configured to detect only the rising edge, only the falling edge, or both rising and falling edges simultaneously, and trigger an interrupt signal when the corresponding edge is detected. These various detection methods can be selected through a software configuration register to meet the needs of different application scenarios. In some embodiments, when the interrupt generation module detects the rising edge of the first PCIe reset signal, it generates an interrupt signal. After receiving the interrupt signal, the local processor can pause data transmission, refresh the cache, or save critical states. Since the PCIe reset signal (PERST#) is active low, its rising edge indicates that the external root complex (RC) has been released and reset, and the system main power supply is ready, thus realizing the parallel coordination of software-driven loading and hardware-level link training on the time axis.

[0052] The interrupt generation module monitors the state transition of the first external PCIe reset signal in real time and generates an interrupt signal to immediately notify the local processor. This allows the software running on the local processor to detect changes in the PCIe reset signal without constantly querying registers, thus enabling rapid execution of link initialization or recovery operations. The interrupt scheme triggers notification only when the first PCIe reset signal changes state, saving processor resources, reducing system power consumption, and improving response speed.

[0053] In one alternative embodiment, reference Figure 2The notification module 500 also has an enable pin 502. The enable pin 502 is used to receive a mode indication signal. The notification module 500 is enabled when the mode indication signal indicates EP mode (i.e., interrupt signal generation is allowed), and disabled when the mode indication signal indicates RC mode (i.e., interrupt signal generation is masked). Since the chip actively generates a second PCIe reset signal and outputs it externally in RC mode, it does not need to generate an interrupt by monitoring the state change of the externally input first PCIe reset signal. Therefore, disabling the notification module 500 can mask invalid notifications, reduce processor overhead, and lower power consumption. In EP mode, the chip needs to receive the first PCIe reset signal from external sources and perform a local reset operation based on this signal. Therefore, enabling the notification module 500 allows for real-time monitoring of the state change of the first PCIe reset signal and timely notification to the local processor inside the chip.

[0054] refer to Figure 3 This embodiment provides a PCIe reset signal processing circuit. Based on the previous embodiment, this processing circuit further includes a filtering logic module 600. The input terminal 601 of the filtering logic module 600 is connected to the output terminal 204 of the input gating module 200, and is used to receive the signal output by the input gating module 200; the output terminal 602 of the filtering logic module 600 is connected to the first reset source input terminal 301 of the reset generation module 300. The filtering logic module 600 is used to perform filtering processing on the first PCIe reset signal output by the input gating module 200.

[0055] In EP mode, the input gating module 200 selects the first input terminal 201 and outputs the first PCIe reset signal received through the external signal port 100 to the filtering logic module 600. The filtering logic module 600 performs filtering processing on the first PCIe reset signal to filter out signal jitter caused by electromagnetic interference or other noise introduced by the inter-chip traces, so as to avoid the PCIe link from being falsely started or falsely reset due to noise interference. The filtered first PCIe reset signal is then output to the first reset source input terminal 301 of the reset generation module 300.

[0056] In RC mode, the input gating module 200 disables the output of the first PCIe reset signal, and its output terminal outputs a high-level signal to the filtering logic module 600. After being filtered by the filtering logic module 600, this high-level signal remains high and is output to the reset generation module 300. Since the high-level signal is an invalid reset state, it will not trigger the reset generation module 300 to generate a reset output. Therefore, the filtering processing of the filtering logic module 600 in RC mode does not affect the working state of the reset generation module 300.

[0057] In one optional embodiment, the filtering time window of the filtering logic module 600 is configurable. The filtering time window refers to the time threshold used by the filtering logic module 600 when performing glitching filtering on the input signal. When the first PCIe reset signal output by the input gating module 200 remains stable within the filtering time window, the filtering logic module 600 determines that the signal is a valid level and outputs this state to the reset generation module 300. When the first PCIe reset signal experiences a jump or spikes within the filtering time window, the filtering logic module 600 determines that the signal is invalid interference and maintains the original output state. By setting the duration of the filtering time window, short-duration noise spikes can be effectively filtered out, ensuring that only a continuously stable valid level can trigger the reset logic, thereby improving the anti-interference capability and system reliability of the PCIe link.

[0058] The length of the filtering time window can be flexibly adjusted via a software configuration register to adapt to different application environments and noise levels. As an example, the filtering logic module 600 may include a parameter configuration register, which receives and stores filtering time window configuration information, the length of which is determined by this configuration information. The subsystem software can configure the filtering time window to different lengths by writing different configuration values ​​to this parameter configuration register. For example, in automotive-grade applications with strong electromagnetic interference, a longer filtering time window can be set to enhance anti-interference capabilities; in laboratory testing scenarios with relatively good electromagnetic environments, a shorter filtering time window can be set to improve response speed. Those skilled in the art can flexibly adjust the specific value of the filtering time window by writing different configuration values ​​to the parameter configuration register according to the needs of the actual application scenario.

[0059] refer to Figure 4 This embodiment provides a PCIe reset signal processing circuit. Based on the aforementioned embodiment, the processing circuit also includes a notification module 500 and a filtering logic module 600.

[0060] Specifically, the output terminal 204 of the input gating module 200 is connected to the input terminal 601 of the filtering logic module 600. The filtering logic module 600 performs filtering processing on the first PCIe reset signal output by the input gating module 200, and outputs the filtered first PCIe reset signal from the output terminal 602 of the filtering logic module 600. The output terminal 602 of the filtering logic module 600 is connected to the input terminal 501 of the notification module 500 and the first reset source input terminal 301 of the reset generation module 300, respectively. That is, the filtered first PCIe reset signal is simultaneously sent to the notification module 500 and the reset generation module 300. The specific structure and function of the filtering logic module 600 are described in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0061] The input terminal 501 of the notification module 500 is connected to the output terminal 602 of the filtering logic module 600. It receives the filtered first PCIe reset signal and, based on the filtered first PCIe reset signal, provides the local processor with the state change of the PCIe reset signal. The notification module 500 can be implemented using interrupt mode or register mode; for details, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0062] The first reset source input terminal 301 of the reset generation module 300 is connected to the output terminal 602 of the filtering logic module 600, and is used to receive the filtered first PCIe reset signal as one of the reset sources. Based on the filtered first PCIe reset signal and other local reset control signals, the reset generation module 300 outputs a second PCIe reset signal from its output terminal 304. The specific structure and function of the reset generation module 300 are described in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0063] In EP mode, the first PCIe reset signal input from outside the chip is filtered by the input gating module 200 and then by the filtering logic module 600. The filtered first PCIe reset signal is simultaneously sent to the notification module 500 and the reset generation module 300. The notification module 500 provides the local processor with the status change of the PCIe reset signal based on the filtered first PCIe reset signal. The reset generation module 300 outputs the second PCIe reset signal from its output terminal 304 based on the filtered first PCIe reset signal and other local reset control signals. The output control module 400 disables the output signal according to the mode indication signal. That is, the second PCIe reset signal entering the output control module 400 is blocked by the output control module 400 and cannot be output to the outside through the external signal port 100. At this time, the external signal port 100 is only used to receive the PERST# signal from outside the chip.

[0064] In RC mode, the input gating module 200 disables the output of the first PCIe reset signal and outputs a high-level signal to the filtering logic module 600. This high-level signal remains high after being filtered by the filtering logic module 600 and is simultaneously sent to the notification module 500 and the reset generation module 300. Since the high-level signal is an invalid reset input state, it will not trigger the notification module 500 to generate an interrupt signal or modify the status register, nor will it trigger the reset generation module 300 to generate a reset output. Based on the local reset control signal, the reset generation module 300 outputs a second PCIe reset signal from its output terminal 304 to the PCIe controller 700 and the output control module 400. The output control module 400 outputs the second PCIe reset signal to the external device via the external signal port 100.

[0065] In this embodiment, the filtering logic module 600 and the notification module 500 are connected in series. The filtering logic module 600 first performs filtering, and then the filtered PCIe reset signal is simultaneously provided to both the notification module 500 and the reset generation module 300, thus achieving multiplexing of the filtering logic module 600. This solution possesses the dual advantages of real-time interrupt response and anti-interference filtering. It can enable software to quickly detect changes in the PCIe reset signal through the interrupt mechanism, and it can also prevent false triggering of the signal due to noise interference through the filtering mechanism, thereby achieving a balance between system response speed and operational reliability.

[0066] This embodiment provides a chip that includes the PCIe reset signal processing circuit found in any of the foregoing embodiments. This chip is a dual-role PCIe chip, capable of switching between RC mode and EP mode. The structure and function of the PCIe reset signal processing circuit are described in the foregoing embodiments and will not be repeated here.

[0067] By integrating the aforementioned PCIe reset signal processing circuit within the chip, the same chip can flexibly switch the processing mode of the PCIe reset signal according to the working mode, eliminating the need to design two separate reset signal processing circuits for RC mode and EP mode within the chip, thereby saving chip area and reducing manufacturing costs.

[0068] refer to Figure 5 This embodiment provides a PCIe system, including a root complex device 10 and an endpoint device 20.

[0069] The root complex device 10 includes a chip operating in RC mode, which includes the PCIe reset signal processing circuit of any of the preceding embodiments, operating in RC mode. In RC mode, the mode configuration module 800 outputs a mode indication signal MODE_RC representing the RC mode. Under the control of the mode indication signal MODE_RC, the input gating module 200 prevents the transmission of signals received at the first input terminal 201 to the output terminal 204. The reset generation module 300 outputs a PERST# signal from its output terminal 304 to the output control module 400 according to the local reset control signals RST1 and RST2. Under the control of the mode indication signal MODE_RC, the output control module 400 outputs the PERST# signal to the endpoint device 20 through the external signal port 100. Simultaneously, the PERST# signal output by the reset generation module 300 is also output to the local PCIe controller 700 to control the PCIe controller 700 within the root complex device 10 to perform corresponding reset or initialization operations, ensuring that the local PCIe controller 700 is synchronized with the state of the endpoint device 20.

[0070] Endpoint device 20 includes a chip operating in EP mode. This chip includes the PCIe reset signal processing circuit described in any of the preceding embodiments. The PCIe reset signal processing circuit in endpoint device 20 operates in EP mode. In EP mode, mode configuration module 800 outputs a mode indication signal MODE_EP representing the EP mode. Input gating module 200 outputs the PERST# signal received through external signal port 100 to reset generation module 300 based on the mode indication signal MODE_EP. Reset generation module 300 outputs a reset signal perst_n from its output terminal 304 for internal use by endpoint device 20 based on the PERST# signal. This reset signal perst_n is input to the PCIe controller 700 of endpoint device 20 to control the PCIe controller 700 of endpoint device 20 to perform a reset or release reset operation based on the state of the reset signal perst_n. Simultaneously, output control module 400, under the control of mode indication signal MODE_EP, disables the output of the reset signal perst_n to avoid its output signal interfering with the PERST# signal input through external signal port 100.

[0071] It should be noted that in endpoint device 20, the signals connected to the second reset source input terminals (such as 302 and 303) of the reset generation module 300 can be flexibly configured according to the actual chip design requirements. In some embodiments, all second reset source input terminals are in an unconnected state or maintain a default level (e.g., high level). In this case, the reset generation module 300 only outputs the reset signal perst_n based on the PERST# signal from outside the chip, and the local reset control signal does not participate in the reset determination. In other embodiments, all or some of the second reset source input terminals receive the local reset control signal (e.g., SOC reset, subsystem reset, software triggered reset, or test mode reset, etc.), which, together with the PERST# signal from outside the chip, serve as reset sources for AND gate determination. If any reset source is valid, the reset signal perst_n is output.

[0072] The PCIe reset signal processing circuit in the PCIe system of this application can adopt the PCIe reset signal processing circuit in any of the foregoing embodiments. Its specific working mode in RC mode and EP mode can be found in the relevant description of the foregoing embodiments, and will not be repeated here.

[0073] After both root complex device 10 and endpoint device 20 have completed their resets, the PCIe system enters the link establishment and data transmission phase, as follows: Link establishment phase: The root complex device 10 initiates link training, negotiates the link width (e.g., x1, x2, x4, x8, x16) and data transmission rate (e.g., Gen1, Gen2, Gen3, Gen4) through the physical layer; enumerates the connected endpoint devices 20, identifies their device type and function, and allocates a base address register (BAR) address space for the endpoint devices 20 to establish the address mapping relationship between the root complex device 10 and the endpoint devices 20; and enables the direct memory access (DMA) permission of the endpoint devices 20.

[0074] Endpoint device 20 responds to the training sequence sent by root complex device 10, completes physical layer synchronization, and establishes a stable data link. After the link is established, local processor 900 receives an interrupt signal generated by notification module 500 and then prepares configuration data. Endpoint device 20 receives the BAR address allocated by root complex device 10 and initializes the DMA channel according to the allocated BAR address.

[0075] Data communication phase: After the link is established, the root complex device 10 accesses the registers of the endpoint device 20 through memory read / write transactions to read the status, configure parameters, and control the functions of the endpoint device 20; the endpoint device 20 directly reads and writes system memory through DMA to achieve high-speed data transmission without the need for successive intervention from the root complex device 10; the root complex device 10 and the endpoint device 20 communicate via message signal interrupt (MSI) or MSI-X interrupt to ensure that both parties can respond to each other's data transmission requests in a timely manner and complete the sending and receiving of business data.

[0076] This embodiment provides a PCIe reset signal processing method, which can be applied to PCIe chips with dual-role capabilities, enabling the chip to flexibly switch between RC mode and EP mode, and adapt to the PCIe reset signal processing flow in different modes. The PCIe reset signal processing method includes the following steps: Step S1: Obtain the mode indication signal.

[0077] This mode indicator signal is used to indicate whether the chip is currently in RC mode or EP mode.

[0078] Step S2: Perform input routing control according to the mode indication signal.

[0079] The specific input selection control logic is as follows: When the mode indicator signal indicates EP mode, the first PCIe reset signal from outside the chip is selected as the input of the reset generation module; when the mode indicator signal indicates RC mode, the first PCIe reset signal is disabled (or a high-level signal is selected as the input of the reset generation module to provide an invalid reset state). The specific implementation of this step can be found in the input gating module 200 in the aforementioned circuit embodiment, and will not be repeated here.

[0080] Step S3: Generate a second PCIe reset signal based on the first reset source input and the local reset source input, and output the second PCIe reset signal to the local PCIe controller.

[0081] The specific implementation of the reset generation logic in step S3 can be found in the reset generation module 300 in the aforementioned circuit embodiment, and will not be repeated here. The first reset source input corresponds to the first reset source input terminal 301 of the reset generation module 300; the local reset source input corresponds to at least one second reset source input terminal (e.g., 302, 303) of the reset generation module 300.

[0082] It should be noted that the local reset source input is optional, and may include zero or one or more local reset control signals in different implementations. This embodiment does not limit this.

[0083] Step S4: Perform output control according to the mode indication signal.

[0084] The output control logic is as follows: when the mode indicator signal indicates RC mode, a second PCIe reset signal is output to the external circuit; when the mode indicator signal indicates EP mode, the output of the second PCIe reset signal to the external circuit is disabled. The specific implementation of this step can be found in the output control module 400 in the aforementioned circuit embodiment, and will not be repeated here.

[0085] In an optional embodiment, the method further includes step S5: when the mode indication signal indicates EP mode, an interrupt signal is generated based on the first PCIe reset signal to notify the local processor. The specific implementation of this step can be found in the notification module 500 in the aforementioned circuit embodiment, and will not be repeated here.

[0086] In an optional embodiment, before performing step S3, the method further includes a filtering step: filtering the first PCIe reset signal from outside the chip selected in step S2, and using the filtered first PCIe reset signal as the input to step S3. The specific implementation of this step can be found in the filtering logic module 600 in the aforementioned circuit embodiment, and will not be repeated here.

[0087] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the descriptions of the above embodiments are only for the purpose of helping to understand the methods of the embodiments of this application and should not be construed as limiting the embodiments of this application. Any changes or substitutions that can be made by those skilled in the art should be covered within the protection scope of the embodiments of this application.

Claims

1. A PCIe reset signal processing circuit, characterized in that, The processing circuit, applied to a PCIe dual-role chip, includes: External signal ports; An input gating module is provided, wherein the first input terminal of the input gating module is connected to the external signal port to receive a first PCIe reset signal from the external source; the mode configuration terminal of the input gating module is used to receive a mode indication signal; and the input gating module outputs or disables the output of the first PCIe reset signal based on the mode indication signal. A reset generation module includes a first reset source input terminal and at least one second reset source input terminal. The first reset source input terminal is connected to the output terminal of the input gating module, and the second reset source input terminal is used to receive a local reset control signal. The reset generation module is used to generate a second PCIe reset signal when any input signal is valid. The output terminal of the reset generation module is connected to a local PCIe controller. An output control module is provided, wherein the input terminal of the output control module is connected to the output terminal of the reset generation module, and the output terminal of the output control module is connected to the external signal port; the control terminal of the output control module is used to receive the mode indication signal, and the output control module outputs or disables the output of the second PCIe reset signal based on the mode indication signal. Specifically, when the input gating module outputs the first PCIe reset signal, the output control module disables the output of the second PCIe reset signal; when the input gating module disables the output of the first PCIe reset signal, the output control module outputs the second PCIe reset signal.

2. The processing circuit according to claim 1, characterized in that, The chip includes a local processor; The processing circuit further includes a notification module, the input of which is connected to the output of the input gating module, for providing the local processor with the state change of the first PCIe reset signal according to the signal output by the input gating module.

3. The processing circuit according to claim 2, characterized in that, The notification module includes an interrupt generation module, which generates an interrupt signal when an edge transition of the first PCIe reset signal is detected, in order to notify the local processor.

4. The processing circuit according to claim 2, characterized in that, The notification module includes a status register, the status value of which is updated according to the first PCIe reset signal for query by the local processor.

5. The processing circuit according to claim 3, characterized in that, The notification module includes an enable terminal, which is used to receive the mode indication signal and output or disable the output of the interrupt signal based on the mode indication signal.

6. The processing circuit according to claim 1, characterized in that, The processing circuit further includes a filtering logic module, which is connected between the output terminal of the input gating module and the first reset source input terminal of the reset generation module. The filtering logic module is used to perform filtering processing on the first PCIe reset signal output by the input gating module and output the filtered first PCIe reset signal to the reset generation module.

7. The processing circuit according to claim 6, characterized in that, The filtering logic module includes a parameter configuration register, which is used to receive and store filtering time window configuration information, and the filtering time window configuration information is used to determine the time length of the filtering time window of the filtering logic module.

8. The processing circuit according to any one of claims 1 to 7, characterized in that, The input gating module also has a second input terminal, which is connected to a high-level signal. Specifically, the input gating module is used to select and output the first PCIe reset signal or the high-level signal according to the mode indication signal.

9. A chip, characterized in that, Includes a PCIe reset signal processing circuit and a PCIe controller as described in any one of claims 1 to 8.

10. A PCIe system, characterized in that, This includes root complex equipment and endpoint equipment; The root complex device includes a PCIe reset signal processing circuit as described in any one of claims 1 to 8, wherein the PCIe reset signal processing circuit in the root complex device operates in RC mode; in the root complex device: the mode indication signal indicates that the current operating mode is RC mode; the input gating module, based on the mode indication signal, disables the output of the first PCIe reset signal; and the output control module, based on the mode indication signal, outputs the second PCIe reset signal. The endpoint device includes a PCIe reset signal processing circuit as described in any one of claims 1 to 8, wherein the PCIe reset signal processing circuit in the endpoint device operates in EP mode; in the endpoint device: the mode indication signal indicates that the current operating mode is EP mode, the input gating module outputs the first PCIe reset signal based on the mode indication signal; the output control module disables the output of the second PCIe reset signal based on the mode indication signal; Wherein, the second PCIe reset signal of the root complex device is the first PCIe reset signal of the endpoint device.

Images