A computing power expansion module, an integrated chip and a vertical expansion network architecture

Abstract

The application provides a computing power expansion module, an integrated chip and a vertical expansion network architecture, aiming to break through the computing power bottleneck of a single chip. The computing power expansion module is arranged between a switching chip and other chips (such as computing or storage chips), and includes a first adapter plate, a second adapter plate and a spatial optical communication module arranged on the same side. The spatial optical communication module realizes high-speed optical communication between chips by emitting and receiving laser, replaces traditional electrical interconnection, and reduces delay and power consumption. The integrated chip integrates multiple computing power expansion modules, switching chips and other chips on the same carrier, supports flexible optical path layout and chip cooperation. The vertical expansion network architecture adopts multiple integrated chips to form a computing power cluster, forming a high-performance computing system similar to a powerful single computer, meeting the demand for high computing power and efficient cooperation in AI, big data and other scenarios.

Description

Technical Field

[0001] This application relates to the field of computing chip technology, and in particular to a computing power expansion module, an integrated chip, and a vertically expandable network architecture. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence, big data analytics, and high-performance computing, the demand for computing power in computing chips has exploded. In applications such as AI training, scientific computing simulation, and real-time data processing, computing chips need to complete massive data processing tasks in a very short time, which places extremely high demands on the chip's computing speed and data processing capabilities.

[0003] Currently, the industry primarily meets computing power demands by improving the manufacturing process of individual computing chips, increasing the number of cores, or optimizing the architecture design. However, as Moore's Law gradually slows down, chip manufacturing processes are approaching their physical limits, and further improvements in integration and computing speed face multiple technical bottlenecks, including excessive power density, heat dissipation difficulties, and signal latency. Simply relying on upgrades to single chips is no longer sufficient to meet the ever-increasing computing power demands; the physical limitations of chip computing power have become a key factor restricting overall computing performance improvements. Summary of the Invention

[0004] The purpose of this application is to provide a computing power expansion module, an integrated chip, and a vertically expandable network architecture that can solve the above-mentioned problems.

[0005] The embodiments of this application are implemented as follows: In a first aspect, this application discloses a computing power expansion module, which is disposed between an adjacent switching chip and other chips, wherein the other chips are configured to generate and / or store data. The computing power expansion module includes a first adapter board, a second adapter board and a spatial optical communication module disposed on the same side of the carrier. The first adapter plate is provided with a first receiving groove, and the second adapter plate is provided with a second receiving groove, the openings of the first receiving groove and the second receiving groove facing the carrier; The spatial optical communication module is disposed within the space enclosed by the switching chip, the other chips, the first accommodating slot, the second accommodating slot, and the carrier, and is configured to realize optical communication between two adjacent computing chips by emitting and / or receiving lasers.

[0006] It is understandable that the key to overcoming the computing power limitations of a single chip lies in upgrading the electrical interconnects between chips to free-space optical interconnects, bypassing the physical bottlenecks of a single chip. Traditional single-chip computing power is increasingly difficult to improve due to limitations in manufacturing processes, excessively high power density, and severe signal latency. This module embeds a spatial optical communication module between the switching chip and other chips, utilizing mirror-reflected lasers to achieve direct optical communication between chips in free space. This offers three major advantages: first, high bandwidth and low latency, with optical communication performance far exceeding that of electrical interconnects; second, low power consumption and easy heat dissipation, avoiding long-distance loss of high-frequency electrical signals; and third, support for vertical expansion, allowing multiple chips to interconnect at high speed through this module, aggregating computing power and working collaboratively like a powerful "single computer." Therefore, this module effectively stacks and expands computing power by replacing the on-chip electrical bottlenecks with inter-chip optical interconnects.

[0007] In addition, the main functions of the receiving slots (first receiving slot and second receiving slot) include: 1. Providing installation space to accommodate optical emitting units (such as laser chips and driver chips) and optical receiving units (such as photodetector chips and receiver processing chips), and achieving electrical connection with switching chips or other chips through electrical circuits within the slots. 2. Ensuring optical path accuracy. The receiving slots, together with the switching chip, other chips, and the carrier, form a closed space, ensuring that the relative positions of the refractive component and the optical transceiver unit are fixed, improving optical path alignment accuracy, and avoiding signal attenuation. 3. Supporting heat dissipation. A heat dissipation coating can be installed inside the slots to help dissipate heat from the chips and improve system stability.

[0008] In optional embodiments of this application, the other chips include at least one of the following: a computing chip or a memory chip. It is understood that the other chips can be either computing chips or memory chips, enabling the computing power expansion module to flexibly adapt to different types of inter-chip communication. Whether it's data exchange between the processor and memory, or collaborative computation between multiple computing chips, high-speed transmission can be achieved through optical interconnects, thereby improving the overall computing power aggregation efficiency of the system.

[0009] In an optional embodiment of this application, the first surface of the first adapter plate facing the second adapter plate is combined with the second surface of the second adapter plate facing the first adapter plate; the first receiving groove is in communication with the second receiving groove.

[0010] In an optional embodiment of this application, the first adapter plate and the second adapter plate are integrally formed.

[0011] It is understandable that combining or integrating the first and second adapter boards significantly simplifies the module's assembly structure. Compared to a separate design, the combined or integrated approach eliminates assembly gaps between the two, improves optical path alignment accuracy, and avoids signal attenuation caused by relative displacement. Simultaneously, the integrated structure enhances mechanical strength, improves vibration and shock resistance, and helps ensure long-term operational stability. Furthermore, simplified assembly processes reduce manufacturing costs and packaging complexity, facilitating mass production. Overall, this design achieves high-speed inter-chip optical interconnection while improving module reliability and integration, which is beneficial for stable operation in high-density computing clusters. The interconnected mounting slots provide a larger and more coherent installation space for the space optical communication module, facilitating optical path layout, reducing optical path alignment complexity, and thus improving optical transmission efficiency and module reliability.

[0012] In an optional embodiment of this application, the space optical communication module includes a receiving space optical communication module configured to transmit target data from the other chips to the switching chip; and / or, the space optical communication module includes a transmitting space optical communication module configured to transmit target data from the switching chip to the other chips.

[0013] It is understandable that by setting up receiving and / or transmitting space optical communication modules, a flexible data transmission path is provided between the switching chip and other chips. The receiving module enables other chips to upload data to the switching chip, while the transmitting module enables the switching chip to send data to other chips. The combination of the two supports bidirectional full-duplex communication. Using free-space laser transmission instead of traditional electrical interconnects not only significantly reduces signal latency and power consumption but also avoids PCB trace losses and crosstalk, significantly improving bandwidth density. This design allows multiple chips to efficiently aggregate computing power and work collaboratively like a powerful chip, thereby effectively overcoming the physical performance bottlenecks of a single chip.

[0014] In an optional embodiment of this application, both the receiving space optical communication module and the transmitting space optical communication module include an optical transmitting unit, an optical receiving unit, and a refractive component; the optical transmitting unit is configured to output a target modulated laser beam according to the target data; the refractive component is configured to guide the target modulated laser beam output by the optical transmitting unit into the optical receiving unit through specular reflection in free space.

[0015] It is understandable that integrating the optical transmitting unit, optical receiving unit, and refractive component on the same side of the carrier, and using free-space mirror reflection to guide the laser beam transmission and reception, eliminates the need for optical fiber as the transmission medium. Non-fiber transmission offers significant advantages: First, it avoids the additional losses and signal reflections caused by fiber bending and connector coupling, reducing link budget requirements; second, it eliminates the need for fiber cabling and end-face cleaning and maintenance, simplifying packaging processes and system integration; third, the free-space optical path eliminates the dispersion and nonlinear effects introduced by optical fibers, resulting in better signal integrity. Overall, this design achieves high-speed, low-latency optical communication between chips with lower cost and higher reliability, effectively supporting computing power expansion.

[0016] In an optional embodiment of this application, the refractive assembly includes a refractive element disposed on the carrier, the refractive element having a first reflective surface and a second reflective surface; the first reflective surface is configured to reflect the target modulated laser beam output by the light emitting unit, causing it to exit in a direction parallel to the surface of the carrier; the second reflective surface is configured to reflect the target modulated laser beam incident in a direction parallel to the surface of the carrier, causing it to be guided into the light receiving unit in a direction away from the carrier.

[0017] It is understandable that by integrating a refractive element into the carrier, the vertical and horizontal directions of the laser beam can be converted using the first and second reflective surfaces, enabling inter-chip optical path coupling without the need for optical fibers. This design shortens the optical path, simplifies the alignment process, reduces signal loss and packaging costs, and enhances vibration resistance, providing a compact and reliable solution for high-speed, low-latency inter-chip optical interconnects.

[0018] In an optional embodiment of this application, the refractive component includes a light guide groove disposed on the carrier or other layer structure on the carrier. The light guide groove includes a first inner sidewall and a second inner sidewall disposed opposite to each other. A first reflective surface is disposed on the first inner sidewall, and a second reflective surface is disposed on the second inner sidewall. The first reflective surface is configured to reflect the target modulated laser beam output by the light emitting unit, causing it to exit in a direction parallel to the surface of the carrier. The second reflective surface is configured to reflect the target modulated laser beam incident in a direction parallel to the surface of the carrier, causing it to be guided into the light receiving unit in a direction away from the carrier.

[0019] It is understandable that optical path deflection is achieved through light guide grooves integrated on the carrier or in the layer structure, eliminating the need for independent refractive elements. The reflective surface on the inner sidewall can precisely guide the horizontal transmission and vertical transmission / reception of the laser beam, resulting in a compact structure and good process compatibility. This design reduces assembly complexity, improves integration and alignment reliability, and is suitable for high-density inter-chip optical interconnects.

[0020] In an optional embodiment of this application, in the receiving space optical communication module, the optical transmitting unit is disposed in the first receiving slot and electrically connected to the other chips through electrical connection lines within the first receiving slot; the optical receiving unit is disposed in the second receiving slot and electrically connected to the switching chip through electrical connection lines within the second receiving slot. In the transmitting space optical communication module, the optical transmitting unit is disposed in the second receiving slot and electrically connected to the switching chip through electrical connection lines within the second receiving slot; the optical receiving unit is disposed in the first receiving slot and electrically connected to the other chips through electrical connection lines within the first receiving slot.

[0021] It is understandable that by placing the optical transceiver units in two separate slots and flexibly configuring the electrical connections according to the communication direction, the interchangeability and reuse of the receiving and transmitting modules are achieved. This design simplifies module wiring, shortens the electrical signal path between the chip and optoelectronic devices, improves signal integrity and integration flexibility, and supports bidirectional full-duplex high-speed optical communication.

[0022] In an optional embodiment of this application, the first adapter board is directly bonded to the other chips to achieve electrical connection.

[0023] In an optional embodiment of this application, the second adapter board is directly bonded to the switching chip to achieve electrical connection.

[0024] It is understandable that by directly bonding the first adapter board to other chips and the second adapter board to the switching chip, an intermediate adapter layer is eliminated. Direct bonding shortens the electrical transmission path, reduces parasitic inductance and signal loss, and improves high-speed signal integrity; at the same time, it simplifies the packaging structure, reduces the number of material layers and process steps, which helps to reduce manufacturing costs and improve reliability. These embodiments eliminate the intermediate adapter layer by directly bonding the first adapter board to other chips and the second adapter board to the switching chip. Direct bonding shortens the electrical transmission path, reduces parasitic inductance and signal loss, and improves high-speed signal integrity; at the same time, it simplifies the packaging structure, reduces the number of material layers and process steps, which helps to reduce manufacturing costs and improve reliability.

[0025] In an optional embodiment of this application, an intermediate adapter board is provided between the first adapter board and the other chips. The first adapter board is bonded to the surface of the intermediate adapter board facing the first adapter board, and the surface of the intermediate adapter board facing away from the first adapter board is bonded to the other chips. The intermediate adapter board is provided with conductive vias to connect corresponding solder joints on the two surfaces, so as to realize the electrical connection between the first adapter board and the other chips.

[0026] In an optional embodiment of this application, an intermediate adapter board is provided between the second adapter board and the switching chip. The second adapter board is bonded to the surface of the intermediate adapter board facing the second adapter board, and the surface of the intermediate adapter board facing away from the second adapter board is bonded to the switching chip. The intermediate adapter board is provided with conductive vias to connect corresponding solder points on the two surfaces, so as to realize the electrical connection between the second adapter board and the switching chip.

[0027] It is understandable that by adding intermediate adapter boards between the first adapter board and other chips, and between the second adapter board and the switching chip, vertical interconnection can be achieved using conductive vias. The intermediate adapter boards can act as buffers, reducing stress caused by thermal expansion coefficient mismatch and improving package reliability; at the same time, they facilitate matching solder joints with different spacings, enhancing the flexibility and compatibility of heterogeneous integration.

[0028] In an optional embodiment of this application, the light emitting unit includes a driver chip and a laser chip stacked together, the driver chip being bonded to the first accommodating slot and / or the second accommodating slot, and the laser chip being bonded to the driver chip; the light receiving unit includes a receiving processing chip and a photodetector chip stacked together, the receiving processing chip being bonded to the first accommodating slot and / or the second accommodating slot, and the photodetector chip being bonded to the receiving processing chip; the depth of the first accommodating slot and / or the second accommodating slot is greater than a first depth threshold.

[0029] It is understandable that by stacking the driver chip and laser chip, and the receiving and processing chip and photoelectric detection chip, the planar area occupied by the receiving slot is effectively saved, and the integration density is improved. At the same time, limiting the depth of the receiving slot to be greater than a first depth threshold ensures that there is enough vertical space to accommodate the stacked chips, avoiding chip exposure or packaging conflicts, and enhancing the structural stability and signal transmission reliability of the module.

[0030] In an optional embodiment of this application, the light emitting unit includes a laser chip, which is bonded to the first receiving groove. A driving chip is also disposed on the surface of the first adapter plate opposite to the first receiving groove. The driving chip is electrically connected to the laser chip through a conductive via on the first adapter plate. The depth of the first receiving groove and / or the second receiving groove is less than a first depth threshold and greater than a second depth threshold.

[0031] In an optional embodiment of this application, the light emitting unit includes a laser chip, which is bonded to the second accommodating groove. A driving chip is also disposed on the surface of the second adapter plate opposite to the second accommodating groove. The driving chip is electrically connected to the laser chip through a conductive via on the second adapter plate. The depth of the first accommodating groove and / or the second accommodating groove is less than a first depth threshold and greater than a second depth threshold.

[0032] In an optional embodiment of this application, the light receiving unit includes a photodetector chip, which is bonded to the first receiving groove. A receiving processing chip is also disposed on the surface of the first adapter plate opposite to the first receiving groove. The receiving processing chip is electrically connected to the photodetector chip through a conductive via on the first adapter plate. The depth of the first receiving groove and / or the second receiving groove is less than a first depth threshold and greater than a second depth threshold.

[0033] In an optional embodiment of this application, the light receiving unit includes a photodetector chip, which is bonded to the second accommodating groove. A receiving processing chip is also disposed on the surface of the second adapter plate opposite to the second accommodating groove. The receiving processing chip is electrically connected to the photodetector chip through a conductive via on the second adapter plate. The depth of the first accommodating groove and / or the second accommodating groove is less than a first depth threshold and greater than a second depth threshold.

[0034] As can be understood, unlike the stacked configuration where all chips are piled up in a slot, this series of embodiments adopts a "split" layout: only the laser chip or photodetector chip is placed in a shallower receiving slot (depth between two thresholds), while the driver chip or receiving / processing chip is placed on the back of the adapter board, and vertical interconnection is achieved through conductive vias. The beneficial effects of this mounting scheme include: first, it reduces the requirement for the depth of the receiving slot, simplifies the difficulty of processes such as etching, and helps improve yield; second, it externalizes the driver / processing chip, which generates a lot of heat, improving heat dissipation conditions; and third, it reduces the number of chip stacking layers in the slot, reduces packaging stress and signal crosstalk risks, and enhances the long-term reliability of the module.

[0035] In an optional embodiment of this application, the sum of the first depth threshold and the thickness of the other chips is recorded as a first calculated value; or, the sum of the first depth threshold and the thickness of the switching chip is recorded as a first calculated value; the thickness of the light emitting unit or the thickness of the light receiving unit is recorded as a second calculated value; the thickness of the refractive component exposed on the carrier surface is recorded as a third calculated value; the first calculated value is greater than the sum of the second calculated value and the third calculated value.

[0036] It is understandable that by limiting the first calculated value (the sum of the accommodating slot depth and the chip thickness) to be greater than the sum of the second and third calculated values, it is ensured that the refractive component can complete optical path coupling without interference after the chip is installed. This dimensional constraint avoids mechanical collisions between the optical transceiver unit and the refractive component, ensures optical path alignment accuracy, and improves the feasibility and yield of packaging.

[0037] In an optional embodiment of this application, a heat dissipation coating is provided in the first receiving groove and the second receiving groove, and there is a preset distance between the heat dissipation coating and the electrical connection line.

[0038] It is understandable that placing a heat-dissipating coating within the housing slot can effectively and quickly dissipate the heat generated by the light emitting / receiving unit, reducing the chip junction temperature and improving the module's operational stability and lifespan. Simultaneously, maintaining a preset distance between the heat-dissipating coating and electrical connection lines avoids the risk of short circuits caused by the coating, thus balancing heat dissipation efficiency and electrical safety.

[0039] Secondly, this application discloses an integrated chip, including a carrier and at least one computing power expansion module as described in any of the first aspects, at least one switching chip, and at least one other chip for generating and / or storing data, disposed on the same side of the carrier, wherein each computing power expansion module is disposed between adjacent switching chips and other chips.

[0040] It is understandable that traditional single-chip systems are limited by process technology and power consumption, making it difficult to infinitely improve performance. This integrated chip, however, integrates multiple switching chips, multiple computing / storage chips, and computing power expansion modules located on the same side of the carrier. Each computing power expansion module utilizes free-space lasers to establish high-speed, low-latency, and low-power optical communication channels between adjacent chips. This allows multiple relatively small-scale chips to work closely together through optical interconnects, aggregating into a logically powerful computing unit. Through parallel processing and efficient data flow, the overall computing power of this integrated chip is no longer limited by the physical limits of a single chip, but can be flexibly expanded by increasing the number of chips and the optical interconnect bandwidth, thus effectively breaking through the computing power bottleneck of traditional single-chip systems.

[0041] In an optional embodiment of this application, the switching chip and the other chips are all bare chips, the carrier is a circuit board, the bare chips are electrically connected to the surface of the circuit board, and the circuit board is provided with a refractive component as described in any of the above claims.

[0042] Understandably, directly mounting the bare die onto the circuit board surface eliminates the need for a chip package, shortens electrical interconnection paths, and reduces parasitic parameters and signal delay. Simultaneously, integrating the refractive component onto the circuit board, in coordination with the bare die layout, enables high-density integration. The overall solution balances low cost, miniaturization, and high-speed optical communication performance, facilitating large-scale applications.

[0043] In an optional embodiment of this application, the switching chip and the other chips are all bare chips, the carrier is a carrier substrate, and the carrier substrate is provided with at least one light guide carrier plate and at least two circuit boards; a single bare chip is soldered on each of the circuit boards, and each light guide carrier plate is provided with a refractive component as described in any of the above.

[0044] It is understandable that a carrier substrate is used to integrate multiple circuit boards and light guide carrier boards, with each circuit board having a single bare core soldered onto it, and the light guide carrier board having an independently installed refractive assembly. This modular design facilitates individual testing and replacement of each bare core and its optical path, reducing maintenance difficulty. Simultaneously, the separate layout of the light guide and circuit boards optimizes the space allocation for optical paths and electrical traces, which helps improve signal integrity and reduce crosstalk.

[0045] In an optional embodiment of this application, the other chip is a calculator circuit board carrying a bare computing chip and its peripheral auxiliary circuits; the switching chip is a switch circuit board carrying a bare switching chip and its peripheral auxiliary circuits; the carrier is a substrate, and the calculator circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described in any of the above claims.

[0046] It is understandable that integrating computing and switching chips onto a circuit board with peripheral auxiliary circuitry facilitates independent testing and mass production. The substrate integrates a refractive component, enabling free-space optical interconnection between boards, achieving high-speed communication capabilities without the need for high-precision mounting of bare chips. This solution balances ease of engineering and performance scalability requirements, lowering the barrier to system integration.

[0047] In an optional embodiment of this application, the other chip is a memory circuit board carrying a bare memory chip and its peripheral auxiliary circuits; the switching chip is a switch circuit board carrying a bare switch chip and its peripheral auxiliary circuits; the carrier is a substrate, and the memory circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described in any of the above claims.

[0048] It is understandable that integrating the bare memory chip and its peripheral circuits into the memory circuit board and the switch circuit board respectively facilitates independent testing and standardized production. The substrate integrates a refractive component, enabling free-space optical interconnection between boards, avoiding the losses and crosstalk of traditional long-distance electrical interconnections on PCBs. This solution is beneficial for building high-capacity, high-bandwidth storage and switching networks, improving the computing power aggregation efficiency of data-intensive applications.

[0049] In an optional embodiment of this application, the switching chip includes a single-sided switching chip and a multi-sided switching chip; the single-sided switching chip sends target data to other chips or receives target data from other chips through the computing power expansion module; the multi-sided switching chip sends target data to other chips through the first computing power expansion module and also receives target data from another chip through the second computing power expansion module.

[0050] It is understandable that differentiating between single-sided and multi-sided switching chips provides a flexible data exchange topology. Single-sided switching chips are suitable for point-to-point unidirectional transmission, simplifying design; multi-sided switching chips can simultaneously perform bidirectional transmission and reception with multiple other chips, supporting complex network structures. The combination of the two enables the construction of efficient and scalable inter-chip optical interconnect architectures on demand, optimizing the communication efficiency of computing clusters.

[0051] Thirdly, this application discloses a vertically scalable network architecture, which employs a computing power cluster composed of multiple integrated chips as described in any one of the second aspects.

[0052] The vertically scalable network architecture disclosed in the third aspect of this application can be a scale-up architecture. A scale-up architecture refers to improving system performance by enhancing the computing power of individual nodes (such as increasing CPU / memory or integrating more chips), rather than increasing the number of nodes. The scale-up architecture in this application uses inter-chip optical interconnect technology to interconnect multiple integrated chips at high speed, aggregating computing power and enabling them to work collaboratively like a powerful "single computer" to meet the demands of high-performance computing. This architecture, by employing multiple of the aforementioned integrated chips to build a high-density computing cluster, aims to meet the core requirements of computing power aggregation and efficient collaboration in large-scale parallel computing scenarios.

[0053] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, optional embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0054] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a top view of the first integrated chip provided in this application.

[0056] Figure 2 yes Figure 1 The first dashed cross-sectional view of the integrated chip shown.

[0057] Figure 3 yes Figure 1 The second dashed cross-sectional view of the integrated chip shown.

[0058] Figure 4 yes Figure 1 The third dashed cross-sectional view of the integrated chip shown.

[0059] Figure 5 yes Figure 1 The fourth dashed cross-sectional view of the integrated chip shown.

[0060] Figure 6 yes Figure 1 The fifth dashed cross-sectional view of the integrated chip shown.

[0061] Figure 7 yes Figure 1 The sixth dashed cross-sectional view of the integrated chip shown.

[0062] Figure 8 yes Figure 1 The seventh dashed cross-sectional view of the integrated chip shown. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0064] In a first aspect, this application discloses a computing power expansion module, which is disposed between an adjacent switching chip and other chips. The other chips are configured to generate and / or store data. The computing power expansion module includes a first adapter board, a second adapter board, and a spatial optical communication module disposed on the same side of the carrier. The first adapter plate is provided with a first receiving groove, and the second adapter plate is provided with a second receiving groove. The openings of the first receiving groove and the second receiving groove face the carrier. The spatial optical communication module is located in the space enclosed by the switching chip, other chips, the first accommodating slot, the second accommodating slot, and the carrier, and is configured to realize optical communication between two adjacent computing chips by emitting and / or receiving lasers.

[0065] It is understandable that the key to overcoming the computing power limitations of a single chip lies in upgrading the electrical interconnects between chips to free-space optical interconnects, bypassing the physical bottlenecks of a single chip. Traditional single-chip computing power is increasingly difficult to improve due to limitations in manufacturing processes, excessively high power density, and severe signal latency. This module embeds a spatial optical communication module between the switching chip and other chips, utilizing mirror-reflected lasers to achieve direct optical communication between chips in free space. This offers three major advantages: first, high bandwidth and low latency, with optical communication performance far exceeding that of electrical interconnects; second, low power consumption and easy heat dissipation, avoiding long-distance loss of high-frequency electrical signals; and third, support for vertical expansion, allowing multiple chips to interconnect at high speed through this module, aggregating computing power and working collaboratively like a powerful "single computer." Therefore, this module effectively stacks and expands computing power by replacing the on-chip electrical bottlenecks with inter-chip optical interconnects.

[0066] In addition, the main functions of the receiving slots (first receiving slot and second receiving slot) include: 1. Providing installation space to accommodate optical emitting units (such as laser chips and driver chips) and optical receiving units (such as photodetector chips and receiver processing chips), and achieving electrical connection with switching chips or other chips through electrical circuits within the slots. 2. Ensuring optical path accuracy. The receiving slots, together with the switching chip, other chips, and the carrier, form a closed space, ensuring that the relative positions of the refractive component and the optical transceiver unit are fixed, improving optical path alignment accuracy, and avoiding signal attenuation. 3. Supporting heat dissipation. A heat dissipation coating can be installed inside the slots to help dissipate heat from the chips and improve system stability.

[0067] In optional embodiments of this application, other chips include at least one of the following: computing chips or storage chips.

[0068] In this embodiment, the other chips can be computing chips or storage chips, specifically including the following situations: First, the other chips are computing chips. Examples include central processing units (CPUs), graphics processing units (GPUs), neural network processors (NPUs), tensor processors (TPUs), field-programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs). In this case, the computing power expansion module is used to establish a high-speed optical communication link between the switching chip and the computing chip, enabling data collaboration and aggregation among multiple computing chips. This allows multiple computing chips to work in parallel as a single logical unit, thereby breaking through the single-chip computing power limit and meeting the needs of high-performance scenarios such as AI training and scientific computing. Second, the other chips are storage chips. Examples include high-bandwidth memory (HBM), dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory (NVM). In this case, the optical interconnect module is used for high-speed data access between the switching chip and the storage chip, solving the bottlenecks of traditional electrical interconnects in terms of storage bandwidth, access latency, and power consumption, and improving data throughput efficiency. Third, the other chips simultaneously include computing chips and storage chips. Multiple computing chips and storage chips can be heterogeneously integrated through switching chips and optical interconnect modules. The switching chip can be connected to both chips through optical interconnect modules to achieve flexible scheduling and efficient collaboration of computing and storage resources, and build a high-density, low-latency computing and storage unit.

[0069] It is understandable that other chips can be computing chips or storage chips, enabling the computing power expansion module to flexibly adapt to inter-chip communication of different types. Whether it is data exchange between the processor and memory, or collaborative computing between multiple computing chips, high-speed transmission can be achieved through optical interconnects, thereby improving the overall computing power aggregation efficiency of the system.

[0070] The following explanation uses a computing chip as an example.

[0071] like Figure 1 As shown, a first computing power expansion module 800, disposed between the first computing chip 1 and the switching chip 3, is configured to realize data transmission between the first computing chip 1 and the switching chip 3. A second computing power expansion module 900, disposed between the switching chip 3 and the second computing chip 2, is configured to realize data transmission between the switching chip 3 and the second computing chip 2.

[0072] like Figure 1 The switching chip 3 is configured to receive target data from the first computing chip 1 through the first computing power expansion module 800, process the target data according to a preset protocol, and then transmit the processed target data to the second computing chip 2 through the second computing power expansion module 900 according to a preset path, thereby realizing the data flow between the first computing chip 1 and the second computing chip 2.

[0073] The above-mentioned processing of target data according to a preset protocol includes protocol conversion or data reassembly of the target data; the preset path includes a preset routing strategy or target address information to determine the transmission path.

[0074] Switching chip 3 is the core of the inter-chip optical interconnect. It is responsible for receiving data from one computing chip, performing protocol conversion or data reassembly, and accurately forwarding it to another computing chip according to a preset routing strategy. It enables efficient collaboration and data aggregation among multiple chips, thereby breaking through the physical limitations of a single chip and serving as a key hub for building high-performance computing clusters.

[0075] The internal structure of the second computing power expansion module 900 is similar to that of the first computing power expansion module 800. The following detailed explanation will take the first computing power expansion module 800, which is located between the first computing chip 1 and the switching chip 3, as an example. Figure 2 As shown, the first computing power expansion module 800 includes a first adapter plate 10, a second adapter plate 20, and a spatial optical communication module 30, all disposed on the same side of the circuit board 500 (i.e., the carrier). The first adapter plate 10 has a first receiving groove 11 on its surface facing the circuit board 500, and the second adapter plate 20 has a second receiving groove 21 on its surface facing the circuit board 500. Because... Figure 2 yes Figure 1 The dashed cross-section only shows the location of the receiving space optical communication module 31. Since the other optical communication modules within the space optical communication module are all arranged side-by-side between the two computing chips, Figure 2 The location of the receiving space optical communication module 31 can also indicate the location of the space optical communication module 30. The space optical communication module 30 is disposed in the space enclosed by the first computing chip 1, the switching chip 3, the first accommodating slot 11, and the second accommodating slot 21, and is configured to emit and / or receive lasers by means of mirror reflection, so as to realize optical communication between the first computing chip 1 and the switching chip 3 in free space.

[0076] In an optional embodiment of this application, the first surface of the first adapter plate facing the second adapter plate is combined with the second surface of the second adapter plate facing the first adapter plate; the first receiving groove is connected to the second receiving groove.

[0077] In an optional embodiment of this application, the first adapter plate and the second adapter plate are integrally formed.

[0078] like Figure 6 As shown, the first adapter board 10 and the second adapter board 20 are connected to form an integral adapter board 100. The two ends of the integral adapter board 100 are fixed to the first computing chip 1 and the switching chip 3, respectively. The first accommodating slot 11 and the second accommodating slot 21 are connected to form an integral accommodating slot 300.

[0079] It is understandable that combining or integrating the first and second adapter boards significantly simplifies the module's assembly structure. Compared to a separate design, the combined or integrated approach eliminates assembly gaps between the two, improves optical path alignment accuracy, and avoids signal attenuation caused by relative displacement. Simultaneously, the integrated structure enhances mechanical strength, improves vibration and shock resistance, and helps ensure long-term operational stability. Furthermore, simplified assembly processes reduce manufacturing costs and packaging complexity, facilitating mass production. Overall, this design achieves high-speed inter-chip optical interconnection while improving module reliability and integration, which is beneficial for stable operation in high-density computing clusters. The interconnected mounting slots provide a larger and more coherent installation space for the space optical communication module, facilitating optical path layout, reducing optical path alignment complexity, and thus improving optical transmission efficiency and module reliability.

[0080] In an optional embodiment of this application, the space optical communication module includes a receiving space optical communication module configured to transmit target data from other chips to the switching chip; and / or, the space optical communication module includes a transmitting space optical communication module configured to transmit target data from the switching chip to other chips.

[0081] In optional embodiments of this application, such as Figure 1 As shown, the space optical communication module 30 includes a receiving space optical communication module 31, configured to transmit a first target data from the first computing chip 1 to the switching chip 3. The space optical communication module 30 also includes a transmitting space optical communication module 32, configured to transmit a second target data from the switching chip 3 to the first computing chip 1.

[0082] It is understandable that by setting up receiving and / or transmitting space optical communication modules, a flexible data transmission path is provided between the switching chip and other chips. The receiving module enables other chips to upload data to the switching chip, while the transmitting module enables the switching chip to send data to other chips. The combination of the two supports bidirectional full-duplex communication. Using free-space laser transmission instead of traditional electrical interconnects not only significantly reduces signal latency and power consumption but also avoids PCB trace losses and crosstalk, significantly improving bandwidth density. This design allows multiple chips to efficiently aggregate computing power and work collaboratively like a powerful chip, thereby effectively overcoming the physical performance bottlenecks of a single chip.

[0083] In an optional embodiment of this application, both the receiving space optical communication module and the transmitting space optical communication module include an optical transmitting unit, an optical receiving unit, and a refractive component; the optical transmitting unit is configured to output a target modulated laser beam according to target data; the refractive component is configured to guide the target modulated laser beam output by the optical transmitting unit into the optical receiving unit through mirror reflection in free space.

[0084] like Figure 2 As shown, the receiving space optical communication module 31 includes components disposed on a carrier (such as...). Figure 2 The circuit board 500 contains a light emitting unit 41, a light receiving unit 42, and a refractive assembly 43 on the same side. The light emitting unit 41 is configured to output a target-modulated laser beam based on first target data. The refractive assembly 43 is configured to guide the target-modulated laser beam output by the light emitting unit into the light receiving unit 42 through mirror reflection in free space. The light emitting unit 41 is disposed in the first receiving slot 11 and is electrically connected to the first computing chip 1 through electrical connection lines on the first adapter board 10. The light receiving unit 42 is disposed in the second receiving slot 21 and is electrically connected to the switching chip 3 through electrical connection lines on the second adapter board 20.

[0085] The structure of the transmitting space optical communication module 32 is consistent with that of the receiving space optical communication module 31, also including a light emitting unit, a light receiving unit, and a refractive assembly disposed on the same side of the carrier. However, the light emitting unit is configured to output a target-modulated laser beam based on the second target data. The light emitting unit of the transmitting space optical communication module 32 is disposed on the second receiving slot 21 and emits light toward the circuit board 500, and is electrically connected to the switching chip 3 through the electrical connection lines on the second adapter board 20. The light receiving unit of the transmitting space optical communication module 32 is disposed on the first receiving slot 11 and is electrically connected to the first computing chip 1 through the electrical connection lines on the first adapter board 10. The structure of the refractive assembly in the transmitting space optical communication module 32 is the same as that in the receiving space optical communication module 31.

[0086] It is understandable that integrating the optical transmitting unit, optical receiving unit, and refractive component on the same side of the carrier, and using free-space mirror reflection to guide the laser beam transmission and reception, eliminates the need for optical fiber as the transmission medium. Non-fiber transmission offers significant advantages: First, it avoids the additional losses and signal reflections caused by fiber bending and connector coupling, reducing link budget requirements; second, it eliminates the need for fiber cabling and end-face cleaning and maintenance, simplifying packaging processes and system integration; third, the free-space optical path eliminates the dispersion and nonlinear effects introduced by optical fibers, resulting in better signal integrity. Overall, this design achieves high-speed, low-latency optical communication between chips with lower cost and higher reliability, effectively supporting computing power expansion.

[0087] In optional embodiments of this application, such as Figure 4 As shown, the refractive assembly 43 includes a refractive element disposed on a carrier, and the refractive element is provided with a first reflective surface 431 and a second reflective surface 432; the first reflective surface 431 is configured to reflect the target modulated laser beam output by the light emitting unit 41, so that it is emitted in a direction parallel to the surface of the circuit board 500; the second reflective surface 432 is configured to reflect the target modulated laser beam incident in a direction parallel to the surface of the circuit board 500, so that it is guided into the light receiving unit 42 in a direction away from the carrier.

[0088] It is understandable that by integrating a refractive element into the carrier, the vertical and horizontal directions of the laser beam can be converted using the first and second reflective surfaces 432, enabling inter-chip optical path coupling without the need for optical fibers. This design shortens the optical path, simplifies the alignment process, reduces signal loss and packaging costs, and enhances vibration resistance, providing a compact and reliable solution for high-speed, low-latency inter-chip optical interconnects.

[0089] In an optional embodiment of this application, the refractive component includes a light guide groove disposed on a carrier or other layered structure on the carrier. For example... Figure 2 As shown, a light guide groove is provided on the circuit board 500, which serves as the carrier; as Figure 7 As shown, light guide grooves are provided on the first light guide carrier 602 and the second light guide carrier 604 on the carrier substrate 200. The light guide groove includes a first inner sidewall and a second inner sidewall disposed opposite to each other. A first reflective surface 431 is provided on the first inner sidewall, and a second reflective surface 432 is provided on the second inner sidewall. The first reflective surface 431 is configured to reflect the target modulated laser beam output by the light emitting unit, so that it is emitted in a direction parallel to the carrier surface. The second reflective surface 432 is configured to reflect the target modulated laser beam incident in a direction parallel to the carrier surface, so that it is guided into the light receiving unit in a direction away from the carrier.

[0090] It is understandable that optical path deflection is achieved through light guide grooves integrated on the carrier or in the layer structure, eliminating the need for independent refractive elements. The reflective surface on the inner sidewall can precisely guide the horizontal transmission and vertical transmission / reception of the laser beam, resulting in a compact structure and good process compatibility. This design reduces assembly complexity, improves integration and alignment reliability, and is suitable for high-density inter-chip optical interconnects.

[0091] In optional embodiments of this application, such as Figure 2 As shown, in the receiving space optical communication module 31, the optical transmitting unit 41 is disposed in the first receiving slot 11 and electrically connected to the first computing chip 1 through the electrical connection lines within the first receiving slot 11. The optical receiving unit 42 is disposed in the second receiving slot 22 and electrically connected to the switching chip 3 through the electrical connection lines within the second receiving slot 22. The structure of the transmitting space optical communication module 32 is the same as that of the receiving space optical communication module 31, but the optical transmitting unit of the transmitting space optical communication module 32 is disposed in the second receiving slot 21 and electrically connected to the switching chip 3 through the electrical connection lines within the second receiving slot 21, and the optical receiving unit is disposed in the first receiving slot 11 and electrically connected to the first computing chip 1 through the electrical connection lines within the first receiving slot 11.

[0092] It is understandable that by placing the optical transceiver units in two separate slots and flexibly configuring the electrical connections according to the communication direction, the interchangeability and reuse of the receiving and transmitting modules are achieved. This design simplifies module wiring, shortens the electrical signal path between the chip and optoelectronic devices, improves signal integrity and integration flexibility, and supports bidirectional full-duplex high-speed optical communication.

[0093] In an optional embodiment of this application, the first adapter board is directly bonded to other chips to achieve electrical connection.

[0094] In an optional embodiment of this application, the second adapter board is directly bonded to the switching chip to achieve electrical connection.

[0095] It is understandable that by directly bonding the first adapter board to other chips and the second adapter board to the switching chip, an intermediate adapter layer is eliminated. Direct bonding shortens the electrical transmission path, reduces parasitic inductance and signal loss, and improves high-speed signal integrity; at the same time, it simplifies the packaging structure, reduces the number of material layers and process steps, which helps to reduce manufacturing costs and improve reliability. These embodiments eliminate the intermediate adapter layer by directly bonding the first adapter board to other chips and the second adapter board to the switching chip. Direct bonding shortens the electrical transmission path, reduces parasitic inductance and signal loss, and improves high-speed signal integrity; at the same time, it simplifies the packaging structure, reduces the number of material layers and process steps, which helps to reduce manufacturing costs and improve reliability.

[0096] In an optional embodiment of this application, an intermediate adapter board is provided between the first adapter board and other chips. The first adapter board is bonded to the surface of the intermediate adapter board facing the first adapter board, and the surface of the intermediate adapter board facing away from the first adapter board is bonded to other chips. The intermediate adapter board is provided with conductive vias to connect corresponding solder points on the two surfaces, so as to realize the electrical connection between the first adapter board and other chips.

[0097] In an optional embodiment of this application, an intermediate adapter board is provided between the second adapter board and the switching chip. The second adapter board is bonded to the surface of the intermediate adapter board facing the second adapter board, and the surface of the intermediate adapter board facing away from the second adapter board is bonded to the switching chip. The intermediate adapter board is provided with conductive vias to connect corresponding solder points on the two surfaces, so as to realize the electrical connection between the second adapter board and the switching chip.

[0098] like Figure 5 As shown, a first intermediate adapter plate 81 is provided between the first adapter plate 10 and the first computing chip 1. The first adapter plate 10 is bonded to the surface of the first intermediate adapter plate 81 facing the first adapter plate 10, and the surface of the first intermediate adapter plate 81 facing away from the first adapter plate 10 is bonded to the first computing chip 1. The first intermediate adapter plate 81 is provided with conductive through holes to connect corresponding solder points on the two surfaces, so as to realize the electrical connection between the first adapter plate 10 and the first computing chip 1.

[0099] like Figure 5 As shown, a second intermediate adapter plate 82 is provided between the second adapter plate 20 and the switching chip 3. The second adapter plate 20 is bonded to the surface of the second intermediate adapter plate 82 facing the second adapter plate 20, and the surface of the second intermediate adapter plate 82 facing away from the second adapter plate 20 is bonded to the switching chip. The second intermediate adapter plate 82 is provided with conductive through holes to connect corresponding solder points on the two surfaces, so as to realize the electrical connection between the second adapter plate 20 and the switching chip 3.

[0100] It is understandable that by adding intermediate adapter boards between the first adapter board and other chips, and between the second adapter board and the switching chip, vertical interconnection can be achieved using conductive vias. The intermediate adapter boards can act as buffers, reducing stress caused by thermal expansion coefficient mismatch and improving package reliability; at the same time, they facilitate matching solder joints with different spacings, enhancing the flexibility and compatibility of heterogeneous integration.

[0101] In an optional embodiment of this application, the light emitting unit includes a driver chip and a laser chip stacked together, the driver chip being bonded to a first accommodating groove and / or a second accommodating groove, and the laser chip being bonded to the driver chip; the light receiving unit includes a receiving processing chip and a photodetector chip stacked together, the receiving processing chip being bonded to the first accommodating groove and / or the second accommodating groove, and the photodetector chip being bonded to the receiving processing chip; the depth of the first accommodating groove and / or the second accommodating groove is greater than a first depth threshold.

[0102] like Figure 2 As shown, in the receiving space optical communication module 31, the optical transmitting unit 41 includes a driver chip 52 and a laser chip 51 stacked together. The driver chip 52 is bonded to the first receiving groove 11, and the laser chip 51 is bonded to the driver chip 52. The optical receiving unit 42 includes a receiving processing chip 62 and a photodetector chip 61 stacked together. The receiving processing chip 62 is bonded to the second receiving groove 21, and the photodetector chip 61 is bonded to the receiving processing chip 62. The transmitting space optical communication module 32 has a similar structure to the receiving space optical communication module 31. In the transmitting space optical communication module 32, the laser chip is also bonded to the driver chip, but the driver chip is bonded to the second receiving groove 21. In the transmitting space optical communication module 32, the photodetector chip is also bonded to the receiving processing chip, but the receiving processing chip is bonded to the first receiving groove 11.

[0103] Preferably, the first depth threshold is equal to the thickness of the light emitting unit (i.e., the sum of the thicknesses of the driving chip and the laser chip) or the thickness of the light receiving unit (i.e., the sum of the thicknesses of the receiving processing chip and the photoelectric detection chip), ensuring that the chip group is completely embedded in the slot and avoiding protrusions from the carrier surface that could affect the optical path coupling and the flatness of the module packaging.

[0104] It is understandable that by stacking the driver chip and laser chip, and the receiving and processing chip and photoelectric detection chip, the planar area occupied by the receiving slot is effectively saved, and the integration density is improved. At the same time, limiting the depth of the receiving slot to be greater than a first depth threshold ensures that there is enough vertical space to accommodate the stacked chips, avoiding chip exposure or packaging conflicts, and enhancing the structural stability and signal transmission reliability of the module.

[0105] In optional embodiments of this application, such as Figure 3 As shown, in the receiving spatial optical communication module 31, the optical emitting unit 41 includes a laser chip 51, which is bonded to the first receiving groove 11. A driving chip 52 is also disposed on the surface of the first adapter plate 10 opposite to the first receiving groove 11. The driving chip 52 is electrically connected to the laser chip 51 through conductive vias on the first adapter plate 10. In the transmitting spatial optical communication module 32, the laser chip and the driving chip are respectively disposed on opposite sides of the second adapter plate 20. A driving chip is also disposed on the surface of the second adapter plate 20 opposite to the second receiving groove 21. The driving chip is electrically connected to the laser chip through conductive vias on the second adapter plate 20. In this structure, the depth of the first receiving groove and / or the second receiving groove is less than a first depth threshold and greater than a second depth threshold.

[0106] In optional embodiments of this application, such as Figure 3As shown, in the receiving-type space optical communication module 31, the optical receiving unit 42 includes a photodetector chip 61, which is bonded to the second receiving groove 21. A receiving processing chip 62 is also disposed on the surface of the second adapter plate 20 opposite to the second receiving groove 21. The receiving processing chip 62 is electrically connected to the photodetector chip 61 through conductive vias on the second adapter plate 20. In the transmitting-type space optical communication module 32, the photodetector chip and the receiving processing chip are respectively disposed on opposite sides of the second adapter plate 20. The photodetector chip is bonded to the first receiving groove 11. A receiving processing chip is also disposed on the surface of the first adapter plate 10 opposite to the first receiving groove 11. The receiving processing chip is electrically connected to the photodetector chip through conductive vias on the first adapter plate 10. In this case, the depth of the first receiving groove and / or the second receiving groove is less than a first depth threshold and greater than a second depth threshold.

[0107] Preferably, the second depth threshold is equal to the thickness of the laser chip or the thickness of the photoelectric detection chip, ensuring that the chip group is completely embedded in the slot and avoiding protrusions from the carrier surface that could affect optical path coupling and module packaging flatness.

[0108] As can be understood, unlike the stacked configuration where all chips are piled up in a slot, this series of embodiments adopts a "split" layout: only the laser chip or photodetector chip is placed in a shallower receiving slot (depth between two thresholds), while the driver chip or receiving / processing chip is placed on the back of the adapter board, and vertical interconnection is achieved through conductive vias. The beneficial effects of this mounting scheme include: first, it reduces the requirement for the depth of the receiving slot, simplifies the difficulty of processes such as etching, and helps improve yield; second, it externalizes the driver / processing chip, which generates a lot of heat, improving heat dissipation conditions; and third, it reduces the number of chip stacking layers in the slot, reduces packaging stress and signal crosstalk risks, and enhances the long-term reliability of the module.

[0109] In an optional embodiment of this application, the sum of the first depth threshold and the thickness of other chips is recorded as the first calculated value; or, the sum of the first depth threshold and the thickness of the switching chip is recorded as the first calculated value; the thickness of the light emitting unit or the thickness of the light receiving unit is recorded as the second calculated value; the thickness of the refractive component exposed on the carrier surface is recorded as the third calculated value; the first calculated value is greater than the sum of the second calculated value and the third calculated value.

[0110] like Figure 4 As shown, the thickness of the non-fiber optic light guide component exposed on the carrier surface is the thickness of the non-fiber optic light guide element 43; as Figure 2 As shown, the thickness of the non-fiber optical guide component exposed on the carrier surface is zero.

[0111] It is understandable that by limiting the first calculated value (the sum of the accommodating slot depth and the chip thickness) to be greater than the sum of the second and third calculated values, it is ensured that the refractive component can complete optical path coupling without interference after the chip is installed. This dimensional constraint avoids mechanical collisions between the optical transceiver unit and the refractive component, ensures optical path alignment accuracy, and improves the feasibility and yield of packaging.

[0112] In an optional embodiment of this application, a heat dissipation coating is provided in the first receiving groove and the second receiving groove, and there is a preset distance between the heat dissipation coating and the electrical connection line.

[0113] It is understandable that placing a heat-dissipating coating within the housing slot can effectively and quickly dissipate the heat generated by the light emitting / receiving unit, reducing the chip junction temperature and improving the module's operational stability and lifespan. Simultaneously, maintaining a preset distance between the heat-dissipating coating and electrical connection lines avoids the risk of short circuits caused by the coating, thus balancing heat dissipation efficiency and electrical safety.

[0114] In optional embodiments of this application, the aforementioned computing chip can be selected from any one of a Graphics Processing Unit (GPU), a custom AI accelerator XPU, or an Application-Specific Integrated Circuit (ASIC) chip. The custom AI accelerator XPU is not a single chip, but rather a strategic concept for heterogeneous computing, designed to address complex computing needs through diverse hardware combinations. Its essence is "Right Tool for the Right Job," meaning using the most suitable hardware to handle specific tasks, thereby improving overall system efficiency. The custom AI accelerator XPU can be, for example, a Central Processing Unit (CPU), a Neural Processing Unit (NPU), a Field-Programmable Gate Array (FPGA), or at least one of an AI accelerator. For example, the XPU can be any one of a CPU, GPU, or NPU to accelerate the training of large-scale models. Application-Specific Integrated Circuit (ASIC) chips include serializer / deserializer (SerDes) chips for encoding and decoding data via a Digital Signal Processor (DSP) interface. Further, when the computing chip is an ASIC chip, it may include an integrated modulation driver and a microcontroller. The integrated modulation driver is configured to drive optical signal modulation using PAM-4, PAM-6, or PAM-8 pulse amplitude modulation formats. The microcontroller is configured to control the operation of the integrated modulation driver.

[0115] An adapter board serves as the electrical and mechanical connection platform between optical modules and system circuitry. It typically utilizes high-temperature laminated materials, embedding high-frequency signal traces and power layers internally to provide high-speed differential signal transmission channels and thermal management paths for optical chips such as lasers and detectors. Through precisely controlled impedance matching and low-loss media, the adapter board ensures signal integrity for tens of Gbps optical modules while supporting chip mounting and wire bonding. The material selection for the adapter board must balance high-frequency performance, heat dissipation, and integration; at least one of the following can be used: organic high-frequency laminates; ceramic substrates such as aluminum nitride and alumina; silicon substrates; and glass substrates.

[0116] Optical refractive elements are used to guide light emitted from a light source from one point to another without relying on glass or plastic optical fibers. These elements include optical waveguides, microprism arrays, optical tubes, or liquid crystal light guides, utilizing total internal reflection or multiple reflections to deflect and homogenize the light path. Common applications include backlight modules, optical sensor coupling, and near-eye displays. The design focus is on controlling light uniformity, coupling efficiency, and transmission loss, while also considering thinness and manufacturing costs.

[0117] The driver chip is responsible for providing the required power, voltage, or current drive signal to the load. It receives low-voltage commands from the control terminal and converts them into a sufficiently strong signal through internal amplification and output stages to drive the laser chip.

[0118] The laser chip is the core of a semiconductor laser, utilizing carrier recombination in the PN junction region to generate stimulated emission of light. By forming a Fabry-Perot resonator through cleavage or employing a grating structure, the chip can output coherent light of a specific wavelength. Laser chips can be vertical-cavity surface-emitting lasers (VCSELs).

[0119] The receiving processing chip includes a transimpedance amplifier (TIA) and a clock data recovery circuit (CDR); the transimpedance amplifier is configured to receive the target electrical signal, convert it into a voltage signal, and amplify it; the clock data recovery circuit is configured to extract the clock signal and shape the data from the amplified voltage signal to restore the target data.

[0120] Photodetector chips are used to convert incident light signals into electrical signals (current or voltage). At their core is a light-sensitive photodiode, which utilizes the photogenerated carrier effect of a PN junction or PIN structure to achieve photoelectric conversion.

[0121] Secondly, this application discloses an integrated chip, including a carrier and at least one computing power expansion module according to any one of the first aspects, at least one switching chip, and at least one other chip that generates and / or stores data, disposed on the same side of the carrier, wherein each computing power expansion module is disposed between adjacent switching chips and other chips.

[0122] Taking computing chips as an example, such as Figure 1 and Figure 2 As shown, a switching chip 3 is disposed between the first computing chip 1 and the second computing chip 2. The first computing chip 1, the second computing chip 2, and the switching chip 3 are all disposed on the same side of the carrier (circuit board 500 in the figure). The first target data generated by the first computing chip 1 is transmitted to the second computing chip through the switching chip 3; the second target data generated by the second computing chip 2 is transmitted to the first computing chip 1 through the switching chip 3.

[0123] It is understandable that traditional single-chip systems are limited by process technology and power consumption, making it difficult to infinitely improve performance. This integrated chip, however, integrates multiple switching chips, multiple computing / storage chips, and computing power expansion modules located on the same side of the carrier. Each computing power expansion module utilizes free-space lasers to establish high-speed, low-latency, and low-power optical communication channels between adjacent chips. This allows multiple relatively small-scale chips to work closely together through optical interconnects, aggregating into a logically powerful computing unit. Through parallel processing and efficient data flow, the overall computing power of this integrated chip is no longer limited by the physical limits of a single chip, but can be flexibly expanded by increasing the number of chips and the optical interconnect bandwidth, thus effectively breaking through the computing power bottleneck of traditional single-chip systems.

[0124] In an optional embodiment of this application, the switching chip and other chips are bare chips, the carrier is a circuit board, the bare chips are electrically connected to the surface of the circuit board, and the circuit board is provided with a refractive component as described above.

[0125] like Figure 2 As shown in the figure, each computing chip is a bare die, which is bonded to the circuit board 100. The circuit board 100 is provided with any of the above-mentioned refractive components, such as the refractive component 43 in the receiving spatial optical communication module 31.

[0126] Understandably, directly mounting the bare die onto the circuit board surface eliminates the need for a chip package, shortens electrical interconnection paths, and reduces parasitic parameters and signal delay. Simultaneously, integrating the refractive component onto the circuit board, in coordination with the bare die layout, enables high-density integration. The overall solution balances low cost, miniaturization, and high-speed optical communication performance, facilitating large-scale applications.

[0127] In an optional embodiment of this application, the switching chip and other chips are bare chips, the carrier is a carrier substrate, and the carrier substrate is provided with at least one light guide carrier plate and at least two circuit boards; a single bare chip is soldered on each circuit board, and each light guide carrier plate is provided with a refractive component as described above.

[0128] like Figure 7 As shown, each computing chip is a bare die. The carrier substrate 200 is sequentially provided with a first circuit board 601, a first light guide carrier 602, a second circuit board 603, a second light guide carrier 604, and a third circuit board 605. The first computing chip is soldered on the first circuit board 601. A light-refractive component is fixed on the first light guide carrier 602. A switching chip 3 is soldered on the second circuit board 603. Another light-refractive component is fixed on the second light guide carrier 604. The second computing chip 2 is soldered on the third circuit board 605.

[0129] It is understandable that a carrier substrate is used to integrate multiple circuit boards and light guide carrier boards, with each circuit board having a single bare core soldered onto it, and the light guide carrier board having an independently installed refractive assembly. This modular design facilitates individual testing and replacement of each bare core and its optical path, reducing maintenance difficulty. Simultaneously, the separate layout of the light guide and circuit boards optimizes the space allocation for optical paths and electrical traces, which helps improve signal integrity and reduce crosstalk.

[0130] In an optional embodiment of this application, the other chips are calculator circuit boards carrying a bare computing chip and its peripheral auxiliary circuits; the switching chip is a switch circuit board carrying a bare switching chip and its peripheral auxiliary circuits; the carrier is a substrate, and the calculator circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described above.

[0131] In optional embodiments of this application, the peripheral auxiliary circuitry includes at least one of the following: a power management circuit, a clock circuit, a data interface circuit, and a storage circuit.

[0132] like Figure 8 As shown, there is a first calculator circuit board 701 containing a first computing chip die and peripheral auxiliary circuits, a second calculator circuit board 702 containing a second computing chip die and peripheral auxiliary circuits, and a switch circuit board 703 containing a switch chip die and peripheral auxiliary circuits.

[0133] like Figure 8 As shown, the carrier is a silicon substrate 700, and the first calculator circuit board 701, the second calculator circuit board 702 and the switch circuit board 703 are fixed on the substrate 700.

[0134] It is understandable that integrating computing and switching chips onto a circuit board with peripheral auxiliary circuitry facilitates independent testing and mass production. The substrate integrates a refractive component, enabling free-space optical interconnection between boards, achieving high-speed communication capabilities without the need for high-precision mounting of bare chips. This solution balances ease of engineering and performance scalability requirements, lowering the barrier to system integration.

[0135] In an optional embodiment of this application, the other chips are memory circuit boards carrying bare memory chips and their peripheral auxiliary circuits; the switching chip is a switch circuit board carrying bare switching chips and their peripheral auxiliary circuits; the carrier is a substrate, and the memory circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described above.

[0136] In optional embodiments of this application, the peripheral auxiliary circuitry includes at least one of the following: a power management circuit, a clock circuit, a data interface circuit, and a storage circuit.

[0137] It is understandable that integrating the bare memory chip and its peripheral circuits into the memory circuit board and the switch circuit board respectively facilitates independent testing and standardized production. The substrate integrates a refractive component, enabling free-space optical interconnection between boards, avoiding the losses and crosstalk of traditional long-distance electrical interconnections on PCBs. This solution is beneficial for building high-capacity, high-bandwidth storage and switching networks, improving the computing power aggregation efficiency of data-intensive applications.

[0138] In an optional embodiment of this application, the switching chip includes a single-sided switching chip and a multi-sided switching chip; the single-sided switching chip sends target data to other chips or receives target data from other chips through a computing power expansion module; the multi-sided switching chip sends target data to other chips through a first computing power expansion module and also receives target data from another chip through a second computing power expansion module.

[0139] Continue to refer to Figure 2 The first computing chip 1 and the second computing chip 2 are the aforementioned single-sided computing chips. The first computing chip 1 is electrically connected only to the optical transmitting unit of the first computing power expansion module 800, and the second computing chip 2 is electrically connected only to the optical receiving unit of the second computing power expansion module 900. Furthermore, Figure 2 The switching chip 3 in the above-mentioned multilateral computing chip is not only electrically connected to the optical receiving unit of the first computing power expansion module 800, but also electrically connected to the optical transmitting unit of the second computing power expansion module 900.

[0140] It is understandable that differentiating between single-sided and multi-sided switching chips provides a flexible data exchange topology. Single-sided switching chips are suitable for point-to-point unidirectional transmission, simplifying design; multi-sided switching chips can simultaneously perform bidirectional transmission and reception with multiple other chips, supporting complex network structures. The combination of the two enables the construction of efficient and scalable inter-chip optical interconnect architectures on demand, optimizing the communication efficiency of computing clusters.

[0141] Thirdly, this application discloses a vertically scalable network architecture, which employs a computing power cluster composed of multiple integrated chips as described in any one of the second aspects.

[0142] The vertically scalable network architecture disclosed in the third aspect of this application can be a scale-up architecture. A scale-up architecture refers to improving system performance by enhancing the computing power of individual nodes (such as increasing CPU / memory or integrating more chips), rather than increasing the number of nodes. The scale-up architecture in this application uses inter-chip optical interconnect technology to interconnect multiple integrated chips at high speed, aggregating computing power and enabling them to work collaboratively like a powerful "single computer" to meet the demands of high-performance computing. This architecture, by employing multiple of the aforementioned integrated chips to build a high-density computing cluster, aims to meet the core requirements of computing power aggregation and efficient collaboration in large-scale parallel computing scenarios.

[0143] In a scale-up architecture, multiple integrated chips are interconnected via chip-level optical communication through a computing power expansion module, forming a tightly coupled pool of computing resources. Optical interconnects offer advantages such as high bandwidth, low latency, and interference resistance, effectively overcoming the signal attenuation and power consumption bottlenecks of traditional electrical interconnects during expansion, and supporting high-speed, stable data exchange between chips. This architecture supports flexible scheduling of various computing resources and is widely applicable to application scenarios with extremely high requirements for computing power aggregation, such as artificial intelligence training, high-performance computing, and real-time big data analysis.

[0144] Furthermore, this vertically scaling architecture boasts excellent modularity and scalability, enabling dynamic adjustment of the cluster size based on computing power demands, thereby achieving elastic deployment and efficient utilization of computing resources. This design provides an engineering-feasible technical path for building next-generation high-performance computing platforms.

[0145] The terms "first," "second," "first," or "second" as used in the various embodiments of this disclosure may modify various components regardless of their order and / or importance, but these terms do not limit the corresponding components. The above terms are configured only for the purpose of distinguishing an element from other elements. For example, "first user equipment" and "second user equipment" refer to different user equipments, although both are user equipment. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0146] When a component (e.g., a first component) is referred to as being "(operably or communicatively) coupled" or "(operably or communicatively) coupled to" or "connected to" another component (e.g., a second component), it should be understood that the first component is directly connected to the second component or that the first component is indirectly connected to the second component via yet another component (e.g., a third component). Conversely, it can be understood that when a component (e.g., a first component) is referred to as being "directly connected" or "directly coupled" to another component (the second component), no component (e.g., a third component) is inserted between the two.

[0147] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0148] The above description is merely an optional embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0149] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0150] The above description is merely an optional embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0151] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A computing power expansion module, disposed between adjacent switching chips and other chips, said other chips being configured to generate and / or store data, characterized in that, It includes a first adapter board, a second adapter board, and a space optical communication module, all located on the same side of the carrier; The first adapter plate is provided with a first receiving groove, and the second adapter plate is provided with a second receiving groove, the openings of the first receiving groove and the second receiving groove facing the carrier; The spatial optical communication module is disposed within the space enclosed by the switching chip, the other chips, the first accommodating slot, the second accommodating slot, and the carrier, and is configured to realize optical communication between adjacent switching chips and other chips by emitting and / or receiving lasers. The space optical communication module includes a receiving space optical communication module, and / or the space optical communication module includes a transmitting space optical communication module. Both the receiving space optical communication module and the transmitting space optical communication module include an optical transmitting unit, an optical receiving unit, and a refractive component; In the receiving space optical communication module, the optical transmitting unit is disposed in the first accommodating slot and is electrically connected to the other chips through the electrical connection lines in the first accommodating slot; the optical receiving unit is disposed in the second accommodating slot and is electrically connected to the switching chip through the electrical connection lines in the second accommodating slot. In the transmitting space optical communication module, the optical transmitting unit is disposed in the second accommodating slot and is electrically connected to the switching chip through the electrical connection lines in the second accommodating slot. The optical receiving unit is disposed in the first accommodating slot and is electrically connected to the other chips through the electrical connection lines in the first accommodating slot.

2. The computing power expansion module according to claim 1, characterized in that, The first surface of the first adapter plate facing the second adapter plate is combined with the second surface of the second adapter plate facing the first adapter plate; The first receiving slot is connected to the second receiving slot.

3. The computing power expansion module according to claim 2, characterized in that, The first adapter plate and the second adapter plate are integrally formed.

4. The computing power expansion module according to claim 1, characterized in that, The receiving spatial optical communication module is configured to transmit target data from the other chips to the switching chip; The transmitting space optical communication module is configured to transmit the target data of the switching chip to the other chips.

5. The computing power expansion module according to claim 4, characterized in that, The optical emitting unit is configured to output a target-modulated laser beam according to the target data; The refractive component is configured to guide the target modulated laser beam output by the light emitting unit into the light receiving unit through specular reflection in free space.

6. The computing power expansion module according to claim 5, characterized in that, The refractive component includes at least one of the following: A refractive element is disposed on the carrier, and the refractive element is provided with a first reflective surface and a second reflective surface; A light guide groove is disposed on the carrier or other layer structure on the carrier. The light guide groove includes a first inner sidewall and a second inner sidewall disposed opposite to each other. A first reflective surface is disposed on the first inner sidewall and a second reflective surface is disposed on the second inner sidewall. The first reflective surface is configured to reflect the target modulated laser beam output by the light emitting unit, causing it to exit in a direction parallel to the surface of the carrier; the second reflective surface is configured to reflect the target modulated laser beam incident in a direction parallel to the surface of the carrier, causing it to be guided into the light receiving unit in a direction away from the carrier.

7. The computing power expansion module according to claim 1, characterized in that, The first adapter board is electrically connected to the other chips and includes at least one of the following: The first adapter board is directly bonded to the other chips to achieve electrical connection; An intermediate adapter board is provided between the first adapter board and the other chips. The first adapter board is bonded to the surface of the intermediate adapter board facing the first adapter board, and the surface of the intermediate adapter board facing away from the first adapter board is bonded to the other chips. The intermediate adapter board is provided with conductive vias to connect corresponding solder joints on the two surfaces, so as to realize the electrical connection between the first adapter board and the other chips.

8. The computing power expansion module according to claim 1, characterized in that, The second adapter board is electrically connected to the switching chip and includes at least one of the following: The second adapter board is directly bonded to the switching chip to achieve electrical connection; An intermediate adapter board is provided between the second adapter board and the switching chip. The second adapter board is bonded to the surface of the intermediate adapter board facing the second adapter board, and the surface of the intermediate adapter board facing away from the second adapter board is bonded to the switching chip. The intermediate adapter board is provided with conductive vias to connect corresponding solder joints on the two surfaces, so as to realize the electrical connection between the second adapter board and the switching chip.

9. The computing power expansion module according to claim 1, characterized in that, The light emitting unit includes a driver chip and a laser chip stacked together. The driver chip is bonded to the first accommodating groove and / or the second accommodating groove, and the laser chip is bonded to the driver chip. The optical receiving unit includes a receiving processing chip and a photodetector chip stacked together. The receiving processing chip is bonded to the first accommodating slot and / or the second accommodating slot, and the photodetector chip is bonded to the receiving processing chip. The depth of the first receiving groove and / or the second receiving groove is greater than the first depth threshold.

10. The computing power expansion module according to claim 1, characterized in that, It also includes at least one of the following: The light emitting unit includes a laser chip, which is bonded to the first receiving groove. A driving chip is also disposed on the surface of the first adapter plate opposite to the first receiving groove. The driving chip is electrically connected to the laser chip through a conductive through hole on the first adapter plate. The light emitting unit includes a laser chip, which is bonded to the second receiving groove. A driving chip is also disposed on the surface of the second adapter plate opposite to the second receiving groove. The driving chip is electrically connected to the laser chip through a conductive through hole on the second adapter plate. The light receiving unit includes a photodetector chip, which is bonded to the first receiving groove. A receiving processing chip is also provided on the surface of the first adapter plate opposite to the first receiving groove. The receiving processing chip is electrically connected to the photodetector chip through a conductive through hole on the first adapter plate. The optical receiving unit includes a photodetector chip, which is bonded to the second accommodating groove. A receiving processing chip is also disposed on the surface of the second adapter plate opposite to the second accommodating groove. The receiving processing chip is electrically connected to the photodetector chip through a conductive through hole on the second adapter plate. The depth of the first receiving groove and / or the second receiving groove is less than a first depth threshold and greater than a second depth threshold.

11. The computing power expansion module according to claim 9, characterized in that, The sum of the first depth threshold and the thickness of the other chips is recorded as the first calculated value; or, the sum of the first depth threshold and the thickness of the switching chip is recorded as the first calculated value. The thickness of the light emitting unit or the thickness of the light receiving unit is denoted as the second calculated value; The thickness of the refractive component exposed on the surface of the carrier is denoted as the third calculated value; The first calculated value is greater than the sum of the second calculated value and the third calculated value.

12. The computing power expansion module according to any one of claims 1 to 11, characterized in that, The first and second receiving slots are provided with heat dissipation coatings, and there is a preset distance between the heat dissipation coatings and the electrical connection lines.

13. The computing power expansion module according to any one of claims 1-11, characterized in that, The other chips include at least one of the following: a computing chip or a storage chip.

14. An integrated chip, characterized in that, It includes a carrier and at least one computing power expansion module as described in any one of claims 1-13, at least one switching chip, and at least one other chip that generates and / or stores data, disposed on the same side of the carrier.

15. The integrated chip according to claim 14, characterized in that, The switching chip and the other chips are all bare chips, the carrier is a circuit board, the bare chips are electrically connected to the surface of the circuit board, and the circuit board is provided with a refractive component as described in any one of claims 4-11.

16. The integrated chip according to claim 14, characterized in that, The switching chip and the other chips are all bare chips. The carrier is a carrier substrate, and at least one light guide carrier plate and at least two circuit boards are disposed on the carrier substrate. Each of the circuit boards has a single bare core soldered on it, and each of the light guide carriers has a refractive component as described in any one of claims 4-11.

17. The integrated chip according to claim 14, characterized in that, The other chips are calculator circuit boards carrying a bare computing chip and its peripheral auxiliary circuits; the switching chip is a switch circuit board carrying a bare switching chip and its peripheral auxiliary circuits; the carrier is a substrate, and the calculator circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described in any one of claims 4-11.

18. The integrated chip according to claim 14, characterized in that, The other chips are memory circuit boards carrying bare memory chips and their peripheral auxiliary circuits; the switching chip is a switch circuit board carrying a bare switching chip and its peripheral auxiliary circuits; the carrier is a substrate, and the memory circuit board and the switch circuit board are fixed on the substrate; the substrate is provided with a refractive component as described in any one of claims 4-11.

19. The integrated chip according to claim 14, characterized in that, The switching chip includes a single-sided switching chip and a multi-sided switching chip; The unilateral switching chip sends target data to other chips or receives target data from other chips through the computing power expansion module; The multilateral exchange chip sends target data to other chips through the first computing power expansion module, and also receives target data from another chip through the second computing power expansion module.

20. A vertically scalable network architecture, characterized in that, The architecture employs multiple integrated chips as described in any one of claims 14-19 to form a computing power cluster.

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