Board card and electronic device

Abstract

This application provides a circuit board and electronic device to increase computing and storage capacity within a limited space (area or even volume). The circuit board includes N packages, each package including a packaging substrate and at least one chip, the at least one chip being electrically connected to the packaging substrate, and the at least one chip including a computing chip and / or a storage chip; a printed circuit board electrically connected to the packaging substrates of the N packages, the printed circuit board being used to supply power to the chips in the N packages; and a flexible printed circuit board (FPC) electrically connected to the packaging substrates of the N packages, the flexible printed circuit board being used for data transmission between the chips in the N packages.

Description

Technical Field

[0001] This application relates to the field of semiconducting technology, and in particular to a circuit board and electronic device. Background Technology

[0002] With the development of artificial intelligence (AI) technology, AI, represented by machine learning, has dramatically changed people's work and lifestyles. Machine learning requires training machine learning models with massive amounts of data, and the trained models are then used for inference. As the scale of machine learning models grows, the training and inference of these models require a large amount of parallel computing and storage resources.

[0003] During model training and inference, a large amount of intermediate data is stored and retrieved. Therefore, while expanding computing and storage resources, it is necessary to increase the bandwidth between computing and storage units to ensure that computing units can efficiently access data in storage units, thereby improving model training or inference efficiency. For example, the bandwidth between computing and storage units can be increased by setting up optical paths or high-speed switches.

[0004] However, connecting computing and storage units via optical paths or high-speed switches presents problems such as large space requirements and complex data center deployment. Summary of the Invention

[0005] This application provides a board and electronic device to increase computing and storage capacity within a limited space (area or even volume) and reduce the complexity of data center deployment.

[0006] The first aspect provides a circuit board. The circuit board includes: N packages, each package including a packaging substrate and at least one chip, the at least one chip being electrically connected to the packaging substrate, and the at least one chip including a computing chip and / or a storage chip, where N is an integer greater than or equal to 2; a printed circuit board, electrically connected to the packaging substrate of the N packages, the printed circuit board being used to supply power to the chips in the N packages; and a flexible printed circuit board (FPC), electrically connected to the packaging substrate of the N packages, the flexible printed circuit board being used for data transmission between the chips in the N packages. By directly connecting multiple packages using an FPC, data can be transmitted between packages via the FPC. The FPC has a large transmission bandwidth, which can meet the high-bandwidth data transmission needs between chips in different packages, thus not being limited by the trace density constraints of the printed circuit board. This allows for an increase in the number of packages mounted on the printed circuit board, i.e., an increase in the number of chips packaged on the printed circuit board, thereby increasing computing and / or storage capacity within a limited space (area or even volume). Since computing and / or storage capacity is increased at the circuit board level, the number of circuit boards required for deployment in a data center can be reduced, thereby reducing deployment complexity and the space required.

[0007] In one possible implementation, N packages include a first package and a second package, where the chip type in the first package is the same as the chip type in the second package. Packages with the same function can be connected via an FPC to form a board-level package cluster, thereby increasing the board's computing or storage capacity.

[0008] In one possible implementation, all chips in the first package are computing chips, and all chips in the second package are computing chips; or all chips in the first package are memory chips, and all chips in the second package are memory chips.

[0009] In one possible implementation, the first package includes at least one computing chip and at least one memory chip, and the second package includes at least one computing chip and at least one memory chip.

[0010] In one possible implementation, N packages include a first package and a second package, where the chip type in the first package differs from the chip type in the second package. After the packages with different functions are connected via an FPC, near-memory computing can be implemented on the board, reducing communication latency between the computing chip and the memory chip and improving energy efficiency.

[0011] In one possible implementation, the chips in the first package are all computing chips, and the chips in the second package are all memory chips; or the first package includes at least one computing chip and at least one memory chip, and the chips in the second package are all memory chips; or the first package includes at least one computing chip and at least one memory chip, and the chips in the second package are all computing chips.

[0012] In one possible implementation, the board also includes: N connectors for electrically connecting the N packages to the FPC, with each of the N connectors corresponding to one of the N packages.

[0013] In one possible implementation, the package substrate includes a first pad array comprising a plurality of first pads, with a spacing of less than 6.5 mm between adjacent first pads. The FPC includes a second pad array comprising a plurality of second pads, with a spacing of less than 6.5 mm between adjacent second pads. A connector is electrically connected to the first and second pad arrays. Thus, a high-density connection between the package 12 and the FPC can be achieved through the connector, improving the bandwidth of the FPC.

[0014] In one possible implementation, the connector includes opposing first and second surfaces. The first surface includes a first array of metal bumps, and the second surface includes a second array of metal bumps. Multiple metal bumps in the first array are connected one-to-one to multiple first pads in the first pad array, and multiple metal bumps in the second array are connected one-to-one to multiple second pads in the second pad array. Thus, the connector enables high-density connection between the package 12 and the FPC, improving the bandwidth of the FPC.

[0015] In one possible implementation, the FPC has multiple wirings, each connecting two of N packages. Each of the N packages is connected to at least one other package via at least one wiring. Each wiring is used for data transmission between the two packages connected by the wiring. Connecting packages via wiring on the FPC eliminates the need for traces on the printed circuit board, thus freeing it from the constraints of the printed circuit board and increasing the density of packages on the board, thereby increasing computing and / or storage capacity at the board level.

[0016] The second aspect provides an electronic device. This electronic device includes at least one board as described in the first aspect or any possible implementation of the first aspect. Attached Figure Description

[0017] Figure 1A This is a top view of a circuit board provided in an embodiment of this application;

[0018] Figure 1B for Figure 1A A cross-sectional view of the board along the AA direction;

[0019] Figure 2A A schematic diagram of a scenario for an FPC-connected package;

[0020] Figure 2B A schematic diagram of another scenario for an FPC-connected package;

[0021] Figure 2C A schematic diagram of another scenario for an FPC-connected package;

[0022] Figure 2D A schematic diagram of another scenario for an FPC-connected package;

[0023] Figure 2E A schematic diagram of another scenario for an FPC-connected package;

[0024] Figure 3A A schematic diagram of one shape of FPC;

[0025] Figure 3B This is a schematic diagram of another shape of FPC;

[0026] Figure 3C This is a schematic diagram of another shape of FPC;

[0027] Figure 3D This is a schematic diagram of another shape of FPC;

[0028] Figure 4A This is a schematic cross-sectional view of a single-layer FPC structure.

[0029] Figure 4B This is a schematic diagram of a multi-layer FPC structure;

[0030] Figure 5A This is a schematic diagram of the structure of a connector;

[0031] Figure 5B This is a schematic diagram of another type of connector;

[0032] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0034] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0035] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly, for example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0036] It should be noted that the terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any or all possible combinations including one or more of the associated listed items. In the description of this application, unless otherwise stated, “a plurality” means two or more.

[0037] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0038] Artificial intelligence, especially deep learning, typically requires processing massive datasets and performing complex mathematical operations such as matrix multiplication and gradient descent. These tasks place high demands on computing power. Furthermore, AI models rely on large amounts of data for training, meaning sufficient storage space is needed to store these datasets. In addition, various intermediate results generated during training also require temporary storage. Besides capacity, how to efficiently manage and access massive amounts of data is also a critical issue.

[0039] Deep learning models are becoming increasingly complex and large, leading to a dramatic increase in the demand for computing and storage resources. Furthermore, as computing and storage resources grow in scale, rapid data retrieval speeds are crucial for improving the efficiency of AI model training.

[0040] To support more powerful AI hardware computing by expanding storage capacity, one approach is to connect external storage to the computing unit via an optical path. This optical path ensures sufficient communication bandwidth between the two. However, lasers are temperature-sensitive, lack versatility, and suffer from high reliability failure rates under high-bandwidth interconnects. Furthermore, this optical path connection method between the computing unit and external storage increases the overall system complexity, adding to the complexity of data center deployment and heat dissipation, as well as requiring more space.

[0041] In this embodiment, the board may have different names in different scenarios. For example, when the board is used in a server or computer, it can also be called a motherboard. As another example, when the board is used in AI computing scenarios, it can also be called an AI computing power card, an AI acceleration card, or an AI inference card, etc. Of course, the board can also have other names, such as motherboard, etc., and there is no limitation here.

[0042] like Figure 1A and Figure 1B As shown, Figure 1A This is a top view of a circuit board provided in an embodiment of this application; Figure 1B for Figure 1A The diagram shows a cross-sectional view of the board along the AA direction. Board 10 includes a printed circuit board (PCB) 11, N packaged boxes (PKGs) 12, and an open-circuit circuit board (FPC) 13. The N packaged boxes 12 are electrically connected to the PCB 11, which powers the N packaged boxes 12. Furthermore, the N packaged boxes 12 are electrically connected to the FPC 13, which is used for data transmission between the N packaged boxes 12. N is an integer greater than or equal to 2. It should be noted that... Figure 1A The number and layout of the packages 12 in the board 10 are for illustrative purposes only and should not be construed as a limitation of this application. For example, the number of packages 12 provided on the board 10 may be more or less, and no limitation is made here.

[0043] Each of the N packages 12 includes a package substrate 121 and at least one chip 122. In this embodiment, the chip 122 with functional circuitry is electrically connected to the package substrate 121, and then electrically connected to the PCB 11 and FPC 13 through the package substrate 121. Thus, the PCB 11 can supply power to the chip 122 in the package 12. The FPC 13 can transmit data between the chips 122 in different packages 12.

[0044] like Figure 1BAs shown, the packaging substrate 121 has opposing third surfaces s3 and fourth surfaces s4. A third pad array (not shown) is provided on the third surface s3 of the packaging substrate 121, comprising multiple pads. The chip 122 has multiple bumps 1221 facing the third surface s3 of the packaging substrate 121, aligning the bumps 1221 with the pads of the third pad array on the third surface s3 of the packaging substrate 121. A soldering process is then used to achieve a packaged interconnection between the chip 122 and the packaging substrate 121, enabling electrical connection between the chip 122 and the packaging substrate 121 via the bumps. The fourth surface s4 is connected to the PCB 11 via a connector 14. This achieves electrical connection between the package 12 and the PCB 11. The connector 14 can be one or more combinations of microbumps, copper pillars, and solder balls; this application does not specifically limit its use. Furthermore, the packaging substrate 121 may also comprise a multilayer board containing an interposer and a metal layer.

[0045] The packaging substrate 121 includes, but is not limited to, organic substrates, ceramic substrates, silicon substrates, etc. The packaging substrate 121 can be a cored packaging substrate or a coreless packaging substrate.

[0046] The structure of the packaging substrate 121 is not limited in this application embodiment. The packaging substrate 121 only needs to be able to transmit signals from the fourth surface s4 to the third surface s3. For example, the packaging substrate 121 includes multiple signal line layers, with an insulating layer disposed between adjacent signal line layers. The adjacent signal line layers are coupled through vias in the insulating layer to realize signal transmission.

[0047] For example, taking the packaging substrate 121 as a cored packaging substrate, such as... Figure 1B As shown, the packaging substrate 121 includes a first wiring layer 1211, a core layer 1212, and a second wiring layer 1213 stacked sequentially. The surface of the first wiring layer 1211 furthest from the core layer 1212 serves as the third surface s3 of the packaging substrate 121. A third pad array is disposed on the first wiring layer 1211. Thus, the chip 122 can be electrically connected to the packaging substrate 121 via the third pad array. The surface of the second wiring layer 1213 furthest from the core layer 1212 serves as the fourth surface s4 of the packaging substrate 121. The second wiring layer 1213 is electrically connected to the PCB 11 via a connector 14, thereby enabling the chip 122 to be electrically connected to the PCB 11 via the packaging substrate 121.

[0048] The embodiments of this application do not limit the number of chips 122 included in each package 12.

[0049] For example, package 12 includes a chip 122. That is, package substrate 121 carries a chip 122.

[0050] Alternatively, the package 12 may include multiple chips 122. In one possible implementation, the multiple chips 122 are arranged side-by-side on the package substrate 121. Alternatively, in another possible implementation, the multiple chips 122 are stacked and then arranged on the package substrate 121. Alternatively, multiple stacked chips 122 may also be arranged side-by-side on the package substrate 121. This application embodiment does not limit the arrangement of the multiple chips 122; any arrangement can be made reasonably according to the actual situation.

[0051] Chip 122 can be a functional chip. A single chip 122 within package 12 can be a die, also known as a bare chip or die. A bare chip refers to a pre-manufactured wafer / die with specific functions that can be assembled and integrated.

[0052] In this embodiment, the chip type of the chip 122 in the package 12 includes a storage chip and / or a computing chip. For example, the computing chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip 122, a neural network processing unit (NPU) chip, or a tensor processing unit (TPU) chip, etc., chips with high computing capabilities. Alternatively, the computing chip can also be a chip 122 dedicated to a certain type of calculation, such as a chip for matrix calculation, a chip for accumulation calculation, or a chip for vector calculation. The storage chip can be a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), or a high bandwidth memory (HBM) chip, etc.

[0053] In this embodiment, the package 12 may include only one type of chip 122, for example, all chips 122 in the package 12 may be memory chips, or all chips 122 in the package 12 may be computing chips. Alternatively, the package 12 may include chips 122 of different types, for example, the package 12 may include memory chips and computing chips. When the package 12 includes memory chips and computing chips, there is no limitation on the ratio of the number of memory chips to the number of computing chips in the package 12. For example, when the processing speed of the computing chip is greater than the access speed of a memory chip, the number of memory chips in the package 12 may be greater than the number of computing chips. When the processing speed of the computing chip is comparable to the access speed of a memory chip, the number of memory chips in the package 12 may be equal to the number of computing chips. When the processing speed of the computing chip is less than the access speed of a memory chip, the number of memory chips in the package 12 may be less than the number of computing chips. Alternatively, when a package 12 is expected to have higher storage resources, the number of memory chips in the package 12 may be greater than the number of computing chips. When a package 12 is expected to have higher computing resources, the number of computing chips in the package 12 can be greater than the number of memory chips.

[0054] When a package 12 includes at least two computing chips, the computing chips in the same package 12 can be of the same type. For example, the computing chips in the same package 12 can all be CPU chips, GPU chips, NPU chips, or TPU chips. Alternatively, the computing chips in the same package 12 can all be chips for matrix calculations, chips for accumulation calculations, or chips for vector calculations. Alternatively, the computing chips in the same package 12 can also be of different types. For example, the computing chips in the same package 12 can include at least two of CPU chips, GPU chips, NPU chips, and TPU chips. Alternatively, the computing chips in the same package 12 can include at least two of chips for matrix calculations, chips for accumulation calculations, and chips for vector calculations.

[0055] When a package 12 includes at least two memory chips, the memory chips in the same package 12 can be of the same type. For example, the memory chips in the same package 12 can all be DRAM, SDRAM, SRAM, or HBM. Alternatively, the memory chips in the same package 12 can also be of different types. For example, the memory chips in the same package 12 can include at least two of DRAM, SDRAM, SRAM, or HBM.

[0056] In N packages 12, the chip types of the chips 122 in different packages 12 can be the same or different. In one possible implementation, the chip types of the chips 122 in all packages 12 of the N packages 12 are the same. In another possible implementation, the chip types of the chips 122 in any two packages 12 of the N packages 12 are different. In yet another possible implementation, the chip types of the chips 122 in some packages 12 of the N packages 12 are the same. For example, the N packages 12 include package a, package b, and package c, where the chip types of the chips 122 in package a and package b are the same, and the chip types of the chips 122 in package a and package b are different from those in package c.

[0057] There are several possibilities where chips 122 in different packages have the same chip type, and there are also several possibilities where chips 122 in different packages have different chip types. The following explanation uses the first and second packages among N packages 12 as examples to illustrate the different scenarios.

[0058] The cases where the chip type of the first package and the chip 122 of the second package are the same include Case 1 and Case 2.

[0059] Scenario 1: Both the first package and the second package include chips 122 of p chip types, and the p chip types corresponding to the first package and the p chip types corresponding to the second package are the same. Herein, p is an integer greater than or equal to 2. The package 12 that includes chips 122 of at least two chip types will be referred to as a composite package 12.

[0060] For example, taking p=2 as an example, such as Figure 2A As shown, the first package includes chips 122 of type DIE-1 and type DIE-2, and the second package also includes chips 122 of type DIE-1 and type DIE-2.

[0061] Among them, DIE-1 type chips are, for example, computing chips, and DIE-2 type chips are, for example, storage chips.

[0062] Using FPC to electrically connect two or more similar composite packages can ensure the transmission bandwidth between different packages 12 without being constrained by PCB wiring, thereby increasing the number of computing chips and / or storage chips on the board 10, thus improving computing and storage capacity within a limited space (area or even volume).

[0063] Scenario 2: Both the first package and the second package include a chip of the same type, and the chip types of the first package and the second package are the same.

[0064] For example, such as Figure 2B As shown, the chips in the first package are all DIE-3 type chips, and the chips in the second package are all DIE-3 type chips.

[0065] Among them, DIE-3 type chips are, for example, computing chips. Or, DIE-3 type chips are, for example, memory chips.

[0066] Cases where the chip type of the first package and the chip of the second package are the same include cases three and four.

[0067] Scenario 3: Both the first package and the second package include a chip of the same type, and the chip types of the first package and the second package are different.

[0068] For example, such as Figure 2C As shown, the chips in the first package are all DIE-4 type chips, and the chips in the second package are all DIE-5 type chips.

[0069] Among them, DIE-4 type chips are, for example, computing chips, and DIE-5 type chips are, for example, storage chips.

[0070] Scenario 4: The first package includes chips of type i, and the second package includes chips of type j. Furthermore, the i chip types in the first package include chip types that are not present in the j chip types in the second package. Here, i is an integer greater than or equal to 2, j is an integer greater than or equal to 1, and i is greater than or equal to j.

[0071] For example, taking i=2 and j=1 as an example, such as Figure 2D As shown, the first package contains DIE-6 and DIE-7 type chips, while the second package contains only DIE-6 type chips.

[0072] Among them, DIE-6 type chips are, for example, computing chips, and DIE-7 type chips are, for example, memory chips. Alternatively, DIE-6 type chips are, for example, memory chips, and DIE-7 type chips are, for example, computing chips.

[0073] For example, taking i=2 and j=2 as an example, such as Figure 2E As shown, the first package includes DIE-8 and DIE-9 type chips, and the second package includes DIE-8 and DIE-10 type chips.

[0074] Among them, DIE-8 type chips are, for example, computing chips, and DIE-9 type chips are, for example, memory chips. Alternatively, DIE-8 type chips are, for example, memory chips, and DIE-9 type chips are, for example, computing chips. DIE-10 type chips are, for example, communication chips.

[0075] Using FPC13 to electrically connect two or more different types of composite packages 12 ensures the transmission bandwidth between different packages 12 without being constrained by the wiring of PCB11. This allows for an increase in the number of computing chips and / or memory chips on the board 10, thereby improving computing and storage capacity within a limited space (area or even volume). Furthermore, since different types of chips 122 are integrated on the same board 10, such as computing chips and memory chips, the computing chips and memory chips are connected through the high-bandwidth FPC13, enabling more efficient near-memory computing and improving the overall performance of the board 10.

[0076] In this embodiment, FPC 13 connects at least a portion of the packages 12 in board 10. In one possible implementation, FPC 13 connects all the packages 12 in board 10. For example, if the number of packages 12 in board 10 is N, FPC 13 connects N packages 12. In another possible implementation, FPC 13 connects a portion of the packages 12 in board 10. For example, if the number of packages 12 in board 10 is M (M is a positive integer greater than N), FPC 13 connects N packages 12 out of the M packages 12.

[0077] This application embodiment does not limit the number of FPCs 13 used for data transmission between different packages 12 in a single board 10. In one possible implementation, the number of FPCs 13 used for data transmission between different packages 12 in a single board 10 is one. In another possible implementation, when the number of packages 12 in the board 10 is M, the number of FPCs 13 used for data transmission between different packages 12 in a single board 10 is greater than or equal to two. Each FPC 13 connects to some packages 12 among the M packages 12, and the packages 12 connected by different FPCs 13 do not overlap or partially overlap. For example, the board 10 includes a first FPC and a second FPC. The first FPC connects to N1 packages 12, and the second FPC connects to N2 packages 12. N1 is less than M, and N2 is less than M. The values ​​of N1 and N2 can be the same or different. The packages 12 connected by different FPCs 13 do not overlap, that is, any one of the N1 packages 12 does not exist in the N2 packages 12. The packages 12 connected to different FPC13 partially overlap, meaning that some packages 12 in the N1 packages 12 also exist in the N2 packages 12. The number of FPC13s in a board 10 used for data transmission between different packages 12 can be determined based on the number of packages 12 in the board 10 and the layout of the packages 12 on the PCB 11, and is not limited here.

[0078] The shape of FPC13 can be I-shaped, extended I-shaped, octopus-shaped, or square, etc. The shape of FPC13 can be determined according to the number of packages 12 in board 10 and the layout of packages 12 on PCB 11. FPC13 can also be other shapes. As long as FPC13 can connect N packages 12 in board 10, this application does not limit it.

[0079] For example, such as Figure 3A As shown, the FPC is H-shaped. Board 1 includes PCB1, FPC1, package 1, package 2, package 3, and package 4. Packages 1, 2, 3, and 4 are electrically connected to PCB1, allowing PCB1 to supply power to packages 1, 2, 3, and 4. FPC1 is also electrically connected to packages 1, 2, 3, and 4. Therefore, different packages within packages 1, 2, 3, and 4 can transmit data via FPC1.

[0080] For example, such as Figure 3BAs shown, the FPC has an extended I-shape. Board 2 includes PCB2, FPC2, package 5, package 6, package 7, package 8, package 9, and package 10. Packages 5, 6, 7, 8, 9, and 10 are electrically connected to PCB2, allowing PCB2 to supply power to packages 5, 6, 7, 8, 9, and 10. FPC2 is electrically connected to packages 5, 6, 7, 8, 9, and 10. Therefore, different packages among packages 5, 6, 7, 8, 9, and 10 can transmit data via FPC2.

[0081] For example, such as Figure 3C As shown, the FPC is octopus-shaped. Board 3 includes PCB3, FPC3, package 11, package 12, package 13, and package 14. Packages 11, 12, 13, and 14 are electrically connected to PCB3, allowing PCB3 to supply power to packages 11, 12, 13, and 14. FPC3 is electrically connected to packages 11, 12, 13, and 14. Therefore, different packages among packages 11, 12, 13, and 14 can transmit data via FPC3.

[0082] For example, such as Figure 3D As shown, the FPC is square in shape, and a square FPC can be used to connect two adjacent packages. Board 4 includes PCB4, FPC4, FPC5, package 15, package 16, and package 17. Packages 15, 16, and 17 are electrically connected to PCB4, allowing PCB4 to supply power to packages 15, 16, and 17. FPC4 is electrically connected to packages 15 and 16, enabling data transmission between packages 15 and 16. FPC5 is electrically connected to packages 16 and 17, enabling data transmission between packages 16 and 17. Multiple square FPCs can be connected in series to connect multiple packages, facilitating pipelined tasks between them. For example, data processed by the computing chip in package 15 can be input into package 16, and data processed by the computing chip in package 16 can be input into package 17 for storage or further processing. Alternatively, the data processed by the computing chip in package 15 can be input into package 16 for caching, and the data in package 16 can be input into package 17 for further processing.

[0083] Understandable. Figures 3A-3DThe number and layout of the package 12 and the number of FPC 13 are for illustrative purposes only and should not be construed as limitations on this application. In practice, the number of package 12 / FPC 13 may be more or less, and the layout of the package 12 on the PCB 11 may also be in other ways, which are not limited in themselves.

[0084] By connecting the package 12 with the I-shaped FPC13, extended I-shaped FPC13, or octopus-shaped FPC13 provided in the embodiments of this application, the signal attenuation problem caused by the distance between computing and storage can be solved to a certain extent, thereby partially solving the area-space limitation caused by the expansion of computing power / storage of the board 10, and thus increasing the capacity and flexibility of the storage package deployed on the board 10.

[0085] The structure of FPC13 is described below. A second pad array is formed on the side of FPC13 facing the package 12, so that FPC13 can be electrically connected to the package 12 through the second pad array.

[0086] To provide greater bandwidth, FPC13 can be a multilayer board structure. Each layer in FPC13 includes a flexible copper clad laminate (FCCL), a cover film, and a substrate. The FCCL can be a two-layer FCCL (2L-FCCL) or a three-layer FCCL (3L-FCCL). The two-layer FCCL can be single-sided or double-sided. The FCCL includes copper foil, an insulating base film, etc. The copper foil carries circuitry for signal transmission. To ensure high-speed signal transmission, the insulating base film is a low-loss-factor medium, such as polytetrafluoroethylene (PTFE), modified polyphenylene ether (MPPE), modified polyimide (MPI), or liquid crystal polyester (LCP).

[0087] For example, such as Figure 4A The diagram shown is a cross-sectional schematic of a single-layer FPC13 structure. The single-layer FPC13 structure includes a first cover film, a first FCCL, a substrate, a second FCCL, and a second cover film stacked together.

[0088] For example, taking FPC13, which includes a 6-layer structure, as an example, Figure 4B As shown, the FPC13 comprises a 6-layer structure, with each layer's structure referencing the diagram. To achieve electrical connections between the multiple layers, starting from the second layer (from top to bottom), the vias between each layer and the surface layer are blind vias, as shown... Figure 4BAs shown in the dashed box, this enables interconnection between any layers, allowing for signal transmission control, data transmission, and storage. Ultimately, all layers are connected to the second pad array via vias, thus enabling FPC13 to interconnect with package 12 through the second pad array.

[0089] The connection structure between FPC 13 and package 12 is described below. In one possible implementation, board 10 also includes N connectors 15. The N connectors 15 correspond one-to-one with the N packages 12, and each connector 15 is used for connecting one package 12 to the FPC 13, so that the FPC 13 can be connected to the N packages 12 through the N connectors.

[0090] The package substrate 121 of the package 12 also includes a first pad array (not shown). The first pad array can be disposed on the third surface s3 or the fourth surface s4 of the package substrate 121, and this application does not limit this. The first pad array and the second pad array are connected by a connector 15, thereby realizing the electrical connection between the package substrate 121 and the FPC 13. The package substrate 121 includes circuitry connecting the first pad array and the second pad array, so that the chip 122 in the package 12 can be connected to the FPC 13 through the package substrate 121, and thus the chips 122 in different packages 12 can transmit data through the FPC 13.

[0091] The first pad array includes multiple first pads, and the second pad array includes multiple second pads. Each first pad corresponds one-to-one with a second pad; that is, one first pad is electrically connected to only one second pad, and different first pads are connected to different second pads. In the first pad array, the first spacing between adjacent first pads is less than or equal to 6.5 mm, for example, a first spacing of 6.5 mm, 6 mm, 5 mm, 4.5 mm, 4 mm, 3.5 mm, 3 mm, 2 mm, or 1 mm. Similarly, in the second pad array, the second spacing between adjacent second pads is less than or equal to 6.5 mm, for example, a second spacing of 6.5 mm, 6 mm, 5 mm, 4.5 mm, 4 mm, 3.5 mm, 3 mm, 2 mm, or 1 mm. This increases the density of the first and second pad arrays, thereby increasing the transmission bandwidth of the FPC13. In this embodiment, the first and second spacings can be the same or close to each other.

[0092] There are several ways to implement connector 15. In one possible implementation, connector 15 is a conductive film or multiple solder balls. For example... Figure 5AAs shown, a solder ball is used to connect a first pad and a second pad, thereby electrically connecting the package substrate 121 and the FPC 13. The spacing between adjacent solder balls is the same as or close to the first / second spacing, that is, the spacing between adjacent solder balls is less than or equal to 6.5 mm, such as 6.5 mm, 6 mm, 5 mm, 4.5 mm, 4 mm, 3.5 mm, 3 mm, 2 mm, or 1 mm.

[0093] In another possible implementation, such as Figure 5B As shown, connector 15 is a silicone conductive material. Connector 15 includes opposing first and second surfaces. The first surface includes a first metal bump array (not shown), and the second surface includes a second metal bump array (not shown). Multiple metal bumps in the first metal bump array are connected one-to-one to multiple first pads in the first pad array, and multiple metal bumps in the second metal bump array are connected one-to-one to multiple second pads in the second pad array. The spacing between adjacent metal bumps in the first metal bump array is the same as or close to the first spacing / second spacing. The spacing between adjacent metal bumps in the second metal bump array is the same as or close to the first spacing / second spacing. That is, the spacing between adjacent metal bumps on connector 15 is less than or equal to 6.5 mm, for example, 6.5 mm, 6 mm, 5 mm, 4.5 mm, 4 mm, 3.5 mm, 3 mm, 2 mm, or 1 mm, etc.

[0094] The silicone conductor contains conductive particles, with conductive pillars formed by these particles in the center. One end of each conductive pillar is a metal bump from a first metal bump array, and the other end is a metal bump from a second metal bump array. In other words, multiple metal bumps in the first metal bump array correspond one-to-one with multiple metal bumps in the second metal bump array, and each metal bump in the first metal bump array is connected to its corresponding metal bump in the second metal bump array via a conductive pillar. When the conductive pillar is compressed, the conductive particles in the center come into contact with each other and conduct electricity, thus providing a path for signal transmission and data transmission. The silicone conductor has higher density and smaller volume, providing higher transmission bandwidth while miniaturizing, and it also features flexible and removable functionality. Therefore, the silicone conductor enables the connection between the first pad array and the second pad array, i.e., the connection between the package 12 and the FPC 13.

[0095] The FPC13 has multiple wirings, each wiring connecting two of the N packages 12. Each wiring is used for data transmission between the two packages 12 connected by the wiring. Optionally, the wiring width is less than or equal to 30 micrometers (µm), which can increase the wiring density on the FPC13, thereby increasing the transmission bandwidth of the FPC13.

[0096] Each of the N packages 12 is connected to at least one other package 12 among the N packages 12 via at least one wiring.

[0097] In one possible implementation, every two packages 12 out of the N packages 12 are connected via wiring in the FPC 13; that is, each package 12 out of the N packages 12 is connected to the other N-1 packages 12 via wiring in the FPC 13. For example, the FPC 13 includes N*(N-1) / 2 wirings, which connect the N packages 12 to each other. Of course, the number of wirings in the FPC 13 can also be greater than N*(N-1) / 2, which is not limited here.

[0098] In another possible implementation, some of the N packages 12 are connected to the other N-1 packages 12 via FPC 13, and some packages 12 are connected to the other K packages 12 via FPC 13. Here, K is an integer greater than or equal to 1 and less than N-1.

[0099] In another possible implementation, each of the N packages 12 is connected to the other K packages 12 via wiring in the FPC 13. Here, K is an integer greater than or equal to 1 and less than N-1.

[0100] Packages 12 that are not connected by wiring in FPC13 can be connected by wiring on PCB11. For example, packages 12 that are close to each other can be connected by wiring on PCB11. Of course, packages 12 that are not connected by wiring in FPC13 may also not be connected. For example, parallel packages 12 that have the same function and do not need to exchange information may not be connected by PCB11 and FPC13.

[0101] For example, such as Figure 3BAs shown, the chips in packages 9, 10, and 7 are all computing chips, while the chips in packages 8, 9, and 90 are all memory chips. FPC2 may include wiring connecting packages 9 and 8 (not shown), wiring connecting packages 9 to each other (not shown), wiring connecting packages 9 and 10 (not shown), wiring connecting packages 10 and 8 (not shown), wiring connecting packages 10 and 9 (not shown), wiring connecting packages 10 and 10 (not shown), wiring connecting packages 7 and 8 (not shown), wiring connecting packages 7 and 9 (not shown), and wiring connecting packages 7 and 10 (not shown). Therefore, the chips in packages 9, 10, and 7 can share the memory resources provided by packages 8, 9, and 10. FPC2 does not include wiring for connecting any two of packages 9, 10, and 7. Optionally, PCB2 may include wiring connecting any two of packages 9, 10, and 7. FPC2 does not include wiring for connecting any two of packages 8, 9, and 10. Optionally, PCB2 may include wiring connecting any two of packages 8, 9, and 10.

[0102] For example, such as Figure 3C As shown, the chip in package 11 is a computing chip, and the chips in packages 12, 13, and 14 are all memory chips. FPC3 may include wiring connecting package 11 and package 12 (not shown), wiring connecting package 11 and package 13 (not shown), and wiring connecting package 11 and package 14 (not shown). FPC3 does not include wiring for connecting any two of packages 12, 13, and 14. Optionally, PCB3 may include wiring connecting any two of packages 12, 13, and 14.

[0103] Optionally, the two packages 12 connected by the wiring of FPC 13 can also be connected simultaneously via wiring on PCB 11. The wiring on FPC 13 is used for high-bandwidth, low-latency data transmission between the two packages 12, such as data to be processed, model parameters, operators, intermediate data, or calculation results required for model training or inference. The wiring on PCB 11 is used for low-bandwidth data transmission between the two packages 12, such as control signals.

[0104] In this embodiment, an FPC 13 is used to directly connect multiple packages 12. Data can be transmitted between packages 12 via the FPC 13. The FPC 13 has a large transmission bandwidth, which can meet the high-bandwidth data transmission between chips 122 in different packages 12. Therefore, it is not limited by the trace density of the printed circuit board, and the number of packages 12 on the printed circuit board can be increased, that is, the number of chips 122 packaged on the printed circuit board can be increased, thereby increasing the computing and storage capacity within a limited space (area or even volume). By increasing the computing and / or storage capacity of a single board 10, when configuring the same amount of computing and storage resources in a data center, the number of boards 10 used can be reduced, thereby reducing the data center complexity and the required space size between boards 10.

[0105] like Figure 6 As shown. Figure 6 This is a schematic diagram of an electronic device provided in an embodiment of this application. The electronic device includes at least one board 10 and a housing 20. The board 10 is mounted on the housing 20 for fixing the board 10. The housing 20 may also include a power interface, which is connected to the board 10 for supplying power to the board 10. Of course, the electronic device may also include other components, which will not be described in detail here.

[0106] Electronic devices can be mobile phones, tablets, computers, servers, smart wearable devices, etc. Electronic devices can also be AI clusters, etc.

[0107] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, The board includes: N packages, each package including a package substrate and at least one chip, the at least one chip being electrically connected to the package substrate, the at least one chip including a computing chip and / or a memory chip, where N is an integer greater than or equal to 2; A printed circuit board is electrically connected to the packaging substrate of the N packages, and the printed circuit board is used to supply power to the chips in the N packages; The flexible printed circuit board (FPC) is electrically connected to the packaging substrate of the N packages, and the flexible printed circuit board is used for data transmission between the chips of the N packages.

2. The board according to claim 1, characterized in that, The N packages include a first package and a second package, wherein the chip type of the chip in the first package is the same as the chip type of the chip in the second package.

3. The board according to claim 2, characterized in that, The chips in the first package are all computing chips, and the chips in the second package are all computing chips; or The chips in the first package are all memory chips, and the chips in the second package are all memory chips.

4. The circuit board according to claim 2, characterized in that, The first package includes at least one computing chip and at least one memory chip, and the second package includes at least one computing chip and at least one memory chip.

5. The board according to claim 1, characterized in that, The N packages include a first package and a second package, wherein the chip type of the chip in the first package is different from the chip type of the chip in the second package.

6. The board according to claim 5, characterized in that, The chips in the first package are all computing chips, and the chips in the second package are all memory chips; or The first package includes at least one computing chip and at least one memory chip, and the chips in the second package are all memory chips; or The first package includes at least one computing chip and at least one memory chip, and the chips in the second package are all computing chips.

7. The circuit board according to any one of claims 1 to 6, characterized in that, The board also includes: N connectors are used to electrically connect the N packages to the FPC, and the N connectors correspond one-to-one with the N packages.

8. The board according to claim 7, characterized in that, The packaging substrate includes a first pad array, the first pad array including a plurality of first pads, the spacing between adjacent first pads being less than 6.5 mm; the FPC includes a second pad array, the second pad array including a plurality of second pads, the spacing between adjacent second pads being less than 6.5 mm; and the connector is electrically connected to the first pad array and the second pad array.

9. The board according to claim 8, characterized in that, The connector includes a first surface and a second surface opposite to each other. The first surface includes a first metal bump array, and the second surface includes a second metal bump array. A plurality of metal bumps in the first metal bump array are connected one-to-one with a plurality of first pads in the first pad array, and a plurality of metal bumps in the second metal bump array are connected one-to-one with a plurality of second pads in the second pad array.

10. The circuit board according to any one of claims 1 to 9, characterized in that, The FPC is provided with multiple wirings, each wiring connecting two of the N packages. Each of the N packages is connected to at least one other package through at least one wiring. Each wiring is used for data transmission between the two packages connected by the wiring.

11. An electronic device, characterized in that, The electronic device includes at least one board as claimed in any one of claims 1 to 10.

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