Topology inversion-based fault indicator logic verification method, device and equipment

Abstract

This invention provides a method, apparatus, and device for logic verification of fault indicators based on topology inversion, relating to the field of power grid fault detection technology. The method includes: generating an instantaneous inversion topology map; identifying conflicting nodes in the instantaneous inversion topology map, and correcting the topology map based on the conflicting nodes to obtain a reference topology map; for any activated fault indicator, treating the activated fault indicator as a virtual fault point, and determining the theoretical current direction characteristic values ​​from each active node to the virtual fault point based on the reference topology map; determining the measured current direction characteristic values ​​based on the voltage-current phase angle difference sequence of the activated fault indicator; and comparing the measured current direction characteristic values ​​with each theoretical current direction characteristic value to obtain the verification result of the activated fault indicator. This invention generates a topology map based on inversion, which fits the current power grid state and effectively adapts to the characteristics of multi-source distribution networks, effectively improving the accuracy of fault indicator state assessment.

Description

Technical Field

[0001] This invention relates to the field of power grid fault detection technology, and in particular to a fault indicator logic verification method, apparatus and equipment based on topology inversion. Background Technology

[0002] Fault indicators are critical monitoring devices widely installed on distribution network feeder lines. They determine whether a short circuit or grounding fault has occurred by detecting sudden changes in characteristic quantities such as line current or electric field. When a fault occurs, fault indicators located upstream of the fault point along the power supply path will activate sequentially and transmit their activation signals to the master station system via the communication network. The master station system performs logical verification on the received fault indicator activation signals, confirms the actual fault, and achieves rapid fault location, isolation, and power restoration.

[0003] In existing technologies, master station systems typically employ a static topology comparison method for logic verification. This involves retrieving the static physical topology diagram of the distribution network, assuming a radial network structure based on a single power source, inferring theoretically faulty sections from fault information, and determining whether indicators function as expected to assess the logical correctness of the indicators. However, due to frequent changes in the physical connections of the distribution network, the lag in updating the static physical topology diagram, and the increasingly complex and variable power flow direction, this verification method cannot adapt to these new network characteristics. Consequently, the master station system frequently makes incorrect judgments about correctly functioning indicators, severely impacting the efficiency and accuracy of fault handling. Summary of the Invention

[0004] This invention provides a fault indicator logic verification method, apparatus, and device based on topology inversion to solve the problems of untimely updates to static physical topology maps and misjudgments of indicators caused by the assumption of a radial network with a single power source, which affect the efficiency and accuracy of fault handling.

[0005] In a first aspect, embodiments of the present invention provide a fault indicator logic verification method based on topology inversion, comprising: Obtain the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window; Generate an instant inversion topology map based on the action state sequence of each activated fault indicator; The conflicting nodes in the instantaneous inversion topology diagram are identified, and the topological connection relationship of each conflicting node is corrected according to the voltage and current phase angle difference sequence of each conflicting node to obtain the reference topology diagram. Identify active nodes in the baseline topology graph; For any activated fault indicator, the activated fault indicator is taken as a virtual fault point. According to the reference topology, the theoretical current direction characteristic value from each active node to the virtual fault point is determined. According to the voltage-current phase angle difference sequence of the activated fault indicator, the measured current direction characteristic value is determined. The measured current direction characteristic value is compared with each theoretical current direction characteristic value to obtain the verification result of the activated fault indicator.

[0006] Secondly, embodiments of the present invention provide a fault indicator logic verification device based on topology inversion, comprising: The parameter acquisition module is used to acquire the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window. The topology building module is used to generate an instant inversion topology map based on the action state sequence of each activated fault indicator. The topology correction module is used to identify conflicting nodes in the instantaneous inversion topology diagram, and corrects the topological connection relationship of each conflicting node according to the voltage and current phase angle difference sequence of each conflicting node to obtain the reference topology diagram. The active node identification module is used to identify active nodes in the baseline topology graph; The verification module is used to take any activated fault indicator as a virtual fault point, determine the theoretical current direction characteristic value from each active node to the virtual fault point according to the reference topology diagram, determine the measured current direction characteristic value according to the voltage and current phase angle difference sequence of the activated fault indicator, and compare the measured current direction characteristic value with each theoretical current direction characteristic value to obtain the verification result of the activated fault indicator.

[0007] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect or any possible implementation thereof.

[0008] This invention provides a method, apparatus, and device for verifying the logic of fault indicators based on topology inversion. The method includes: acquiring the operational state sequence and voltage-current phase angle difference sequence of each activated fault indicator within a fault time window; generating an instantaneous inversion topology diagram based on the operational state sequence of each activated fault indicator; identifying conflicting nodes in the instantaneous inversion topology diagram; correcting the topological connection relationships of each conflicting node based on its voltage-current phase angle difference sequence to obtain a reference topology diagram; identifying active nodes in the reference topology diagram; for any activated fault indicator, treating it as a virtual fault point, and determining the theoretical current direction characteristic values ​​from each active node to the virtual fault point based on the reference topology diagram; determining the measured current direction characteristic values ​​based on the voltage-current phase angle difference sequence of the activated fault indicator; and comparing the measured current direction characteristic values ​​with the theoretical current direction characteristic values ​​to obtain the verification result of the activated fault indicator. This application first quickly inverts the fault topology of the distribution network and corrects conflicting nodes, making the topology diagram more consistent with the actual power grid state. At the same time, it considers the current direction verification of the fault indicator by each active node, which improves the accuracy of the indicator's logic judgment, thereby effectively improving the accuracy and reliability of fault location. Attached Figure Description

[0009] Figure 1 This invention provides a fault indicator logic verification method based on topology inversion. Figure 2 This is a schematic diagram of the structure of the fault indicator logic verification device based on topology inversion provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0010] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0011] See Figure 1 The document illustrates a flowchart of a fault indicator logic verification method based on topology inversion provided by an embodiment of the present invention, which is described in detail below: The above-mentioned fault indicator logic verification method based on topology inversion includes: S101: Obtain the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window; When a fault occurs, the short-circuit current propagates along the power supply path from the power source to the fault point, and the fault indicators are triggered sequentially. This application focuses only on the activated fault indicators and precisely filters data during the fault period to ensure the data purity for subsequent topology inversion and direction calculation. Furthermore, this application uses dual data acquisition of time series and electrical phase angles to obtain the full characteristics of the fault process within a precise time window. This provides a path basis for topology inversion and a measured benchmark for electrical verification and direction determination, fundamentally solving the problems of inaccurate verification and topology lag in multi-source distribution networks.

[0012] Prior to S101, the above method may also include: S106: Monitor the event alarm bus of the main station system and obtain the fault start signal; The event alarm bus is the standard channel for the master station system to publish information such as changes in the status of various devices and alarms.

[0013] This application includes a monitoring module that continuously subscribes to and connects to the event alarm bus of the distribution network master station system. The monitoring module parses the data stream flowing through the event alarm bus in real time and, based on preset event codes or keywords, captures fault initiation signals reported by any fault indicator that indicate the detection of fault current, thus establishing a passive, event-driven initiation mechanism.

[0014] S107: Analyze the fault start signal to obtain the feeder identifier and approximate fault time; Upon receiving a fault start signal, key information is analyzed to determine the scope of analysis, expanding from a single alarm point to the relevant network area.

[0015] Specifically, once a valid fault initiation signal is detected, the signal message (fault initiation signal) is immediately parsed. The message must contain two key fields: the unique device ID of the fault indicator that triggered the alarm, and the time of fault occurrence recorded by the master system, which is the approximate fault time. Using the device ID, the fault indicator is linked back to its feeder identifier by querying the device ledger database. The feeder identifier refers to the unique identification code or name of a specific power supply branch line (i.e., feeder) in the distribution network.

[0016] S108: Determine the fault time window based on the approximate fault time and determine the relevant fault indicator set based on the feeder identifier.

[0017] This application defines a fault time window based on a rough fault time, that is, defines a data range that can fully cover the transient and steady-state processes of the fault.

[0018] Specifically, using the approximate fault moment as a time reference point, the time is extended forward and backward according to preset rules to define the fault time window used for this data acquisition. For example, using the approximate fault moment as a time reference point, the time is extended forward by 2 power frequency cycles, approximately 40 milliseconds, to include the normal operating state before the fault; and extended backward by 10 power frequency cycles, approximately 200 milliseconds, to ensure complete capture of the entire process of fault occurrence, development, and steady state.

[0019] This application also filters out a list of device IDs of all fault indicators installed under the feeder network in the equipment ledger based on the feeder identifier. These devices together constitute the relevant fault indicator set.

[0020] Perform precise data retrieval based on a defined equipment and time range, and collect all raw data for subsequent analysis.

[0021] S109: Obtain data from each fault indicator in the relevant fault indicator set and determine the fault indicators that have been activated.

[0022] A batch data query request is initiated to the historical database or the real-time database. The request is to obtain all telemetry records of each fault indicator in the relevant fault indicator set within the defined fault time window, mainly including the action state sequence and the voltage and current phase angle difference sequence, thereby completing the data preparation work.

[0023] An action status sequence refers to a series of action status values ​​reported by a fault indicator within a fault time window, sampled at fixed time intervals (such as every millisecond or every power frequency cycle). This sequence is essentially a time series of Boolean values ​​(0 or 1, or TRUE / FALSE), where "1" or "TRUE" indicates that the fault indicator detected a fault characteristic (such as current exceeding the limit) at the corresponding sampling time and triggered an action (such as flipping a sign, flashing an alarm, or sending an alarm signal); "0" or "FALSE" indicates that the fault indicator is in a normal, inactive state at that sampling time. A voltage-current phase angle difference sequence refers to a sequence of phase difference (angle) values ​​between voltage and current measured and reported by a fault indicator at the same time intervals within the same fault time window.

[0024] Based on the above, the action state sequence is a dataset containing the Boolean values ​​of the action states of all relevant fault indicators at each sampling point within the fault time window. By traversing this dataset, fault indicators whose action state values ​​have changed from zero to one at least once are identified as activated fault indicators. This application ensures, through monitoring, that all necessary input data can be captured promptly and accurately at the initial moment of a fault occurrence, providing a complete and high-quality data foundation for subsequent topology inversion and logical analysis.

[0025] S102: Generate an instantaneous inversion topology diagram based on the action state sequence of each activated fault indicator; Based on the action timing of each activated fault indicator in the action state sequence, this application transforms the discrete, time-based fault indicator action signals into a structured, real-time inversion topology map that reflects the actual physical connection relationship, according to the timing and proximity of current propagation. It does not rely on a preset network diagram and can effectively interpret the time imprint left by the fault current as it propagates in the network.

[0026] In one possible implementation, S102 may include: S1021: Determine the first activation time of each activated fault indicator based on the activation state sequence of each activated fault indicator; Each activated fault indicator is defined as an active node. The action state sequence of each active node is traced back to pinpoint the timestamp corresponding to the first sampling point where its action state changes from zero to one, i.e., the first action moment. This timestamp typically requires millisecond-level accuracy to effectively distinguish the action sequence between adjacent nodes. The system pairs the identifiers of all active nodes with their corresponding first action moments.

[0027] S1022: Sort each activated fault indicator according to its first activation time to obtain the node activation timing sequence; The nodes are globally sorted from smallest to largest timestamp values, ultimately generating an ordered sequence of actions. This sequence serves as the sole basis for subsequent path construction. This application performs time-series labeling and sorting of active nodes, with the engineering aim of establishing a causal chain reflecting the order of fault propagation for subsequent topology construction.

[0028] S1023: Take the first preset number of activated fault indicators in the node action sequence as the starting point, and connect each activated fault indicator in the node action sequence according to the principle of temporal proximity to form at least one action propagation chain. Each activated node is a basic vertex that constitutes the instantaneous inversion topology graph. The starting point of the fault current propagation is located, and the root node of the topology inversion is determined.

[0029] Specifically, one or several (a preset number) of the nodes that are ranked first in the node action sequence, i.e., the nodes with the smallest first action time, are directly selected as the starting point for current propagation.

[0030] In another embodiment, to increase robustness, all active nodes whose first action time is within a preset tolerance time window, such as those with a first action time difference of less than 1 to 2 milliseconds, can be regarded as parallel starting points. This can cope with the complex situation where multiple branches in the near end fail at the same time.

[0031] Based on the principle of temporal proximity, current paths are iteratively constructed to connect discrete active nodes into paths with upstream and downstream relationships. Starting from the origin of current propagation, subsequent active nodes in the node action sequence are processed sequentially. For each active node to be processed, its most likely upstream node is searched among all processed and placed in the path. The criterion is minimizing the time difference; that is, among all active nodes that acted before it, the node with the shortest time interval between its first action and its first action is selected as its parent node, and a directed connection is established from the parent node to this node. The above process is repeated until all active nodes are connected, forming one or more tree-like or chain-like action propagation chains.

[0032] S1024: Combine at least one action propagation chain to obtain an instant inversion topology; wherein, each action fault indicator forms a node of the instant inversion topology.

[0033] By combining at least one action propagation chain generated above, all activated nodes are treated as vertices of the graph, and all established parent-child directed connections are treated as directed edges. This directed acyclic graph, consisting of the set of vertices and directed edges, is the final output instantaneous inversion topology graph.

[0034] S103: Determine the conflicting nodes in the instantaneous inversion topology diagram, and correct the topological connection relationship of each conflicting node according to the voltage and current phase angle difference sequence of each conflicting node to obtain the reference topology diagram. Identify conflicting nodes in the instantaneous inversion topology graph and locate the parts of the instantaneous inversion topology graph with the most ambiguous connections and the most likely errors.

[0035] Iterate through all active nodes. If the time difference between the first action of an active node and the first action of the active node is less than a fuzzy threshold (e.g., 5 milliseconds), and the first action of the active node is earlier, then the active node is considered an upstream active node that may have a direct physical connection with it, and is defined as a potential upstream node. Simultaneously, all action propagation chains containing potential upstream nodes are marked as candidate action propagation chains for that active node.

[0036] In one possible implementation, S103 may include: S1031: For any node in the instantaneous inversion topology graph, if the node has at least two potential upstream nodes, then the node is regarded as a conflict node, and the action propagation chain of each potential upstream node of the node is regarded as the candidate upstream action propagation chain of the node. If a node has at least two potential upstream nodes, it indicates that the upstream connection relationship of that node is uncertain, thus locating the part of the instantaneous inversion topology graph where the connection relationship is the most ambiguous and most likely to be erroneous.

[0037] S1032: For any conflict node, determine the correlation index between the conflict node and each candidate upstream action propagation chain, determine the target upstream action propagation chain based on each correlation index, and connect the conflict node to the target upstream action propagation chain.

[0038] In real-world business systems, a conflict node typically has only one true upstream action propagation chain. Therefore, calculating the correlation index between the conflict node and each candidate upstream action propagation chain, quantifying the "node-chain" affinity, and selecting the chain with the highest correlation index to assign the conflict node to that chain maximizes the probability of restoring the true causal relationship, constructing a clear action propagation chain, and making the corrected baseline topology graph more closely match the actual application scenario, thus improving the accuracy and reliability of the topology graph.

[0039] Furthermore, the instantaneous inverted topology graph can be compared with the static topology graph to identify nodes with differences, which are defined as nodes to be adjudicated. For any node to be adjudicated, if the node to be adjudicated has at least two potential upstream nodes, the node to be adjudicated is regarded as a conflict node, and the action propagation chain of each potential upstream node of the node to be adjudicated is regarded as the candidate upstream action propagation chain of the node. Then, the steps of S1032 are continued.

[0040] In other words, problems are discovered by comparing with the static topology diagram, that is, the current physical connection does not match the historical record, and then the temporal cause is located and the conflicting nodes are identified.

[0041] Specifically, the voltage and current phase angle difference sequence can be used to solve the problem of uncertainty in connection relationship caused by the high similarity of the action timing.

[0042] In one possible implementation, S1032 includes: 1. For any candidate upstream action propagation chain of this conflict node: (1) Determine the Pearson correlation coefficient between the voltage and current phase angle difference sequence of the head node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node, and use it as the first correlation value; (2) Determine the Pearson correlation coefficient between the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node, and use it as the second correlation value; (3) The first correlation value and the second correlation value form the correlation index between the conflict node and the candidate upstream action propagation chain.

[0043] The voltage, current, and phase angle difference sequences of the first node (the earliest node to act in the chain) and the last node (the current last node in the chain) reflect the dynamic changes in electrical quantities along the propagation path. Conflict nodes exhibit abnormal fluctuations in electrical quantities such as voltage, current, and phase angle difference, and their timing sequences carry the propagation characteristics of the fault. Therefore, this application calculates the correlation coefficients of the phase angle difference sequences between the first node and the conflict node, and between the last node and the conflict node, forming a pair of correlation indices. These indices comprehensively reflect the degree of correlation between the conflict node and the entire candidate upstream action propagation chain, thereby determining whether the candidate upstream action propagation chain is the true upstream path that triggered the current node conflict.

[0044] Specifically, the formula for calculating the Pearson correlation coefficient is as follows:

[0045] in, This is the Pearson correlation coefficient, also known as the first or second correlation value. This is the voltage-current phase angle difference sequence of the conflicting nodes. The representative reference sequence is the voltage-current phase angle difference sequence of the tail node or the voltage-current phase angle difference sequence of the head node of a candidate upstream action propagation chain. Used to calculate the covariance of two sequences. Used to calculate the standard deviation of a sequence. It is a dimensionless value between -1 and 1. The closer the value is to 1, the stronger the linear correlation between the two sequences, that is, the higher the electrical homology.

[0046] Furthermore, the first correlation value and the second correlation value form the correlation index between the conflict node and the candidate upstream action propagation chain. More specifically, when comparing the magnitude of the correlation index, the correlation index can be the average of the first correlation value and the second correlation value, or the larger of the first correlation value and the second correlation value; no specific limitation is made here.

[0047] Because the voltage and current phase angle differences between nodes along the same motion propagation path are continuous, gradual, and physically consistent, the phase angle difference between a conflicting node and a node in its candidate upstream motion propagation chain should both be within a reasonable range. If a conflicting node is outside this range, it can be determined that it did not originate from this candidate upstream motion propagation chain and is physically not on the same path.

[0048] Based on this, in one possible implementation, S1032 may include: 2. For any candidate upstream action propagation chain of this conflict node: (1) Take the first action time of the first node of the candidate upstream action propagation chain as the starting time, extract the voltage and current phase angle difference in the voltage and current phase angle difference sequence of the first node of the candidate upstream action propagation chain within the first preset time from the starting time, and calculate the average value to obtain the first average phase angle value. (2) Extract the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain within the first preset time period starting from the start time, and calculate the average value to obtain the second average phase angle value; (3) Extract the voltage and current phase angle difference within the first preset time period from the start time of the conflict node in the voltage and current phase angle difference sequence, and calculate the average value to obtain the third average phase angle value; (4) Determine a reasonable phase interval based on the first average phase angle value and the second average phase angle value; (5) If the third average phase angle value is within a reasonable phase range, then add the candidate upstream action propagation chain to the candidate chain set; otherwise, do not add it to the candidate chain set. (6) The candidate upstream action propagation chain with the largest correlation index in the candidate chain set is taken as the target upstream action propagation chain.

[0049] Therefore, this application extracts the voltage and current phase angle difference sequence within a first preset time period after the start time for the chain head node, chain tail node, and conflict node, and calculates the mean value to obtain the first average phase angle value, the second average phase angle value, and the third average phase angle value. Through averaging, the influence of instantaneous disturbances, noise, and sampling errors is weakened, the overall phase trend is highlighted, and the robustness of judgment is improved. Using the average phase angle value at the chain head (first average phase angle value) and the average phase angle value at the chain tail (second average phase angle value), a reasonable phase interval is constructed. This interval reflects the normal phase change range of the candidate upstream action propagation chain during propagation and serves as the electrical basis for determining whether a conflict node belongs to the propagation path.

[0050] Compare the third average phase angle value of the conflict node with the reasonable phase range: if it falls within the range, it means that the conflict node and the propagation chain are consistent in electrical phase change, and it belongs to the reasonable subsequent propagation node and is included in the candidate chain set; if it is not within the range, it means that the electrical characteristics of the two are significantly different, and the conflict node cannot have evolved from the propagation chain, so it is directly eliminated.

[0051] This application rapidly filters propagation chains with electrical feature mismatches through phase intervals, significantly reducing the number of candidate chains entering the correlation ranking. Then, from the set of electrically reliable candidate chains, the upstream action propagation chain with the highest correlation index is selected as the target chain for topology correction. Through these steps, the previously ambiguous connection relationships are eliminated, and the inverted topology is corrected and confirmed, resulting in a unique and physically highly reliable structure that satisfies both electrophysical laws and possesses the highest correlation reliability.

[0052] For example, the first preset duration can be 2 to 3 power frequency cycles.

[0053] Because fault and action propagation has short-term, rapid, and periodic electrical characteristics, selecting 2 to 3 cycles as the statistical duration can, on the one hand, cover the complete transient response process after the fault / action occurs and obtain sufficient phase angle difference samples to ensure the representativeness of the mean calculation; on the other hand, this duration matches the duration of typical power system disturbances and the time scale of protection actions, which can accurately capture the electrical correlation characteristics on the same propagation chain and avoid statistical bias caused by too short a duration or the introduction of subsequent irrelevant disturbances due to too long a duration.

[0054] In one possible implementation, determining the reasonable phase interval based on the first average phase angle value and the second average phase angle value may include: 1) Obtain the preset line impedance phase shift tolerance generated by the comprehensive calibration of the inherent measurement error of the fault indicator and the maximum possible phase shift of the line impedance between adjacent nodes; 2) Determine the shortest circumferential angle distance between the first average phase angle value and the second average phase angle value, and take the minor arc formed by the shortest circumferential angle distance as the reference, and expand outwards to both ends considering the preset line impedance phase shift tolerance to obtain a reasonable phase range.

[0055] This application dynamically reconstructs and corrects the network topology based on the actual physical response during a fault, providing a more accurate network foundation for all subsequent logical verifications, thereby improving the accuracy of device status assessment.

[0056] S104: Identify active nodes in the baseline topology graph; Scan the device attribute data (including device type) of all nodes (operated fault indicators) in the baseline topology diagram. Nodes whose device type is identified as substation outgoing circuit breakers or feeder switches are identified as primary power supply nodes; nodes whose device type is identified as grid-connected photovoltaic, energy storage, or other distributed generation equipment, and whose operating status is grid-connected, are identified as distributed power supply nodes. The primary power supply nodes and all distributed power supply nodes are aggregated to form an active node set.

[0057] S105: For any activated fault indicator, take the activated fault indicator as a virtual fault point, and determine the theoretical current direction characteristic value from each active node to the virtual fault point according to the reference topology diagram; determine the measured current direction characteristic value according to the voltage-current phase angle difference sequence of the activated fault indicator; compare the measured current direction characteristic value with each theoretical current direction characteristic value to obtain the verification result of the activated fault indicator.

[0058] Using the location of the activated fault indicator as the virtual fault point, calculate the theoretical current direction characteristic value from each active node to the virtual fault point.

[0059] In one possible implementation, S105 may include: S1051: For any active node, determine the electrical path impedance from the active node to the virtual fault point based on the reference topology diagram. Based on the electrical path impedance and the equivalent power supply model of the active node, determine the theoretical short-circuit current generated at the virtual fault point under the action of the active node alone, and use it as the theoretical current direction characteristic value of the active node.

[0060] The electrical path impedance from each active node to the virtual fault point is calculated independently, quantifying the total resistance encountered by current flowing from that specific power source to the fault point. For each active node in the set of active nodes, a shortest path algorithm from graph theory, such as Dijkstra's algorithm, is used to find a unique electrical path back from the virtual fault point to the current active node in the baseline topology graph. The weight of the path is determined by the line parameters, namely the complex impedance value of each line segment, which is retrieved from the system line ledger database. The complex impedances of all line segments on the path are vector-superimposed to obtain a total complex impedance value, which is the electrical path impedance corresponding to the active node.

[0061] Using basic circuit laws, the theoretical current direction contributed by each active node is calculated, transforming the electrical path impedance into a current phase angle directly comparable to measured data. For each active node, the characteristic value of the theoretical current direction generated at the virtual fault point under its individual action is calculated using the following formula:

[0062] in, It is a complex number representing the theoretical short-circuit current. It is the power supply voltage in the equivalent power source model of the active node, usually the rated voltage vector of the node before the fault. It is a known complex quantity obtained from the power grid model parameter library. This is the electrical path impedance from the active node to the virtual fault point, calculated in the previous step. The calculated complex number... The phase angle is the theoretical current direction contributed by the active node to the virtual fault point, i.e., the characteristic value of the theoretical current direction.

[0063] The equivalent power source model of an active node refers to the Thevenin equivalent circuit model used to characterize the short-circuit characteristics of the power source. It consists of two core parameters: one is the operating voltage phasor of the node before the fault (as the equivalent potential) obtained from the real-time database of the distribution network; the other is the internal complex impedance characterizing the output characteristics of the power source (for the main power source, it is the short-circuit impedance of the main grid system; for distributed power sources, it is the equivalent transient impedance of the generator or inverter).

[0064] This application constructs a theoretical reference for the direction of current on a verified and accurate reference topology through circuit calculations. This reference can accurately reflect the electrical phase characteristics of the current flowing from each power source to a specific fault point in a multi-power source network.

[0065] In one possible implementation, S105 may include: S1052: Take the first activation time of the activated fault indicator as the starting time, extract the voltage and current phase angle difference within the second preset time period from the starting time in the voltage and current phase angle difference sequence of the activated fault indicator, and calculate the average value to obtain the fourth average phase angle value, which is used as the measured current direction characteristic value.

[0066] This application determines the characteristic value of the measured current direction to avoid interference from transient processes and obtain a single angle value that can be used for accurate comparison. For example, to ensure the consistency of the verification benchmark and the efficiency of the calculation, the second preset time period selected here can be the same as the first preset time period used in the electrical homogeneity verification.

[0067] In one possible implementation, the active node includes: a main power node and a distributed power node; S105 may include: S1053: Match the measured current direction characteristic value with the theoretical current direction characteristic value corresponding to the main power supply node to generate the first matching result; S1054: If the first matching result is a match, then the verification result of the activated fault indicator is that the action logic is valid; S1055: If the first matching result is a mismatch, the measured current direction characteristic value is matched with the theoretical current direction characteristic value corresponding to each distributed power node to obtain the second matching result. S1056: If the second matching result is that at least one distributed power node has a theoretical current direction characteristic value that matches the measured current direction characteristic value, then the verification result of the activated fault indicator is a direction logic configuration error. S1057: If the second matching result is that there is no theoretical current direction characteristic value corresponding to the distributed power node that matches the measured current direction characteristic value, then the verification result of the activated fault indicator is a hardware measurement unit fault.

[0068] This application matches the measured current direction characteristic value with various theoretical scenarios to definitively reveal the real physical cause of the fault indicator's action, whether it is a conventional forward fault or a reverse feed caused by distributed power sources.

[0069] Specifically, the matching process consists of two rounds. The first round of matching is used to check whether the fault indicator action conforms to the most common fault model driven by the main power supply. The second round of matching is used to search whether the fault indicator action is caused by the reverse current of the distributed power supply.

[0070] First round of matching: The measured current direction characteristic value (characterizing the measured current direction) is matched with the theoretical current direction characteristic value (characterizing the theoretical current direction of the main power supply) corresponding to the main power supply node in the first round to verify the consistency of the positive fault and generate the first matching result; if the first matching result is a match, it means that the action logic is effective.

[0071] Specifically, the difference between the measured current direction characteristic value and the theoretical current direction characteristic value corresponding to the main power supply node is calculated. It is then determined whether this difference falls within a preset directional consistency tolerance range, such as ±15 degrees. If the difference falls within the directional consistency tolerance range, the measured direction is considered to be consistent with the theoretical direction of the main power supply, indicating a typical forward fault.

[0072] Second round of matching: If the first matching result is a mismatch, a second round of matching is triggered to check the consistency of the reverse current of the distributed power source and explore whether the fault indicator action is caused by the reverse current of the distributed power source.

[0073] For each distributed power node, the difference is calculated separately, and it is determined whether the difference is within a preset directional consistency tolerance range.

[0074] If at least one difference exists within the directional consistency tolerance range, it indicates that the current causing the fault indicator to activate mainly originates from the distributed power source, meaning a backflow current from the distributed power source has occurred, thus ruling out the possibility of a traditional forward fault. Check the directional discrimination settings of the fault indicator and, based on whether the settings are suitable for multi-source scenarios, output a diagnostic conclusion of directional logic configuration error.

[0075] If no difference exists within the directional consistency tolerance range, it indicates a mismatch with all theoretical current directions. In this case, the diagnostic conclusion of the hardware measurement unit fault is output based on the current amplitude information of the fault indicator.

[0076] This application independently calculates and matches the theoretical current contribution of each active node to the fault point, effectively identifying indicator actions caused by backflow current from distributed generation sources. This overcomes the poor applicability of traditional unidirectional verification models in multi-source distribution networks, thus enhancing the method's adaptability to complex network structures and novel fault modes. Each calculation step in the verification method of this application has a substantial physical correspondence, ensuring the traceability and verifiability of the output diagnostic conclusions. This method provides a physical mechanism-based judgment basis for distribution network equipment condition assessment, thereby improving the accuracy and interpretability of fault indicator action logic diagnosis in multi-source complex network environments.

[0077] Furthermore, this application can also transform the matching results into a final and clear diagnostic opinion on the status of the fault indicator device, and trigger corresponding operation and maintenance operations based on different diagnostic results, thereby realizing a closed loop from data analysis to actual operation and maintenance work orders.

[0078] For example, when the first matching result is a match, it indicates that the measured current direction of the fault indicator is consistent with the theoretical direction of the main power supply. This matching result is directly interpreted as the equipment's operating logic being correct and able to accurately respond to traditional forward short-circuit faults. Based on this, a diagnostic conclusion indicating that the operating logic is valid is generated and output, indicating that the fault indicator is working normally and requires no maintenance.

[0079] When the first matching result is a mismatch, it indicates that the fault indicator action does not conform to the main power drive fault model, triggering the second round of matching and generating a second matching result.

[0080] If the second matching result shows that at least one distributed power node's theoretical current direction characteristic value matches the measured current direction characteristic value, then the fault indicator's device parameter file is retrieved, and the preset direction discrimination setting is checked. This setting typically includes one or more angle sectors used to define the forward fault current. It is then checked whether this direction discrimination setting includes sectors capable of covering the direction of the reverse current from the distributed power source. If the check result is negative, meaning the fault indicator's current configuration cannot recognize this reverse current, the root cause is determined to be outdated software configuration, and a diagnostic conclusion of incorrect direction logic configuration is output. Simultaneously, the system automatically generates a maintenance work order suggestion stating "Direction protection settings or logic need to be updated to adapt to multi-source networks," clearly indicating software-level rectification.

[0081] The specific steps for checking the direction determination value are as follows: Analysis of the setpoint range: Retrieve the direction discrimination setpoint of the fault indicator from the equipment parameter file, extract its preset allowable phase angle boundary range, and denote it as the phase angle sector. ; Extracting the comparison target: Obtaining the theoretical current direction feature value corresponding to the distributed power node that matches the measured current direction feature value, denoted as ; Inclusivity decision: Determine Does it fall into the phase angle sector? If it does not fall within the specified range, it is determined that the setpoint sector of the fault indicator fails to cover the current reverse current direction, and thus outputs the diagnostic conclusion of "direction logic configuration error".

[0082] If the second matching result shows that there is no match between the theoretical current direction characteristic value and the measured current direction characteristic value for the distributed power node, a final comprehensive judgment is made. If the short-circuit current amplitude reported by the fault indicator exceeds its preset action threshold, but its phase angle measurement result shows an irregular state that deviates significantly from any physical model, it is finally determined that the sensor, transformer, or related processing circuit used to measure voltage or current phase inside the fault indicator has suffered physical damage, and a hardware measurement unit fault diagnosis conclusion is output, while a maintenance work order with the suggestion of "equipment replacement" is generated.

[0083] The preset action threshold refers to the current amplitude start-up setting value pre-configured inside the fault indicator to determine whether a short circuit or overcurrent fault has occurred in the line. Specifically, it is an inherent attribute parameter retrieved from the equipment parameter file, representing the minimum measured effective current value (or current mutation amount) required to trigger the indicator to generate and report a fault action signal.

[0084] Finally, the analysis process and results can be structured and encapsulated to generate a comprehensive and standardized report. All key data assets in this verification process are collected, including but not limited to: the final output diagnostic conclusion text, the data structure of the baseline topology diagram used as the basis for verification, and key intermediate data used in the matching and comparison process to support the conclusions, such as measured current direction characteristic values ​​and all calculated theoretical current direction characteristic values. This data is then organized and formatted according to a predefined template, and packaged to generate a unique verification report with a timestamp and event ID.

[0085] The execution results are persistently stored and automatically pushed to ensure proper archiving of analysis results and proactively drive downstream business processes. After the report is generated, it is completely written to a dedicated historical database for subsequent auditing, querying, and big data analysis. Simultaneously, the work order creation interface of the power distribution operation and maintenance management system is called, which is typically a WebService or API-based interface. The core content of the verification report, especially the diagnostic conclusions and operation and maintenance recommendations, is populated as parameters into the interface request, automatically creating a new operation and maintenance work order and assigning it to the relevant operation and maintenance team.

[0086] The system's self-correction mechanism is triggered based on specific diagnostic conclusions, dynamically optimizing the system's foundational data by utilizing the problems discovered during the diagnosis. The system checks if the diagnostic conclusions include the specific type "topology record error." If this conclusion is detected, in addition to generating regular reports and pushing work orders, a topology map update prompt is also generated. This prompt is specifically pushed to the Geographic Information System (GIS) maintenance module. The prompt includes a verified, real-time inverted topology map, serving as direct evidence for correcting erroneous connections in the GIS database. This leverages a fault diagnosis opportunity to improve the accuracy of the foundational data and prevent similar problems from recurring in the future.

[0087] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0088] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0089] Figure 2 A schematic diagram of the fault indicator logic verification device based on topology inversion provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: like Figure 2 As shown, the fault indicator logic verification device based on topology inversion includes: Parameter acquisition module 21 is used to acquire the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window; Topology building module 22 is used to generate an instant inversion topology map based on the action state sequence of each activated fault indicator; The topology correction module 23 is used to determine the conflicting nodes in the instantaneous inversion topology diagram, and correct the topology connection relationship of each conflicting node according to the voltage and current phase angle difference sequence of each conflicting node to obtain the reference topology diagram. The active node identification module 24 is used to identify active nodes in the baseline topology graph; The verification module 25 is used to take any activated fault indicator as a virtual fault point, determine the theoretical current direction characteristic value from each active node to the virtual fault point according to the reference topology diagram, determine the measured current direction characteristic value according to the voltage and current phase angle difference sequence of the activated fault indicator, and compare the measured current direction characteristic value with each theoretical current direction characteristic value to obtain the verification result of the activated fault indicator.

[0090] In one possible implementation, the topology building module 22 may include: The action time extraction unit is used to determine the first action time of each activated fault indicator based on the action state sequence of each activated fault indicator. The sorting unit is used to sort each activated fault indicator according to the time of its first activation, so as to obtain the node activation timing sequence. The action propagation chain construction unit is used to take the first preset number of activated fault indicators in the node action time sequence as the starting point, and connect each activated fault indicator in the node action time sequence according to the principle of temporal proximity to form at least one action propagation chain. A topology graph construction unit is used to combine at least one action propagation chain to obtain an instant inversion topology graph; wherein, each action fault indicator forms a node of the instant inversion topology graph.

[0091] In one possible implementation, the topology correction module 23 may include: The conflict node determination unit is used to identify any node in the instantaneous inversion topology graph as a conflict node if the node has at least two potential upstream nodes, and to identify the action propagation chains of each potential upstream node as candidate upstream action propagation chains of the node. The conflict node correction unit is used to determine the correlation index between any conflict node and each candidate upstream action propagation chain, determine the target upstream action propagation chain based on each correlation index, and connect the conflict node to the target upstream action propagation chain.

[0092] In one possible implementation, the conflict node correction unit can be specifically used for: 1. For any candidate upstream action propagation chain of this conflict node: (1) Determine the Pearson correlation coefficient between the voltage and current phase angle difference sequence of the head node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node, and use it as the first correlation value; (2) Determine the Pearson correlation coefficient between the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node, and use it as the second correlation value; (3) The first correlation value and the second correlation value form the correlation index between the conflict node and the candidate upstream action propagation chain.

[0093] In one possible implementation, the conflict node correction unit can also be specifically used for: 2. For any candidate upstream action propagation chain of this conflict node: (1) Take the first action time of the first node of the candidate upstream action propagation chain as the starting time, extract the voltage and current phase angle difference in the voltage and current phase angle difference sequence of the first node of the candidate upstream action propagation chain within the first preset time from the starting time, and calculate the average value to obtain the first average phase angle value. (2) Extract the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain within the first preset time period starting from the start time, and calculate the average value to obtain the second average phase angle value; (3) Extract the voltage and current phase angle difference within the first preset time period from the start time of the conflict node in the voltage and current phase angle difference sequence, and calculate the average value to obtain the third average phase angle value; (4) Determine a reasonable phase interval based on the first average phase angle value and the second average phase angle value; (5) If the third average phase angle value is within a reasonable phase range, then add the candidate upstream action propagation chain to the candidate chain set; otherwise, do not add it to the candidate chain set. (6) The candidate upstream action propagation chain with the largest correlation index in the candidate chain set is taken as the target upstream action propagation chain.

[0094] In one possible implementation, the verification module 25 may include: The first current direction determination unit is used to determine the electrical path impedance from the active node to the virtual fault point based on the reference topology diagram for any active node, and to determine the theoretical short-circuit current generated at the virtual fault point under the action of the active node alone based on the electrical path impedance and the equivalent power source model of the active node, which is used as the theoretical current direction characteristic value of the active node.

[0095] In one possible implementation, the verification module 25 may include: The second current direction determination unit is used to take the first action time of the activated fault indicator as the starting time, extract the voltage and current phase angle difference within a second preset time period from the starting time in the voltage and current phase angle difference sequence of the activated fault indicator, and calculate the average value to obtain the fourth average phase angle value, which is used as the measured current direction characteristic value.

[0096] In one possible implementation, the active node includes: a main power node and distributed power nodes; the verification module 25 may include: The first matching unit is used to match the measured current direction characteristic value with the theoretical current direction characteristic value corresponding to the main power supply node to generate the first matching result; The first result output unit is used to determine that the verification result of the activated fault indicator is valid if the first matching result is a match. The second matching unit is used to match the measured current direction feature value with the theoretical current direction feature value corresponding to each distributed power node if the first matching result is a mismatch, so as to obtain the second matching result. The second result output unit is used to determine the direction logic configuration error if the second matching result is that at least one distributed power node has a theoretical current direction characteristic value that matches the measured current direction characteristic value. The third result output unit is used to determine the hardware measurement unit fault if the second matching result is that there is no theoretical current direction characteristic value and the measured current direction characteristic value corresponding to the distributed power node.

[0097] Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. For example... Figure 3 As shown, the electronic device 3 of this embodiment includes a processor 30 and a memory 31. The memory 31 stores a computer program 32. When the processor 30 executes the computer program 32, it implements the steps in the various method embodiments described above. Alternatively, when the processor 30 executes the computer program 32, it implements the functions of each module / unit in the various device embodiments described above.

[0098] For example, computer program 32 may be divided into one or more modules / units, which are stored in memory 31 and executed by processor 30 to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 32 in electronic device 3.

[0099] Electronic device 3 may include, but is not limited to, processor 30 and memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 3 may also include input / output devices, network access devices, buses, etc.

[0100] For the sake of simplicity and clarity, only the above-described functional modules / units are used as examples. In practical applications, the functions described above can be assigned to different functional modules / units as needed. These modules / units can be implemented in hardware, software, or a combination of both.

[0101] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0102] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A fault indicator logic verification method based on topology inversion, characterized in that, include: Obtain the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window; Generate an instant inversion topology map based on the action state sequence of each activated fault indicator; The conflicting nodes in the instantaneous inversion topology diagram are identified, and the topological connection relationship of each conflicting node is corrected according to the voltage and current phase angle difference sequence of each conflicting node to obtain the reference topology diagram. Identify the active nodes in the baseline topology graph; For any activated fault indicator, the activated fault indicator is taken as a virtual fault point, and the theoretical current direction characteristic value from each active node to the virtual fault point is determined according to the reference topology diagram. Based on the voltage-current phase angle difference sequence of the activated fault indicator, determine the characteristic value of the measured current direction; The measured current direction characteristic value is compared with each of the theoretical current direction characteristic values ​​to obtain the verification result of the activated fault indicator.

2. The fault indicator logic verification method based on topology inversion according to claim 1, characterized in that, The step of generating an instantaneous inversion topology map based on the action state sequence of each activated fault indicator includes: The first activation time of each activated fault indicator is determined based on the action state sequence of each activated fault indicator. The action timing sequence of each activated fault indicator is obtained by sorting the first activation time of each activated fault indicator. Starting from the first preset number of activated fault indicators in the node action time sequence, connect each activated fault indicator in the node action time sequence according to the principle of temporal proximity to form at least one action propagation chain. The combination of at least one action propagation chain yields the instantaneous inversion topology; wherein each activated fault indicator forms a node in the instantaneous inversion topology.

3. The fault indicator logic verification method based on topology inversion according to claim 1, characterized in that, The process of determining the conflicting nodes in the instantaneous inversion topology diagram, and correcting the topological connection relationships of each conflicting node based on the voltage-current phase angle difference sequence of each conflicting node to obtain a reference topology diagram, includes: For any node in the instantaneous inversion topology graph, if the node has at least two potential upstream nodes, then the node is regarded as the conflict node, and the action propagation chain of each potential upstream node of the node is regarded as the candidate upstream action propagation chain of the node. For any conflict node, determine the correlation index between the conflict node and each candidate upstream action propagation chain, determine the target upstream action propagation chain based on each correlation index, and connect the conflict node to the target upstream action propagation chain.

4. The fault indicator logic verification method based on topology inversion according to claim 3, characterized in that, The determination of the correlation index between the conflict node and each candidate upstream action propagation chain includes: For any candidate upstream action propagation chain of this conflict node: The Pearson correlation coefficient between the voltage and current phase angle difference sequence of the head node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node is determined as the first correlation value. The Pearson correlation coefficient between the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain and the voltage and current phase angle difference sequence of the conflict node is determined as the second correlation value. The first correlation value and the second correlation value form the correlation index between the conflict node and the candidate upstream action propagation chain.

5. The fault indicator logic verification method based on topology inversion according to claim 4, characterized in that, The process of determining the upstream action propagation chain of the target based on various correlation indicators includes: For any candidate upstream action propagation chain of this conflict node: The first action time of the first node of the candidate upstream action propagation chain is taken as the starting time. The voltage and current phase angle difference within a first preset time period starting from the starting time is extracted from the voltage and current phase angle difference sequence of the first node of the candidate upstream action propagation chain, and the average value is calculated to obtain the first average phase angle value. Extract the voltage and current phase angle difference sequence of the tail node of the candidate upstream action propagation chain within the first preset time period starting from the start time, and calculate the average value to obtain the second average phase angle value. Extract the voltage and current phase angle difference within the first preset time period starting from the starting time from the voltage and current phase angle difference sequence of the conflict node, and calculate the average value to obtain the third average phase angle value; A reasonable phase interval is determined based on the first average phase angle value and the second average phase angle value; If the third average phase angle value is within the reasonable phase interval, then the candidate upstream action propagation chain is added to the candidate chain set; otherwise, it is not added to the candidate chain set. The candidate upstream action propagation chain with the highest correlation index in the candidate chain set is taken as the target upstream action propagation chain.

6. The fault indicator logic verification method based on topology inversion according to claim 1, characterized in that, The step of determining the theoretical current direction characteristic values ​​from each of the active nodes to the virtual fault point based on the reference topology diagram includes: For any active node, the electrical path impedance from the active node to the virtual fault point is determined according to the reference topology diagram. Based on the electrical path impedance and the equivalent power supply model of the active node, the theoretical short-circuit current generated at the virtual fault point under the action of the active node alone is determined as the theoretical current direction characteristic value of the active node.

7. The fault indicator logic verification method based on topology inversion according to claim 1, characterized in that, The step of determining the characteristic value of the measured current direction based on the voltage-current phase angle difference sequence of the activated fault indicator includes: The first activation time of the activated fault indicator is taken as the starting time. The voltage and current phase angle difference within a second preset time period starting from the starting time is extracted from the voltage and current phase angle difference sequence of the activated fault indicator, and the average value is calculated to obtain the fourth average phase angle value, which is used as the measured current direction feature value.

8. The fault indicator logic verification method based on topology inversion according to claim 1, characterized in that, The active node includes: a main power node and a distributed power node; the step of comparing the measured current direction characteristic value with each of the theoretical current direction characteristic values ​​to obtain the verification result of the activated fault indicator includes: The measured current direction feature value is matched with the theoretical current direction feature value corresponding to the main power node to generate a first matching result; If the first matching result is a match, then the verification result of the activated fault indicator is that the action logic is valid; If the first matching result is a mismatch, then the measured current direction feature value is matched with the theoretical current direction feature value corresponding to each of the distributed power nodes to obtain the second matching result; If the second matching result is that at least one distributed power node has a theoretical current direction feature value that matches the measured current direction feature value, then the verification result of the activated fault indicator is a direction logic configuration error. If the second matching result is that there is no theoretical current direction feature value corresponding to the distributed power node that matches the measured current direction feature value, then the verification result of the activated fault indicator is a hardware measurement unit fault.

9. A fault indicator logic verification device based on topological inversion, characterized in that, include: The parameter acquisition module is used to acquire the action status sequence and voltage-current phase angle difference sequence of each activated fault indicator within the fault time window. The topology building module is used to generate an instant inversion topology map based on the action state sequence of each activated fault indicator. The topology correction module is used to determine the conflicting nodes in the instantaneous inversion topology diagram, and correct the topological connection relationship of each conflicting node according to the voltage and current phase angle difference sequence of each conflicting node to obtain a reference topology diagram. An active node identification module is used to identify active nodes in the baseline topology graph; The verification module is used to take any activated fault indicator as a virtual fault point and determine the theoretical current direction characteristic value from each active node to the virtual fault point according to the reference topology. Based on the voltage-current phase angle difference sequence of the activated fault indicator, determine the characteristic value of the measured current direction; The measured current direction characteristic value is compared with each of the theoretical current direction characteristic values ​​to obtain the verification result of the activated fault indicator.

10. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the fault indicator logic verification method based on topology inversion as described in any one of claims 1 to 8.

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