A method for encapsulating implementation of a BU / UT authentication reference model fast reuse for IT / ST environment

Abstract

The application discloses a packaging implementation method for quick reuse of a BU / UT verification reference model for an IT / ST environment, and belongs to the field of integrated circuit design verification. In order to solve the problem that a large number of cross-layer signal path combing and repeated connection are needed for reuse of the existing BU / UT stage reference model in the IT / ST stage, resulting in low verification efficiency, the application provides a packaging implementation method, which comprises the following steps: constructing a packaging module in the BU / UT stage, wherein the physical interface of the packaging module is consistent with the design under test, the packaging module internally integrates the design under test and the reference model, and an internal verification comparison path is formed; adopting conditional compilation macros to isolate the verification logic so that the verification logic is enabled only in a simulation scenario; and directly instantiating the packaging module in the top-level environment in the IT / ST stage so that the reference model is instantiated together with the design under test, and only the physical interfaces of the packaging modules are connected. The application is used for efficient reuse of the BU / UT reference model in the IT / ST verification of an integrated circuit, effectively avoids complicated connection of the top-level signal path, reduces repeated development, does not affect RTL synthesis and back-end physical implementation, and improves verification efficiency and reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a packaging implementation method for rapid reuse of a BU / UT verification reference model in an IT / ST environment. Background Technology

[0002] In the field of integrated circuit design verification, comparing the output results between the Design Under Test (DUT) and the Reference Model (RM) is a fundamental verification method to ensure the correctness of chip functional logic. With the continuous increase in chip scale and integration, the traditional chip verification process is typically divided into two main stages: Block Unit / Unit Test (BU / UT) verification and Integration Test / System Test (IT / ST) verification. Figure 1 This is a schematic diagram of the connection structure between the DUT and RM in a current BU / UT verification environment. For example... Figure 1 As shown, during the BU / UT verification phase, verification engineers typically develop dedicated RM components for each independent module and compare their outputs to finely verify the behavior of the underlying modules. When verification moves to the higher-level IT / ST phase, in order to reduce redundant development and improve the portability of the verification environment, the industry highly expects to effectively port and reuse the mature RM components from the BU / UT phase in the IT / ST environment.

[0003] Currently, to reuse RM components from the BU / UT phase in high-level verification environments, the industry commonly uses the virtual interface mechanism provided by the SystemVerilog language. In practice, virtual interfaces are typically defined in the top-level module of the IT / ST environment, and their handles are bound to specific physical signal ports within the DUT via system functions or hierarchical path references. This establishes a signal interaction channel between the hardware logic and the software reference model, thereby enabling RM reuse and functional checks.

[0004] However, as modern chip designs become increasingly large and highly modular and reusable, existing virtual interface-based interconnection solutions have revealed many technical defects that cannot be ignored in practical applications. Figure 2 This is a schematic diagram of the signal connection between the cascaded DUT and RM in an existing IT / ST verification environment. (Example:) Figure 2As shown, in an IT / ST verification environment containing multiple cascaded DUTs (such as DUT1 and DUT2 cascaded), verification personnel not only need to connect the outputs of the previous DUT to the inputs of the next DUT at the hardware level, but also have to handle the complex signal connections between the input and output pins of the corresponding RMs (RM1 and RM2) in an extremely tedious manner in the top-level verification environment. If the chip contains a large number of modules, verification personnel need to sort out and connect a massive number of low-level signal paths in the top-level environment, and the manual wiring workload is huge and extremely tedious. If a specific module is repeatedly instantiated multiple times in the IT / ST environment according to the system architecture requirements, verification personnel need to perform repetitive and identical signal path lookup and binding operations for each instantiation instance, resulting in serious manpower redundancy. In addition, when the DUT is located in a deep nested level in the IT / ST environment, the difficulty of cross-level path debugging also increases accordingly.

[0005] In current IT / ST verification practices of many real-world projects, the high cost of building top-level signal connections often prevents the fully developed RM checking function in the BU / UT stage from being fully and efficiently reused in the IT / ST stage. This directly reduces the efficiency of the overall verification process and affects the quality assurance of the chip in the system-level verification stage.

[0006] Therefore, there is an urgent need for a method that can effectively simplify the hierarchical path sorting process, avoid repetitive development, and enable BU / UT verification components to be efficiently reused in IT / ST environments. Summary of the Invention

[0007] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows: This invention discloses a method for rapidly reusing a BU / UT verification reference model in an IT / ST environment, comprising the following steps: During the BU / UT verification phase, a packaging module is built. The physical interface of the packaging module is consistent with the physical interface of the design under test. The packaging module integrates the design under test and the reference model. The input signal is split to the design under test and the reference model within the packaging module, and the output signal of the design under test is fed to the reference model to form an internal verification comparison path. Conditional compilation macros are used to isolate and control the reference model and verification logic within the packaging module, so that the reference model and verification logic are only enabled in the simulation scenario. During the IT / ST verification phase, the packaging module is instantiated in the top-level environment, so that the reference model is instantiated along with the design under test; the top-level environment only connects to the physical interfaces of each packaging module.

[0008] In one embodiment, the physical interface of the packaging module includes: Clock input interface, reset input interface, input data interface, and output data interface; Inside the packaging module, each pin of the design under test is directly connected to the corresponding physical interface of the packaging module.

[0009] In one type of embodiment, the conditional compilation macro includes a simulation macro: Define the simulation macro in the simulation verification scenario to enable the reference model and verification logic; In the RTL synthesis scenario, the simulation macro is not defined to shield the reference model and verification logic, so that the gate-level netlist output by synthesis only contains the hardware circuit of the design under test, which can be directly used for back-end physical implementation.

[0010] In one embodiment, the method of forming an internal verification comparison path within the packaging module includes: A verification interface is instantiated inside the packaging module, and the signals of the clock input interface and reset input interface of the packaging module are connected to the verification interface. Using continuous assignment statements, the signals from the input data interface and output data interface of the packaging module are assigned to the data variables of the verification interface in real time.

[0011] In one type of embodiment, it further includes: In the simulation initialization statement block of the packaging module, an instance of the reference model class is constructed, and the verification interface is passed as a parameter to the instance of the reference model class to realize the signal binding between the verification interface and the reference model.

[0012] In one embodiment, during the IT / ST verification phase, instantiating the packaging module in the top-level environment includes: Depending on the system architecture requirements, the packaging module may be instantiated once or multiple times in the top-level environment to form multiple independent packaging module instances; Each of the aforementioned packaging module instances independently contains the corresponding design under test and reference model.

[0013] In one embodiment, when multiple packaging module instances are cascaded, the top-level environment only needs to complete the conventional connection of the hardware physical interfaces of each packaging module, including the cascading of the output data interface of the previous packaging module instance and the input data interface of the next packaging module instance, as well as the unified allocation of the global clock and reset signal, without the need for additional processing of signal connections related to the reference model.

[0014] In one embodiment, the packaging module is a parameterized configuration module, which has a built-in data bit width parameter to adapt to functional modules with different data bit widths.

[0015] In one embodiment, the packaging module can be reused as a packaging layer for the design under test in the chip design for testability and back-end physical implementation process.

[0016] In one type of embodiment, a simulation verification step is also included: During BU / UT or IT / ST verification, the reference model outputs the theoretically expected result based on the input data signal in the verification interface, and simultaneously captures the output data signal in the verification interface for comparison, so as to complete the functional correctness verification within the packaging module.

[0017] The technical solution of this invention has one or more of the following beneficial technical effects: (1) By integrating the design under test and the reference model into the same package module during the BU / UT stage, the RM component can be reused by directly instantiating the package module during the IT / ST stage. This eliminates the tedious process of sorting out cross-level signal paths and manually connecting RM pins in the top-level environment, and avoids repeated wiring operations when the same module is instantiated multiple times, which significantly improves the efficiency of building the IT / ST verification environment.

[0018] (2) By pre-completing the input signal splitting, output signal sampling and reference model binding in the packaging module, the problem of incorrect connection and missing connection that is easy to occur in manual top-level connection is avoided, the debugging difficulty of deep-level path is reduced, and the stability of the verification environment topology and the reliability of the verification results are improved.

[0019] (3) The verification logic is isolated by a two-way conditional compilation mechanism consisting of simulation macros and synthesis macros, and the packaging module can be reused with chip DFT and back-end physical packaging layer. While fully retaining the simulation verification capability, it avoids interference with RTL synthesis, testability design and back-end physical implementation process, and will not increase the development workload of hardware design. It has good engineering compatibility.

[0020] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the connection structure between the DUT and RM in a current BU / UT verification environment; Figure 2 This is a schematic diagram of the signal connection between the cascaded DUT and RM in an existing IT / ST verification environment; Figure 3 This is a schematic diagram of the internal structure of the packaging module for encapsulating the design under test and reference model of this invention; Figure 4 This is a schematic diagram of the multi-instance cascaded structure of the packaging module of the present invention in the IT / ST verification environment. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.

[0024] "Instantiation" refers to the process of generating an independent hardware runtime instance in a logic circuit based on the module definition; or, in the System Verilog / UVM verification environment, it refers to the process of deploying verification components to the simulation runtime environment.

[0025] This invention provides a method for rapidly reusing a BU / UT verification reference model in an IT / ST environment. Its core concept is to overturn the traditional hierarchical verification environment where the Design Under Test (DUT) and Reference Model (RM) are isolated and rely on top-level path connections for reuse. In the BU / UT verification stage, both are integrated and encapsulated into a self-contained hardware verification unit. When entering the Integration Level / System Level Verification (IT / ST) stage, this encapsulated unit is directly reused for plug-and-play functionality, effectively avoiding the cumbersome signal path routing and wiring work at the top level. Furthermore, verification logic is isolated through compiler macros to prevent interference with front-end logic (Register Transfer Level, RTL) synthesis and back-end physical implementation processes. The specific embodiments of this invention are further described in detail below with reference to the accompanying drawings.

[0026] Figure 3 This is a schematic diagram of the internal structure of the packaging module for encapsulating the design under test and reference model in this invention. (See diagram for example.) Figure 3As shown, this embodiment first constructs a parameterized wrapper module (dut_rm_wrapper) during the BU / UT verification stage. This module presents a standardized hardware physical interface consistent with the original Design Under Test (DUT) and internally integrates a DUT instance and a reference model (RM) component controlled by conditional compilation. As a preferred implementation, the wrapper module has a built-in parameterized configuration mechanism that allows setting the data bit width parameter WIDTH (e.g., the default bit width is 8). By simply adjusting this parameter, it can adapt to functional modules with different data throughput bit widths, thereby improving the versatility and reusability of the encapsulation structure. Those skilled in the art can adjust this parameter value according to the actual module's bit width requirements, and are not limited to the values ​​listed in this embodiment. The external physical interface of the wrapper module specifically includes a clock input interface (clk), a reset input interface (rst_n), and input and output data interfaces matching the bit width parameter. The definitions of each interface are consistent with the physical pins of the original DUT, ensuring that the connection logic of the top-level environment does not need to be modified during subsequent integration in each verification stage.

[0027] Internally, the packaging module's hardware connections are directly instantiated to establish a one-to-one correspondence between the packaging module's physical interfaces and the DUT's hardware pins. Specifically, the packaging module's clock and reset input interfaces are connected to the DUT's clock and reset pins, respectively. The packaging module's data input interface is connected to the DUT's data input pins, and the DUT's data output pins are connected to the packaging module's data output interface. This completes the physical connection of the main hardware path, ensuring at the hardware level that the packaging module's functional behavior is equivalent to that of the original independent DUT.

[0028] To address the compatibility issues between software verification components and hardware design processes (such as RTL synthesis, Design for Test (DFT), and backend physical implementation) in the verification process, this invention employs conditional compilation macro instructions to isolate and control the reference model and its associated verification infrastructure. This embodiment preferably uses simulation macros (e.g., SIMULATION macros) for conditional compilation, but can also utilize synthesis macros (e.g., SYNTHESIS macros) for bidirectional isolation protection.

[0029] In this embodiment, the SIMULATION macro is preferably used as the simulation compilation switch. The system defines this macro and compiles the relevant verification logic only in the simulation verification scenario. During RTL synthesis, since the simulation macro is not defined, the compiler will automatically skip the verification logic code segment contained in the macro when parsing the code of the package module. The corresponding verification code will be automatically removed during the compilation stage. The gate-level netlist output by synthesis only contains the hardware circuit of the design under test, which can be directly used for design for testability and back-end physical implementation process without having any logical impact on the hardware implementation result, further avoiding the risk of logic pollution caused by the omission of a single macro definition. When the simulation compilation macro is active, the package module first instantiates a dedicated verification interface for communication with the reference model and connects the clock and reset signals of the package module to the interface to provide a synchronization timing reference. Subsequently, continuous assignment statements are used to directly assign and attach the input data signals and output data signals of the package module to the data variables corresponding to the verification interface. Thus, the hardware stimulus is driven to the RM and the DUT output signal is fed to the RM for sampling at the bottom layer of the packaging module. All the signal connections required for verification are automatically completed at the physical bottom layer inside the module. All verification-related signal lines are closed inside the module and will not be led out.

[0030] After the verification interface logic is built, an instance of the reference model class is declared and constructed in the simulation initialization block of the packaging module. At simulation startup, the aforementioned verification interface, which has been synchronized with hardware signals, is passed as a parameter to the reference model instance by calling the constructor of this class, thus achieving deep binding between the software behavior model and the physical hardware signals. During simulation, the reference model internally calculates the theoretically expected results based on the received input stimuli and synchronously captures the actual output of the DUT, independently performing result comparison and correctness verification within the module.

[0031] Figure 4 This is a schematic diagram of the multi-instance cascaded structure of the packaging module of this invention in an IT / ST verification environment. For example... Figure 4As shown, when the verification process progresses from BU / UT to IT / ST, this invention greatly simplifies the setup of the top-level integration environment. Verification engineers no longer need to handle the cumbersome input / output connections between RM1 and RM2 at the top level as in existing technologies; instead, they can directly instantiate and reuse the pre-packaged modules. In the top-level environment, the packaging modules can be instantiated once or multiple times according to the actual needs of the system architecture to form multiple independent packaging module instances. This implementation takes a two-level cascading approach as an example, corresponding to the first packaging module instance (u_wrapper_inst1) and the second packaging module instance (u_wrapper_inst2). Each packaging module instance can be independently configured with data bit width parameters during instantiation to meet the differentiated needs of different channels or modules. Furthermore, each instance contains an independent design under test and reference model, and their operation is independent of each other.

[0032] In a multi-module cascaded IT / ST scenario, the top-level environment only needs to handle standard hardware physical interface connections. Figure 4 Taking the two-tiered cascaded logic as an example, only the output data interface of the first packaging module instance needs to be directly connected to the input data interface of the second packaging module instance via physical wiring, and a global clock and reset signal should be provided for both instances. Since each packaging module has pre-completed self-contained verification connections for input splitting and output sampling between the RM component and the corresponding DUT, after the top-level cascade is completed, the RM inside the first packaging module automatically samples the stimulus and output of its own level for comparison, and the RM inside the second packaging module also independently completes its own level functional verification. The top-level verification environment does not need to additionally perceive or process any RM-related signal paths, does not need to repeatedly write RM connection code for each module instance, and does not need to spend a lot of time sorting out deep-level paths, effectively eliminating the tedious process of manually connecting verification components at the top level, and greatly improving the construction efficiency and topology reliability of the IT / ST verification environment.

[0033] It is worth mentioning that, since no simulation compilation macro is defined in the RTL synthesis stage, the verification components such as RM and verification interfaces inside the packaging module will not be compiled and instantiated. The packaging module in the netlist of the synthesis output is equivalent to an original design-to-test module containing only hardware logic, which can directly enter the DFT design for testability and back-end physical implementation process without having any additional impact on the hardware design process.

[0034] Furthermore, in practical engineering, the chip's DFT and back-end processing themselves require adding wrapper layers or packaging layers to the modules. The packaging module of this invention can be reused as such a wrapper layer, thereby avoiding additional design and development workload due to the reuse of the packaging module of this invention. At the same time, when performing system-on-chip (SoC) integration at the chip top level, hardware signal connections between modules need to be completed. Using the solution of this invention, there is no need to add additional top-level wiring workload. This systematic design enables this invention to improve verification efficiency while maintaining a high degree of engineering friendliness and zero intrusion into the hardware process.

[0035] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.

[0036] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for rapidly reusing a BU / UT verification reference model in an IT / ST environment, characterized in that, Includes the following steps: During the BU / UT verification phase, a packaging module is built. The physical interface of the packaging module is consistent with the physical interface of the design under test. The packaging module integrates the design under test and the reference model. The input signal is split to the design under test and the reference model within the packaging module, and the output signal of the design under test is fed to the reference model to form an internal verification comparison path. Conditional compilation macros are used to isolate and control the reference model and verification logic within the packaging module, so that the reference model and verification logic are only enabled in the simulation scenario. During the IT / ST verification phase, the packaging module is instantiated in the top-level environment, so that the reference model is instantiated along with the design under test; the top-level environment only connects to the physical interfaces of each packaging module.

2. The method according to claim 1, characterized in that, The physical interface of the packaging module includes: Clock input interface, reset input interface, input data interface, and output data interface; Inside the packaging module, each pin of the design under test is directly connected to the corresponding physical interface of the packaging module.

3. The method according to claim 1, characterized in that, The conditional compilation macros include simulation macros: Define the simulation macro in the simulation verification scenario to enable the reference model and verification logic; In the RTL synthesis scenario, the simulation macro is not defined to shield the reference model and verification logic, so that the gate-level netlist output by synthesis only contains the hardware circuit of the design under test, which can be directly used for back-end physical implementation.

4. The method according to claim 2, characterized in that, The methods for forming an internal verification comparison pathway within the packaging module include: A verification interface is instantiated inside the packaging module, and the signals of the clock input interface and reset input interface of the packaging module are connected to the verification interface. Using continuous assignment statements, the signals from the input data interface and output data interface of the packaging module are assigned to the data variables of the verification interface in real time.

5. The method according to claim 4, characterized in that, Also includes: In the simulation initialization statement block of the packaging module, an instance of the reference model class is constructed, and the verification interface is passed as a parameter to the instance of the reference model class to realize the signal binding between the verification interface and the reference model.

6. The method according to claim 1, characterized in that, During the IT / ST verification phase, the packaging module is instantiated in the top-level environment, including: Depending on the system architecture requirements, the packaging module may be instantiated once or multiple times in the top-level environment to form multiple independent packaging module instances; Each of the aforementioned packaging module instances independently contains the corresponding design under test and reference model.

7. The method according to claim 6, characterized in that: When multiple packaging module instances are cascaded, the top-level environment only needs to complete the conventional connection of the hardware physical interfaces of each packaging module, including the cascading of the output data interface of the previous packaging module instance and the input data interface of the next packaging module instance, as well as the unified allocation of the global clock and reset signal, without the need for additional processing of signal connections related to the reference model.

8. The method according to claim 1, characterized in that: The packaging module is a parameterized configuration module, which has a built-in data bit width parameter to adapt to functional modules with different data bit widths.

9. The method according to claim 1, characterized in that: The packaging module can be reused as a packaging layer for the design under test in the chip design for testability and back-end physical implementation process.

10. The method according to any one of claims 1 to 9, characterized in that, It also includes simulation verification steps: During BU / UT or IT / ST verification, the reference model outputs the theoretically expected result based on the input data signal in the verification interface, and simultaneously captures the output data signal in the verification interface for comparison, so as to complete the functional correctness verification within the packaging module.

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