A design method and system suitable for large-scale chip ATE test vector management

Abstract

The application provides a design method and system suitable for management of large-scale chip ATE test vectors. The method comprises: customizing ATE test vectors according to test engineer requirements; generating test vector exclusive forms for the package according to package requirements; issuing the test vector exclusive forms to an automatic test equipment and performing tests; obtaining test determination results; when the test determination results are failed, analyzing reasons and adding unique version labels to generate new test vectors, issuing the new test vectors to the automatic test equipment to continue performing tests; when the test determination results are passed, performing optimization processing on current test vectors according to test engineer requirements, adding vector optimization labels to generate new test vector types, issuing the new test vector types to the automatic test equipment to continue performing tests; and repeating the step of obtaining test determination results until the test determination results are passed and the test process is ended.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip testing and verification technology, and more specifically, to a management design method and system applicable to large-scale chip ATE (Automatic Test Equipment) vectors. Background Technology

[0002] As integrated circuit process nodes continue to shrink and system-on-a-chip (SoC) functional modules become increasingly complex, automated test equipment (ATE) plays a crucial role in chip factory verification and production line screening. ATE test vectors, as the core data carrier driving test equipment to perform stimulus acquisition, logic comparison, and fault diagnosis, are experiencing exponential growth in scale and management complexity. Given that chip test vectors often number in the thousands and undergo multiple version iterations, existing technologies have revealed several inherent shortcomings in practical engineering applications.

[0003] First, the massive amount of ATE test vector files lacks a structured version control mechanism during storage, retrieval, and version iteration. Test engineers often rely on manual naming rules and scattered folders for management when dealing with different packaging forms and multiple rounds of design changes. Due to the lack of a unified version traceability chain, historical test vectors and current vectors are easily confused, leading to the repeated issuance of invalid test commands. This not only lengthens the chip development and verification cycle but also significantly increases storage overhead and project coordination costs.

[0004] Secondly, current vector iteration processes rely heavily on trial-and-error experience for manual adjustments, lacking a systematic mechanism to address differences in package pin arrangements and electrical characteristics. When a specific package type changes, test vectors often fail to accurately adapt to new pins or timing constraint changes. Because a form-level generation logic and fault coverage mapping relationship are not established, test equipment frequently triggers timing violations or electrical parameter exceedance alarms during execution. Test engineers must repeatedly manually check equipment logs and regenerate vectors, resulting in a significant reduction in production line testing throughput.

[0005] Furthermore, the vector optimization stage lacks quantifiable merging rules and timing constraint verification methods. Logical mutual exclusion or stimulus duty cycle conflicts often exist between test vectors, and blindly pruning or recombining vectors can easily lead to missed tests. Due to the lack of non-mutually exclusive verification algorithms and optimized tag tracing mechanisms, test time compression and fault coverage improvement often mutually constrain each other. The fault capture rate remains stagnant below the threshold for a long time, making it difficult to simultaneously achieve the dual engineering goals of test efficiency and screening quality.

[0006] Given the aforementioned shortcomings, designing an efficient and clear vector version control method that can simultaneously reduce test time and improve fault coverage while ensuring test accuracy has become a pressing technical challenge in the semiconductor testing field. Summary of the Invention

[0007] The objective of this invention is to provide a management and design method and system applicable to large-scale chip ATE test vectors. Through the method and / or system, the technical problems of large-scale chip ATE test vectors being large in scale, having frequent version iterations and lacking optimization logic in the prior art, resulting in a lack of structured traceability in the test process, lengthy test time, and difficulty in synchronously improving the fault capture rate are addressed.

[0008] In a first aspect of the invention, the aforementioned task is solved by a management design method suitable for large-scale chip ATE test vectors, the method comprising the following steps: Customize ATE test vectors according to the needs of test engineers; Based on the encapsulation requirements, a test vector-specific form is generated for this encapsulation. The test vector-specific form includes instructions for vector usage and execution order definition. The test vector-specific form is sent to the automated testing equipment and the test is executed. Obtain the test results; When the test result is "failed", the reason is analyzed and a unique version tag is attached to generate a new test vector. The new test vector is then sent to the automatic test device to continue the test. When the test result is passed, the current test vector is optimized according to the test engineer's requirements. An optimization tag is added to generate a new test vector type, which is then sent to the automated testing equipment to continue testing. Repeat the steps to obtain the test result until the test result is passed and the test process ends.

[0009] In one embodiment of the present invention, parsing the cause and attaching labels to generate a new test vector includes: Extract the mismatch point index and trigger clock cycle from the test log; Locate specific failure nodes by comparing with the vector specification; Adjust the excitation threshold or timing compensation parameters based on the positioning results; and The failure cause classification code and update basis are encapsulated into a unique version tag and embedded in the vector file name.

[0010] In one embodiment of the present invention, performing optimization processing on the current test vector according to the needs of the test engineer includes: Traverse the vector instruction set to identify logically mutually exclusive stimulus combinations; Mark redundant segments and perform non-mutual exclusion checks; Merge compatible vectors and adjust excitation duty cycles; and Generate merging ratio and coverage gain data and encapsulate them into vector optimization labels.

[0011] In one embodiment of the present invention, the data structure of the test vector-specific form includes vector name, applicable encapsulation type, fault model category, execution priority, clock frequency constraint, stimulus duty cycle threshold, and acquisition window alignment rule.

[0012] In one embodiment of the present invention, the field information of the unique version tag includes version number, date code, failure reason classification code, update basis description, modification timestamp, and responsible person identifier.

[0013] In one embodiment of the present invention, the test vector format received by the automatic test device is STIL format, and the system's built-in format conversion interface converts the STIL format into a proprietary binary format recognized by the automatic test device.

[0014] In a second aspect of the invention, the aforementioned task is further addressed by a management design system suitable for large-scale chip ATE test vectors, the system comprising: The test vector customization module is configured to customize ATE test vectors according to the needs of test engineers; The form generation module is configured to generate a test vector-specific form for this encapsulation based on the encapsulation requirements. The test vector-specific form includes vector usage instructions and execution order definitions. The test execution module is configured to send the test vector-specific form to the automated testing device, execute the test, and return the test judgment result. The failure analysis and tag generation module is configured to, when the test result is a failure, analyze the cause and attach a unique version tag to generate a new test vector, and send the new test vector to the automatic test equipment to continue the test; The vector optimization module is configured to, when the test result is passed, optimize the current test vector according to the test engineer's requirements, attach a vector optimization tag to generate a new test vector type, and send the new test vector type to the automated testing equipment to continue testing; and The version iteration control module is configured to repeatedly execute the step of returning the test judgment result until the test judgment result is passed and the test process ends.

[0015] In one embodiment of the present invention, the form generation module is deployed on the engineering terminal and uses table editing software to perform form rendering and syntax verification. The test execution module is deployed inside the automated test equipment and has a built-in format conversion interface to convert data from STIL format to proprietary binary format; The failure analysis and tag generation module is deployed on the vector management server and includes a log parsing unit, a rule matching engine, and a tag writing unit. The vector optimization module, deployed on the vector management server, includes a non-mutually exclusive verifier, a merging scheduler, and a timing constraint verifier; and The version iteration control module is deployed on the vector management server, which maintains the version state machine and records the tag change history.

[0016] In one embodiment of the present invention, the engineering terminal, the vector management server and the automatic testing equipment are connected via an Ethernet communication link, and data exchange is completed based on the standard file transfer protocol without relying on specific middleware or database.

[0017] In a third aspect, the present invention also provides a computer-readable storage medium having stored thereon computer-readable instructions that, when executed by a processor, perform the steps of the management design method applicable to large-scale chip ATE test vectors.

[0018] The technical solution provided by this invention has the following advantages: First, by establishing form generation logic based on testability design fault coverage and package impact, test vectors can accurately adapt to different package pin arrangements and electrical characteristics. The system can automatically define the vector execution order and timing constraints without relying on discrete human experience, thereby significantly reducing version obfuscation probability and redundant testing overhead.

[0019] Secondly, a dual traceability mechanism of unique version tags and optimization tags is introduced. Tags are directly embedded in the vector filename and metadata structure, clearly recording the cause of failure, the basis for updates, and optimization rules. Because there is a direct mapping relationship between tags and subsequent vector correction instructions, test engineers can quickly locate the failure node and perform targeted refactoring, avoiding blind trial and error.

[0020] Furthermore, the vector merging algorithm based on non-mutually exclusive verification effectively eliminates redundant instructions and adjusts the excitation duty cycle. Under the same chip model and test scale, the total number of vectors decreased from 1218 to 569 after adopting this method; the single test time was shortened from 652ms to 393ms, a reduction of 39.8%; and the fault detection rate increased from 98.97% to 99.85%. All improvements in these metrics are supported by clear data and are reproducible in engineering.

[0021] In summary, this invention achieves efficient iteration and accurate chip screening of large-scale chip test vectors through the synergistic combination of structured form management, tag-based version control, and algorithm-driven vector optimization, and has significant industrial application value. Attached Figure Description

[0022] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0023] Figure 1 A flowchart illustrating a management design method for large-scale chip ATE test vectors according to an embodiment of the present invention is shown; and Figure 2 A schematic diagram of a management design system for large-scale chip ATE test vectors according to an embodiment of the present invention is shown. Detailed Implementation

[0024] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of the embodiments of the invention. However, the invention is not limited to these specific details.

[0025] It should be noted that the attached diagram is only a schematic topology, and the physical layout and logic hierarchy in the actual chip design may vary reasonably due to process node and architecture requirements.

[0026] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0027] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0028] Figure 1 This diagram illustrates a flowchart of a management and design method for large-scale chip ATE test vectors according to an embodiment of the present invention. The management and design method for large-scale chip ATE vectors provided by the present invention relies on a collaborative environment comprised of an engineering terminal, a vector management server, and test equipment. Figure 1 As shown, the design method includes the following main steps: Step 101: Customize the ATE test vectors according to the test engineer's requirements.

[0029] Step 102: Based on the encapsulation requirements, generate a test vector-specific form for this encapsulation. The test vector-specific form includes vector usage instructions and execution order definitions.

[0030] Due to the objective need for a large number of test vectors and frequent version iterations, the design methodology generates a dedicated test vector form based on the design for testability (DPT) to cover fault types and the degree of package impact. Since the DPT pre-defines the scan chain structure and fault injection points during the chip back-end placement and routing stage, the system extracts the coverage of static sticky faults, transition delay faults, and path delay faults by reading the DPT netlist and package pin definition files. Given the different sensitivities of different package types to specific fault types, the system filters invalid excitation nodes and constructs the form execution sequence based on package electrical characteristic parameters and pin arrangement matrices. The form internally uses a standardized data structure to define the vector usage instructions and execution order for each vector type. In one embodiment of this invention, the data structure of the dedicated test vector form includes vector name, applicable package type, fault model category, execution priority, clock frequency constraint, excitation duty cycle threshold, and acquisition window alignment rules, so that the test equipment can directly load and parse it.

[0031] Step 103: Send the test vector-specific form to the automated testing device and execute the test.

[0032] Once the form is generated, the process transitions to the test execution phase. The system sends the form and initial vectors to the test equipment via standard network communication protocols. The test equipment generates analog or digital stimulus signals based on the vector instruction set, driving the chip under test (DUT) to run and collect response data. Since the test vectors often number in the thousands, the test execution module employs a pipeline scheduling strategy, issuing instructions segment by segment according to preset timing constraints and comparing the results with the expected values ​​in real time. If a mismatch is found, the test equipment immediately generates a test log and returns the record of the mismatch point.

[0033] In one embodiment of the present invention, the test vector received by the automatic test device is in STIL format, and the system's built-in format conversion interface converts the STIL format into a proprietary binary format that the automatic test device can recognize.

[0034] Step 104: Obtain the test judgment result.

[0035] Step 105: When the test result is "failed", analyze the reason and attach a unique version tag to generate a new test vector, and send the new test vector to the automatic test device to continue the test.

[0036] Given that test failures may encompass various failure modes, including exceeding electrical parameter limits, timing violations, or functional logic errors, the system enters the failure analysis and tag generation phase. The test log is first read by the log parsing unit, extracting the mismatch point index, trigger clock cycle, and corresponding excitation vector number. Since the log only records surface-level mismatches, the system needs to perform in-depth analysis in conjunction with the Design for Testability (DTest) specifications and vector generation rules. If the mismatch is determined to be due to electrical characteristics of a specific package pin, the system automatically adjusts the excitation voltage threshold; if it is determined to be a timing violation captured by the scan chain, the system recalculates the clock offset compensation value. After analysis, the system adds a unique version tag to generate a new vector. Since the tag is directly added to the vector file name, the tag fields include the version number, date code, failure cause classification code, update basis description, modification timestamp, and responsible person identifier. This version tag has a clear mapping relationship with subsequent vector correction instructions; test engineers can directly retrieve correction rules and verify the new vector through the tag index.

[0037] Step 106: When the test result is passed, optimize the current test vector according to the test engineer's requirements, attach a vector optimization tag to generate a new test vector type, and send the new test vector type to the automatic test equipment to continue the test.

[0038] If the test passes, the process moves to the vector optimization phase. Considering both technical feasibility and test time reduction, the system optimizes the vectors based on test requirements and adds optimization tags. The optimization objective function primarily aims to reduce test time and improve fault coverage. Since the original vectors often contain overlapping stimuli or redundant acquisitions, the system uses a non-mutually exclusive verification algorithm to prune and reconstruct the original vectors. The algorithm first traverses the vector instruction set, identifies logically mutually exclusive stimulus combinations, and marks redundant segments; then it merges compatible vectors and adjusts the stimulus duty cycle to meet the coverage requirements of more fault types. The generated new vector type maintains the same instruction set architecture and data format as the original version, with substantial differences only in execution sequence length and internal merging logic. After optimization, the system adds optimization tags, with tag fields recording the merging ratio, estimated coverage improvement, estimated time reduction, and optimization rule index.

[0039] Step 107: Repeat the steps to obtain the test judgment result until the test judgment result is passed and the test process ends.

[0040] Since the optimized vectors still need to be verified in actual testing, the process returns to the test execution module for a new round of evaluation. If it fails, the system re-enters the failure analysis and tag generation stage; if it passes, the ATE vector testing process for the current chip model ends. Through the above closed-loop iterative mechanism, the system can continuously compress the vector size and improve the fault detection rate while ensuring test accuracy.

[0041] This invention also provides a management and design system suitable for large-scale chip ATE test vectors, such as... Figure 2 As shown, the system includes: The test vector customization module 201 is configured to customize ATE test vectors according to the needs of test engineers; The form generation module 202 is configured to generate a test vector-specific form for this encapsulation according to the encapsulation requirements. The test vector-specific form includes vector usage instructions and execution order definitions. Test execution module 203 is configured to send the test vector-specific form to the automated test device and execute the test, and return the test judgment result; The failure analysis and tag generation module 204 is configured to, when the test result is failure, analyze the cause and attach a unique version tag to generate a new test vector, and send the new test vector to the automatic test equipment to continue the test; Vector optimization module 205 is configured to, when the test result is passed, optimize the current test vector according to the test engineer's requirements, attach a vector optimization tag to generate a new test vector type, and send the new test vector type to the automated test equipment to continue testing; and The version iteration control module 206 is configured to repeatedly execute the step of obtaining the test judgment result until the test judgment result is passed and the test process ends.

[0042] The management and design system for large-scale chip ATE vectors provided in this embodiment consists of an engineering terminal, a vector management server, and a test bench. Each hardware component establishes a data exchange channel via Ethernet and serial communication links, and relies on an operating system and test management software for function scheduling, without depending on specific middleware or databases.

[0043] The test vector customization module and form generation module are deployed on the engineering terminal, using either a Windows operating system with Excel or a Linux operating system with LibreOffice for form editing. Due to the large volume of form data, the modules incorporate a table rendering engine and syntax validator to ensure that the vector usage instructions and execution order conform to the machine's loading specifications.

[0044] The test execution module is deployed inside the test equipment and is responsible for receiving vector files and driving the probe cards and load boards to perform physical tests. Because the test equipment has specific requirements for the input format, the module has a built-in STIL format conversion interface that converts standard STIL format vectors into a proprietary binary format recognized by the test equipment in real time. The conversion process is completed using the ATE's built-in toolchain and does not rely on any specific middleware or database, thereby reducing system coupling complexity and operational costs.

[0045] The failure analysis and tag generation module is deployed on the vector management server and is responsible for parsing test logs and generating version tags. The module includes a log parsing unit, a rule matching engine, and a tag writing unit. The log parsing unit reads the log files returned by the test equipment and extracts mismatch points and triggering conditions; the rule matching engine compares the vector specifications against a preset rule base to locate specific failure nodes; the tag writing unit encapsulates the analysis results into unique version tags, directly embedding them into the vector filename and metadata header. Because the tag structure is compact and the fields are fixed, test engineers can directly read the update reason through text parsing without opening a dedicated database.

[0046] The vector optimization module, also deployed on the vector management server, is responsible for performing vector merging and specification adjustments. The module includes a non-mutual exclusion checker, a merge scheduler, and a timing constraint checker. The non-mutual exclusion checker traverses the vector instruction set, identifying segments that can be safely merged; the merge scheduler reassembles the instruction sequence according to the optimization objective function; and the timing constraint checker examines the clock alignment and duty cycle parameters of the merged vector to ensure no new timing violations are introduced. After optimization, the module generates optimization tags and updates the vector files.

[0047] The version iteration control module acts as the system's central hub, coordinating the workflows of various modules and maintaining the version state machine. Since the testing process involves multiple loop checks, the control module records the pass / fail status of each test, the history of tag changes, and the number of optimization iterations. When the test finally passes, the control module locks the final vector version and archives it to the engineering terminal for batch testing on the production line.

[0048] Optionally, the management and design system for large-scale chip ATE test vectors provided by this invention can be equipped with an automated script scheduling unit to automatically trigger the vector merging process based on a preset time threshold, avoiding delays caused by manual waiting. Furthermore, the test equipment can be configured with a multi-channel parallel acquisition architecture to simultaneously execute vector tests for multiple package types, further improving production line throughput. Alternatively, the vector format conversion interface can support common data formats such as XML and JSON, and can be adapted to different vendors' equipment through custom parsing plugins. If the test log parsing results show multiple concurrent causes, the failure analysis module can generate composite tags, recording the classification code and correction priority of each failure cause, so that subsequent vector reconstruction can be executed in weighted order.

[0049] To further illustrate the technical advantages of this invention, a set of data records from typical embodiments are provided. Under the same chip model and test scale, before optimization, the initial total number of vectors was 1218, the single test time was 652ms, and the fault coverage rate was 98.97%. After optimization (e.g., three failure analysis iterations and two optimization iterations), the total number of vectors decreased to 569, the test time was shortened to 393ms, a reduction of 39.8%, and the fault capture rate increased to 99.85%. The improvements in all indicators are supported by clear data and are reproducible in engineering, verifying the reliability of the method provided by this invention in engineering applications.

[0050] This invention also provides a computer-readable storage medium storing computer-readable instructions. When executed by a processor, the computer-readable instructions perform the following steps: Customizing ATE test vectors according to the needs of the test engineer; generating a test vector-specific form for this package according to the packaging requirements, the test vector-specific form including vector usage instructions and execution order definitions; sending the test vector-specific form to an automated testing device and executing the test; obtaining the test judgment result; when the test judgment result is a failure, analyzing the reason and attaching a unique version tag to generate a new test vector, sending the new test vector to the automated testing device to continue executing the test; when the test judgment result is a pass, optimizing the current test vector according to the needs of the test engineer, attaching a vector optimization tag to generate a new test vector type, sending the new test vector type to the automated testing device to continue executing the test; repeating the step of obtaining the test judgment result until the test judgment result is a pass and the test process ends.

[0051] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined according to the technical solutions of the invention and their equivalents.

Claims

1. A management design method for large-scale chip ATE test vectors, characterized in that, Includes the following steps: Customize ATE test vectors according to the needs of test engineers; Based on the encapsulation requirements, a test vector-specific form is generated for this encapsulation. The test vector-specific form includes instructions for vector usage and execution order definition. The test vector-specific form is sent to the automated testing equipment and the test is executed. Obtain the test results; When the test result is "failed", the reason is analyzed and a unique version tag is attached to generate a new test vector. The new test vector is then sent to the automatic test device to continue the test. When the test result is passed, the current test vector is optimized according to the test engineer's requirements. A new test vector type is generated by attaching a vector optimization tag and the new test vector type is sent to the automatic test equipment to continue the test. as well as Repeat the steps to obtain the test result until the test result is passed and the test process ends. The process of analyzing the causes and adding labels to generate new test vectors includes: Extract the mismatch point index and trigger clock cycle from the test log; Locate specific failure nodes by comparing with the vector specification; Adjust the excitation threshold or timing compensation parameters based on the positioning results; and The failure cause classification code and update basis are encapsulated into a unique version tag and embedded in the vector file name; The optimization process performed on the current test vectors according to the needs of the test engineers includes: Traverse the vector instruction set to identify logically mutually exclusive stimulus combinations; Mark redundant segments and perform non-mutual exclusion checks; Merge compatible vectors and adjust excitation duty cycles; and Generate merging ratio and coverage gain data and encapsulate them into vector optimization labels.

2. The management and design method for large-scale chip ATE test vectors according to claim 1, characterized in that, The data structure of the test vector-specific form includes vector name, applicable encapsulation type, fault model category, execution priority, clock frequency constraint, stimulus duty cycle threshold, and acquisition window alignment rules.

3. The management and design method for large-scale chip ATE test vectors according to claim 1, characterized in that, The unique version tag includes the following fields: version number, date code, failure reason classification code, update basis description, modification timestamp, and responsible person identifier.

4. The management and design method for large-scale chip ATE test vectors according to claim 1, characterized in that, The test vector received by the automated testing equipment is in STIL format, and the system's built-in format conversion interface converts the STIL format into a proprietary binary format that the automated testing equipment can recognize.

5. A management and design system for large-scale chip ATE test vectors, applied to the management and design method for large-scale chip ATE test vectors as described in claim 1, characterized in that, include: The test vector customization module is configured to customize ATE test vectors according to the needs of test engineers; The form generation module is configured to generate a test vector-specific form for this encapsulation based on the encapsulation requirements. The test vector-specific form includes vector usage instructions and execution order definitions. The test execution module is configured to send the test vector-specific form to the automated testing device, execute the test, and return the test judgment result. The failure analysis and tag generation module is configured to, when the test result is failure, analyze the cause and attach a unique version tag to generate a new test vector, and send the new test vector to the automatic test equipment to continue the test; The vector optimization module is configured to perform optimization processing on the current test vector according to the test engineer's requirements when the test judgment result is pass, attach vector optimization tags to generate a new test vector type, and send the new test vector type to the automatic test equipment to continue the test. as well as The version iteration control module is configured to repeatedly execute the step of returning the test judgment result until the test judgment result is passed and the test process ends.

6. The management and design system for large-scale chip ATE test vectors according to claim 5, characterized in that, The form generation module is deployed on the project terminal and uses table editing software for form rendering and syntax validation. The test execution module is deployed inside the automated test equipment and has a built-in format conversion interface to convert data from STIL format to proprietary binary format; The failure analysis and tag generation module is deployed on the vector management server and includes a log parsing unit, a rule matching engine, and a tag writing unit. The vector optimization module, deployed on the vector management server, includes a non-mutually exclusive verifier, a merging scheduler, and a timing constraint verifier. as well as The version iteration control module is deployed on the vector management server, which maintains the version state machine and records the tag change history.

7. The management and design system for large-scale chip ATE test vectors according to claim 5, characterized in that, The engineering terminal, vector management server, and automatic testing equipment are connected via an Ethernet communication link. Data exchange is completed using the standard file transfer protocol and does not rely on any specific middleware or database.

8. A computer-readable storage medium, characterized in that, It stores computer-readable instructions, which, when executed by a processor, perform the steps of the management design method for large-scale chip ATE test vectors according to any one of claims 1-4.

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