Method and device for modifying formula embedded in model, electronic equipment and storage medium

Abstract

The application provides a semiconductor device model formula modification method and device, electronic equipment and storage medium. The method comprises the following steps: determining a target calculation formula to be modified in a semiconductor device model, the target calculation formula comprising a target model parameter and an initial function; constructing a sub-circuit, and defining a correction factor in the sub-circuit based on a replacement function and the initial function; and in the model definition, updating the target model parameter by using the correction factor, so that the semiconductor device model is simulated based on the updated target model parameter. The application avoids modification of the underlying code, is compatible with the simulator optimization, ensures the simulation speed, eliminates the mutual restriction between the device effect parameters, and improves the fitting precision of the model on the test data.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method, apparatus, electronic device, and storage medium for modifying embedded formulas in a semiconductor device model. Background Technology

[0002] In the process of semiconductor integrated circuit design and simulation, it is usually necessary to rely on semiconductor device models (such as the commonly used BSIM4 model) to accurately predict and simulate the physical characteristics and electrical behavior of the devices.

[0003] However, in existing semiconductor device models, the mathematical formulas are typically deeply integrated into the underlying code. This architecture makes modifying the model formulas exceptionally difficult. If developers attempt to modify the underlying formulas, they not only need to provide additional code files, but the modified code often fails to be compatible with the underlying simulation optimizations made by various circuit simulators (such as Spectre simulators) for the standard model. This not only significantly slows down the simulation speed but, in severe cases, can even lead to simulation non-convergence.

[0004] Furthermore, existing model formulas have limitations in parameter reuse. For example, the effective width (weff) parameter of a device is repeatedly used in multiple locations within the model (e.g., the same effective width calculation logic is used when calculating saturation current and junction leakage current). However, in actual silicon wafer test data, the changing trends of different physical effects may not be consistent, making it impossible to accurately characterize them using the same effective width parameter. Even if existing models provide binning parameter functionality (and some parameters do not even support binning), they often cannot achieve high-precision fitting of test data. Due to the mutual constraints between device effect parameters, adjusting one parameter to fit a specific characteristic often leads to the deterioration of other characteristics.

[0005] Therefore, the industry urgently needs a simple and efficient method that can flexibly modify the embedded formulas of the model without modifying the underlying code of the model or breaking the simulator optimization, thereby removing the mutual constraints between device effect parameters and improving the model's fitting accuracy to actual test data. Summary of the Invention

[0006] This application aims to solve the technical problems of existing semiconductor device models where mathematical formulas are integrated into the underlying code, making modification difficult and incompatible with simulator optimization, resulting in slow simulation or non-convergence; and the limitations of the model formulas and the mutual constraints between device effect parameters, making it impossible to achieve high-precision fitting of test data.

[0007] This application provides a method for modifying embedded formulas in semiconductor device models, including:

[0008] Step 1: Determine the target calculation formula to be modified in the semiconductor device model. The target calculation formula includes the target model parameters and the initial function.

[0009] Step 2: Construct a sub-circuit, in which a correction factor is defined based on the substitution function and the initial function;

[0010] Step 3: In the model definition, the target model parameters are updated using the correction factor so that the semiconductor device model can be simulated based on the updated target model parameters.

[0011] Preferably, in step one, the target calculation formula is used to calculate the current, voltage, charge, or capacitance of the semiconductor device.

[0012] Preferably, in step one, the independent variables of the initial function include device size parameters and initial model parameters.

[0013] Preferably, in step two, the independent variables of the substitution function include the device size parameters and the substitution model parameters.

[0014] Preferably, in step three, updating the target model parameters using the correction factor includes: multiplying the target model parameters by the correction factor to obtain the updated target model parameters.

[0015] Preferably, in step one, the semiconductor device model is the BSIM4 model, the target calculation formula is the gate edge sidewall trap-assisted saturation current calculation formula, and the initial function is the initial effective width function.

[0016] Preferably, in step two, the replacement function is a replacement effective width function, and the replacement model parameters in the replacement effective width function include size deviation parameters, length-related parameters, width-related parameters, and length-width-related parameters.

[0017] This application also provides a device for modifying embedded formulas in a semiconductor device model, including:

[0018] The determination module is configured to determine the target calculation formula to be modified in the semiconductor device model, wherein the target calculation formula includes target model parameters and initial functions;

[0019] A construction module is configured to construct sub-circuits, in which a correction factor is defined based on a substitution function and the initial function;

[0020] The update module is configured to update the target model parameters in the model definition using the correction factor, so that the semiconductor device model can be simulated based on the updated target model parameters.

[0021] This application also provides an electronic device, including:

[0022] Processor; and memory configured to store computer programs;

[0023] The processor, when executing the computer program, implements the above-mentioned method for modifying the embedded formula of the semiconductor device model.

[0024] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for modifying the embedded formula of the semiconductor device model.

[0025] As described above, the method, apparatus, electronic device, and storage medium for modifying the embedded formula of the semiconductor device model of the present invention have the following beneficial effects:

[0026] This disclosure presents a simple and efficient method for modifying embedded model formulas by defining correction factors in sub-circuits and updating target model parameters in the model definition. This method avoids direct modification of the model's underlying code, requires no additional code files, and is perfectly compatible with the underlying simulation optimizations performed by various simulators for standard models, ensuring simulation speed and avoiding convergence issues. Simultaneously, this method removes the mutual constraints between device effect parameters, allowing researchers to adjust specific physical effects individually, significantly improving the model's fitting accuracy to actual silicon wafer test data and providing highly reliable model support for integrated circuit design at advanced semiconductor process nodes. Attached Figure Description

[0027] Figure 1 The diagram shows a flowchart illustrating the method for modifying the embedded formula of the semiconductor device model according to the present invention.

[0028] Figure 2 The diagram shows a schematic of the structure of the device for modifying the embedded formula of the semiconductor device model according to the present invention.

[0029] Figure 3 The diagram shown is a structural schematic of the electronic device of the present invention.

[0030] Figure 4 The diagram shows a comparison of the current-voltage characteristic curves of the semiconductor device of the present invention at the first device width.

[0031] Figure 5 The diagram shows a comparison of the current-voltage characteristic curves of the semiconductor device of the present invention at the second device width.

[0032] Figure 6 The diagram shows a comparison of the current-voltage characteristic curves of the semiconductor device of the present invention at the third device width.

[0033] Figure 7 The diagram shows a comparison of the current-voltage characteristic curves of the semiconductor device of the present invention at the fourth device width.

[0034] Figure 8 The diagram shows a comparison curve of the turn-off current per unit width of the semiconductor device of the present invention as a function of the device width. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] This application provides a method for modifying embedded formulas in a semiconductor device model. This method can be executed by an electronic device, including a personal computer, server, workstation, or cloud computing node, or other computing device with data processing capabilities. The electronic device is equipped with circuit simulation tools, such as the Spectre simulator, HSPICE simulator, Eldo simulator, or other simulation software compatible with SPICE syntax. By executing instructions stored in memory through the processor of the electronic device, flexible adjustments to the semiconductor device model can be achieved. In some embodiments, the semiconductor device model can be applied to the simulation of various semiconductor devices, including planar metal-oxide-semiconductor field-effect transistors, three-dimensional gate transistors, tunneling field-effect transistors, or bipolar junction transistors.

[0037] Figure 1 This is a flowchart illustrating a method for modifying embedded formulas in a semiconductor device model according to some embodiments of this application.

[0038] like Figure 1 As shown, the methods for modifying the embedded formulas in the semiconductor device model include:

[0039] Step 1: Determine the target calculation formula to be modified in the semiconductor device model. The target calculation formula includes the target model parameters and the initial function.

[0040] In the process of performing step one, the method for determining the target calculation formula may include obtaining actual silicon wafer test data of the semiconductor device and comparing it with the initial simulation data of the semiconductor device model under default parameters. When it is found that the deviation of characteristics such as current or capacitance under specific bias conditions exceeds the preset tolerance, the underlying mathematical expression causing the deviation, i.e., the target calculation formula, is located by analyzing the model architecture.

[0041] In some embodiments, in step one, the target calculation formula is used to calculate the current, voltage, charge, or capacitance of the semiconductor device. Semiconductor device models typically contain numerous mathematical formulas describing the physical behavior of the device, which are hard-coded into the simulator's low-level code. In addition to current, voltage, charge, or capacitance, in alternative embodiments, the target calculation formula can also be used to calculate parameters such as transconductance, output conductance, parasitic resistance, thermal noise, or flicker noise. By clearly defining the target calculation formula to be modified, the device characteristics that need optimization can be precisely located, avoiding unnecessary interference with other well-performing characteristics in the model, thereby improving the efficiency and accuracy of model calibration.

[0042] In some embodiments, in step one, the independent variables of the initial function include device size parameters and initial model parameters. Device size parameters typically include geometric features such as the device's channel width, channel length, number of finger electrodes, number of fins, or nanowire diameter. Initial model parameters are empirical values ​​or physical quantities preset in the model to fit physical effects. The initial function reflects the combined influence of device size and initial model parameters on the target calculation formula under the default model architecture.

[0043] In some embodiments, in step one, the semiconductor device model is the BSIM4 model, the target calculation formula is the gate edge sidewall trap-assisted saturation current calculation formula, and the initial function is the initial effective width function. In alternative embodiments, the semiconductor device model can also be other standard compact models such as BSIM3, BSIM-CMG, BSIM-IMG, or UTSOI.

[0044] During the actual silicon wafer test data fitting process, researchers discovered a deviation between the test data trend of the gate edge sidewall trap-assisted saturation current and the model's default calculation results. Specifically, in the BSIM4 model, the gate edge sidewall trap-assisted saturation current Ijun_gate can be simply described as Ijun_gate = weffcj * nf * jtsswgs * f(y). The initial effective width function weffcj is calculated as weffcj = w / nf + xw - 2 * (dwj + wlc / l) wln +wwc / w wwn +wwlc / (l wln *w wwnIn this formula, w is the device width, nf is the number of finger electrodes, and l is the device length; jtsswgs, xw, dwj, wlc, wrn, wwc, wwn, and wwlc are all model parameters; f(y) represents other parameters. Since model parameters such as xw, dwj, wlc, wrn, wwc, wwn, and wwlc not only participate in the calculation of the gate edge sidewall trap-assisted saturation current but also in the calculation of other key characteristics such as saturation current, directly modifying these parameters will lead to changes in other characteristics. To independently adjust the gate edge sidewall trap-assisted saturation current and remove the mutual constraints between device effect parameters, this formula and function were chosen as the modification target, which can specifically address the problem of insufficient leakage current fitting accuracy.

[0045] Step 2: Construct a sub-circuit, and define a correction factor in the sub-circuit based on the substitution function and the initial function.

[0046] During the construction of subcircuits, subcircuit code can be manually written using a netlist editor, or subcircuit netlists can be generated using automated scripts configured in electronic devices. The port configuration of subcircuits can be flexibly adjusted according to the number of terminals of semiconductor devices, for example, configured as a four-terminal structure including drain, gate, source, and substrate, or configured as a three-terminal or five-terminal structure for specific devices.

[0047] In some embodiments, in step two, the independent variables of the substitution function include device size parameters and substitution model parameters. A subcircuit is a modular structure defined at the circuit netlist level, allowing users to customize node and internal component connections. By constructing subcircuits, new computational logic can be introduced using the simulator-supported syntax without modifying the underlying code. The substitution function represents a mathematical relationship derived by researchers from actual silicon wafer test data that better reflects the actual physical behavior of the device. Methods for forming substitution functions can include polynomial fitting of test data, nonlinear regression analysis, or equation reconstruction based on semiconductor physics mechanisms. The substitution model parameters are a new set of parameters independent of the initial model parameters, specifically used to adjust the behavior of the substitution function. Defining the correction factor as the ratio of the substitution function to the initial function cleverly calculates the proportion of difference between the default model calculation result and the expected calculation result. This ratio definition method smoothly integrates custom physical effects into the existing model, ensuring the continuity and mathematical rationality of the correction process.

[0048] In some embodiments, in step two, the replacement function is a replacement effective width function. The replacement model parameters in the replacement effective width function include size deviation parameters, length-related parameters, width-related parameters, and length-width-related parameters. Specifically, the size deviation parameters may include a first size deviation parameter and a second size deviation parameter, used to characterize the fixed deviation between the actual size and the design size caused by the manufacturing process; the length-related parameters may include a first length-related parameter and a second length-related parameter, used to describe the influence of short-channel effects on the effective width; the width-related parameters may include a first width-related parameter and a second width-related parameter, used to describe narrow-channel effects; and the length-width-related parameters may include a first length-width-related parameter, used to describe the complex physical effects generated by the coupling of length and width. By introducing these rich replacement model parameters, a replacement effective width function that is more flexible and better fits the actual process characteristics than the initial effective width function can be constructed. In alternative embodiments, the replacement model parameters may also include temperature-related parameters or stress-related parameters to compensate for the influence of thermal effects or mechanical stress on device characteristics.

[0049] Step 3: In the model definition, update the target model parameters using correction factors so that the semiconductor device model can be simulated based on the updated target model parameters.

[0050] During the simulation, the simulator reads the netlist file containing the updated target model parameters and performs simulation tasks such as DC analysis, AC analysis, transient analysis, or RF analysis, outputting the corrected electrical characteristic curves.

[0051] In some embodiments, step three, updating the target model parameters using a correction factor, includes multiplying the target model parameters by the correction factor to obtain the updated target model parameters. A model definition is a block of statements in a simulation netlist used to declare device types and their corresponding parameter sets. Updating parameters within the model definition means that the update will apply to all device instances referencing that model. Multiplying the target model parameters by the correction factor effectively offsets the inaccuracies of the initial function during the model's calculation of the target formula, replacing the influence of the replacement function. This multiplicative update method is simple to implement and fully compatible with existing simulator parsers. In alternative embodiments, if the algebraic structure of the target calculation formula is additive, it can also be updated by adding the target model parameters to the correction factor. In this way, when the semiconductor device model is simulated, the underlying code still executes the original calculation process, but because the input parameters have been dynamically adjusted by the correction factor, the final output calculation result will highly match the actual test data. This not only avoids the cumbersome operations caused by providing additional code files, but also fully preserves the underlying matrix solving optimizations and multi-threaded calculation optimizations made by various simulators for the standard model, ensuring that the simulation speed is not affected, while avoiding convergence problems that may be caused by modifying the underlying equations.

[0052] To more clearly illustrate the complete execution process of steps one through three above, a general example of mathematical formula replacement is provided here. If a calculation formula in the model code is A=m*f(x,m1,m2..mn), where A is current, voltage, charge, or capacitance, m is the target model parameter to be corrected, x is device size parameters such as channel width w and channel length l, f(x,m1,m2..mn) is the initial function of x, and m1,m2..mn are the initial model parameters. Assume g(x,N1,N2..Nn) is the function of the replaced x, and N1,N2..Nn are the replaced model parameters. Taking a metal-oxide-semiconductor field-effect transistor as an example, the following sub-circuit can be constructed to correct the calculation formula of A: First, define the sub-circuit .subckt nchd gsb, and pass in the initial model parameters M1=m1, M2=m2..Mn=mn, and define the correction factor N=g(x,N1,N2..Nn) / f(x,M1,M2..Mn); then instantiate the device mxckt dgsb nch_model; finally, in the model definition .model nch_model, retain the original parameters m1=m1, m2=m2..mn=mn, and update the target model parameters to m=m*N.

[0053] Furthermore, drawing on the example of gate edge sidewall trap-assisted saturation current in the aforementioned BSIM4 model, in the specific netlist implementation, a sub-circuit nch can be defined, and parameters such as width w=10u and length l=10u can be passed in. Inside the sub-circuit, replacement model parameters are defined, for example, the first size deviation parameter dxwcj is set to 1.6e-8, the second size deviation parameter dwjcj is set to -1e-8, the first length-related parameter wlccj is set to 0, the first width-related parameter wwccj is set to -2.45e-15, the first length-width-related parameter wwlccj is set to 0, the second length-related parameter wlncj is set to 1, and the second width-related parameter wwncj is set to 1.

[0054] Based on these parameters, the effective width replacement function `dweffcj` is constructed, with the expression `w / nf + dxwcj - 2 * (dwjcj + wlccj / pwr(l, wlncj) + wwccj / pwr(w, wwncj) + wwlccj / (pwr(l, wlncj) * pwr(w, wwncj))`. Next, the correction factor `djtsswgs_w` is calculated, with the expression `(w / nf - 2.2e-7 - 2.3e-13 / w) / dweffcj`. In the device instance `mxckt` that calls this sub-circuit, the associated model `nch_model` is used, and `w=w` and `l=l` are passed in. In the model definition of nch_model, the original model parameters such as xw=1.6e-8, dwj=-1e-8, wlc=0, wwc=-2.45e-15, wwlc=0, wrn=1, wwn=1 are retained, and the target model parameter jtsswgs is updated to 3e-9*djtsswgs_w. If the fitting result using the default BSIM4 formula is denoted as model_b, and the result after using the method of this application is denoted as model, comparing the simulation curves, it can be found that the leakage current fitting result is better after using the method of this application, and it can be adjusted independently without considering the limitations of other device characteristics.

[0055] Figure 2 This is a schematic diagram of the structure of a device for modifying embedded formulas in a semiconductor device model according to some embodiments of this application. For example... Figure 2 As shown, the device for modifying the embedded formula of a semiconductor device model includes a determination module, a construction module, and an update module.

[0056] The module configuration is determined to identify the target calculation formula to be modified in the semiconductor device model. The target calculation formula includes the target model parameters and the initial function.

[0057] The construction module is configured to build sub-circuits, within which correction factors are defined based on replacement and initialization functions. The update module is configured to update the target model parameters using the correction factors in the model definition, enabling the semiconductor device model to perform simulations based on the updated target model parameters.

[0058] The defining, building, and updating modules can be software program modules integrated into electronic devices, or logic units implemented by hardware circuits such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CAMPs).

[0059] In alternative embodiments, the functionality of these modules can be integrated into a single processing chip or distributed across multiple cooperating computing nodes. These modules work together to provide an automated model modification environment, enabling circuit design engineers to quickly customize complex model formulas via a graphical user interface or command-line scripts, thereby improving the overall R&D efficiency of integrated circuit design.

[0060] This application also provides an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504, wherein the processor 1501, the communication interface 1502, and the memory 1503 communicate with each other through the communication bus 1504.

[0061] Memory 1503 is used to store computer programs;

[0062] When the processor 1501 executes the computer program stored in the memory 1503, it implements the steps of the above embodiments.

[0063] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0064] The communication interface is used for communication between the aforementioned terminal and other devices.

[0065] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0066] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0067] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform the above-described method for modifying the embedded formula of the semiconductor device model.

[0068] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the method for modifying the embedded formula of the semiconductor device model as described in any of the above embodiments.

[0069] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk).

[0070] Figure 4 This is a schematic diagram comparing the current-voltage characteristic curves of semiconductor devices according to some embodiments of this application under specific bias conditions. For example... Figure 4 As shown in the figure, this figure illustrates the curve of drain current Id versus gate-source voltage Vgs for an N-type metal-oxide-semiconductor field-effect transistor under the conditions of drain-source voltage Vds of 1.2V, temperature T of 25.00 degrees Celsius, device width W of 9.000, and device length L of 9.000. The horizontal axis represents the gate-source voltage Vgs in volts; the vertical axis represents the drain current Id on a logarithmic scale in amperes. The data, represented as scatter plots, represents the actual silicon wafer test data. The model_b, represented by the green line, is the fitting result using the default BSIM4 formula, while the model, represented by the red line, is the fitting result after modifying the model using the embedded formula method provided in this application. A comparison clearly shows that in the low gate-source voltage region, the model_b curve using the default formula deviates somewhat from the actual test data, while the model curve modified using the method of this application more accurately matches the actual test data. This indicates that by constructing sub-circuits and introducing correction factors to update the target model parameters, the model's fitting accuracy for characteristics such as leakage current can be effectively improved, and this correction can be adjusted independently without considering the limitations of other device characteristics.

[0071] Figure 5This is a comparative schematic diagram of the current-voltage characteristic curves of semiconductor devices according to other embodiments of this application under specific bias conditions. For example... Figure 5 As shown in the figure, this figure illustrates the curve of drain current Id versus gate-source voltage Vgs for an N-type metal-oxide-semiconductor field-effect transistor under the conditions of drain-source voltage Vds of 1.2V, temperature T of 25.00 degrees Celsius, device width W of 0.9000, and device length L of 9.000. The horizontal axis represents the gate-source voltage Vgs in volts; the vertical axis represents the drain current Id, using a logarithmic coordinate system in amperes. The data represented by scatter plots in the figure represents actual silicon wafer test data; the model_b represented by the green line represents the fitting result using the default BSIM4 formula; and the model represented by the red line represents the fitting result after modifying the model using the embedded formula method provided in this application. Figure 4 Compared to the case where the width W of the device is 9.000, Figure 5 The characteristics of narrow-channel devices (W = 0.9000) are demonstrated. It is evident that in the low gate-source voltage region (e.g., between 0.0V and 0.2V), the leakage current calculated using the default formula's model_b curve is significantly lower than the actual test data, indicating a large fitting error. However, the model curve corrected using the method of this application, by introducing width-related parameters and other replacement model parameters in the replacement effective width function, accurately captures the impact of narrow-channel effects on leakage current, resulting in a perfect fit between the simulation curve and the actual test data. This further demonstrates that the method of this application can provide high-precision model fitting capabilities for different device sizes, effectively solving the problem of insufficient fitting accuracy caused by mutual parameter constraints in traditional models.

[0072] Figure 6 This is a comparative schematic diagram of the current-voltage characteristic curves of semiconductor devices according to some embodiments of this application under specific bias conditions. For example... Figure 6 As shown in the figure, this figure illustrates the curve of drain current Id versus gate-source voltage Vgs for an N-type metal-oxide-semiconductor field-effect transistor under the conditions of drain-source voltage Vds of 1.2V, temperature T of 25.00 degrees Celsius, device width W of 0.5400, and device length L of 9.000. The horizontal axis represents the gate-source voltage Vgs in volts; the vertical axis represents the drain current Id, using a logarithmic coordinate system in amperes. The data represented by scatter plots in the figure represents actual silicon wafer test data; the model_b represented by the green line represents the fitting result using the default BSIM4 formula; and the model represented by the red line represents the fitting result after modifying the model using the embedded formula method provided in this application. Figure 4 and Figure 5 compared to, Figure 6The device characteristics are shown when the channel width is further reduced (W = 0.5400). It is clearly observed that in the low gate-source voltage region (e.g., between 0.0V and 0.2V), the deviation between the model_b curve using the default formula and the actual test data (data) widens further, indicating that the default model has significant limitations in characterizing the leakage current characteristics of narrower channel devices. Conversely, the model curve corrected using the method of this application still closely tracks the actual test data, achieving a high-precision fit. This fully demonstrates that by defining a correction factor in the sub-circuit and updating the target model parameters, the shortcomings of traditional models in handling complex size-dependent effects can be effectively overcome, providing reliable and accurate simulation results for various device sizes.

[0073] Figure 7 This is a comparative schematic diagram of the current-voltage characteristic curves of semiconductor devices according to some embodiments of this application under specific bias conditions. For example... Figure 7 As shown in the figure, this figure illustrates the curve of drain current Id versus gate-source voltage Vgs for an N-type metal-oxide-semiconductor field-effect transistor under the conditions of drain-source voltage Vds of 1.2V, temperature T of 25.00 degrees Celsius, device width W of 0.2700, and device length L of 9.000. The horizontal axis represents the gate-source voltage Vgs in volts; the vertical axis represents the drain current Id, using a logarithmic coordinate system in amperes. The data represented by scatter plots in the figure represents actual silicon wafer test data; the model_b represented by the green line represents the fitting result using the default BSIM4 formula; and the model represented by the red line represents the fitting result after modifying the model using the embedded formula method provided in this application. (As mentioned above...) Figures 4 to 6 compared to, Figure 7 This study demonstrates the device characteristics when the channel width is further reduced to an extremely narrow size (W = 0.2700). It is readily apparent that in the low gate-source voltage region (e.g., the subthreshold leakage region between 0.0V and 0.2V), the deviation between the model_b curve using the default formula and the actual test data becomes significant, indicating that the default model severely underestimates the leakage current at this size. However, the model curve corrected using the method described in this application still accurately covers the actual test data points, maintaining a high degree of fit consistency. This series of comparisons from wide-channel to extremely narrow-channel fully demonstrates that the sub-circuit-defined correction factor method provided in this application can effectively remove the mutual constraints between device effect parameters. Without compromising the overall model architecture and simulator optimization, it enables independent and high-precision adjustment of specific physical effects (such as gate edge sidewall trap-assisted saturation current), thus providing highly reliable model support for circuit design at advanced semiconductor process nodes.

[0074] Figure 8This is a schematic diagram comparing the turn-off current per unit width of a semiconductor device as a function of device width according to some embodiments of this application. Figure 8 As shown in the figure, this graph illustrates the trend of the turn-off current Ioff per unit width as a function of the device width w, under the conditions of a device length L of 9.000 and a temperature T of 25.00 degrees Celsius. The horizontal axis represents the device width w, using a logarithmic coordinate system with units of micrometers (µm); the vertical axis represents the turn-off current Ioff per unit width, using a linear coordinate system with units of picoamperes per micrometer (pA / µm). In the legend, data represented as scatter points represents actual silicon wafer test data, model_b represented as a straight solid line represents the fitting result using the default BSIM4 formula, and model represented as a solid line conforming to the scatter points represents the fitting result after using the model embedding formula modification method provided in this application. Through observation... Figure 8 It can be observed that the actual test data shows that as the device width w decreases, the turn-off current Ioff per unit width exhibits a significant upward trend, reflecting the strong influence of the narrow channel effect on device leakage current. However, the model_b curve using the default formula is almost a horizontal straight line, completely failing to capture this width-dependent characteristic, resulting in a severe underestimation of the turn-off current in the narrow channel region. In contrast, the model curve corrected using the method of this application can accurately track the upward trend of the actual test data, achieving a high degree of fit across various width dimensions. This result intuitively and powerfully demonstrates that this application, by introducing an alternative effective width function containing replacement model parameters such as width-related parameters into the sub-circuit, successfully overcomes the shortcomings of traditional models in characterizing size-dependent effects, providing high-precision device leakage current prediction capabilities for integrated circuit design.

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for modifying embedded formulas in a semiconductor device model, characterized in that, At least including: Step 1: Determine the target calculation formula to be modified in the semiconductor device model. The target calculation formula includes the target model parameters and the initial function. Step 2: Construct a sub-circuit, in which a correction factor is defined based on the substitution function and the initial function; Step 3: In the model definition, the target model parameters are updated using the correction factor so that the semiconductor device model can be simulated based on the updated target model parameters.

2. The method for modifying the embedded formula of a semiconductor device model according to claim 1, characterized in that: In step one, the target calculation formula is used to calculate the current, voltage, charge, or capacitance of a semiconductor device.

3. The method for modifying the embedded formula of a semiconductor device model according to claim 1, characterized in that: In step one, the independent variables of the initial function include device size parameters and initial model parameters.

4. The method for modifying the embedded formula of the semiconductor device model according to claim 3, characterized in that: In step two, the independent variables of the substitution function include the device size parameters and the substitution model parameters.

5. The method for modifying the embedded formula of a semiconductor device model according to claim 1, characterized in that: In step three, updating the target model parameters using the correction factor includes multiplying the target model parameters by the correction factor to obtain the updated target model parameters.

6. The method for modifying the embedded formula of a semiconductor device model according to claim 1, characterized in that: In step one, the semiconductor device model is the BSIM4 model, the target calculation formula is the gate edge sidewall trap-assisted saturation current calculation formula, and the initial function is the initial effective width function.

7. The method for modifying the embedded formula of a semiconductor device model according to claim 6, characterized in that: In step two, the replacement function is a replacement effective width function, and the replacement model parameters in the replacement effective width function include size deviation parameters, length-related parameters, width-related parameters, and length-width-related parameters.

8. A device for modifying embedded formulas in a semiconductor device model, characterized in that, include: The determination module is configured to determine the target calculation formula to be modified in the semiconductor device model, wherein the target calculation formula includes target model parameters and initial functions; A construction module is configured to construct sub-circuits, in which a correction factor is defined based on a substitution function and the initial function; The update module is configured to update the target model parameters in the model definition using the correction factor, so that the semiconductor device model can be simulated based on the updated target model parameters.

9. An electronic device, characterized in that, include: processor; as well as Memory, configured to store computer programs; Wherein, when the processor executes the computer program, it implements the method for modifying the embedded formula of the semiconductor device model as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for modifying the embedded formula of the semiconductor device model according to any one of claims 1 to 7.

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