Ophthalmic surgery scene customized core chip scale dedicated production system

Abstract

This invention relates to the field of semiconductor manufacturing technology, specifically to a large-scale dedicated production system for customized core chips used in ophthalmic surgery scenarios. The system includes a mesh construction module, a fitting and correction module, a coordinate correction module, a benchmark establishment module, an encoding generation module, and a decoding execution module. By extracting the initial position information of chip cells with complete adjacent topologies from the original wafer defect map and fitting it with the theoretical position mesh to generate a correction transformation relationship, the description of defect locations is completely decoupled from the coordinate system conventions of upstream and downstream equipment, eliminating the risk of silent misalignment caused by coordinate system inconsistencies. This ensures the positional certainty and reproducibility of defect location information when it flows between different manufacturers' equipment. It significantly improves the accuracy and robustness of wafer defect map data transmission in complex production environments, meeting the requirements of data accuracy and process traceability for large-scale production of customized chips for ophthalmic surgery.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a large-scale dedicated production system for customized core chips used in ophthalmic surgery scenarios. Background Technology

[0002] In the mass production of customized chips for ophthalmic surgery, wafers need to be transferred between different testing, dicing, and sorting equipment, and may even involve multiple external suppliers. Wafer defect maps, which record the locations of defective chip cells on the wafer, are crucial for guiding subsequent defect masking, sorting, and packaging processes. However, different equipment or manufacturers often have different coordinate system conventions for wafer defect maps, specifically in the selection of different coordinate origins, opposite row and column increment directions, or mirror relationships.

[0003] In the prior art, when a wafer defect map file is transmitted between systems with inconsistent coordinate system conventions, even if the file format itself conforms to industry standards, the coordinate information of the defective points recorded in the file may be incorrectly mapped to the wrong physical location on the wafer due to different parsing methods, which is called silent misalignment. This misalignment will not trigger system error reports, but it will cause chip units that should be identified as defective points to be misjudged as good products and enter the subsequent packaging process, or good chip units to be incorrectly marked as defective points and discarded.

[0004] For customized chips used in ophthalmic surgery, which are directly applied to human eye surgery, the reliability and safety requirements of the chips are extremely high. Any quality defects caused by incorrect location of bad pixels may lead to serious medical accidents. Existing technologies usually rely on the prior negotiation and agreement of coordinate systems among all parties in the supply chain to solve the above problems. However, in the actual production environment with many participating manufacturers and dynamically changing equipment models, it is difficult to ensure that this negotiation mechanism is strictly and consistently implemented. It is also difficult to meet the stringent requirements of data accuracy and process traceability for the large-scale production of customized chips for ophthalmic surgery. Summary of the Invention

[0005] To address the technical problems existing in the background art, this invention proposes a large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios, the specific solution of which is as follows: A large-scale dedicated production system for core chips customized for ophthalmic surgical scenarios, including: The mesh construction module is used to obtain the original wafer defect map and wafer layout design file, and generate a theoretical position mesh based on the wafer layout design file. The original wafer defect map records the initial position information of the bad chip cells on the wafer. The fitting and correction module is used to extract the initial position information of chip cells with complete adjacent topology based on the original wafer defect map, fit it with the corresponding points in the theoretical position grid, and generate a correction transformation relationship. The coordinate correction module is used to correct the theoretical position of the defective chip unit by applying the correction transformation relationship to obtain the corrected coordinates in the global correction space. The reference establishment module is used to establish an intrinsic reference reference in the global correction space, with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis. The encoding generation module is used to perform pure integer arithmetic encoding on the corrected coordinates of each defective chip unit according to the intrinsic reference benchmark, generate deterministic position encoding, and generate an intrinsic defect map file based on all deterministic position encodings; The decoding execution module is used to reproduce the intrinsic reference benchmark in its local coordinate system when the downstream device parses the intrinsic defect map file, and to perform pure integer arithmetic decoding, which is the inverse of the encoding generation module, on each deterministic position encoding to obtain the position of the bad pixel chip unit in the local coordinate system and perform the corresponding operation.

[0006] Furthermore, in the mesh construction module, a theoretical location mesh is generated based on the wafer layout design file, as follows: Extract the standard width dimension, standard height dimension, and dicing slot width dimension between chip cells from the wafer layout design file; Using the wafer design center as the grid origin, the coordinates of the center points of all theoretically existing chip cells on the wafer are calculated based on the standard width dimension, the standard height dimension, and the dicing groove width dimension, thus forming the theoretical position grid.

[0007] Furthermore, in the fitting and correction module, the chip cell with a complete adjacent topology refers to a chip cell in which there are recorded adjacent chip cells at four adjacent positions along the row and column directions among all the chip cells recorded in the original wafer defect map.

[0008] Furthermore, in the fitting and correction module, based on the original wafer defect map, the initial position information of chip cells with complete adjacent topology is extracted and fitted with the corresponding points in the theoretical position grid to generate a correction transformation relationship, as follows: The original wafer defect map is traversed, and chip cells that have recorded chip cells in all four adjacent directions of increasing row direction, decreasing row direction, increasing column direction, and decreasing column direction are selected. Their initial position information is extracted as a reference point set. In the theoretical position grid, the theoretical coordinate points corresponding to the reference point set are determined to form the target point set. A two-dimensional rigid transformation matrix is ​​calculated by the point set registration algorithm to minimize the positional deviation between the reference point set and the target point set after transformation. The two-dimensional rigid transformation matrix is ​​the correction transformation relationship.

[0009] Furthermore, in the coordinate correction module, the theoretical position of the defective chip unit is corrected using the aforementioned correction transformation relationship to obtain the corrected coordinates in the global correction space, as follows: The theoretical coordinates corresponding to each defective chip unit are determined in the theoretical location grid; The theoretical coordinates are multiplied by the correction transformation relationship to obtain the corrected coordinates of the defective chip unit after systematic deviation correction. The corrected coordinates of all defective chip units constitute the coordinate set in the global correction space.

[0010] Furthermore, in the reference establishment module, within the global correction space, an intrinsic reference reference is established with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis, as follows: In the global correction space, the geometric center of the outer contour of the wafer is taken as the physical geometric center of the wafer; Using the direction vector pointing from the physical geometric center of the wafer to the midpoint of the physical reference feature of the wafer as the reference axis, an intrinsic reference reference is established that is independent of the conventions of the origin and direction of the external coordinate system.

[0011] Furthermore, in the encoding generation module, pure integer arithmetic encoding is performed on the corrected coordinates of each defective chip unit based on the intrinsic reference benchmark to generate a deterministic positional encoding, as follows: The sum of the squared values ​​of the abscissa and ordinate of the corrected coordinates is calculated as the squared value of the radial distance; Calculate the integer cross product and integer dot product between the position vector of the corrected coordinates and the direction vector of the reference axis, and determine a coprime integer pair and a quadrant sign value based on the integer cross product and integer dot product. The radial distance squared value, the coprime integer pair, and the quadrant sign value are combined into an integer tuple as the deterministic position code.

[0012] Furthermore, in the encoding generation module, an intrinsic defect map file is generated based on encoding all deterministic locations, as follows: The intrinsic defect map file is generated by using the deterministic location encoding set of all defective chip cells as the main data of the file and writing metadata containing at least wafer identifier, chip cell size parameters and chip cell spacing parameters in the file header.

[0013] Furthermore, in the decoding execution module, when the downstream device parses the intrinsic defect map file, it reproduces the intrinsic reference datum in its local coordinate system, as follows: The downstream device captures an image of the current physical wafer through its metering system, and identifies the geometric center of the outer contour of the wafer and the midpoint of the physical reference feature through an image processing algorithm. The geometric center is used as the local origin, and the direction from the geometric center to the midpoint of the physical reference feature is used as the local reference axis to complete the reproduction of the intrinsic reference reference.

[0014] Furthermore, in the decoding execution module, the encoding of each deterministic position is performed using pure integer arithmetic decoding, which is the inverse of the encoding generation module, to obtain the position of the defective chip unit in the local coordinate system and perform the corresponding operation, as follows: Call the same integer arithmetic library used by the encoding generation module to perform inverse operation on the integer tuple contained in the deterministic position code to obtain the local Cartesian coordinates of the bad pixel chip unit relative to the local origin and the local reference axis; The local Cartesian coordinates are output to the motion control system to drive the end effector to perform a skip action when it reaches the local Cartesian coordinates.

[0015] Compared with the prior art, the present invention can achieve at least the following beneficial effects: 1. This invention extracts the initial position information of chip cells with complete adjacent topologies and fits it with a theoretical position grid to generate a correction transformation relationship. This automatically identifies and quantifies the systematic translational and rotational deviations of the physical loading system generated when the wafer is transferred between different devices, avoiding the overall offset of defect coordinates caused by differences in wafer placement. An intrinsic reference benchmark is established with the wafer's own physical geometric center as the origin and the direction pointing to the wafer's physical reference features as the reference axis. This ensures that the description of defect locations depends entirely on the inherent geometric features of the wafer, completely decoupling it from the coordinate system origin and coordinate axis direction conventions adopted by upstream testing equipment and downstream execution equipment. Therefore, it eliminates the risk of silent misalignment caused by inconsistencies in upstream and downstream coordinate system conventions, eliminating the need for supply... The chain involves meticulous pre-conference negotiations and unification among all parties. Pure integer arithmetic is used throughout the encoding and decoding process, avoiding calculation errors caused by differences in floating-point representation precision and rounding rules across different devices. This ensures the bit-to-bit certainty and reproducibility of bad pixel location encoding during cross-vendor and cross-device transfer, further enhancing data transmission reliability. By not relying on specific device software configurations or human agreements, downstream devices only need to identify wafer geometric features through their own metrology systems to autonomously complete the reproduction of positioning benchmarks and the analysis of bad pixel coordinates. This demonstrates high device universality and supply chain adaptability, making it particularly suitable for the large-scale production environment of customized ophthalmic surgical chips with numerous participating manufacturers and dynamically changing equipment models. It significantly reduces medical quality risks caused by data analysis errors.

[0016] 2. This invention extracts the initial position information of chip cells with complete adjacent topologies from the original wafer defect map and fits it with the theoretical position grid to generate a correction transformation relationship. This automatically compensates for systematic translation and rotation deviations in the physical loading of the wafer. Based on this, an intrinsic reference benchmark is established with the physical geometric center of the wafer as the origin and the direction pointing to the physical reference feature as the reference axis. This completely decouples the description of the defect location from the inherent geometric features of the wafer and the coordinate system conventions of upstream and downstream equipment, eliminating the risk of silent misalignment caused by inconsistencies in coordinate systems. At the same time, the entire process uses pure integer arithmetic operations to complete position encoding and decoding, avoiding the precision loss introduced by cross-platform floating-point calculation differences. This ensures the positional certainty and reproducibility of defect location information when it is transferred between different manufacturers' equipment. Downstream equipment only needs to identify the wafer geometric features through its own metrology system to independently reproduce the benchmark and accurately analyze the defect location without relying on prior agreements between the supply chain parties. This significantly improves the accuracy and robustness of wafer defect map data transmission in complex production environments and meets the requirements of data accuracy and process traceability for the large-scale production of customized chips for ophthalmic surgery. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a system principle block diagram of the present invention. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] Please refer to Figure 1 This invention provides a large-scale dedicated production system for customized core chips for ophthalmic surgery scenarios, including a mesh construction module, a fitting correction module, a coordinate correction module, a benchmark establishment module, an encoding generation module, and a decoding execution module; The mesh construction module is used to obtain the original wafer defect map and wafer layout design file, and generate a theoretical location mesh based on the wafer layout design file. The original wafer defect map records the initial location information of the bad chip cells on the wafer.

[0020] It should be noted that the original wafer defect map refers to a data file generated by upstream wafer testing equipment after performing electrical performance testing or optical inspection on the wafer, recording the location information of chip cells on the wafer that have been determined to be defective. This original wafer defect map is usually associated with the local coordinate system of the testing equipment that generated the file. The coordinate system conventions used by different manufacturers and different models of testing equipment may differ. For example, the origin of the coordinate system may be selected at the upper left corner, lower left corner, or center of the wafer, and the direction of the row and column increment of the coordinate axes may also be different.

[0021] It should be noted that the wafer layout design file refers to an electronic design file containing physical layout information of chip cells on the wafer, and its format can be GDSII or OASIS. This file defines the design location of each chip cell on the wafer, the geometric dimensions of the chip cell itself, and the scribe line width between adjacent chip cells. Specifically, the standard width of a chip cell refers to the physical span of a single chip cell in the wafer row direction, the standard height refers to the physical span of a single chip cell in the wafer column direction, and the scribe line width refers to the reserved gap width between adjacent chip cells for dicing and separation.

[0022] In an optional embodiment, the mesh building module generates a theoretical location mesh based on the wafer layout design file, as follows: Extract the standard width dimension, standard height dimension, and dicing slot width dimension between chip cells from the wafer layout design file; Using the wafer design center as the grid origin, the coordinates of the center points of all theoretically existing chip cells on the wafer are calculated based on the standard width dimension, the standard height dimension, and the dicing groove width dimension, thus forming the theoretical position grid.

[0023] It should be noted that the theoretical location grid is a set of coordinates constructed in mathematical space representing the center points of all theoretically existing chip cells on the wafer. Using the wafer design center as the grid origin means taking the geometric symmetry center of the wafer in the layout design file as the zero point of the coordinate system. Based on the standard width, standard height, and scribe line width of the chip cells, the Cartesian coordinates of each theoretical chip cell center relative to the grid origin can be calculated using row and column indices. This theoretical location grid provides an ideal reference standard independent of the test equipment coordinate system for subsequent deviation correction.

[0024] The fitting and correction module is used to extract the initial position information of chip cells with complete adjacent topology based on the original wafer defect map, and fit it with the corresponding points in the theoretical position grid to generate a correction transformation relationship.

[0025] In an optional embodiment, in the fitting correction module, the chip cell with a complete adjacent topology refers to a chip cell in which there are recorded adjacent chip cells at four adjacent positions along the row and column directions among all the chip cells recorded in the original wafer defect map.

[0026] It should be noted that the chip cells with complete adjacent topology refer to those located within the wafer's internal region and without any missing chip cells in their vicinity. Specifically, in the chip cell array recorded in the original wafer defect map, if a chip cell has adjacent chip cell records on both its row-wise increasing and decreasing sides, and on both its column-wise increasing and decreasing sides, then that chip cell is considered to have a complete adjacent topology. Because such chip cells are not located at the wafer edge or near large-area defect regions, their initial position information is less affected by boundary effects and local data gaps, thus possessing higher position confidence and making them suitable as reference points for calculating correction transformation relationships.

[0027] In an optional embodiment, the fitting and correction module extracts the initial position information of chip cells with complete adjacent topologies based on the original wafer defect map, and fits it with the corresponding points in the theoretical position grid to generate a correction transformation relationship, as follows: The original wafer defect map is traversed, and chip cells that have recorded chip cells in all four adjacent directions of increasing row direction, decreasing row direction, increasing column direction, and decreasing column direction are selected. Their initial position information is extracted as a reference point set. In the theoretical position grid, the theoretical coordinate points corresponding to the reference point set are determined to form the target point set. A two-dimensional rigid transformation matrix is ​​calculated by the point set registration algorithm to minimize the positional deviation between the reference point set and the target point set after transformation. The two-dimensional rigid transformation matrix is ​​the correction transformation relationship.

[0028] It should be noted that the initial position information of the aforementioned chip cells is extracted as a reference point set because the coordinates recorded in the original wafer defect map may include physical loading deviations of the wafer on the test equipment chuck, such as minute translational and rotational offsets. Each point in the reference point set represents the position of the corresponding chip cell on the actual physical wafer as observed by the test equipment. The theoretical coordinate points corresponding to the reference point set are determined in the theoretical position grid to form the target point set, and there is a one-to-one mapping relationship between these two point sets.

[0029] It should be noted that the purpose of the point set registration algorithm is to find an optimal two-dimensional rigid transformation matrix, which consists of translation and rotation components. Applying this matrix to the target point set minimizes the overall positional deviation between the transformed target point set and the reference point set. This positional deviation can be measured by the least squares error or the sum of point-to-point Euclidean distances. The calculated two-dimensional rigid transformation matrix is ​​the correction transformation relationship, which precisely quantifies the systematic translation and rotation of the actual physical wafer relative to its theoretical design position, providing a unified mathematical basis for the subsequent position correction of each defective chip cell. The above fitting process can be achieved using either an iterative nearest-point alignment algorithm or a least squares registration algorithm based on singular value decomposition.

[0030] The coordinate correction module is used to correct the theoretical position of the defective chip unit by applying the correction transformation relationship to obtain the corrected coordinates in the global correction space.

[0031] It should be noted that the application of the correction transformation relationship to correct the theoretical location of the defective chip cell aims to eliminate the systematic deviation of the wafer physical loading system calculated in the fitting correction module from the location information of each defective chip cell. Since the correction transformation relationship generated in the fitting correction module is based on the global deviation quantification result calculated from a high-confidence reference point set across the entire wafer, applying this correction transformation relationship to each defective chip cell can achieve unified deviation compensation for all defective locations on the entire wafer.

[0032] In an optional embodiment, the coordinate correction module applies the correction transformation relationship to correct the theoretical position of the defective chip unit, obtaining the corrected coordinates in the global correction space, as follows: The theoretical coordinates corresponding to each defective chip unit are determined in the theoretical location grid; It should be noted that determining the theoretical coordinates of each defective chip cell in the theoretical location grid means finding the coordinates of the theoretical center point corresponding to the row and column index of the defective chip cell in the theoretical location grid generated by the grid construction module. Since there is a one-to-one correspondence between the physical locations of the defective chip cells recorded in the original wafer defect map and the chip cells in the theoretical location grid on the wafer layout, a mapping between the two can be established through row and column indices.

[0033] The theoretical coordinates are multiplied by the correction transformation relationship to obtain the corrected coordinates of the defective chip unit after systematic deviation correction. The corrected coordinates of all defective chip units constitute the coordinate set in the global correction space.

[0034] It should be noted that multiplying the theoretical coordinates with the correction transformation relationship specifically refers to using the theoretical coordinates as an input vector and performing a matrix multiplication operation with the two-dimensional rigid transformation matrix representing the correction transformation relationship. This two-dimensional rigid transformation matrix contains translation and rotation components, and the result of the multiplication operation is the new coordinate value obtained after the theoretical coordinates have undergone translation and rotation compensation. This new coordinate value is the corrected coordinate of the defective chip unit after systematic deviation correction.

[0035] It should be noted that the global correction space refers to the coordinate space jointly formed by the corrected coordinates of all defective chip cells. Within this space, the position coordinates of all defective chip cells have been freed from systematic errors introduced by physical loading deviations of the wafer on the test equipment chuck, and the relative positional relationships between each defective chip cell are consistent with the theoretical relative positional relationships in the wafer layout design file. This global correction space provides a unified and accurate coordinate basis for establishing an internal reference datum decoupled from the external coordinate system in subsequent steps.

[0036] It's important to note that the location correction is performed only on the chip cells recorded as bad pixels in the original wafer defect map, without needing to perform this operation on the good chip cells on the wafer. This design reduces computational load, improves processing efficiency, and ensures that subsequent steps only require accurate encoding and transmission of the actual bad pixel locations that need to be processed.

[0037] The reference establishment module is used to establish an intrinsic reference reference in the global correction space, with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis.

[0038] It should be noted that the purpose of establishing the intrinsic reference benchmark is to construct a position description system entirely based on the physical geometric characteristics of the wafer itself. This ensures that the positional representation of defective chip cells no longer depends on any coordinate system artificially defined by external devices or software. In traditional methods, the interpretation of wafer defect maps relies on consistent agreements between upstream and downstream devices regarding the origin position and coordinate axis directions. Inconsistent agreements or misconfigurations will lead to systematic misalignment of defective cell positions. The intrinsic reference benchmark established in this step fundamentally solves this problem.

[0039] In an optional embodiment, in the reference establishment module, an intrinsic reference reference is established in the global correction space with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis, as follows: In the global correction space, the geometric center of the outer contour of the wafer is taken as the physical geometric center of the wafer; It should be noted that the physical geometric center of the wafer refers to the geometric center of the wafer's outer contour. Since wafers are typically circular or approximately circular with flat edges, the geometric center of their outer contour can be obtained by performing circle fitting or centroid calculation on the wafer's edge contour points. This geometric center is an inherent physical property of the wafer itself and does not change with the wafer's placement position or rotation angle on the equipment chuck; therefore, it is suitable as the origin of an intrinsic reference datum.

[0040] It should be noted that the wafer physical reference feature refers to the physical structural feature on the wafer used to identify the wafer's crystal orientation and position, typically a flat edge or notch. This physical reference feature is formed during the wafer manufacturing process, and its orientation relative to the chip cell array on the wafer is fixed and known. Specifically, the direction pointing to the wafer physical reference feature refers to the direction vector originating from the wafer's physical geometric center and pointing towards the midpoint of that physical reference feature.

[0041] Using the direction vector pointing from the physical geometric center of the wafer to the midpoint of the physical reference feature of the wafer as the reference axis, an intrinsic reference reference is established that is independent of the conventions of the origin and direction of the external coordinate system.

[0042] It should be noted that by using the geometric center of the wafer's outer contour as the wafer's physical geometric center and the direction vector pointing from the wafer's physical geometric center to the midpoint of the wafer's physical reference feature as the reference axis, the established intrinsic reference datum has the characteristic of being independent of the origin and direction conventions of the external coordinate system. Specifically, regardless of whether the upstream test equipment uses the upper left corner or the lower left corner as the origin, and regardless of whether its row direction increments to correspond to the positive X-axis or the positive Y-axis, the intrinsic reference datum established in this step is solely based on the wafer's own geometric center and physical reference feature, completely decoupling from external conventions. This characteristic provides a unified reference framework for generating platform-independent deterministic position codes in subsequent steps.

[0043] It should be noted that, because the coordinate correction module has eliminated systematic translational and rotational deviations during the wafer physical loading process, the wafer physical geometric center and reference axis established in the reference establishment module can accurately reflect the true geometric properties of the wafer itself, unaffected by the chuck loading error of the test equipment. This sequence ensures the accuracy of the internal reference datum establishment.

[0044] The encoding generation module is used to perform pure integer arithmetic encoding on the corrected coordinates of each defective chip unit according to the intrinsic reference benchmark, generate deterministic position encoding, and generate an intrinsic defect map file based on all deterministic position encodings.

[0045] It should be noted that the purpose of performing pure integer arithmetic encoding is to transform the corrected coordinates obtained by the coordinate correction module and the internal reference base established by the reference establishment module into a position encoding form that does not rely on any floating-point operations. In semiconductor manufacturing equipment, control systems from different manufacturers and models may use different floating-point representation precisions and rounding rules. If floating-point operations are introduced during encoding or decoding, pixel-level offsets of bad pixel positions are highly likely to occur due to minute calculation differences between systems. This step uses pure integer arithmetic operations to complete all geometric calculations, fundamentally eliminating the problems of floating-point error accumulation and cross-platform calculation inconsistencies, ensuring the absolute determinism and reproducibility of the position encoding.

[0046] In an optional embodiment, the encoding generation module performs pure integer arithmetic encoding on the corrected coordinates of each defective chip unit based on the intrinsic reference benchmark to generate a deterministic positional encoding, as follows: The sum of the squared values ​​of the abscissa and ordinate of the corrected coordinates is calculated as the squared value of the radial distance; It should be noted that the sum of the squared values ​​of the abscissa and ordinate of the corrected coordinates, i.e., the squared radial distance, is used to characterize the distance information of the defective chip cell relative to the intrinsic origin. Using the squared distance value instead of the distance value itself is to avoid square root operations throughout the calculation process, thus constraining all calculations to the integer domain. Since the corrected coordinates of the defective chip cell are all represented as integer values ​​on a predefined high-resolution integer grid, their sum of squares remains an integer, without introducing any loss of precision.

[0047] Calculate the integer cross product and integer dot product between the position vector of the corrected coordinates and the direction vector of the reference axis, and determine a coprime integer pair and a quadrant sign value based on the integer cross product and integer dot product. It should be noted that the integer cross product and integer dot product results are intermediate calculations used to determine the orientation angle of the defective chip unit relative to the reference axis. Specifically, the integer dot product between the corrected coordinate position vector and the reference axis direction vector reflects the cosine relationship of the angle between the two vectors, while the integer cross product reflects the sine relationship of the angle and the direction of rotation. Since the reference axis direction vector is also represented as an integer value on a predefined high-resolution integer grid, the above cross product and dot product operations can be performed in the integer domain. Based on the ratio of the integer cross product and integer dot product results, a coprime integer pair can be reduced to uniquely determine the orientation angle of the defective chip unit relative to the reference axis, and this angle representation does not depend on any floating-point trigonometric function operations.

[0048] The radial distance squared value, the coprime integer pair, and the quadrant sign value are combined into an integer tuple as the deterministic position code.

[0049] It should be noted that the quadrant sign value is used to distinguish symmetrical positions that may be indistinguishable by relying solely on coprime integer pairs. For example, when two defective chip cells are located in mirror positions with the reference axis as the axis of symmetry, their radial distance squared value and coprime integer pair may be the same, but they are located in different quadrants. By introducing the quadrant sign value, the specific orientation of the defective chip cell in the two-dimensional plane can be completely and uniquely identified.

[0050] It should be noted that the integer tuple formed by combining the squared radial distance, the coprime integer pair, and the quadrant sign value constitutes the deterministic location code of the defective chip unit. Since the generation process of this code is entirely based on integer values ​​and integer operations, and its calculation is solely based on the internal reference datum established by the datum establishment module and the corrected coordinates obtained by the coordinate correction module, this code is unrelated to any external coordinate system convention and possesses datum-independent characteristics. Defective chip units at different locations will generate different integer tuples, ensuring the uniqueness of the code.

[0051] In an optional embodiment, the encoding generation module generates an intrinsic defect map file based on encoding all deterministic locations, as follows: The intrinsic defect map file is generated by using the deterministic location encoding set of all defective chip cells as the main data of the file and writing metadata containing at least wafer identifier, chip cell size parameters and chip cell spacing parameters in the file header.

[0052] It should be noted that the process of generating an intrinsic defect map file based on all deterministic location codes involves storing the set of deterministic location codes for all defective chip cells as the main data portion of the file. Unlike traditional wafer defect map files that only record coordinate values, the intrinsic defect map file generated in this step also includes metadata in the file header. The wafer identifier is used to uniquely identify the physical wafer corresponding to the defect map file, ensuring traceability during data transfer. Chip cell size parameters include standard width and standard height, and chip cell spacing parameters, i.e., scribe line width, provide necessary information for downstream equipment to reconstruct the theoretical location grid and verify data integrity when parsing the file.

[0053] It should be noted that the generated intrinsic defect map file has a data format and encoding rules that are completely decoupled from the local coordinate system conventions of downstream devices. Regardless of the coordinate origin definition or coordinate axis orientation conventions used by the downstream devices, as long as they can locate the physical geometric center and physical reference features of the wafer in the manner described, they can accurately reproduce the intrinsic reference datum in the local coordinate system and correctly decode the deterministic position encoding accordingly. This design allows the intrinsic defect map file to be seamlessly transferred between devices from different manufacturers and of different models without any coordinate transformation configuration or manual alignment conventions.

[0054] The decoding execution module is used to reproduce the intrinsic reference benchmark in its local coordinate system when the downstream device parses the intrinsic defect map file, and to perform pure integer arithmetic decoding, which is the inverse of the encoding generation module, on each deterministic position encoding to obtain the position of the bad pixel chip unit in the local coordinate system and perform the corresponding operation.

[0055] It should be noted that the downstream equipment refers to semiconductor manufacturing equipment that receives and executes the intrinsic defect map file. Specifically, it can be equipment such as sorting machines, die mounters, probe stations, or wafer dicing machines that require positioning operations on specific chip units on the wafer. After receiving the intrinsic defect map file generated by the step encoding generation module, these downstream devices must first reproduce the intrinsic reference benchmark of the current physical wafer before correctly converting the deterministic position codes in the file into physical coordinates in the device's local coordinate system.

[0056] In an optional embodiment, during the decoding execution module, when the downstream device parses the intrinsic defect map file, it reproduces the intrinsic reference datum in its local coordinate system as follows: The downstream device captures an image of the current physical wafer through its metering system, and identifies the geometric center of the outer contour of the wafer and the midpoint of the physical reference feature through an image processing algorithm. The geometric center is used as the local origin, and the direction from the geometric center to the midpoint of the physical reference feature is used as the local reference axis to complete the reproduction of the intrinsic reference reference.

[0057] It should be noted that the downstream equipment captures images of the current physical wafer through its metrology system, which is typically a high-resolution industrial camera or a charge-coupled device (CCD) optical imaging system. The captured images contain complete or partial outer contour information of the physical wafer currently placed on the equipment's workbench, as well as morphological information of the physical reference features. Image processing algorithms analyze these images to identify the set of edge points on the wafer's outer contour, and then determine the geometric center position of the wafer's outer contour using a circle fitting algorithm or geometric moment calculation method. Simultaneously, template matching or edge feature extraction algorithms can identify the morphology of the wafer's physical reference features and determine their midpoint position. These physical reference features are typically flat edges or notches on the wafer's edge, formed during the wafer manufacturing process, with fixed positions and a defined geometric relationship to the crystal orientation of the chip cell array.

[0058] It should be noted that using the geometric center as the local origin and the direction from the geometric center to the midpoint of the physical reference feature as the local reference axis constitutes the process of reproducing the intrinsic reference in the local device coordinate system of the downstream device. Since the determination of the local origin and local reference axis is entirely based on the geometric characteristics of the current physical wafer itself, and is independent of any coordinate system conventions preset in the downstream device's control software, a local reference frame that completely corresponds to the established intrinsic reference can be established regardless of the coordinate system definition method used by the downstream device. This characteristic ensures the consistency of cross-device data parsing.

[0059] In an optional embodiment, the decoding execution module performs pure integer arithmetic decoding, which is the inverse of the encoding generation module, on each deterministic position encoding to obtain the position of the defective chip unit in the local coordinate system and perform the corresponding operation, as follows: Call the same integer arithmetic library used by the encoding generation module to perform inverse operation on the integer tuple contained in the deterministic position code to obtain the local Cartesian coordinates of the bad pixel chip unit relative to the local origin and the local reference axis; The local Cartesian coordinates are output to the motion control system to drive the end effector to perform a skip action when it reaches the local Cartesian coordinates.

[0060] It should be noted that the pure integer arithmetic decoding performed on each deterministic position code, which is the inverse of the encoding generation module, refers to the downstream device calling its pre-built integer arithmetic library to perform decoding operations on the integer tuple contained in the deterministic position code. The algorithm logic of this decoding operation is the inverse process of the encoding algorithm logic used in the encoding generation module to generate the deterministic position code. Specifically, the decoding process first extracts the radial distance square value, coprime integer pairs, and quadrant sign value from the integer tuple. Then, based on the direction vector of the local reference axis and the azimuth angle relationship represented by the coprime integer pairs, the position vector of the defective chip unit relative to the local origin is calculated in reverse, and finally the local Cartesian coordinates of the defective chip unit in the local device coordinate system are obtained.

[0061] It should be noted that using the same integer arithmetic library as the encoding / generation module is a key technical measure to ensure bit-to-bit consistency in the calculation results during encoding and decoding. This integer arithmetic library predefines integer implementations for all geometric operations, including vector cross products, dot products, scaling, and truncation rules. Since the entire calculation process does not involve floating-point operations, computational differences between different devices and operating systems are completely eliminated. Even if downstream devices and upstream testing devices use different processor architectures or compilation environments, as long as the same integer arithmetic library is used for decoding, a precise one-to-one correspondence will be achieved between the obtained local coordinates and the original corrected coordinates on a predefined high-resolution integer grid.

[0062] It should be noted that outputting the local Cartesian coordinates to the motion control system to drive the end effector to perform a skip action means that the downstream equipment sets corresponding position coordinates in its motion control program based on the decoded defective chip cell location information. When the end effector traverses each chip cell on the wafer along a predetermined path, the motion control system will issue a skip command when it reaches the coordinate point, preventing the end effector from performing normal operations such as picking, dispensing, or testing on the chip cell at that location. Taking a sorting machine as an example, its end effector is a vacuum nozzle; the skip action means controlling the nozzle to move to that coordinate and not perform a picking action, thereby achieving automatic avoidance of defective chip cells. Taking a pick-and-place machine as an example, its end effector is a placement head; the skip action means controlling the placement head to move to that coordinate and not perform a placement action. In this way, the accurately identified and transmitted defective chip location information is ultimately transformed into physical operation commands for downstream production equipment, completing a complete closed loop from data generation to physical execution.

[0063] It should be noted that the execution of the decoding module relies entirely on the inherent defect map file generated by the encoding generation module, without requiring upstream testing equipment to transmit any coordinate system configuration information to downstream equipment. Downstream equipment only needs to autonomously identify the wafer's geometric features through the metrology system as described in this step to complete all positioning preparations. This design makes this method highly applicable and robust in complex multi-vendor supply chain environments, completely eliminating the risk of silent misalignment of defect locations caused by inconsistencies or misconfigurations in the coordinate systems of upstream and downstream equipment.

[0064] In summary, this invention effectively solves the problem of misaligned defect locations caused by inconsistent coordinate system conventions when wafer defect maps are transferred across multiple workstations and manufacturers in the prior art, thus meeting the extreme requirements of data accuracy and process traceability in the production of customized chips for ophthalmic surgery.

[0065] Furthermore, any content not described in detail in this specification is existing technology known to those skilled in the art.

[0066] In the embodiments provided by this invention, it should be understood that the disclosed system or method can be implemented in other ways. For example, the embodiments of the invention described above are merely illustrative; for instance, the division of modules is only a logical functional division, and there may be other division methods in actual implementation.

[0067] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0069] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the basic characteristics of the present invention.

[0070] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A large-scale dedicated production system for customized core chips used in ophthalmic surgical scenarios, characterized in that: include: The mesh construction module is used to obtain the original wafer defect map and wafer layout design file, and generate a theoretical position mesh based on the wafer layout design file. The original wafer defect map records the initial position information of the bad chip cells on the wafer. The fitting and correction module is used to extract the initial position information of chip cells with complete adjacent topology based on the original wafer defect map, fit it with the corresponding points in the theoretical position grid, and generate a correction transformation relationship. The coordinate correction module is used to correct the theoretical position of the defective chip unit by applying the correction transformation relationship to obtain the corrected coordinates in the global correction space. The reference establishment module is used to establish an intrinsic reference reference in the global correction space, with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis. The encoding generation module is used to perform pure integer arithmetic encoding on the corrected coordinates of each defective chip unit according to the intrinsic reference benchmark, generate deterministic position encoding, and generate an intrinsic defect map file based on all deterministic position encodings; The decoding execution module is used to reproduce the intrinsic reference benchmark in its local coordinate system when the downstream device parses the intrinsic defect map file, and to perform pure integer arithmetic decoding, which is the inverse of the encoding generation module, on each deterministic position encoding to obtain the position of the bad pixel chip unit in the local coordinate system and perform the corresponding operation.

2. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the mesh construction module, a theoretical location mesh is generated based on the wafer layout design file, as follows: Extract the standard width dimension, standard height dimension, and dicing slot width dimension between chip cells from the wafer layout design file; Using the wafer design center as the grid origin, the coordinates of the center points of all theoretically existing chip cells on the wafer are calculated based on the standard width dimension, the standard height dimension, and the dicing groove width dimension, thus forming the theoretical position grid.

3. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the fitting and correction module, the chip cell with a complete adjacent topology refers to a chip cell in which there are four adjacent recorded chip cells in the row and column directions among all the chip cells recorded in the original wafer defect map.

4. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 3, characterized in that: In the fitting and correction module, based on the original wafer defect map, the initial position information of chip cells with complete adjacent topologies is extracted and fitted with the corresponding points in the theoretical position grid to generate a correction transformation relationship, as follows: The original wafer defect map is traversed, and chip cells that have recorded chip cells in all four adjacent directions of increasing row direction, decreasing row direction, increasing column direction, and decreasing column direction are selected. Their initial position information is extracted as a reference point set. In the theoretical position grid, the theoretical coordinate points corresponding to the reference point set are determined to form the target point set. A two-dimensional rigid transformation matrix is ​​calculated by the point set registration algorithm to minimize the positional deviation between the reference point set and the target point set after transformation. The two-dimensional rigid transformation matrix is ​​the correction transformation relationship.

5. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the coordinate correction module, the theoretical position of the defective chip unit is corrected using the aforementioned correction transformation relationship to obtain the corrected coordinates in the global correction space, as follows: The theoretical coordinates corresponding to each defective chip unit are determined in the theoretical location grid; The theoretical coordinates are multiplied by the correction transformation relationship to obtain the corrected coordinates of the defective chip unit after systematic deviation correction. The corrected coordinates of all defective chip units constitute the coordinate set in the global correction space.

6. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the reference establishment module, within the global correction space, an intrinsic reference reference is established with the wafer physical geometry center as the origin and the direction pointing to the wafer physical reference feature as the reference axis, as follows: In the global correction space, the geometric center of the outer contour of the wafer is taken as the physical geometric center of the wafer; Using the direction vector pointing from the physical geometric center of the wafer to the midpoint of the physical reference feature of the wafer as the reference axis, an intrinsic reference reference independent of the origin and direction conventions of the external coordinate system is established.

7. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the encoding generation module, pure integer arithmetic encoding is performed on the corrected coordinates of each defective chip unit based on the intrinsic reference benchmark to generate a deterministic positional encoding, as follows: The sum of the squared values ​​of the abscissa and ordinate of the corrected coordinates is calculated as the squared value of the radial distance; Calculate the integer cross product and integer dot product between the position vector of the corrected coordinates and the direction vector of the reference axis, and determine a coprime integer pair and a quadrant sign value based on the integer cross product and integer dot product. The radial distance squared value, the coprime integer pair, and the quadrant sign value are combined into an integer tuple as the deterministic position code.

8. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 7, characterized in that: In the encoding generation module, an intrinsic defect map file is generated based on encoding all deterministic locations, as follows: The intrinsic defect map file is generated by using the deterministic location encoding set of all defective chip cells as the main data of the file and writing metadata containing at least wafer identifier, chip cell size parameters and chip cell spacing parameters in the file header.

9. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 1, characterized in that: In the decoding execution module, when the downstream device parses the intrinsic defect map file, it reproduces the intrinsic reference datum in its local coordinate system, as follows: The downstream device captures an image of the current physical wafer through its metering system, and identifies the geometric center of the outer contour of the wafer and the midpoint of the physical reference feature through an image processing algorithm. The geometric center is used as the local origin, and the direction from the geometric center to the midpoint of the physical reference feature is used as the local reference axis to complete the reproduction of the intrinsic reference reference.

10. The large-scale dedicated production system for customized core chips for ophthalmic surgical scenarios as described in claim 9, characterized in that: In the decoding execution module, the encoding of each deterministic position is performed using pure integer arithmetic decoding, which is the inverse of the encoding generation module, to obtain the position of the defective chip unit in the local coordinate system and perform the corresponding operation, as follows: Call the same integer arithmetic library used by the encoding generation module to perform inverse operation on the integer tuple contained in the deterministic position code to obtain the local Cartesian coordinates of the bad pixel chip unit relative to the local origin and the local reference axis; The local Cartesian coordinates are output to the motion control system to drive the end effector to perform a skip action when it reaches the local Cartesian coordinates.

Images