Shift register, control method thereof, gate driving circuit and display device

Abstract

The application relates to the technical field of display, and particularly provides a shift register and a control method thereof, a gate driving circuit and a display device, aiming to solve the problem of how to conveniently and effectively locate a fault point in a circuit. To this end, the shift register comprises a shift register unit and a detection unit coupled with a to-be-detected node in the shift register unit; wherein the detection unit is configured to control the light-emitting state thereof according to the potential of the to-be-detected node, and the light-emitting state of the detection unit when the to-be-detected node is in a fault state is different from the light-emitting state of the detection unit when the to-be-detected node is in a normal state. The scheme can reduce the influence on the shift register unit, avoid introducing a large number of outgoing wires, and is conducive to conveniently and efficiently detecting the fault state of the to-be-detected node.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically providing a shift register and its control method, a gate driving circuit, and a display device. Background Technology

[0002] GOA (Gate Driver on Array) technology is widely used in screen development. This technology not only simplifies the driver integrated circuit (IC) but also enables narrow bezel designs. However, the complex circuit structure of the GOA can negatively impact the overall yield of the panel. Therefore, accurately locating the fault point in the GOA is a prerequisite for discovering and repairing such defects. Traditional location methods rely on numerous terminal traces, which are complex and impractical, or on the overall screen illumination status to aid in judgment. However, these methods are easily affected by interference from the overall screen circuitry, reducing the accuracy of fault location. Summary of the Invention

[0003] This application aims to solve the aforementioned technical problem, namely, how to conveniently and effectively locate fault points in GOA circuits.

[0004] In a first aspect, this application provides a shift register, which includes a shift register unit and a detection unit coupled to a node to be detected in the shift register unit;

[0005] The detection unit is configured to control the light emission state of the node to be detected according to the potential of the node to be detected. The light emission state of the detection unit when the node to be detected is in a fault state is different from the light emission state when the node to be detected is in a normal state.

[0006] In some embodiments, the detection unit includes at least one of a first light-emitting circuit, a second light-emitting circuit, and a third light-emitting circuit;

[0007] The first light-emitting circuit is coupled to the first control node of the shift register unit, and the first light-emitting circuit is configured to control its light-emitting state according to the potential of the first control node.

[0008] The second light-emitting circuit is coupled to the output terminal of the shift register unit, and the second light-emitting circuit is configured to control its light-emitting state according to the potential of the output terminal;

[0009] The third light-emitting circuit is coupled to the second control node of the shift register unit, and the third light-emitting circuit is configured to control its light-emitting state according to the potential of the second control node;

[0010] The first control node is used to control the transmission of the clock signal to the output of the shift register unit; the second control node is used to control the transmission of the reference signal to the output of the shift register unit and / or the first control node.

[0011] In some embodiments, the first light-emitting circuit is configured to control its light-emitting state according to the potential of the first control node, including:

[0012] When the first control node is in a normal state, the first light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the first control node.

[0013] Alternatively, the first light-emitting circuit is configured to emit light continuously during the triggering period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, based on the potential of the first control node.

[0014] In some embodiments, the second light-emitting circuit is configured to control its light-emitting state according to the potential of the output terminal, including:

[0015] When the output terminal is in a normal state, the second light-emitting circuit is configured to emit light during the output period of the shift register unit according to the potential of the output terminal;

[0016] Alternatively, the second light-emitting circuit is configured to emit light continuously during the output period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, based on the potential of the output terminal.

[0017] In some embodiments, when the first light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the first control node; and / or, when the second light-emitting circuit is configured to emit light during the output period of the shift register unit according to the potential of the output terminal,

[0018] At least one of the first light-emitting circuit and the second light-emitting circuit includes a first transistor and a first light-emitting device. The first electrode of the first transistor is coupled to a first power supply terminal, the second electrode of the first transistor is coupled to the anode of the first light-emitting device, the cathode of the first light-emitting device is coupled to a second power supply terminal, and the control electrode of the first transistor is coupled to the node to be detected corresponding to its light-emitting circuit.

[0019] In some embodiments, when the first light-emitting circuit is configured to continuously emit light according to the potential of the first control node, from the triggering period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, and / or the second light-emitting circuit is configured to continuously emit light according to the potential of the output terminal, from the output period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, the light-emitting circuits in the first and second light-emitting circuits that continuously emit light before the full-screen reset signal corresponding to the next frame is at an effective potential include:

[0020] The system comprises a first transistor, a first light-emitting device, a second transistor, a third transistor, and a storage capacitor. The first terminal of the first transistor is coupled to a first power supply terminal, the second terminal of the first transistor is coupled to the anode of the first light-emitting device, and the cathode of the first light-emitting device is coupled to a second power supply terminal. The first terminal and the control terminal of the second transistor are both coupled to the node to be detected in its current light-emitting circuit. The second terminal of the second transistor is coupled to the first terminal of the third transistor. The second terminal of the third transistor is coupled to a first level signal terminal, and the control terminal of the third transistor is coupled to a full-screen reset signal terminal. One terminal of the storage capacitor is coupled to the first level signal terminal, and the other terminal of the storage capacitor is coupled to the control terminal of the first transistor and the second terminal of the second transistor, respectively.

[0021] In some embodiments, the third light-emitting circuit is configured to control its light-emitting state according to the potential of the second control node, including:

[0022] When the second control node is in a normal state, the third light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the second control node.

[0023] In some embodiments, the third light-emitting circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second light-emitting device;

[0024] The control electrode and the second electrode of the fourth transistor are both coupled to the third power supply terminal. The first electrode of the fifth transistor is coupled to the second level signal terminal. The control electrode of the fifth transistor is coupled to the second control node. The first electrode of the fourth transistor and the second electrode of the fifth transistor are both coupled to the control electrode of the sixth transistor. The first electrode of the sixth transistor is coupled to the anode of the second light-emitting device. The cathode of the second light-emitting device is coupled to the second power supply terminal. The second electrode of the sixth transistor is coupled to the third power supply terminal.

[0025] In some embodiments, the shift register unit includes:

[0026] A reset circuit is coupled to a full-screen reset signal terminal, a horizontal reset signal terminal, a first-level signal terminal, a second-level signal terminal, and a first control node, respectively. It is used to provide the signal of the first-level signal terminal to the first control node in response to the full-screen reset signal of the full-screen reset signal terminal, and to provide the signal of the second-level signal terminal to the first control node in response to the horizontal reset signal of the horizontal reset signal terminal.

[0027] The trigger circuit is coupled to the trigger signal terminal, the fourth power supply terminal and the first control node respectively, and is used to provide the signal of the fourth power supply terminal to the first control node in response to the trigger signal of the trigger signal terminal.

[0028] The internal logic circuit is coupled to the first control node, the second control node, the third power supply terminal, the first level signal terminal and the second level signal terminal respectively, and is used to provide the potential of the third power supply terminal to the second control node, or, in response to the potential of the first control node, provide the signal of the second level signal terminal to the second control node.

[0029] The output circuit includes a cascaded output sub-circuit and at least one horizontal output sub-circuit. Both the cascaded output sub-circuit and the horizontal output sub-circuit are coupled to a first control node and a second control node. The cascaded output sub-circuit is also coupled to a cascaded clock signal terminal and a second level signal terminal. The horizontal output sub-circuit is also coupled to a horizontal clock signal terminal and a third level signal terminal. The cascaded output sub-circuit is configured to provide a cascaded clock signal from the cascaded clock signal terminal to its own output terminal in response to the potential of the first control node, and to provide a potential from the second level signal terminal to its own output terminal in response to the potential of the second control node. The horizontal output sub-circuit is configured to provide a horizontal clock signal from the horizontal clock signal terminal to its own output terminal in response to the potential of the first control node, and to provide a potential from the third level signal terminal to its own output terminal in response to the potential of the second control node.

[0030] In some embodiments, the shift register further includes:

[0031] The leakage protection circuit is coupled to the fourth power supply terminal and the first control node respectively, and is coupled to the trigger circuit and the pull-down circuit respectively through the third control node. It is used to provide the potential of the fourth power supply terminal to the third control node in response to the potential of the first control node.

[0032] The pull-down circuit is coupled to the first control node, the second control node, and the second level signal terminal respectively, and is used to provide the signal of the second level signal terminal to the first control node in response to the potential of the second control node.

[0033] In some embodiments, the shift register unit includes at least one row output sub-circuit, and the shift register further includes at least one repair circuit;

[0034] The repair circuit and the line output sub-circuit are both coupled to the first control node, the second control node and the third level signal terminal. The repair circuit is also coupled to the repair clock signal terminal, and the line output sub-circuit is also coupled to the line clock signal terminal and the line output terminal.

[0035] The horizontal output sub-circuit is configured to transmit the horizontal clock signal provided by the horizontal clock signal terminal to the corresponding horizontal output terminal in response to the potential of the first control node, or to provide the signal of the third level signal terminal to the corresponding horizontal output terminal in response to the potential of the second control node.

[0036] The repair circuit is configured to replace the horizontal output sub-circuit when the horizontal output terminal corresponding to the horizontal output sub-circuit is in a fault state, and in response to the potential of the first control node, transmit the repair clock signal provided by the repair clock signal terminal to the horizontal output terminal, or, in response to the potential of the second control node, provide the signal of the third level signal terminal to the corresponding horizontal output terminal.

[0037] In a second aspect, this application provides a gate driving circuit that includes a plurality of cascaded shift registers, at least one of which is a shift register as described in any of the preceding claims.

[0038] In some embodiments, each of the plurality of shift registers includes a trigger signal terminal, a row reset signal terminal, and a cascaded output terminal, and the preceding shift register, the target shift register, the following shift register, the first alternative shift register, and the second alternative shift register are shift registers among the plurality of shift registers;

[0039] The trigger signal terminal of the target shift register is coupled to the cascade output terminal of the preceding shift register, and the row reset signal terminal of the target shift register is coupled to the cascade output terminal of the following shift register.

[0040] When the cascaded output of the preceding shift register is in a fault state, the target shift register is configured to disconnect its trigger signal from the cascaded output of the preceding shift register and couple it to the cascaded output of the first alternative shift register.

[0041] When the cascaded output of the subsequent shift register is in a fault state, the target shift register is configured to disconnect its row reset signal from the cascaded output of the subsequent shift register and couple it to the cascaded output of the second alternative shift register.

[0042] The cascaded outputs of both the first and second alternative shift registers are in normal condition.

[0043] In a third aspect, this application provides a display device that includes the gate driving circuit described in any of the preceding claims.

[0044] In a fourth aspect, this application provides a shift register control method, wherein the shift register includes a shift register unit and a detection unit coupled to a node to be detected in the shift register unit; the method includes:

[0045] The detection unit controls the light emission state of the node under test according to the potential of the node under test. The light emission state of the detection unit when the node under test is in a fault state is different from the light emission state when the node under test is in a normal state.

[0046] In some embodiments, the shift register unit includes at least one row output sub-circuit, and the shift register further includes at least one repair circuit; the repair circuit and the row output sub-circuit are both coupled to a first control node, a second control node, and a third level signal terminal; the repair circuit is also coupled to a repair clock signal terminal; the row output sub-circuit is also coupled to a row clock signal terminal and a row output terminal; the method further includes:

[0047] The horizontal output sub-circuit responds to the potential of the first control node by transmitting the horizontal clock signal provided by the horizontal clock signal terminal to the corresponding horizontal output terminal, or responds to the potential of the second control node by providing the signal of the third level signal terminal to the corresponding horizontal output terminal.

[0048] When the horizontal output terminal corresponding to the horizontal output sub-circuit is in a fault state, the repair circuit replaces the horizontal output sub-circuit and, in response to the potential of the first control node, transmits the repair clock signal provided by the repair clock signal terminal to the horizontal output terminal, or, in response to the potential of the second control node, provides the signal of the third level signal terminal to the corresponding horizontal output terminal.

[0049] With the above technical solution adopted, the shift register provided in this application includes a shift register unit and a detection unit coupled to the node to be detected in the shift register unit; wherein, the detection unit is configured to control its light emission state according to the potential of the node to be detected, and the light emission state of the detection unit when the node to be detected is in a fault state is different from the light emission state when the node to be detected is in a normal state. This solution can reduce the impact on the shift register unit, avoid introducing a large number of lead-out traces, and facilitate convenient and efficient detection of the fault state of the node to be detected. Attached Figure Description

[0050] The preferred embodiments of this application are described below with reference to the accompanying drawings, in which:

[0051] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0052] Figure 2 This is a circuit diagram of a shift register unit provided in a specific example of this application;

[0053] Figure 3 This is a schematic diagram of a shift register provided in an embodiment of this application, which includes a first light-emitting circuit and a second light-emitting circuit;

[0054] Figure 4 yes Figure 3 The timing diagram of the shift register in normal state is shown.

[0055] Figure 5 This is a schematic diagram of a shift register with a 3T1C1D first light-emitting circuit provided in an embodiment of this application;

[0056] Figure 6 yes Figure 5 The timing diagram of the shift register is shown.

[0057] Figure 7 This is a schematic diagram of a shift register provided in an embodiment of this application, which includes a first light-emitting circuit and a third light-emitting circuit of 3T1C1D.

[0058] Figure 8 yes Figure 7 The timing diagram of the shift register is shown.

[0059] Figure 9 This is a schematic diagram of a shift register with a repair circuit provided in an embodiment of this application;

[0060] Figure 10 This is a schematic diagram of the shift register in the repair state provided in an embodiment of this application;

[0061] Figure 11 This is a schematic diagram of the gate drive control circuit provided in a specific example of this application;

[0062] Figure 12 yes Figure 11 The timing diagram of the gate drive control circuit in normal state is shown.

[0063] Figure 13 This is a schematic diagram of the gate drive control circuit after fault repair provided in a specific example of this application;

[0064] Figure 14 yes Figure 13 The timing diagram of the gate drive control circuit is shown. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0066] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "coupled," "connected," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0067] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this application, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. In addition, according to the characteristics of transistors, they can be divided into N-type and P-type. The following embodiments are based on N-type transistors. When an N-type transistor is used, the first terminal is the source of the N-type transistor, the second terminal is the drain of the N-type transistor, and when the gate input is high, the source and drain are turned on. The high level is the effective potential, and the signal potential is effective when it is high and ineffective when it is low. The P-type transistor is the opposite. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the protection scope of the embodiments of this application.

[0068] In this application, the signal potentials provided by the first level signal terminal VGL2, the second level signal terminal VGL3, the third level signal terminal VGL1, the reference signal, and the second power supply terminal ELVSS are all low, while the signal potentials provided by the first power supply terminal ELVDD, the third power supply terminal GVDD2, and the fourth power supply terminal GVDD1 are all high. The signal potentials provided by the first level signal terminal VGL2, the second level signal terminal VGL3, the third level signal terminal VGL1, the reference signal, and the second power supply terminal ELVSS can be the same or different; similarly, the signal potentials provided by the first power supply terminal ELVDD, the third power supply terminal GVDD2, and the fourth power supply terminal GVDD1 can be the same or different. For example, the signal potential of the third power supply terminal GVDD2 can be set to be equal to or less than the signal potential of the fourth power supply terminal GVDD1. The specific settings can be configured according to actual needs, and this application does not impose any limitations on this.

[0069] This application provides a shift register, including a shift register unit and a detection unit coupled to a node to be detected in the shift register unit. The detection unit is configured to control the illumination state of the node to be detected based on its potential. The illumination state of the detection unit differs when the node to be detected is in a fault state from its illumination state when the node is in a normal state. This provides a visualized detection unit, enabling convenient and efficient fault state detection of the node to be detected by determining whether the current illumination state of the detection unit differs from its normal illumination state.

[0070] Figure 1 This is a schematic diagram of a shift register structure provided in an embodiment of this application, wherein the shift register unit may include:

[0071] The reset circuit 11 is used to reset the first control node Q in response to a reset signal.

[0072] Trigger circuit 12 is used to provide an effective potential to the first control node Q in response to the trigger signal at the trigger signal terminal.

[0073] The internal logic circuit 13 is coupled to the first control node Q and the second control node QB respectively, and is used to selectively provide an effective potential or an ineffective potential to the second control node QB according to the potential of the first control node Q.

[0074] Output circuit 14 is coupled to the first control node Q and the second control node QB, respectively, and clock signal terminal ( Figure 1 (not shown in the image) and reference signal terminal ( Figure 1(Not shown) is coupled to provide a clock signal from the clock signal terminal to the output terminal in response to the potential of the first control node Q, or to provide a reference signal from the reference signal terminal to the output terminal and / or the first control node Q in response to the potential of the second control node QB.

[0075] The first control node Q is used to control the transmission of the clock signal to the output of the shift register unit; the second control node QB is used to control the transmission of the reference signal to the output of the shift register unit and / or the first control node Q, so that the output of the shift register unit is in a non-gated potential state.

[0076] The non-gated potential state refers to a potential state in which the data write transistor coupled to the output terminal of the shift register unit is turned off. When the reference signal is low, the non-gated potential state is also low. When the clock signal is an active potential and the first control node Q controls the clock signal to be transmitted to the output terminal of the shift register unit, the output terminal of the shift register unit is in the gated potential state.

[0077] In some embodiments, the node to be detected may include at least one of a first control node Q, an output terminal, and a second control node QB. Correspondingly, the detection unit may include at least one of a first light-emitting circuit 15, a second light-emitting circuit 16, and a third light-emitting circuit 17. Figure 1 The example shows a case where the detection unit simultaneously includes a first light-emitting circuit 15, a second light-emitting circuit 16, and a third light-emitting circuit 17.

[0078] The first light-emitting circuit 15 is coupled to the first control node Q of the shift register unit, and is configured to control its light-emitting state according to the potential of the first control node Q. The second light-emitting circuit 16 is coupled to the output terminal of the shift register unit, and is configured to control its light-emitting state according to the potential of the output terminal. The third light-emitting circuit 17 is coupled to the second control node QB of the shift register unit, and is configured to control its light-emitting state according to the potential of the second control node QB. Therefore, fault detection of the first control node Q, the output terminal, and the second control node QB in the shift register unit can be achieved using the first light-emitting circuit 15, the second light-emitting circuit 16, and the third light-emitting circuit 17.

[0079] In some embodiments, when the first control node Q is in a normal state, the first light-emitting circuit 15 is configured to emit light during the triggering period of the shift register unit according to the potential of the first control node Q. When the first light-emitting circuit 15 does not emit light or flashes during the triggering period, it can be determined that the first control node Q is in a fault state, so as to further determine whether the related circuits affecting the first control node Q are faulty.

[0080] The triggering period is the time when the first control node Q is at an effective potential under normal conditions.

[0081] When the output is in a normal state, the second light-emitting circuit 16 is configured to emit light during the output period of the shift register unit according to the output potential. The output period can be the overlapping period of the effective potential period of the first control node Q and the effective potential period of the clock signal during the normal state. During this period, the output of the shift register unit can output a gate control signal.

[0082] When the second control node QB is in a normal state, the third light-emitting circuit 17 is configured to emit light during the triggering period of the shift register unit according to the potential of the second control node QB.

[0083] In normal conditions, the second control node QB is at a low level during the trigger period and returns to a high level after exiting the trigger period. When the light emission state of the third light-emitting circuit 17 is inconsistent with the above normal state, it can be located that the circuit or signal related to the second control node QB may be abnormal. For example, if the third light-emitting circuit 17 is still emitting light after exiting the trigger period and has not switched the light emission state, the reset signal may be abnormal, resulting in the inability to effectively pull down the potential of the second control node QB.

[0084] It should be noted that in other embodiments, the shift register unit may be configured in other ways as needed. See also: [link to relevant documentation] Figure 2 As shown, Figure 2 This is a circuit diagram of a shift register unit provided in a specific example of this application.

[0085] The reset circuit 11 is coupled to the full-screen reset signal terminal TRS, the horizontal reset signal terminal STD, the first level signal terminal VGL2, the second level signal terminal VGL3, and the first control node Q, respectively. It is used to provide the signal of the first level signal terminal VGL2 to the first control node Q in response to the full-screen reset signal of the full-screen reset signal terminal TRS, and to provide the signal of the second level signal terminal VGL3 to the first control node Q in response to the horizontal reset signal of the horizontal reset signal terminal STD.

[0086] The trigger circuit 12 is coupled to the trigger signal terminal STU, the fourth power supply terminal GVDD1 and the first control node Q respectively, and is used to provide the signal of the fourth power supply terminal GVDD1 to the first control node Q in response to the trigger signal of the trigger signal terminal STU.

[0087] The internal logic circuit 13 is coupled to the first control node Q, the second control node QB, the third power supply terminal GVDD2, the first level signal terminal VGL2, and the second level signal terminal VGL3, respectively, and is used to provide the potential of the third power supply terminal GVDD2 to the second control node QB, or, in response to the potential of the first control node Q, provide the signal of the second level signal terminal VGL3 to the second control node QB.

[0088] The output circuit 14 includes a cascaded output sub-circuit 141 and at least one horizontal output sub-circuit 142. Both the cascaded output sub-circuit 141 and the horizontal output sub-circuit 142 are coupled to a first control node Q and a second control node QB. The cascaded output sub-circuit 141 is also coupled to a cascaded clock signal terminal CLKD1 and a second level signal terminal VGL3. The horizontal output sub-circuit 142 is also coupled to a horizontal clock signal terminal VGLi (i is a positive integer greater than or equal to 1) and a third level signal terminal VGL1. The cascaded output sub-circuit 141 is used to provide the cascaded clock signal of the cascaded clock signal terminal CLKD1 to its own output terminal in response to the potential of the first control node Q, and to provide the potential of the second level signal terminal VGL3 to its own output terminal in response to the potential of the second control node QB. The horizontal output sub-circuit 142 is used to provide the horizontal clock signal of the horizontal clock signal terminal to its own output terminal in response to the potential of the first control node Q, and to provide the potential of the third level signal terminal to its own output terminal in response to the potential of the second control node QB.

[0089] The reference signal corresponding to the cascaded output sub-circuit 141 can be provided by the second level signal terminal VGL3. Accordingly, the second level signal terminal VGL3 is used as the reference signal terminal of the cascaded output sub-circuit 141.

[0090] The clock signal corresponding to the horizontal output sub-circuit 142 is the horizontal clock signal. The reference signal corresponding to the horizontal output sub-circuit 142 can be provided by the third level signal terminal VGL1. Accordingly, the third level signal terminal VGL1 is used as the reference signal terminal of the horizontal output sub-circuit 142.

[0091] In some embodiments, such as Figure 2 As shown, the shift register unit may also include an auxiliary trigger circuit 18, a leakage protection circuit 19, and a pull-down circuit 20.

[0092] The auxiliary trigger circuit 18 is coupled to the trigger signal terminal STU, the second level signal terminal VGL3 and the second control node QB respectively, and is used to provide the signal of the second level signal terminal VGL3 to the second control node QB in response to the trigger signal of the trigger signal terminal STU.

[0093] The leakage protection circuit 19 is coupled to the fourth power supply terminal GVDD1 and the first control node Q, respectively, and is coupled to the trigger circuit 11 and the pull-down circuit 20 through the third control node N. It is used to provide the potential of the fourth power supply terminal GVDD1 to the third control node N in response to the potential of the first control node Q, thereby preventing leakage and ensuring the stability of the potential of the first control node Q.

[0094] The pull-down circuit 20 is coupled to the first control node Q, the second control node QB, and the second level signal terminal VGL3, respectively, and is used to provide the signal of the second level signal terminal VGL3 to the first control node Q in response to the potential of the second control node QB.

[0095] In the following description, it will be based on Figure 2 Taking implementation as an example, the shift register provided in the embodiments of this application is described.

[0096] like Figure 2 As shown, the reset circuit 11 may include transistors M17, M18, M23, and M24. The control terminals of transistors M17 and M18 are both coupled to the full-screen reset signal terminal TRS. The first terminal of transistor M17 is coupled to the second terminal of transistor M18, and the second terminal of transistor M17 is coupled to the first control node Q. The first terminal of transistor M18 is coupled to the first level signal terminal VGL2. The control terminals of transistors M23 and M24 are both coupled to the horizontal reset signal terminal STD. The first terminal of transistor M23 is coupled to the second terminal of transistor M24, and the second terminal of transistor M23 is coupled to the first control node Q. The first terminal of transistor M24 is coupled to the second level signal terminal VGL3.

[0097] like Figure 2 As shown, the trigger circuit 12 may include transistors M21, M22, M25, and M26. The control terminals of transistors M21 and M22 are both coupled to the trigger signal terminal STU. The first terminal of transistor M21 and the second terminal of transistor M22 are coupled. The first terminal of transistor M22 is coupled to the first control node Q. The second terminals of transistors M21, M25, and M26, as well as the second terminal of transistor M25, are all coupled to the fourth power supply terminal GVDD1. The first terminal of transistor M25 is coupled to the second terminal of transistor M26, and the first terminal of transistor M26 is coupled to the first terminal of transistor M21.

[0098] The auxiliary trigger circuit 18 includes a transistor M51. The control terminal of the transistor M51 is coupled to the trigger signal terminal STU, the first terminal of the transistor M51 is coupled to the second level signal terminal VGL3, and the second terminal of the transistor M51 is coupled to the second control node QB.

[0099] The internal logic circuit 13 includes transistors M31 to M35. The control electrode of transistor M31, the second electrode of transistor M31, the control electrode of transistor M32, and the second electrode of transistor M34 are all coupled to the third power supply terminal GVDD2. The first electrode of transistor M31 is coupled to the second electrode of transistor M32. The first electrode of transistor M32 is coupled to the control electrode of transistor M34 and the second electrode of transistor M33, respectively. The first electrode of transistor M34 and the second electrode of transistor M35 are both coupled to the second control node QB. The control electrodes of transistors M33 and M35 are both coupled to the first control node Q. The first electrode of transistor M33 is coupled to the first level signal terminal VGL2, and the first electrode of transistor M35 is coupled to the second level signal terminal VGL3.

[0100] like Figure 2 As shown, the cascaded output sub-circuit 141 in the output circuit 14 includes transistors M61 and M62 and a storage capacitor CC. The control electrode of transistor M61 is coupled to the first control node Q, the second electrode of transistor M61 is used to receive the cascaded clock signal, and the first electrode of transistor M61 is coupled to the cascaded output terminal CR. The control electrode of transistor M62 is coupled to the second control node QB, the second electrode of transistor M62 is coupled to the cascaded output terminal CR, the first electrode of transistor M62 is coupled to the second level signal terminal VGL3, and the storage capacitor CC is connected between the control electrode and the first electrode of transistor M61.

[0101] like Figure 2 As shown, multiple horizontal output sub-circuits 142 can be configured in the output circuit 14. Figure 2 The example shows four horizontal output sub-circuits, each corresponding to a horizontal clock signal terminal. These four horizontal output sub-circuits are arranged one-to-one with the horizontal clock signal terminals CLK1 to CLK4 and the horizontal output terminals OUT1 to OUT4, respectively. They can be referred to as the first horizontal output sub-circuit, the second horizontal output sub-circuit, the third horizontal output sub-circuit, and the fourth horizontal output sub-circuit.

[0102] The first line output sub-circuit may include transistor M71, transistor M72 and storage capacitor C1. The control electrode of transistor M71 is coupled to the first control node Q, the second electrode of transistor M71 is coupled to the line clock signal terminal CLK1, the first electrode of transistor M71 is coupled to the line output terminal OUT1, the control electrode of transistor M72 is coupled to the second control node QB, the second electrode of transistor M72 is coupled to the line output terminal OUT1, the first electrode of transistor M72 is coupled to the third level signal terminal VGL1, and the storage capacitor C1 is connected between the control electrode and the first electrode of transistor M71.

[0103] The second row output sub-circuit includes transistors M73 and M74 and storage capacitor C2; the third row output sub-circuit includes transistors M75 and M76 and storage capacitor C3; and the fourth row output sub-circuit includes transistors M77 and M78 and storage capacitor C4. Except for the received row clock signal and the corresponding row output terminal, the second to fourth row output sub-circuits can be configured in the same way as the first row output sub-circuit. Specifically, the second row output sub-circuit is coupled to the row clock signal terminal CLK2 and the row output terminal OUT2; the third row output sub-circuit is coupled to the row clock signal terminal CLK3 and the row output terminal OUT3; and the fourth row output sub-circuit is coupled to the row clock signal terminal CLK4 and the row output terminal OUT4.

[0104] The leakage protection circuit 19 includes transistors M27 and M28. The control terminals of transistors M27 and M28 are both coupled to the first control node Q. The second terminal of transistor M27 is coupled to the fourth power supply terminal GVDD1. The first terminal of transistor M27 is coupled to the second terminal of transistor M28. The first terminal of transistor M28 is coupled to the first terminal of transistor M23 and the pull-down circuit 20 through the third control node N.

[0105] The pull-down circuit 20 includes transistors M41 and M42. The first terminal of transistor M41 and the second terminal of transistor M42 are both coupled to the third control node N. The second terminal of transistor M41 is coupled to the first control node Q. The control terminals of transistors M41 and M42 are both coupled to the second control node QB. The first terminal of transistor M42 is coupled to the second level signal terminal VGL3.

[0106] Figure 3 This is a schematic diagram of a shift register provided in an embodiment of this application, which includes a first light-emitting circuit and a second light-emitting circuit.

[0107] In this embodiment of the application, the first light-emitting circuit 15 and / or the second light-emitting circuit 16 may include a first transistor and a first light-emitting device. The first electrode of the first transistor is coupled to the first power supply terminal ELVDD, the second electrode of the first transistor is coupled to the anode of the first light-emitting device, the cathode of the first light-emitting device is coupled to the second power supply terminal ELVSS, and the control electrode of the first transistor is coupled to the node to be detected corresponding to its light-emitting circuit.

[0108] like Figure 3As shown, the first transistor of the first light-emitting circuit 15 is specifically transistor M1, and the first light-emitting device of the first light-emitting circuit 15 is specifically light-emitting device D1. The first electrode of transistor M1 is coupled to the first power supply terminal ELVDD, the second electrode of transistor M1 is coupled to the anode of light-emitting device D1, the cathode of light-emitting device D1 is coupled to the second power supply terminal ELVSS, and the control electrode of transistor M1 is coupled to the detection node corresponding to its light-emitting circuit, i.e., the first control node Q.

[0109] like Figure 3 As shown, multiple second light-emitting circuits 16 can be provided, and each second light-emitting circuit 16 is configured in a one-to-one correspondence with a horizontal output sub-circuit. Figure 3 The example shows a case where each of the four row output sub-circuits is equipped with a second light-emitting circuit 16. The second light-emitting circuit 16 corresponding to the four row output sub-circuits can be set in the same way.

[0110] In this circuit, the first transistor of the second light-emitting circuit 16 can be one of transistors M2 to M5, and the first light-emitting device of the second light-emitting circuit 16 can be one of light-emitting devices D2 to D5. The second light-emitting circuit 16 corresponding to the first row output sub-circuit can include transistor M2 and light-emitting device D2, with the control electrode of transistor M2 coupled to the row output terminal OUT1. The second light-emitting circuit 16 corresponding to the second row output sub-circuit can include transistor M3 and light-emitting device D3, with the control electrode of transistor M3 coupled to the row output terminal OUT2. The second light-emitting circuit 16 corresponding to the third row output sub-circuit can include transistor M4 and light-emitting device D4, with the control electrode of transistor M4 coupled to the row output terminal OUT3. The second light-emitting circuit 16 corresponding to the fourth row output sub-circuit can include transistor M5 and light-emitting device D5, with the control electrode of transistor M5 coupled to the row output terminal OUT4.

[0111] The first terminals of transistors M2 to M5 are all coupled to the first power supply terminal ELVDD, and the second terminals of transistors M2 to M5 are all coupled to the anode of their respective light-emitting devices, and are coupled to the second power supply terminal ELVSS through the light-emitting devices.

[0112] It should be noted that in other embodiments, the second light-emitting circuit 16 can also be configured correspondingly to the cascaded input sub-circuit to detect whether the cascaded output terminal CR is faulty, and the second light-emitting circuit 16 used to detect the cascaded output terminal CR can be configured in the same way as the second light-emitting circuit 16 used to detect the horizontal output terminal.

[0113] Figure 4 yes Figure 3 The timing diagram of the shift register in normal state is shown.

[0114] like Figure 4As shown, during the full-screen reset period, the signal provided by the full-screen reset signal terminal TRS is at a high level, and both transistors M17 and M18 are turned on. The low level of the first level signal terminal VGL2 is written to the first control node Q to reset the first control node Q. Correspondingly, transistor M1 in the first light-emitting circuit 15 is turned off, and the light-emitting device D1 does not emit light. The transistors in the four horizontal output sub-circuits are also turned off, and the horizontal output terminals are all at a low level. Therefore, transistors M2 to M5 are turned off, and the light-emitting devices D2 to D5 also do not emit light.

[0115] During the trigger-on period, the signal provided by the trigger signal terminal STU is at a high level, and transistors M21, M22, M25, and M26 are all turned on, writing the high level provided by the fourth power supply terminal GVDD1 into the first control node Q. From the start of the trigger-on period to the start of the trigger-off period, corresponding to the trigger period, the first control node Q is at a high potential, and the corresponding light-emitting device D1 emits light during the trigger period. The emitting state of the light-emitting device D1 corresponds to the trigger period of the first control node Q.

[0116] During the triggering period of the shift register unit, the first control node Q remains at a high potential. When the cascade clock signal is high, the cascade output terminal CR of the corresponding cascade output sub-circuit outputs a high level as a transmission signal. When the row clock signal is high, the row output terminal corresponding to the row clock signal outputs a high level, and the light-emitting device in the light-emitting circuit coupled to the corresponding row output terminal emits light. Figure 4 As shown, when the signal provided by the horizontal clock signal terminal CLK1 is high, the horizontal output terminal OUT1 outputs a high level, and the LED D2 illuminates. Similarly, when the signal provided by the horizontal clock signal terminal CLK4 is high, the horizontal output terminal OUT4 outputs a high level, and the LED D5 illuminates. The illumination state of the LED corresponding to each horizontal output sub-circuit corresponds to the overlapping period of the trigger period and the effective level period of the horizontal clock signal. The overlapping period is the output period corresponding to the corresponding horizontal output sub-circuit in the shift register unit.

[0117] During the trigger shutdown period, the signal provided by the horizontal reset signal terminal STD is at a high level, transistors M23 and M24 are turned on, and the signal provided by the second level signal terminal VGL3 is written to the first control node Q. The first control node Q is pulled low, and correspondingly, the light-emitting device D1 switches from the light-emitting state to the non-light-emitting state.

[0118] In some embodiments, such as Figure 4As shown, the clock period of the cascaded clock signal can be 16H, with the effective potential accounting for one-quarter of the clock period. The effective potential of the row clock signal is 1H, and the illumination duration of the second light-emitting circuit 16 is only 1H. To avoid the light-emitting device having a short illumination time, making it difficult to accurately determine the illumination status and affecting fault location and identification, the first light-emitting circuit 15 can also be configured to continuously emit light according to the potential of the first control node Q, from the triggering period of the shift register unit until the corresponding full-screen reset signal of the next frame is at an effective potential; and / or, the second light-emitting circuit 16 can be configured to continuously emit light according to the potential of the output terminal, from the output period of the shift register unit until the corresponding full-screen reset signal of the next frame is at an effective potential, so as to increase the illumination duration of the corresponding light-emitting circuit in normal state and facilitate observation.

[0119] Specifically, for the full-screen reset signal, a frame period is formed between the start times of two adjacent effective potentials.

[0120] Among them, Figure 3 Based on the circuit shown, the first light-emitting circuit 15 and / or the second light-emitting circuit 16 can also be configured to include a first transistor, a first light-emitting device, a second transistor, a third transistor, and a storage capacitor, so as to increase the light-emitting duration of the light-emitting device in the corresponding light-emitting circuit under normal conditions.

[0121] Taking the addition of a second transistor, a third transistor, and a storage capacitor to the first light-emitting circuit 15 as an example, see [link to example]. Figure 5 As shown, Figure 5 This is a schematic diagram of a shift register with a 3T1C1D first light-emitting circuit 15' provided in an embodiment of this application.

[0122] The 3T1C1D circuit comprises three transistors, one storage capacitor, and one light-emitting device. The three transistors are a first transistor, a second transistor, and a third transistor. The first terminal and control terminal of the second transistor are coupled to the detection node (first control node Q) of the first light-emitting circuit 15'. The second terminal of the second transistor is coupled to the first terminal of the third transistor. The second terminal of the third transistor is coupled to the first level signal VGL2, and the control terminal of the third transistor is coupled to the full-screen reset signal terminal. The one capacitor is the storage capacitor C25. One terminal of the storage capacitor is coupled to the first level signal terminal VGL2, and the other terminal is coupled to the control terminal of the first transistor and the second terminal of the second transistor. The one light-emitting device is the light-emitting device D1. Specifically, the first transistor in the first light-emitting circuit 15' is transistor M1, the second transistor is transistor M6, and the third transistor is transistor M7.

[0123] Figure 6 yes Figure 5 The timing diagram of the shift register shown is available in [reference]. Figure 6As shown, from the start of the trigger-on period to the start of the trigger-off period, the first control node Q is at a high potential during the corresponding trigger period, and the corresponding light-emitting device D1 emits light during the trigger period. From the start of the trigger-off period, although the first control node Q switches to a low potential, transistor M6 is turned off, and the storage capacitor C25 keeps the control terminal of transistor M1 at a high potential, so the light-emitting device D1 can continue to emit light until the next frame. The full-screen reset signal terminal TRS provides an effective full-screen reset signal, and the control terminal of transistor M1 writes the first level signal VGL2, so the light-emitting device D1 stops emitting light. Compared with emitting light only during the trigger period, this effectively increases the emitting time of the light-emitting device D1, which is convenient for visual observation and for determining the state of the detection point based on the change in the emitting state.

[0124] Figure 7 This is a schematic diagram of a shift register provided in an embodiment of this application, which includes a first light-emitting circuit (3T1C1D) and a third light-emitting circuit (3T1C1D).

[0125] Among them, the first light-emitting circuit 15' of 3T1C1D can be adopted as follows: Figure 5 As shown, the third light-emitting circuit 17 includes a fourth transistor, a fifth transistor, a sixth transistor, and a second light-emitting device.

[0126] The control electrode and second electrode of the fourth transistor are both coupled to the third power supply terminal GVDD2. The first electrode of the fifth transistor is coupled to the second level signal VGL3 terminal. The control electrode of the fifth transistor is coupled to the second control node QB. The first electrode of the fourth transistor and the second electrode of the fifth transistor are both coupled to the control electrode of the sixth transistor. The first electrode of the sixth transistor is coupled to the anode of the second light-emitting device. The cathode of the second light-emitting device is coupled to the second power supply terminal ELVSS. The second electrode of the sixth transistor is coupled to the third power supply terminal GVDD2. Figure 7 As shown, the fourth transistor is transistor M8, the fifth transistor is transistor M9, the sixth transistor is transistor M10, and the second light-emitting device is light-emitting device D6.

[0127] Figure 8 yes Figure 7 The timing diagram of the shift register shown is available in [reference]. Figure 8As shown, when the second control node QB is high, transistor M9 is turned on, and the signal provided by the second level signal terminal VGL3 is written to the control electrode of transistor M10. The voltage at the control electrode of transistor M10 is low, transistor M10 is turned off, and the light-emitting device D6 does not emit light. When the trigger period begins, the potential of the second control node QB changes from high to low, transistor M9 is turned off, and the signal at the third power supply terminal GVDD2 is written to the control electrode of transistor M10. The voltage at the control electrode of transistor M10 changes from low to high, transistor M10 is turned on, and the light-emitting device D6 emits light. During the trigger-off period, the voltage of the second control node QB returns to high, and correspondingly, the light-emitting device M6 stops emitting light. The light-emitting period of the light-emitting device M6 coincides with the trigger period of the shift register unit.

[0128] In some embodiments, after the detection unit determines that the node to be detected is faulty, the corresponding fault can also be repaired.

[0129] In some embodiments, the shift register unit includes at least one row output sub-circuit, and the shift register may further include at least one repair circuit; the repair circuit and at least one row output sub-circuit are both coupled to a first control node Q, a second control node QB, and a third level signal terminal VGL1; the repair circuit is also coupled to a repair clock signal terminal, and the row output sub-circuit is also coupled to a row clock signal terminal and a row output terminal; wherein, the row output sub-circuit is configured to, in response to the potential of the first control node Q, transmit the row clock signal provided by the row clock signal terminal to the corresponding row output terminal, or, in response to the potential of the second control node QB, provide the signal of the third level signal terminal VGL1 to the corresponding row output terminal.

[0130] Figure 9 This is a schematic diagram of a shift register with a repair circuit provided in an embodiment of this application.

[0131] The output circuit of the shift register unit can be adopted as... Figure 2 The output sub-circuits are configured in the same way, including four horizontal output sub-circuits. The repair circuit and the four horizontal output sub-circuits are all coupled to the first control node Q, the second control node QB, and the third level signal terminal VGL1. The repair circuit includes transistors M11 and M12 and a storage capacitor Cn. The control electrode of transistor M11 is coupled to the first control node Q, and the second electrode of transistor M11 is coupled to the repair clock signal terminal CLKn to receive the repair clock signal. The first electrode of transistor M11 is coupled to the repair output terminal OUTn. The control electrode of transistor M12 is coupled to the second control node QB, and the first electrode of transistor M12 is coupled to the third level signal terminal VGL1. The second electrode of transistor M9 is coupled to the first electrode of transistor M11. The storage capacitor Cn is connected between the control electrode and the first electrode of transistor M11.

[0132] The row output sub-circuit is configured to transmit the row clock signal to the corresponding row output terminal in response to the potential of the first control node Q. Under normal conditions, during the triggering period of the shift register unit, the row output terminals of the four row output sub-circuits respectively output gate control signals at valid potentials to select the corresponding four rows of pixels and control their refresh. The repair circuit is a dummy circuit; its repair output terminal OUTn is configured to be isolated from the row output terminals OUT1 to OUT4 and is not used to drive pixel rows.

[0133] The repair circuit is configured to, when the corresponding horizontal output terminal of the horizontal output sub-circuit is in a fault state, replace the horizontal output sub-circuit and, in response to the potential of the first control node Q, transmit the repair clock signal provided by the repair clock signal terminal CLKn to the horizontal output terminal; or, in response to the potential of the second control node, provide the signal of the third level signal terminal VGL1 to the corresponding horizontal output terminal. For details, see [link to details]. Figure 10 As shown, Figure 10 This is a schematic diagram of the shift register in the repair state provided in the embodiments of this application.

[0134] When the signal output by the horizontal output terminal OUT2 is abnormal, the coupling between the second horizontal output sub-circuit and the horizontal output terminal OUT2 can be disconnected and replaced by the repair circuit coupled to the horizontal output terminal OUT2. Correspondingly, the repair clock signal terminal CLKn can be coupled to the horizontal clock signal terminal CLK2 to reuse the signal of the horizontal clock signal terminal CLK2, or the same signal as the horizontal clock signal terminal CLK2 can be directly provided to the repair clock signal terminal CLKn.

[0135] In some embodiments, laser processing can be performed at the overlap of the lead used to connect the repair output terminal OUTn and the lead used to connect the horizontal output terminal OUT2. By connecting the lead used to connect the repair output terminal OUTn and the lead used to connect the horizontal output terminal OUT2, the signal of the horizontal output terminal OUT2 is replaced with the signal of the repair output terminal OUTn, and the circuit repair is completed without affecting the original screen timing.

[0136] In another aspect of this application, a gate drive circuit is provided, which may include a plurality of cascaded shift registers, at least one of which is a shift register as described in any of the above embodiments.

[0137] Multiple shift registers include a trigger signal terminal STU, a row reset signal terminal STD, and a cascaded output terminal CR. The preceding shift register, the target shift register, the following shift register, the first alternative shift register, and the second alternative shift register are shift registers among multiple shift registers.

[0138] The trigger signal terminal STU of the target shift register is coupled to the cascaded output terminal CR of the preceding shift register, and the row reset signal terminal STD of the target shift register is coupled to the cascaded output terminal CR of the following shift register.

[0139] When the cascaded output CR of the current stage shift register is in a fault state, the target shift register is configured to disconnect its trigger signal STU from the cascaded output CR of the previous stage shift register and couple it to the cascaded output CR of the first alternative shift register.

[0140] When the cascaded output CR of the subsequent shift register is in a fault state, the target shift register is configured to disconnect its row reset signal STD from the cascaded output CR of the subsequent shift register and couple it to the cascaded output CR of the second alternative shift register.

[0141] The cascaded output terminals CR of the first and second alternative shift registers are both in normal condition.

[0142] Within one output cycle of the target shift register, the valid signal received by the trigger signal terminal of the target shift register, the valid signal output by the cascaded output terminal CR, and the valid signal received by the row reset signal terminal appear sequentially in time; and the period from the start time of the valid signal received by the trigger signal terminal to the start time of the valid signal received by the row reset signal terminal forms a trigger period, which overlaps with one valid pulse of the clock signal corresponding to the target shift register.

[0143] See Figures 11 to 13 As shown, Figure 11 This is a schematic diagram of the gate drive control circuit provided in a specific example of this application. Figure 12 yes Figure 11 The timing diagram shown is of the gate drive control circuit in normal state. Figure 13 This is a schematic diagram of the gate drive control circuit after fault repair provided in a specific example of this application. Figure 14 yes Figure 13 The timing diagram corresponding to the gate drive control circuit shown is shown.

[0144] Taking a shift register driving one row, and including 6 different clock signals, with each clock signal having an effective level duration of 1H as an example, such as... Figure 11 As shown, the gate drive circuit may include shift registers GOA1 to GOA6, cascade signals CR1 to CR6, and the high-level start times of cascade signals CR1 to CR6 are sequentially 1H apart. Cascade signal CR7 may be the same as cascade signal CR1. Each shift register includes a trigger signal terminal STU, a row reset signal terminal STD, and a cascade output terminal CR.

[0145] The trigger signal terminal STU of shift register GOA1 is used to receive the cascade signal CR1; the cascade output terminal CR of shift register GOA1 and the trigger signal terminal STU of shift register GOA3 are used to output the cascade signal CR3 and provide it to the trigger signal terminal STU of shift register GOA3; the row reset signal terminal STD of shift register GOA1 is coupled to the cascade output terminal CR of shift register GOA4, and the cascade output terminal CR of shift register GOA4 outputs the cascade signal CR6 and provides it to the row reset signal terminal STD of shift register GOA1.

[0146] See Figure 12 As shown, when the cascaded signal changes from low level to high level, the corresponding shift register unit enters the trigger period. The area where the effective period of the clock signal corresponding to the shift register overlaps with the trigger period is the output period. The row output terminal of the corresponding shift register outputs the gate control signal.

[0147] As an example, taking shift register GOA6 as the target shift register, its trigger signal STU is coupled to the cascaded output CR of the preceding shift register GOA4. When the cascaded output CR of the preceding shift register GOA4 is in a fault state, such as Figure 13 As shown, shift register GOA6 can be configured to disconnect its trigger signal terminal STU from the cascaded output terminal CR of the preceding shift register GOA4, and use shift register GOA3 as the first alternative shift register, so that the trigger signal terminal STU of shift register GOA6 is coupled to the cascaded output terminal CR of shift register GOA3, thereby providing the cascaded signal CR5 output by the cascaded output terminal CR of shift register GOA3 to the trigger signal terminal STU of shift register GOA6.

[0148] contrast Figure 14 and Figure 12 In the trigger period of shift register GOA6, after replacing the cascaded signal CR6 at the STU input terminal of shift register GOA6 with the cascaded signal CR5, the start time of the trigger period of shift register GOA6 is advanced by 1H, and the trigger period changes from 5H to 6H. The trigger period overlaps with one effective pulse of the clock signal corresponding to shift register GOA6, and the output period remains 1H, which has no effect on the output of shift register. Thus, while repairing the faulty circuit, it is not necessary to change the overall driving logic of the circuit.

[0149] See Figure 11 As shown, shift register GOA1 is used as the target shift register, and shift register GOA4 can be used as the subsequent shift register. When the cascaded output CR of shift register GOA4 is in a fault state, see [reference needed]. Figure 13As shown, shift register GOA1 can be configured to disconnect its row reset signal terminal from the cascade output terminal CR of shift register GOA4, and use shift register GOA3 as a second alternative shift register, coupling the row reset signal terminal STD of shift register GOA1 to the cascade output terminal CR of shift register GOA3. Specifically, the cascade output terminal CR of shift register GOA4 provides the cascade signal CR6, and the cascade output terminal CR of shift register GOA3 provides the cascade signal CR5, thus replacing the signal input to the row reset signal terminal STD of shift register GOA1 with the cascade signal CR5 instead of CR6.

[0150] contrast Figure 14 and Figure 12 During the trigger period of shift register GOA1, after the signal input to the STD terminal of the horizontal reset signal of shift register GOA1 is replaced by the cascade signal CR5 instead of the cascade signal CR6, the end time of the trigger period of shift register GOA1 is advanced by 1H, the trigger period changes from 5H to 4H, and the trigger period overlaps with one effective pulse of the clock signal corresponding to shift register GOA1. The output period remains 1H and has no effect on the output of shift register GOA1.

[0151] In another aspect of this application, a display device is provided, which includes the gate driving circuit described in any of the above embodiments.

[0152] As an example, display devices can include any product or component with display functionality, such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0153] Another aspect of this application provides a shift register control method, which can be applied to the control of the shift register provided in any of the above embodiments, wherein the shift register includes a shift register unit and a detection unit coupled to the node to be detected in the shift register unit, and the method may include:

[0154] The detection unit controls the light emission state of the node under test according to the potential of the node under test. The light emission state of the detection unit when the node under test is in a fault state is different from the light emission state when the node under test is in a normal state.

[0155] The detection unit controls the light emission state of the node to be detected based on its potential, which can be specifically as follows:

[0156] When the detection unit includes a first light-emitting circuit (15 or 15'), the light-emitting state of the first light-emitting circuit 15 is controlled according to the potential of the first control node Q, so as to determine whether the first control node Q is faulty based on the light-emitting state of the first light-emitting circuit (15 or 15').

[0157] When the detection unit includes the second light-emitting circuit 16, the light-emitting state of the second light-emitting circuit 16 is controlled according to the potential of the output terminal, so as to determine whether the output terminal is faulty or whether the signal output by the corresponding output terminal is abnormal based on the light-emitting state of the second light-emitting circuit 16.

[0158] When the detection unit includes the third light-emitting circuit 17, the light-emitting state of the third light-emitting circuit 17 is controlled according to the potential of the second control node QB, so as to determine whether the second control node QB is abnormal and whether the row reset signal is abnormal based on the light-emitting state of the third light-emitting circuit 17.

[0159] In some embodiments, the shift register unit may include at least one row output sub-circuit, and the shift register further includes at least one repair circuit; both the repair circuit and the row output sub-circuit are coupled to the first control node Q, the second control node QB, and the third level signal terminal VGL1; the repair circuit is also coupled to a repair clock signal terminal, and the row output sub-circuit is also coupled to a row clock signal terminal and a row output terminal; the method further includes:

[0160] The horizontal output sub-circuit responds to the potential of the first control node Q by transmitting the horizontal clock signal provided by the horizontal clock signal terminal to the corresponding horizontal output terminal, or responds to the potential of the second control node QB by providing the signal of the third level signal terminal VGL1 to the corresponding horizontal output terminal. When the horizontal output terminal corresponding to the horizontal output circuit is in a fault state, the repair circuit replaces the horizontal output sub-circuit, responding to the potential of the first control node Q by transmitting the repair clock signal provided by the repair clock signal terminal to the horizontal output terminal, or responding to the potential of the second control node QB by providing the signal of the third level signal terminal VGL1 to the corresponding horizontal output terminal. This achieves fault repair.

[0161] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A shift register, characterized in that, It includes a shift register unit and a detection unit coupled to the node to be detected in the shift register unit; The detection unit is configured to control the light emission state of the node to be detected according to the potential of the node to be detected. The light emission state of the detection unit when the node to be detected is in a fault state is different from the light emission state when the node to be detected is in a normal state.

2. The shift register according to claim 1, characterized in that, The detection unit includes at least one of a first light-emitting circuit, a second light-emitting circuit, and a third light-emitting circuit; The first light-emitting circuit is coupled to the first control node of the shift register unit, and the first light-emitting circuit is configured to control its light-emitting state according to the potential of the first control node. The second light-emitting circuit is coupled to the output terminal of the shift register unit, and the second light-emitting circuit is configured to control its light-emitting state according to the potential of the output terminal; The third light-emitting circuit is coupled to the second control node of the shift register unit, and the third light-emitting circuit is configured to control its light-emitting state according to the potential of the second control node; The first control node is used to control the transmission of the clock signal to the output of the shift register unit; the second control node is used to control the transmission of the reference signal to the output of the shift register unit and / or the first control node.

3. The shift register according to claim 2, characterized in that, The first light-emitting circuit is configured to control its light-emitting state according to the potential of the first control node, including: When the first control node is in a normal state, the first light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the first control node. Alternatively, the first light-emitting circuit is configured to emit light continuously during the triggering period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, based on the potential of the first control node.

4. The shift register according to claim 2, characterized in that, The second light-emitting circuit is configured to control its light-emitting state according to the potential of the output terminal, including: When the output terminal is in a normal state, the second light-emitting circuit is configured to emit light during the output period of the shift register unit according to the potential of the output terminal; Alternatively, the second light-emitting circuit is configured to emit light continuously during the output period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, based on the potential of the output terminal.

5. The shift register according to any one of claims 2 to 4, characterized in that, When the first light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the first control node; and / or, when the second light-emitting circuit is configured to emit light during the output period of the shift register unit according to the potential of the output terminal, At least one of the first light-emitting circuit and the second light-emitting circuit includes a first transistor and a first light-emitting device. The first electrode of the first transistor is coupled to a first power supply terminal, the second electrode of the first transistor is coupled to the anode of the first light-emitting device, the cathode of the first light-emitting device is coupled to a second power supply terminal, and the control electrode of the first transistor is coupled to the node to be detected corresponding to its light-emitting circuit.

6. The shift register according to any one of claims 2 to 4, characterized in that, When the first light-emitting circuit is configured to continuously emit light according to the potential of the first control node, from the triggering period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, and / or the second light-emitting circuit is configured to continuously emit light according to the potential of the output terminal, from the output period of the shift register unit until the full-screen reset signal corresponding to the next frame is at an effective potential, the light-emitting circuits in the first and second light-emitting circuits that continuously emit light before the full-screen reset signal corresponding to the next frame is at an effective potential include: The system comprises a first transistor, a first light-emitting device, a second transistor, a third transistor, and a storage capacitor. The first terminal of the first transistor is coupled to a first power supply terminal, the second terminal of the first transistor is coupled to the anode of the first light-emitting device, and the cathode of the first light-emitting device is coupled to a second power supply terminal. The first terminal and the control terminal of the second transistor are both coupled to the node to be detected in its current light-emitting circuit. The second terminal of the second transistor is coupled to the first terminal of the third transistor. The second terminal of the third transistor is coupled to a first level signal terminal, and the control terminal of the third transistor is coupled to a full-screen reset signal terminal. One terminal of the storage capacitor is coupled to the first level signal terminal, and the other terminal of the storage capacitor is coupled to the control terminal of the first transistor and the second terminal of the second transistor, respectively.

7. The shift register according to claim 2, characterized in that, The third light-emitting circuit is configured to control its light-emitting state according to the potential of the second control node, including: When the second control node is in a normal state, the third light-emitting circuit is configured to emit light during the triggering period of the shift register unit according to the potential of the second control node.

8. The shift register according to claim 7, characterized in that, The third light-emitting circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second light-emitting device; The control electrode and the second electrode of the fourth transistor are both coupled to the third power supply terminal. The first electrode of the fifth transistor is coupled to the second level signal terminal. The control electrode of the fifth transistor is coupled to the second control node. The first electrode of the fourth transistor and the second electrode of the fifth transistor are both coupled to the control electrode of the sixth transistor. The first electrode of the sixth transistor is coupled to the anode of the second light-emitting device. The cathode of the second light-emitting device is coupled to the second power supply terminal. The second electrode of the sixth transistor is coupled to the third power supply terminal.

9. The shift register according to any one of claims 1 to 4, 7 to 8, characterized in that, The shift register unit includes: A reset circuit is coupled to a full-screen reset signal terminal, a horizontal reset signal terminal, a first-level signal terminal, a second-level signal terminal, and a first control node, respectively. It is used to provide the signal of the first-level signal terminal to the first control node in response to the full-screen reset signal of the full-screen reset signal terminal, and to provide the signal of the second-level signal terminal to the first control node in response to the horizontal reset signal of the horizontal reset signal terminal. The trigger circuit is coupled to the trigger signal terminal, the fourth power supply terminal and the first control node respectively, and is used to provide the signal of the fourth power supply terminal to the first control node in response to the trigger signal of the trigger signal terminal. The internal logic circuit is coupled to the first control node, the second control node, the third power supply terminal, the first level signal terminal and the second level signal terminal respectively, and is used to provide the potential of the third power supply terminal to the second control node, or, in response to the potential of the first control node, provide the signal of the second level signal terminal to the second control node. The output circuit includes a cascaded output sub-circuit and at least one horizontal output sub-circuit. Both the cascaded output sub-circuit and the horizontal output sub-circuit are coupled to a first control node and a second control node. The cascaded output sub-circuit is also coupled to a cascaded clock signal terminal and a second level signal terminal. The horizontal output sub-circuit is also coupled to a horizontal clock signal terminal and a third level signal terminal. The cascaded output sub-circuit is configured to provide a cascaded clock signal from the cascaded clock signal terminal to its own output terminal in response to the potential of the first control node, and to provide a potential from the second level signal terminal to its own output terminal in response to the potential of the second control node. The horizontal output sub-circuit is configured to provide a horizontal clock signal from the horizontal clock signal terminal to its own output terminal in response to the potential of the first control node, and to provide a potential from the third level signal terminal to its own output terminal in response to the potential of the second control node.

10. The shift register according to claim 9, characterized in that, The shift register also includes: The leakage protection circuit is coupled to the fourth power supply terminal and the first control node respectively, and is coupled to the trigger circuit and the pull-down circuit respectively through the third control node. It is used to provide the potential of the fourth power supply terminal to the third control node in response to the potential of the first control node. The pull-down circuit is coupled to the first control node, the second control node, and the second level signal terminal respectively, and is used to provide the signal of the second level signal terminal to the first control node in response to the potential of the second control node.

11. The shift register according to any one of claims 1 to 4, 7 to 8, characterized in that, The shift register unit includes at least one row output sub-circuit, and the shift register also includes at least one repair circuit; The repair circuit and the line output sub-circuit are both coupled to the first control node, the second control node and the third level signal terminal. The repair circuit is also coupled to the repair clock signal terminal, and the line output sub-circuit is also coupled to the line clock signal terminal and the line output terminal. The horizontal output sub-circuit is configured to transmit the horizontal clock signal provided by the horizontal clock signal terminal to the corresponding horizontal output terminal in response to the potential of the first control node, or to provide the signal of the third level signal terminal to the corresponding horizontal output terminal in response to the potential of the second control node. The repair circuit is configured to replace the horizontal output sub-circuit when the horizontal output terminal corresponding to the horizontal output sub-circuit is in a fault state, and in response to the potential of the first control node, transmit the repair clock signal provided by the repair clock signal terminal to the horizontal output terminal, or, in response to the potential of the second control node, provide the signal of the third level signal terminal to the corresponding horizontal output terminal.

12. A gate driving circuit, characterized in that, It includes multiple cascaded shift registers, at least one of which is a shift register according to any one of claims 1 to 11.

13. The gate driving circuit according to claim 12, characterized in that, Each of the multiple shift registers includes a trigger signal terminal, a row reset signal terminal, and a cascaded output terminal. The preceding shift register, the target shift register, the following shift register, the first alternative shift register, and the second alternative shift register are shift registers among the multiple shift registers. The trigger signal terminal of the target shift register is coupled to the cascade output terminal of the preceding shift register, and the row reset signal terminal of the target shift register is coupled to the cascade output terminal of the following shift register. When the cascaded output of the preceding shift register is in a fault state, the target shift register is configured to disconnect its trigger signal from the cascaded output of the preceding shift register and couple it to the cascaded output of the first alternative shift register. When the cascaded output of the subsequent shift register is in a fault state, the target shift register is configured to disconnect its row reset signal from the cascaded output of the subsequent shift register and couple it to the cascaded output of the second alternative shift register. The cascaded outputs of both the first and second alternative shift registers are in normal condition.

14. A display device, characterized in that, Includes the gate drive circuit as described in claim 12 or 13.

15. A shift register control method, characterized in that, The shift register includes a shift register unit and a detection unit coupled to the node to be detected in the shift register unit; the method includes: The detection unit controls the light emission state of the node under test according to the potential of the node under test. The light emission state of the detection unit when the node under test is in a fault state is different from the light emission state when the node under test is in a normal state.

16. The method according to claim 15, characterized in that, The shift register unit includes at least one row output sub-circuit, and the shift register further includes at least one repair circuit; the repair circuit and the row output sub-circuit are both coupled to a first control node, a second control node, and a third level signal terminal; the repair circuit is also coupled to a repair clock signal terminal; the row output sub-circuit is also coupled to a row clock signal terminal and a row output terminal; the method further includes: The horizontal output sub-circuit responds to the potential of the first control node by transmitting the horizontal clock signal provided by the horizontal clock signal terminal to the corresponding horizontal output terminal, or responds to the potential of the second control node by providing the signal of the third level signal terminal to the corresponding horizontal output terminal. When the horizontal output terminal corresponding to the horizontal output sub-circuit is in a fault state, the repair circuit replaces the horizontal output sub-circuit and, in response to the potential of the first control node, transmits the repair clock signal provided by the repair clock signal terminal to the horizontal output terminal, or, in response to the potential of the second control node, provides the signal of the third level signal terminal to the corresponding horizontal output terminal.

Images