A gate driving circuit, method and display panel

Abstract

This application belongs to the field of display driver technology, specifically relating to a gate driving circuit, method, and display panel. The gate driving circuit includes N cascaded gate driving units. The nth-stage gate driving unit includes a partial refresh control module, configured to: in partial refresh mode, if the (n-d)th stage is a non-refresh row and the current stage is a refresh row, at the start of the non-overlapping period of the current stage clock signal, control the pull-up node of the current stage to be electrically connected to the drive control node of the current stage; if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, at the start of the (n+d-i)th stage clock signal, control the pull-up node of the current stage to be disconnected from the drive control node of the current stage, and at the start of the (n-i)th stage clock signal, charge the drive control node of the current stage under the voltage of the drive control node of the current stage. This application will avoid abnormal edge display in the partial refresh area of ​​the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit, method, and display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display of local refresh areas in the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, method, and display panel, which solves the problem of abnormal edge display in the local refresh area of ​​the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to the pull-up node of the current stage, configured to: charge the pull-up node of the current stage in response to the output signal of the nith gate driving unit; a stage transmission output module connected to the pull-up node of the current stage and the clock signal line of the current stage, configured to: output a stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage; and a partial refresh control module connected to the pull-up node of the current stage and the drive control node of the current stage, configured to: in partial refresh mode, if the ndth stage is a non-refresh line and the current stage is a refresh line, ... At the start of a non-overlapping period of the current stage clock signal, the pull-up node of the current stage is electrically connected to the drive control node of the current stage; if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, at the start of the (n+di)th stage clock signal, the pull-up node of the current stage is disconnected from the drive control node of the current stage, and at the start of the (ni)th stage clock signal, the drive control node of the current stage is charged under the voltage of the drive control node of the current stage; the drive output module, connected to the drive control node of the current stage and the clock signal line of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node of the current stage and the clock signal of the current stage.

[0006] Optionally, the local refresh control module includes: a first control submodule, connected to the first local refresh control terminal, the pull-up node of the current level, and the current level's drive control node, configured to: in local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level's clock signal, control the electrical connection between the pull-up node of the current level and the drive control node of the current level according to the first local refresh control signal; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level's clock signal, control the... The pull-up node of the current stage is disconnected from the drive control node of the current stage; the second control submodule, connected to the stage transmission output module of the nj stage and the precharge control node of the current stage, is configured to charge the precharge control node of the current stage under the action of the stage transmission signal of the nj stage; the third control submodule, connected to the precharge control node of the current stage, the drive control node of the current stage, and the second brush control terminal, charges the drive control node of the current stage under the action of the voltage of the precharge control node of the current stage, the voltage of the drive control node of the current stage, and the second brush control signal when the clock signal of the ni stage starts.

[0007] Optionally, the first control submodule includes: a first transistor; the control terminal of the first transistor is connected to the first local brush control terminal, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the drive control node of the current stage.

[0008] Optionally, the second control submodule includes: a second transistor and a first capacitor; the control terminal of the second transistor is connected to the stage output module of the njth stage, the first terminal of the second transistor is connected to the stage output module or a high-level terminal of the njth stage, the second terminal of the second transistor is connected to the first terminal of the first capacitor; the second terminal of the first capacitor is connected to the precharge control node of the current stage.

[0009] Optionally, the third control submodule includes: a third transistor and a fourth transistor; the control terminal of the third transistor is connected to the second brush control terminal, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the control terminal of the fourth transistor is connected to the drive control node of the current stage, and the second terminal of the fourth transistor is connected to the drive control node of the current stage; or, the control terminal of the third transistor is connected to the drive control node of the current stage, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the control terminal of the fourth transistor is connected to the second brush control terminal, and the second terminal of the fourth transistor is connected to the drive control node of the current stage.

[0010] Optionally, the nth stage gate drive unit further includes a reset submodule, connected to the precharge control node of the current stage, and configured to reset the precharge control node of the current stage during the vertical blanking period.

[0011] Optionally, the reset submodule includes: a fifth transistor; the control terminal of the fifth transistor is connected to the reset control terminal, the first terminal of the fifth transistor is connected to the precharge control node of the current stage, and the second terminal of the fifth transistor is connected to the low-level terminal.

[0012] Optionally, the stage output module includes: a sixth transistor and a second capacitor; the control terminal of the sixth transistor and the first terminal of the second capacitor are connected to the pull-up node of the current stage, the first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the second terminal of the second capacitor and serves as the output terminal.

[0013] Secondly, this application provides a gate circuit driving method, applied to the gate driving circuit according to any one of the first aspects, the method comprising: a pull-up module charging the pull-up node of the current stage in response to the output signal of the ni-th stage gate driving unit; a stage transmission output module outputting a stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage; in a local refresh mode, if the current stage is a non-refresh line and the (n+d)-th stage is a refresh line, at the start of the non-overlapping period of the (n+d)-th stage clock signal, a local refresh control module controlling the pull-up node of the current stage to be electrically connected to the driving control node of the current stage; if the current stage is a refresh line and the (n+d)-th stage is a non-refresh line, at the start of the (n+di)-th stage clock signal, a local refresh control module controlling the pull-up node of the current stage to be disconnected from the driving control node of the current stage, and at the start of the ni-th stage clock signal, a local refresh control module charging the driving control node of the current stage; and a driving output module outputting the gate driving signal of the current stage under the action of the voltage on the driving control node of the current stage and the clock signal of the current stage.

[0014] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the drive output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, by setting a local refresh control module, when switching from a non-refresh line to a refresh line, at the start of the non-overlapping period of the current level clock signal, the pull-up node of the current level is electrically connected to the drive control node of the current level. This prevents the drive output module of the nd level from outputting the gate drive signal, avoiding abnormal edge display of the local refresh area of ​​the display panel. The drive output module of the current level will output the gate drive signal to refresh the pixels, thereby performing local refresh of the display panel. When switching from a refresh line to a non-refresh line, at the start of the (n+di) level clock signal, the connection between the pull-up node of the current level and the drive control node of the current level is interrupted. By opening the connection and charging the current stage's drive control node under the voltage of the current stage's drive control node at the start of the ni-th stage clock signal, the current stage's drive output module can output the current stage's gate drive signal to refresh the pixels. Furthermore, setting the local refresh control module to charge the current stage's drive control node at the start of the ni-th stage clock signal can increase the voltage of the current stage's drive control node, promote the conduction of the drive output module, and make the output gate drive signal more stable. It can also stop the n+d-th stage's drive output module from outputting the gate drive signal, avoiding abnormal edge display of the local refresh area of ​​the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0021] Figure 4 A first operating timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A second timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0023] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0024] Figure 7 A flowchart of a gate circuit driving method provided in an embodiment of this application is shown.

[0025] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 Local brush control module; 131 First control submodule; 132 Second control submodule; 133 Third control submodule; 134 Reset submodule; 140 Drive output module; 150 Pull-down module; 160 Noise reduction module.

[0026] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; SW1, first brush control terminal; SW2, second brush control terminal; Reset, reset control terminal; VGH, high level terminal; VSS, low level terminal; Qn, pull-up node of the current stage; Qsn, drive control node of the current stage; An, precharge control node of the current stage. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0028] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0029] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0030] Figure 1 The diagram shows a schematic of a gate driving circuit according to an embodiment of this application. The gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a local brush control module 130, and a drive output module 140. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage output module 120 is connected to the pull-up node Qn of the current stage and the clock signal line CKm of the current stage. The drive output module 140 is connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage.

[0031] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the output terminal of the ni-th stage transmission module, Fn represents the output terminal of the current stage transmission module, and Gn represents the output terminal of the current stage drive output module.

[0032] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn of the current stage in response to the output signal of the nth stage gate drive unit 100.

[0033] For example, i can be 2, and the output signal of the ni-th gate drive unit 100 can be a stage transmission signal. When the pull-up module 110 receives the gate drive signal of the ni-th stage, it will charge the pull-up node Qn of the current stage and generate a voltage on the pull-up node Qn of the current stage.

[0034] In some embodiments, the stage transmission module 120 is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node Qn of the current stage and the clock signal of the current stage.

[0035] For example, when there is a voltage on the pull-up node Qn of the current stage, when the clock signal of the current stage arrives, the stage transmission module 120 will be turned on and output the stage transmission signal of the current stage to perform stage transmission, which will act on the gate drive unit 100 of the adjacent stage.

[0036] In some embodiments, the local refresh control module 130 is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node Qn of the current level to be electrically connected to the drive control node Qsn of the current level; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, at the start of the (n+di)-th level clock signal, control the pull-up node Qn of the current level to be disconnected from the drive control node Qsn of the current level, and charge the drive control node Qsn of the current level at the start of the (ni)-th level clock signal.

[0037] It should be noted that the display panel includes multiple gate driving units 100. In the global refresh mode, each gate driving unit 100 outputs a gate driving signal to refresh each pixel. In the partial refresh mode, some gate driving units 100 in the display panel output gate driving signals to partially refresh pixels, without each gate driving unit 100 needing to output a gate driving signal to refresh the pixels. The non-overlapping period of the current level clock signal represents the period during which the nth level signal and the nith level clock signal do not overlap.

[0038] For example, d can be 1. If the current level is a non-refreshing row and the (n+d)th level is a refreshing row, that is, when the non-refreshing row switches to the refreshing row, at the start of the non-overlapping period of the current level clock signal, the pull-up node Qn of the current level is electrically connected to the drive control node Qsn of the current level. For the nd level, during the pre-charge period of the nd level, the pull-up node of the nd level and the drive control node of the nd level are disconnected, and there is no pre-charge voltage on the drive control node of the nd level. When the clock signal of the nd level arrives, the drive output module 140 of the nd level outputs the gate drive signal to refresh the pixel, which can avoid abnormal display of the edge of the local refresh area of ​​the display panel. For the current level, the voltage of the pull-up node Qn of the current level will be transmitted to the drive control node Qsn of the current level. At the start of the non-overlapping period of the current level clock signal, the drive output module 140 will output the gate drive signal of the current level to refresh the pixel of the current level, so as to realize the local refresh of the display panel.

[0039] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, that is, when the refresh row switches to a non-refresh row, the pull-up node Qn of the current level is disconnected from the drive control node Qsn of the current level at the start of the (n+di)th level clock signal, and the drive control node Qsn of the current level is charged at the start of the nith level clock signal. For the current level, since the (n+di)th level clock signal and the nith level clock signal overlap, disconnecting the pull-up node Qn of the current level from the drive control node Qsn of the current level at the start of the nith level clock signal will result in a shorter charging time for the drive control node Qsn of the current level. At the start of the nith level clock signal, the current level... Under the action of the drive control node Qsn, the current stage's drive control node Qsn is charged to make the voltage of the current stage's drive control node Qsn more sufficient. When the clock signal of the current stage arrives, it can promote the conduction of the current stage's drive output module 140, making the output gate drive signal of the current stage more stable. For the n+d stage, when the clock signal of the n+di stage starts, the pull-up node of the n+d stage is disconnected from the drive control node of the n+d stage. The drive control node of the n+d stage has no pre-charge voltage and will not drive the current stage's drive output module 140 to conduct, thus not outputting a gate drive signal for refresh, avoiding abnormal display at the edge of the local refresh area of ​​the display panel.

[0040] In some embodiments, the drive output module 140, connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node Qsn of the current stage and the clock signal of the current stage.

[0041] For example, if there is a voltage on the current stage's drive control node Qsn, the drive output module 140 will be turned on when the current stage clock signal arrives, thereby outputting the current stage's gate drive signal to refresh the current stage's pixels.

[0042] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the local brush control module 130 includes: a first control submodule 131, a second control submodule 132, and a third control submodule 133; the first control submodule 131 is connected to the first local brush control terminal SW1, the pull-up node Qn of the current stage, and the current stage drive control node Qsn; the second control submodule 132 is connected to the output terminal of the njth stage output module and the current stage precharge control node An; the second control submodule 132 is connected to the njth stage transmission output module 120 and the current stage precharge control node An; and the third control submodule 133 is connected to the current stage precharge control node An, the current stage drive control node Qsn, and the second local brush control terminal SW2.

[0043] In some embodiments, the first control submodule 131 is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node Qn of the current level and the drive control node Qsn of the current level to be electrically connected according to the first refresh control signal; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, at the start of the (n+di)-th level clock signal, control the pull-up node Qn of the current level and the drive control node Qsn of the current level to be disconnected according to the first refresh control signal.

[0044] In some embodiments, the second control submodule 132 is configured to charge the pre-charge control node of the current level under the action of the level transmission signal of the nj level.

[0045] In some embodiments, the third control submodule 133, at the start of the ni-th stage clock signal, charges the current stage drive control node Qsn under the action of the voltage of the current stage pre-charge control node, the voltage of the current stage drive control node Qsn, and the second brush control signal.

[0046] For example, i can be 2, d can be 1, and j can be 3. If the nd-th level is a non-refresh row and the current level is a refresh row, the first control submodule 131 starts at the non-overlapping period of the current level clock signal and controls the pull-up node Qn of the current level to disconnect from the drive control node Qsn of the current level according to the received first refresh control signal. For the nd-th level, during the pre-charge period of the nd-th level, the pull-up node of the nd-th level and the drive control node of the nd-th level are disconnected, and there is no pre-charge voltage on the drive control node of the nd-th level. When the clock signal of the nd-th level arrives, the drive output module 140 of the nd-th level outputs the gate drive signal to refresh the pixel, which can avoid abnormal display of the edge of the local refresh area of ​​the display panel. For the current level, the voltage of the pull-up node Qn of the current level will be transmitted to the drive control node Qsn of the current level. At the start of the non-overlapping period of the current level clock signal, the drive output module 140 will output the gate drive signal of the current level to refresh the pixel of the current level, so as to realize the local refresh of the display panel.

[0047] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, the second control submodule 132 charges the pre-charge control node An of the current level when the clock signal of the (nj)th level arrives, so as to generate voltage on the pre-charge control node An of the current level. The first control submodule 131 controls the pull-up node Qn of the current level to disconnect from the drive control node Qsn of the current level when the clock signal of the (n+di)th level starts. The third control submodule 133 charges the drive control node Qsn of the current level under the action of the voltage of the drive control node Qsn of the current level and the second refresh control signal. For the current level, the clock signal of the (n+di)th level overlaps with the clock signal of the nith level. The voltage charging time of the drive control node Qsn of the current level will be less than the voltage transmitted during normal level transmission. The second control submodule 132 is configured to charge the current stage's drive control node Qsn only when there is voltage at the current stage's drive control node Qsn and a second refresh control signal. This increases the voltage of the current stage's drive control node Qsn, which promotes the conduction of the drive control module when the current stage's clock signal arrives, making the output gate drive signal of the current stage more stable. For the n+d stage, during the pre-charge period of the n+d stage, the pull-up node of the n+d stage is disconnected from the drive control node of the n+d stage, and there is no pre-charge voltage on the drive control node of the n+d stage. The second control submodule 132 of the n+d stage will not conduct to charge the drive control node of the n+d stage, thus preventing the output of a gate drive signal for refresh and avoiding abnormal display at the edge of the local refresh area of ​​the display panel.

[0048] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first transistor T1 is connected to the pull-up node Qn of the current stage, and the second terminal of the first transistor T1 is connected to the drive control node Qsn of the current stage.

[0049] For example, when the control terminal of the first transistor T1 receives the first brush control signal output by the first brush control terminal SW1, the first transistor T1 will be turned on, controlling the current stage pull-up node Qn and the current stage drive control node Qsn to be electrically connected, and the voltage of the current stage pull-up node Qn will be transmitted to the current stage drive control node Qsn.

[0050] In some embodiments, please refer to Figure 3 As shown, the second control submodule 132 includes: a second transistor T2 and a first capacitor C1; the control terminal of the second transistor T2 is connected to the stage output module 120 of the nj stage, the first terminal of the second transistor T2 is connected to the stage output module 120 of the nj stage or the high-level terminal VGH, the second terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the precharge control node An of the current stage.

[0051] For example, when the control terminal of the second transistor T2 receives the transmission signal of the njth stage, the second transistor T2 will be turned on to charge the first capacitor C1 and generate a voltage on the pre-charge control node An of the current stage.

[0052] In some embodiments, please refer to Figure 3 As shown, the third control submodule 133 includes: a third transistor T3 and a fourth transistor T4; the control terminal of the third transistor T3 is connected to the second brush control terminal SW2, the first terminal of the third transistor T3 is connected to the precharge control node An of the current stage, and the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the drive control node Qsn of the current stage, and the second terminal of the fourth transistor T4 is connected to the drive control node Qsn of the current stage.

[0053] For example, the control terminal of the third transistor T3 will turn on when the second brush control terminal SW2 receives the second brush control signal, and the control terminal of the fourth transistor T4 will turn on when it receives the voltage of the current stage drive control node Qsn, thereby realizing the electrical connection between the current stage precharge control node An and the current stage drive control node Qsn. The voltage of the current stage precharge control node An will be transmitted to the current stage drive control node Qsn to charge the current stage drive control node Qsn.

[0054] Figure 4 This paper shows a first operating timing diagram of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, the non-overlapping period of the current level clock signal can be (t9~t10). If the nd level is a non-refresh line and the current level is a refresh line, that is, when the non-refresh line switches to a non-refresh line, for the nd level, the control terminal of the first transistor T1 receives the first local refresh control signal, that is, a high-level signal, at the beginning of the non-overlapping period of the current level clock signal (t9). The first transistor T1 will be turned on, and the pull-up node of the nd level will be electrically connected to the drive control node of the nd level. However, at this time, the clock signal of the nd level has ended, and the level transmission module 120 will not output the gate drive signal, thus avoiding abnormal display of the edge of the local refresh area of ​​the display panel.

[0055] For example, at the beginning of the non-overlapping period of the current stage clock signal (t9), the first transistor T1 receives the first local refresh control signal and turns on. The voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node Qsn of the current stage. The stage transmission module 120 will output the gate drive signal of the current stage to refresh the pixels of the current stage, so as to realize the local refresh of the display panel.

[0056] Figure 5 A second timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 5As shown, if the current level is a refresh line and the (n+d)th level is a non-refresh line, i.e., when switching from a refresh line to a non-refresh line, for the current level, the control terminal of the first transistor T1 receives the first refresh control signal (i.e., a low-level signal) at the beginning of the (n+di)th level clock signal (t6). The first transistor T1 will disconnect the pull-up node Qn of the current level from the drive control node Qsn of the current level. The clock signal of the (n+di)th level overlaps with the clock signal of the nith level. The pull-up node Qn of the current level only charges the drive control node Qsn of the current level during the overlapping period (t5~t6) of the clock signal of the nith level. The charging time of the drive control node Qsn of the current level is only one hour, while the normal level has 2 hours. The current stage has relatively few drive control nodes Qsn; furthermore, when the control terminal of the second transistor T2 transmits a signal at the ni stage, the first terminal of the second transistor T2 will turn on when it receives the signal transmitted at the ni stage or a high-level signal, charging the first capacitor C1 and generating a voltage at the pre-charge control node An of the current stage; the control terminal of the third transistor T3 turns on when it receives the voltage of the drive control node Qsn of the current stage, and the control terminal of the fourth transistor T4 turns on when the clock signal of the ni stage starts (t5), and the voltage of the pre-charge control node An of the current stage will be transmitted to the drive control node Qsn of the current stage to charge the drive control node Qsn of the current stage.

[0057] For example, for the (n+d)th stage, the control terminal of the first transistor T1 receives the first refresh control signal (i.e., a low-level signal) at the beginning of the (n+di)th stage clock signal period (t6). The first transistor T1 will disconnect the pull-up node Qn of the current stage from the drive control node Qsn of the current stage. After the first transistor T1 disconnects the connection of the (n+di)th stage clock signal, there is no pre-charge voltage on the drive control node Qsn of the current stage. The control terminal of the second transistor T2 will not be turned on, so the voltage of the pre-charge control node of the (n+d)th stage will not be transmitted to the drive control node of the (n+d)th stage. Since there is no pre-charge voltage on the drive control node of the (n+d)th stage, when the (n+d)th stage clock signal arrives, the drive output module 140 will not be turned on, and the stage transmission output module 120 will not output the gate drive signal, thus avoiding abnormal display of the edge of the local refresh area of ​​the display panel.

[0058] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 6As shown, the third control submodule 133 includes: a third transistor T3 and a fourth transistor T4; the control terminal of the third transistor T3 is connected to the current stage drive control node Qsn, the first terminal of the third transistor T3 is connected to the current stage precharge control node An, and the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the second brush control terminal SW2, and the second terminal of the fourth transistor T4 is connected to the current stage drive control node Qsn.

[0059] For example, when the control terminal of the third transistor T3 receives the voltage of the current stage's drive control node Qsn, it will conduct; when the control terminal of the fourth transistor T4 receives the second brush control signal output by the second brush control terminal SW2, the fourth transistor T4 will conduct, thereby achieving electrical connection between the current stage's pre-charge control node An and the current stage's drive control node Qsn. The voltage of the current stage's pre-charge control node An will be transmitted to the current stage's drive control node Qsn, charging the current stage's drive control node Qsn. It should be noted that... Figure 6 The working timing and principle of the third control submodule 133 in the middle Figure 3 The third control submodule 133 is the same as that in the previous one, so it will not be described again here.

[0060] In some embodiments, please refer to Figure 6 As shown, the nth stage gate drive unit 100 further includes a reset submodule 134, which is connected to the precharge control node An of the current stage and is configured to reset the precharge control node An of the current stage during the vertical blanking period.

[0061] For example, by setting the reset submodule to reset the precharge control node An of the current stage during the vertical blanking period, the precharge control node An of the current stage can be charged again in the next scan frame.

[0062] In some embodiments, the reset submodule includes: a fifth transistor T5; the control terminal of the fifth transistor T5 is connected to the reset control terminal Reset, the first terminal of the fifth transistor T5 is connected to the current stage precharge control node An, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS.

[0063] For example, when the control terminal of the fifth transistor T5 receives a reset control signal during the vertical blanking period, the fifth transistor T5 will be turned on, pulling down the precharge control node An of the current stage to a low potential. After the second transistor T2 is turned on in the next scan frame, the first capacitor C1 can be charged again.

[0064] In some embodiments, please refer to Figure 3 and Figure 6As shown, the stage output module 120 includes: a sixth transistor T6 and a second capacitor C2; the control terminal of the sixth transistor T6 and the first terminal of the second capacitor C2 are connected to the pull-up node Qn of the current stage, the first terminal of the sixth transistor T6 is connected to the clock signal line CKm of the current stage, and the second terminal of the sixth transistor T6 is connected to the second terminal of the second capacitor C2 and serves as the output terminal.

[0065] For example, when the current stage's drive control node Qsn is charged, the second capacitor C2 will be charged. When the current stage's clock signal arrives, the voltage of the second capacitor C2 will bootstrap the current stage's pull-up node Qn. When the control terminal of the sixth transistor T6 receives the voltage of the current stage's pull-up node Qn, it will turn on and output the current stage's transmission signal for transmission. Even when the current stage's pull-up node Qn is disconnected from the current stage's drive control node Qsn, transmission can still be achieved.

[0066] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the pull-up module 110 includes: a seventh transistor T7, the control terminal of the seventh transistor T7 is connected to the ni-th stage transmission output module 120, the first terminal of the seventh transistor T7 is connected to the ni-th stage transmission output module 120, and the second terminal of the seventh transistor T7 is connected to the pull-up node Qn of the current stage.

[0067] For example, when the control terminal of the seventh transistor T7 receives the stage transmission signal output by the stage transmission output module 120 of the ni stage, and the first terminal of the seventh transistor T7 receives the stage transmission signal from the stage transmission output module 120 of the ni stage, the seventh transistor T7 will be turned on to charge the pull-up node Qn of the current stage.

[0068] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the drive output module 140 includes an eighth transistor T8 and a third capacitor C3. The control terminal of the eighth transistor T8 is connected to the first terminal of the third capacitor C3 and is connected to the drive control node Qsn of the current stage. The first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage. The second terminal of the eighth transistor T8 is connected to the second terminal of the third capacitor C3 and serves as the output terminal.

[0069] For example, when charging the current stage's drive control node Qsn, the third capacitor C3 is also charged. When the current stage's clock signal arrives, the third capacitor C3 will bootstrap the current stage's drive control node Qsn. When the control terminal of the eighth transistor T8 receives the voltage of the current stage's drive control node Qsn and turns on, it will output the current stage's gate drive signal to refresh the current stage's pixels.

[0070] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 150, comprising a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The control terminals of the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are connected to the output terminal of the (n+j)th stage transmission output module 120. The first terminal of the ninth transistor T9 is connected to the pull-up node Qn of the current stage. The second terminals of the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are connected to the low-level terminal VSS. The first terminal of the tenth transistor T10 is connected to the pull-up node Qn of the current stage, and the first terminal of the eleventh transistor T11 is connected to the drive output module 140.

[0071] For example, when the control terminals of the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 receive the transmission signal from the (n+j)th stage transmission output module 120, they will be turned on. The ninth transistor T9 pulls down the pull-up node Qn of the current stage to a low potential, the tenth transistor T10 pulls down the drive control node Qsn of the current stage to a low potential, and the eleventh transistor T11 pulls down the output terminal of the drive output module 140 of the current stage to a low potential, so as to stop the output of the gate drive signal of the current stage to refresh the pixel, so as to recharge the pull-up node Qn of the current stage when the next scan frame arrives.

[0072] In some embodiments, the nth stage gate driving unit 100 further includes a noise reduction module 160, which is connected to the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the output terminal of the stage transmission output module 120 of the current stage, and the output terminal of the drive output module 140 of the current stage, and is configured to perform noise reduction on the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the output terminal of the stage transmission output module 120 of the current stage, and the output terminal of the drive output module 140 of the current stage when there is no voltage on the pull-up node Qn of the current stage.

[0073] It should be noted that the first brush control terminal SW1, the second brush control terminal SW2, and the reset control terminal Reset can all be output terminals of the timing controller. Each gate drive unit is connected to the first brush control terminal SW1, the second brush control terminal SW2, and the reset control terminal Reset. When the first brush control terminal SW1 sends the first brush control signal, the second brush control terminal SW2 sends the second brush control signal, and the reset control terminal Reset sends the reset control signal, each gate drive unit can receive them.

[0074] Figure 7 A flowchart illustrating a gate circuit driving method according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 7As shown, the gate circuit driving method provided in this application is applied to the gate driving circuit described above, and the method includes the following steps S101 to S104.

[0075] S101, the pull-up module responds to the output signal of the ni-th stage gate drive unit and charges the pull-up node of the current stage.

[0076] S102, the stage transmission module outputs the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage.

[0077] S103, in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, the partial refresh control module controls the pull-up node of the current level to be electrically connected to the drive control node of the current level; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, at the start of the (n+di)-th level clock signal, the partial refresh control module controls the pull-up node of the current level to be disconnected from the drive control node of the current level, and at the start of the (ni)-th level clock signal, the partial refresh control module charges the drive control node of the current level. S104, the drive output module outputs the gate drive signal of the current stage under the action of the voltage of the current stage drive control node and the current stage clock signal.

[0078] It should be noted that the working principle of the gate drive method is the same as that of the gate drive circuit, and will not be repeated here.

[0079] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output module of the gate driving circuit is connected to at least one scan line.

[0080] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0081] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0082] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node of the current stage in response to the output signal of the nith stage gate drive unit. The stage transmission module is connected to the pull-up node of the current stage and the clock signal line of the current stage, and is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage. The local refresh control module, connected to the pull-up node and the drive control node of the current level, is configured to: in local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node of the current level to be electrically connected to the drive control node of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level clock signal, control the pull-up node of the current level to be disconnected from the drive control node of the current level, and at the start of the (ni)th level clock signal, charge the drive control node of the current level under the voltage of the drive control node of the current level; The drive output module, connected to the drive control node and clock signal line of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The local brush control module includes: The first control submodule, connected to the first refresh control terminal, the pull-up node of the current level, and the current drive control node of the current level, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node of the current level and the drive control node of the current level to be electrically connected according to the first refresh control signal; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level clock signal, control the pull-up node of the current level and the drive control node of the current level to be disconnected according to the first refresh control signal and the voltage of the current drive control node; The second control submodule, connected to the level transmission output module of the nj level and the precharge control node of the current level, is configured to charge the precharge control node of the current level under the action of the level transmission signal of the nj level. The third control submodule is connected to the precharge control node of the current level, the drive control node of the current level, and the second brush control terminal. When the clock signal of the ni level starts, it charges the drive control node of the current level under the action of the voltage of the precharge control node of the current level, the voltage of the drive control node of the current level, and the second brush control signal.

3. The gate driving circuit according to claim 2, characterized in that, The first control submodule includes: a first transistor; The control terminal of the first transistor is connected to the first local brush control terminal, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the drive control node of the current stage.

4. The gate driving circuit according to claim 2, characterized in that, The second control submodule includes: a second transistor and a first capacitor; The control terminal of the second transistor is connected to the stage output module of the njth stage, the first terminal of the second transistor is connected to the stage output module of the njth stage or the high-level terminal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the precharge control node of the current stage.

5. The gate driving circuit according to claim 2, characterized in that, The third control submodule includes: a third transistor and a fourth transistor; The control terminal of the third transistor is connected to the control terminal of the second local brush, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor. The control terminal of the fourth transistor is connected to the drive control node of the current stage, and the second terminal of the fourth transistor is connected to the drive control node of the current stage. Alternatively, the control terminal of the third transistor is connected to the drive control node of the current stage, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor. The control terminal of the fourth transistor is connected to the control terminal of the second brush, and the second terminal of the fourth transistor is connected to the drive control node of the current stage.

6. The gate driving circuit according to claim 2, characterized in that, The nth-stage gate driving unit further includes: The reset submodule, connected to the precharge control node of the current level, is configured to reset the precharge control node of the current level during the vertical blanking period.

7. The gate driving circuit according to claim 6, characterized in that, The reset submodule includes: a fifth transistor; The control terminal of the fifth transistor is connected to the reset control terminal, the first terminal of the fifth transistor is connected to the precharge control node of the current stage, and the second terminal of the fifth transistor is connected to the low-level terminal.

8. The gate driving circuit according to claim 1, characterized in that, The stage transmission module includes: a sixth transistor and a second capacitor; The control terminal of the sixth transistor is connected to the first terminal of the second capacitor at the pull-up node of the current stage. The first terminal of the sixth transistor is connected to the clock signal line of the current stage. The second terminal of the sixth transistor is connected to the second terminal of the second capacitor and serves as the output terminal.

9. A method for driving a gate circuit, characterized in that, Applied to the gate drive circuit according to any one of claims 1-8, the method comprises: The pull-up module responds to the output signal of the ni-th stage gate drive unit and charges the pull-up node of the current stage; The stage transmission module outputs the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage; In partial refresh mode, if the current level is a non-refresh line and the (n+d)th level is a refresh line, at the start of the non-overlapping period of the (n+d)th level clock signal, the partial refresh control module controls the pull-up node of the current level to be electrically connected to the drive control node of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level clock signal, the partial refresh control module controls the pull-up node of the current level to be disconnected from the drive control node of the current level, and at the start of the (ni)th level clock signal, the partial refresh control module charges the drive control node of the current level. The drive output module outputs the gate drive signal of the current stage under the influence of the voltage of the drive control node of the current stage and the clock signal of the current stage.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-8, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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