Micro display chip, control method thereof and electronic device

Abstract

This invention discloses a control method for a microdisplay chip. In response to power-on of the microdisplay chip, the method initializes and configures the chip, causing it to enter an idle mode. Then, in response to a first event, it controls the chip to enter a sleep mode. Subsequently, while the chip is in sleep mode, in response to a second event, it controls the chip to exit sleep mode and enter an idle mode. By adding a sleep mode, only some modules are shut down in non-display mode, thereby accelerating the restart speed and improving the efficiency of the host computer control.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to a microdisplay chip and its control method, as well as an electronic device. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) microdisplay chips are a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. They integrate arrayed micron-sized LED units on an active addressable driver panel to enable the lighting and individual control of the LED units, thereby outputting the desired display image.

[0003] Existing microdisplay chips typically enter a power-saving mode (DPD) after power-on, following prolonged inactivity or upon receiving a standby command from a host computer. In this mode, most modules within the microdisplay chip are powered down to minimize power consumption. Re-entering the operating mode requires a power-on reset or external reset, resulting in low overall control efficiency. In some applications, such as AR glasses, the chip automatically enters DPD mode when not in wear mode, and then automatically re-enters operating mode upon being worn. However, if the aforementioned method is used, the wake-up process is time-consuming, often resulting in a period of black screen for the user after wearing the AR glasses, leading to a poor user experience. Summary of the Invention

[0004] To address some or all of the problems in the prior art, the first aspect of the present invention provides a control method for a microdisplay chip, comprising:

[0005] In response to the power-on of the microdisplay chip, the microdisplay chip is initialized and configured, causing the microdisplay chip to enter idle mode;

[0006] In response to the occurrence of the first event, the microdisplay chip is controlled to enter sleep mode; and

[0007] When the microdisplay chip is in the sleep state, in response to the occurrence of the second event, the microdisplay chip is controlled to exit the sleep mode and enter the idle mode.

[0008] Furthermore, in response to the power-on of the microdisplay chip, the initialization configuration of the microdisplay chip includes:

[0009] The configuration parameters are read from the one-time programmable storage module (Efuse) to configure the microdisplay chip.

[0010] Furthermore, in response to the power-on of the microdisplay chip, the initialization configuration of the microdisplay chip also includes:

[0011] The compensation information is read from the external flash memory by the Flexible Memory Controller (FMC) and stored in the compensation cache component.

[0012] Furthermore, the compensation information includes demura data and gamma data, which are used to compensate and optimize the original image data.

[0013] Furthermore, the control method further includes:

[0014] When the microdisplay chip is in the idle mode, in response to the display command sent by the host computer, the microdisplay chip is controlled to enter the display mode and display image information.

[0015] Furthermore, controlling the microdisplay chip to enter the display mode includes:

[0016] When the control display signal DISP_ON is high, the display mode is triggered.

[0017] Furthermore, the control method further includes:

[0018] When the microdisplay chip is in the display mode, the microdisplay chip switches from the display mode to the idle mode when the control display signal DISP_ON switches from a high level to a low level.

[0019] Furthermore, the control method further includes:

[0020] When the microdisplay chip is in the idle mode, the display mode parameter is changed accordingly, and the microdisplay chip is controlled to switch between video display mode and command display mode.

[0021] Furthermore, the display mode parameter has two values, 1 and 0. The default value of the display mode parameter is 1. When the display mode parameter is 1, the microdisplay chip is in video display mode, and when the display mode parameter is 0, the microdisplay chip is in instruction display mode.

[0022] Furthermore, the first event includes:

[0023] Within a first specified time period after the microdisplay chip is powered on, the microdisplay chip does not receive a display command; or

[0024] The microdisplay chip received a sleep command.

[0025] Furthermore, when the microdisplay chip is in the sleep mode, the internal clock and analog submodule of the microdisplay chip are turned off.

[0026] Furthermore, the second event includes:

[0027] The microdisplay chip receives a display command; or

[0028] The microdisplay chip received a command to exit sleep mode.

[0029] Furthermore, the control method further includes:

[0030] The microdisplay chip is controlled by registers to switch between the sleep mode and the idle mode.

[0031] Furthermore, the control method further includes:

[0032] In response to the occurrence of the third event, all modules of the microdisplay chip are shut down, and the microdisplay chip is controlled to enter power-saving mode (DPD, Deep Power Down).

[0033] Furthermore, the third event includes:

[0034] Within a second specified time period after the microdisplay chip enters the idle mode or sleep mode, the microdisplay chip does not receive a display command; or

[0035] The microdisplay chip receives a command from the host computer to enter power-saving mode.

[0036] Furthermore, the control method further includes:

[0037] When the microdisplay chip is in the power-saving mode, in response to a power-on or external reset signal, the microdisplay chip is controlled to re-initialize and configure itself.

[0038] Furthermore, the control method further includes:

[0039] When the microdisplay chip is in idle mode, in response to a software reset command generated inside the microdisplay chip, the microdisplay chip is controlled to re-initialize and configure itself.

[0040] A second aspect of the present invention provides a microdisplay chip that employs the control method described above.

[0041] A third aspect of the present invention provides an electronic device comprising:

[0042] A detection module, used to detect the usage status of the electronic device;

[0043] A control module, communicatively connected to the detection module, is used to generate control commands based on the usage state and send them to the microdisplay chip; and

[0044] The microdisplay chip described above is communicatively connected to the control module and operates based on the control commands.

[0045] The present invention provides a microdisplay chip and its control method, which, compared with existing microdisplay chips, adds a sleep mode. In the sleep mode, some sub-modules of the microdisplay chip are still powered on, so when the display operation needs to be restarted, no initialization configuration is required, and the chip can quickly enter the corresponding display mode. The overall restart time is short, the control is convenient, and the control efficiency of the host computer is effectively improved. Attached Figure Description

[0046] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0047] Figure 1 This diagram illustrates the structure of a microdisplay chip according to an embodiment of the present invention.

[0048] Figure 2 This diagram illustrates the structure of a second interface submodule according to an embodiment of the present invention.

[0049] Figure 3 This diagram illustrates the structure of an I / O control component according to an embodiment of the present invention.

[0050] Figure 4a and 4b This diagram illustrates the data flow when a first interface submodule is used in one embodiment of the present invention.

[0051] Figure 5 This diagram illustrates the data flow when a second interface submodule is used in one embodiment of the present invention.

[0052] Figure 6 A schematic diagram of a single-layer micro light-emitting diode structure according to an embodiment of the present invention is shown.

[0053] Figure 7A schematic diagram of a single-layer micro light-emitting diode structure according to another embodiment of the present invention is shown; and

[0054] Figure 8 This is a schematic flowchart illustrating a control method for a microdisplay chip according to an embodiment of the present invention. Detailed Implementation

[0055] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0056] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0057] It should be noted that the embodiments of the present invention describe the process steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.

[0058] In power-saving mode, microdisplay chips require a power-on restart to re-initialize and configure themselves before re-entering the operating state. This power-on restart via a host computer is time-consuming, typically around 100 milliseconds. Alternatively, an external reset can restart the microdisplay chip, taking less time (approximately 10-100 microseconds). However, upon receiving the external reset command, the microdisplay chip still needs to perform initialization and configuration. This process requires reading configuration parameters from efuse, taking at least 4 milliseconds. If external flash data is needed, this process takes approximately 70 milliseconds, resulting in a still significant time consumption. This leads to inefficient host computer control of the microdisplay chip and negatively impacts user experience. To improve the efficiency of host computer control, this invention provides a microdisplay chip control method that incorporates a sleep mode. Under specific conditions, only certain sub-modules within the microdisplay chip are shut down, eliminating the need for re-initialization and configuration upon returning to the operating mode, effectively shortening the restart time.

[0059] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0060] Figure 1 A schematic diagram of a microdisplay chip according to an embodiment of the present invention is shown. Figure 1 As shown, the microdisplay chip includes a control module 001 and a display module 002, both of which are disposed on a substrate 003. The display module 002 is electrically connected to the control module 001 via a metal interconnect structure, such as metal pillars. The control module 001 is used to control the display module 002 to display images. The display module 002 includes a micro light-emitting diode (Micro LED) array, which can realize three-color combined color display or monochrome display.

[0061] like Figure 1 As shown, the control module interface submodule is used to receive control signals and raw data from the host computer and transmit them to the internal structure of the microdisplay chip. To improve compatibility with the host computer, in one embodiment of the invention, the interface submodule may include multiple submodules, each supporting different transmission protocols with different transmission rates. In one embodiment of the invention, the control module includes a first interface submodule 101 and a second interface submodule 102. As previously mentioned, the first interface submodule 101 and the second interface submodule 102 employ different transmission protocols.

[0062] like Figure 1As shown, in one embodiment of the present invention, the first interface submodule 101 employs the MIPI DPHY physical layer protocol and the DSI protocol layer, and the first interface submodule 101 includes a DPHY DSI interface. Figure 1 As shown, the DPHY DSI interface includes CKN pin, CKP pin, DP0 pin, and DN0 pin, wherein the CKN pin and CKP pin are connected to the MIPI clock differential signal, and the DP0 pin and DN0 pin are connected to the MIPI data differential signal. In one embodiment of the present invention, the first interface submodule further includes a data processing component (DSI Process), which is used to unpack the DSI packet format data and reassemble the unpacked signals into signals that conform to the timing requirements of the control module.

[0063] like Figure 1 As shown, in one embodiment of the present invention, the second interface submodule 102 adopts the QSPI transmission protocol. Figure 1 As shown, the second interface submodule 101 includes an SCLK pin, a CSB pin, and IO[0] to IO[3] pins. The SCLK pin is connected to the clock line to provide a clock signal and control the data transmission rate. The CSB pin is connected to the chip select line to select the connected slave device. The IO[0] to IO[3] pins are connected to the data lines, which can be used as inputs or outputs to support four-way parallel data transmission.

[0064] The control module, especially the DPHY DSI interface, often requires configuration of corresponding functions via registers during actual use. These register parameters can be transmitted via a low-speed serial port interface. Based on this, in one embodiment of the present invention, an I... 2 The C interface is used to transmit configuration parameters for configuring registers, etc.

[0065] In one embodiment of the present invention, in order to save I / O overhead, the I... 2 The C interface is multiplexed with the QSPI interface of the second interface submodule; specifically, it is the I... 2 The SCL pin of the C interface is multiplexed with the IO[2] pin of QSPI, and the I... 2 The SDA pin of the C interface is multiplexed with the IO[3] pin of QSPI.

[0066] Figure 2 A schematic diagram of the structure of a second interface submodule according to an embodiment of the present invention is shown. Figure 2 As shown, the second interface submodule includes an I / O control component (QSPI / I). 2 C IO_Ctrl), I 2 C control component (I2 The system includes a C_Controller and a QSPI control component (QSPI_Controller). The I / O control component receives control signals and raw data transmitted from the host computer, determines the data transmission protocol based on the data format, and further transmits the data packets received by the I / O pins to the QSPI_Controller or I_Controller according to the transmission protocol. 2 C_Controller and QSPI_Controller are used for QSPI transmission control. They decode the relevant control signals and data of the QSPI protocol and transmit them to the internal control module, as well as I... 2 C_Controller is used for I 2 C transmission control, which will I 2 The relevant control signals and data of the C protocol are decoded and transmitted to the internal control module.

[0067] Figure 3 A schematic diagram of the structure of an I / O control component according to an embodiment of the present invention is shown. Figure 3 As shown, the IO control component mainly includes a multiplexer MUX and a demultiplexer DEMUX. The first demultiplexer is used to transmit the signals transmitted between the IO[2] and SCL multiplexed pins to the QSPI_Controller or I based on the selection signal SELECT. 2 C_Controller, the second demultiplexer is used to pass the signal transmitted by the IO[3] and SDA multiplexed pin to QSPI_Controller or I based on the select signal SELECT. 2 C_Controller, and the multiplexer are used to select QSPI_Controller or I according to the selection signal SELECT. 2 The signals sent by C_Controller are transmitted to the IO[3] and SDA multiplexed pins, and then transmitted to the host computer. It should be understood that QSPI or I 2 During a single data packet transmission, the select signal SELECT remains unchanged. This, combined with the multiplexer MUX and demultiplexer DEMUX, ensures that at most one controller port is connected to the corresponding pin during a single transmission, guaranteeing QSPI transmission and I / O. 2 There will be no conflicts between C transmissions.

[0068] In one embodiment of the present invention, the select signal SELECT is written externally, for example, through an IO pin or by one-time programming to store settings such as Efuse and OTP.

[0069] In another embodiment of the present invention, the select signal SELECT is configured via an internal register. Configuration via an internal register is more flexible than external control and can further reduce I / O overhead. Therefore, the control module also includes a registers array. The registers array is communicatively connected to the second interface submodule and is used to store the configuration parameters of the second interface submodule. In other embodiments of the present invention, the registers array can also be used to configure the functions and settings of the first interface submodule, i.e., the DPHYDSI interface. In one embodiment of the present invention, the registers array mainly controls the multiplexing selection of the pin by setting two parameters: i2c_lock and qspi_lock. If i2c_lock is 0 and qspi_lock is also 0, or i2c_lock is 1 and qspi_lock is also 1, then the QSPI protocol and I... 2 Both C protocols can be used. In this case, it is necessary to determine the SELECT signal based on the data transmitted from the host computer, that is, to determine whether the data on the multiplexed pin is transmitted to QSPI_Controller or I. 2 C_Controller. Specifically, the SELECT signal is determined based on the CSB pin state. When the host computer uses the QSPI protocol for transmission, the CSB pin is low. In this case, the I / O control component will transmit the data from the multiplexed pin to the QSPI_Controller. 2 C_Controller has no data transmission, when the host computer uses I 2 During C protocol transmission, when the CSB pin is high, the IO control component will transmit the data from the multiplexed pin to the I / O pin. 2 C_Controller, at this time QSPI_Controller has no data transmission. If i2c_lock is 1 and qspi_lock is 0, then I 2 The C protocol is locked, and the QSPI protocol function is disabled, meaning the second interface submodule only supports I... 2 C protocol. At this time, when the host computer uses the QSPI protocol for transmission, although the CSB pin will go low, the QSPI protocol function is disabled, and QSPI_Controller and I... 2 C_Controller will not transmit data when the host computer uses I. 2 During C protocol transmission, when the CSB pin is high, the IO control component will transmit the data from the multiplexed pin to the I / O pin. 2C_Controller, at this time QSPI_Controller has no data transmission. If i2c_lock is 0 and qspi_lock is 1, then the QSPI protocol is locked. 2 The C protocol function is disabled, meaning the second interface submodule only supports the QSPI protocol. In this case, when the host computer uses I... 2 During C protocol transmission, although the CSB pin will remain high, due to I 2 The C protocol functionality is disabled, at which point QSPI_Controller and I... 2 C_Controller will not transmit data. When the host computer uses the QSPI protocol for transmission, the CSB pin goes low. At this time, the I / O control component will transmit the data from the multiplexed pin to QSPI_Controller. 2 No data is being transmitted to C_Controller.

[0070] Through pin multiplexing, the host computer can use QSPI / I 2 The two protocol standards (C and C) enable directional data transmission with the control module, resulting in low overall wiring complexity and no additional I / O overhead. This allows it to be adapted to more types of host computers and has a wider range of compatibility.

[0071] Back Figure 1In one embodiment of the present invention, to improve the display effect, a data processing submodule Algo is also built into the control module. Algo incorporates various image processing algorithms to optimize and improve the data transmitted from the host computer, thereby enhancing the display quality. In one embodiment, Algo includes multiple compensation algorithms, such as demura compensation and gamma compensation, as well as image adjustment algorithms such as rotation and flip processing. Demura compensation primarily addresses brightness and color unevenness by acquiring the gamma value of the demura pixels and calculating the corresponding grayscale values ​​to be compensated for each demura pixel at each grayscale level, based on a target gamma value. Then, it performs corresponding compensation processing on the demura pixels according to the calculation results, thereby eliminating brightness and color unevenness on the display panel. Gamma compensation adjusts the image brightness to better match the perceptual characteristics of the human eye. Specifically, it adjusts the image's gamma curve to make the dark areas of the image clearer and the bright areas relatively blurred, thus improving the overall visual effect of the image. In one embodiment of the present invention, the data processing submodule Algo can configure whether its built-in algorithms are enabled via a register configuration array (Registers array). Simultaneously, some parameters and / or calculated values ​​required by the algorithms can be stored in a compensation cache component. In one embodiment of the present invention, the compensation cache component includes a demura buffer and a gamma buffer, wherein the demura buffer is used to store demura data, and the gamma buffer is used to store gamma data. In practical applications, the data processing submodule Algo reads the data in the demura buffer and / or gamma buffer, performs calculations with the original data transmitted from the host computer, optimizes the original data, and converts it into data to be displayed, resulting in a more perfect display.

[0072] In one embodiment of the present invention, the control module embeds two data buffer components: a frame buffer and a line buffer. Based on this, the control module can implement both video mode control and command mode control. Video mode involves writing data line by line into the line buffer and displaying it by scrolling through the buffers. Video mode has low latency and is advantageous in high-speed mobile environments. Command mode, on the other hand, writes the entire frame of data into the frame buffer and then loads it into the display module's own storage component. It then performs scanning and display via line control. Command mode allows for partial refresh, thus requiring lower drive speed from the host computer and resulting in lower power consumption. In command mode, if the data to be displayed changes, it is not necessary to transmit the entire frame of data; only a portion of the data needs to be modified.

[0073] In embodiments of the present invention, when using the first interface submodule, i.e., the MIPI protocol, both video mode and command mode can be supported simultaneously. If video mode is used, such as... Figure 4a As shown, the data received through the first interface submodule is first reassembled into a signal conforming to the timing requirements of the control module via the DSI Process. The reassembled signal is then optimized line by line by the data processing submodule Algo. The data required for compensation calculations is read from the gamma buffer and / or demura buffer. The optimized data to be displayed is stored line by line in the line buffer and then fed into the display module via the display control submodule for line-by-line scrolling and display. It can be seen that in video mode, the data transmission rate requirement is higher. If command mode is used, such as... Figure 4b As shown, the data received through the first interface submodule is first reconstructed into a signal conforming to the timing requirements of the control module via the DSI Process. Then, one frame or part of the reconstructed image data is written into the data processing submodule Algo according to the row and column addresses for optimization processing. The data required for compensation calculation is read from the gamma buffer and / or demura buffer. The optimized data is stored in the corresponding address space of the frame buffer according to the row and column addresses. Finally, the entire data is loaded into the display module through the display control submodule. In addition, while transmitting image data using the MIPI protocol, it is also possible to further transmit the data through the I in the second interface submodule. 2The C interface writes configuration parameters into the register configuration array Registersarray, which then passes them to other sub-modules or components, thereby configuring algorithms or display modes in the data processing sub-module Algo.

[0074] When using the second interface submodule, namely the QSPI protocol, the QSPI protocol has relatively low transmission efficiency, so it is difficult to support the video mode with high latency requirements, and only supports the command mode. In this case, the line buffer does not participate in data transmission and image display. Figure 5 This diagram illustrates the data flow when a second interface submodule is used in one embodiment of the present invention. Figure 5 As shown, when using the QSPI protocol, configuration parameters are first written to the Registers array via the QSPI protocol, and then passed to other submodules or components. This allows for the configuration of algorithms or display modes in the data processing submodule Algo. Then, a frame or portion of image data received by the second interface submodule is written to the data processing submodule Algo according to row and column addresses for optimization processing. The data required for compensation calculations is read from the gamma buffer and / or demura buffer. The optimized data is stored in the corresponding address space of the frame buffer according to the row and column addresses, and finally, the entire data is loaded into the display module via the display control submodule.

[0075] As mentioned above, in embodiments of the present invention, data needs to be fed into the display module through the display control submodule, and the display of the image needs to be controlled. Figure 1As shown, in one embodiment of the present invention, the display control submodule includes a display control component, a row control component, and a column control component. The display control component is used to read data to be displayed from the frame buffer or line buffer according to the working mode, and further control the row and column control components to achieve image display. Specifically, the display control drives the image data in the frame buffer or line buffer to the row control and column control according to the synchronization flag and display configuration parameters, thereby writing the data to the display module. Then, the display control controls the display module to display the corresponding data according to the configuration parameters. Furthermore, in one embodiment of the present invention, the host computer can also query or debug the status of the chip by reading data or status information in the Registers array, frame buffer, and line buffer. In one embodiment of the present invention, the row control component is used to control the scanning of the display area of ​​the display module, and the column control component is used to transmit data to the display module.

[0076] In one embodiment of the present invention, such as Figure 1 As shown, the gamma buffer, demura buffer, line buffer, and frame buffer all communicate with the data processing submodules or components such as Algo and DSI Process through the bus interconnect submodule Bus Matrix.

[0077] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a temperature compensation submodule LTC, which is communicatively connected to the display control submodule and is used to compensate display brightness according to temperature.

[0078] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a Flexible Memory Controller (FMC) for controlling external flash memory.

[0079] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a test control submodule, which is used for the test control of the chip.

[0080] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes an IP switching submodule SW, which switches between the internal OSC and the external clock input, as well as the internal POR.

[0081] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a one-time programming storage module (Efuse), which is used to store some or all of the configuration parameters of the control module.

[0082] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes an internal oscillator (OSC) for generating the internal clock of the control module.

[0083] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a temperature detection submodule PVT, which is used to obtain the temperature of the control module, thereby ensuring that the internal temperature of the chip does not become too high and avoid burning out the chip.

[0084] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a power-on reset submodule POR, which is used for power-on reset to ensure that the chip operates under a relatively stable voltage.

[0085] In one embodiment of the present invention, such as Figure 1 As shown, the control module also includes a clock and reset module CRG, which is used to provide external clock and reset signals EXCKIN and EXRSTN.

[0086] The circuit structures and functions of LTC, FMC, test control, SW, Efuse, OSC, PVT, POR, and CRG can be implemented using conventional techniques in this field, and will not be elaborated here.

[0087] In one embodiment of the present invention, the display module 002 includes a micro-light-emitting diode array. As mentioned above, in embodiments of the present invention, the control module can be used for both three-color combining to achieve color display and monochrome display. Therefore, in some embodiments, the micro-light-emitting diode array may include a single-layer micro-light-emitting diode structure formed in an array form, such as... Figure 6 and Figure 7 As shown.

[0088] Figure 6 A cross-sectional schematic diagram of a micro light-emitting diode structure according to an embodiment of the present invention is shown. Figure 6 As shown, the micro light-emitting diode structure includes a pixel driving backplate 110, a lower electrode layer 120, a conductive layer 130, a light-emitting mesa 140, an upper electrode layer 150, a passivation layer 160, and a microlens 170.

[0089] For convenience, “up” is used to indicate away from the pixel driving backplate 110, “down” indicates towards the pixel driving backplate 110, and other directional terms such as top, bottom, above, below, directly below, and below are also explained accordingly.

[0090] Miniature light-emitting diodes (LEDs) are the basic components that make up a pixel in a miniature LED. Each miniature LED pixel can include one or more miniature LED structures. Multiple miniature LED pixels arranged in an array constitute a miniature LED display or a miniature LED chip. For example, each pixel in a color miniature LED chip can include multiple miniature LED structures of different colors, while each pixel in a monochrome miniature LED chip can include only one color of miniature LED structure.

[0091] In embodiments of the present invention, the size of each micro-LED chip is no more than 1 cm, preferably no more than 20 micrometers. The micro-LED structures are formed in an array within the micro-LED chips, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro-LED structures is in the nanometer range, for example, 20 nm to 100 nm. In some embodiments, the spacing of the micro-LED array, i.e., the minimum center-to-center distance between the micro-LEDs, can be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro-LED chip can be between thousands and millions.

[0092] In some embodiments, the pixel driving backplane 110 may employ an integrated circuit chip. The pixel driving backplane 110 includes a substrate, driving circuitry, and contact pads 111. Each micro-LED corresponds to one contact pad 111, and the contact pads 111 are electrically connected to the lower electrode layer 120. Each driving circuit is a pixel driver. In some cases, the driving circuitry is a thin-film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the pixel driving backplane 110 is a Si substrate. In another embodiment, the substrate of the pixel driving backplane 110 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. The pixel driving backplane 110 is used to control the lighting and extinguishing of the micro-LEDs within each pixel. In one embodiment, the material of the contact pads 111 is one or more alloys of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0093] In some embodiments of the present invention, a pixel driving backplane may be electrically connected to each micro-light-emitting diode in a micro-light-emitting diode array via separate metal interconnects. In some embodiments, each micro-light-emitting diode may be electrically controlled individually by the pixel driving backplane. In some embodiments, the pixel driving backplane may be electrically connected to the electrodes of the micro-light-emitting diode chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the micro-light-emitting diodes. In some embodiments, a dielectric layer may also be formed in the gaps between interconnects.

[0094] In one embodiment, the lower electrode layer 120 may be a metal bonding composite layer. The light-emitting mesa 140 of the micro-LED can be bonded to the surface of the pixel driving backplane 110 via the metal bonding composite layer 120, and the bonding can be accomplished by methods such as eutectic bonding, thermo-press bonding, and transient liquid phase (TLP) bonding. In one embodiment, the metal bonding composite layer 120 may be disposed on the pixel driving backplane 110. In another embodiment, the metal bonding composite layer 120 is grown on the pixel driving backplane 110. In one embodiment, the thickness of the metal bonding composite layer 120 is 0.1 μm to 3 μm. In a preferred embodiment, the thickness of the metal bonding composite layer 120 is 0.3 μm. In some embodiments, the material of the metal bonding composite layer 120 is one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The metal bonding composite layer 120 may include an ohmic contact layer and a metal bonding layer. In some cases, the metal bonding composite layer 120 includes two metal layers. One of the two metal layers is deposited on a layer above the metal bonding layer within the LED. The corresponding bonding metal layer is deposited on the pixel driver backplane 110. For example, the metal bonding composite layer 120 can be Au-Au bonding, Au-Sn bonding, Au-In bonding, Ti-Ti bonding, Cu-Cu bonding, or a combination thereof. For example, if Au-Au bonding is chosen, the two Au layers require a Cr layer as a binder and a Pt layer as an anti-diffusion layer, respectively. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located at the top and bottom of the two bonded Au layers. In some embodiments, when the two Au layers are of approximately the same thickness, the Au on the two layers diffuses into each other under high pressure and high temperature, bonding the two layers together.

[0095] In some embodiments, the metal-bonded composite layer 120 may also be used as a reflector to reflect light emitted from the upper light-emitting platform 140.

[0096] In some embodiments, a conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 to form an electrical connection between the light-emitting mesa 140 and the metal bonding composite layer 120. In some embodiments, the conductive layer 130 may be a conductive transparent layer that is transparent to the light emitted by the light-emitting mesa 140 to improve conductivity and light transmittance. In some embodiments, an upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the upper electrode layer 150 is electrically connected to a current spreading structure or a top electrode (not shown).

[0097] In one embodiment, the conductive layer 130, the upper electrode layer 150, and their connecting components may be one or more of graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0098] The light-emitting mesa 140 includes a first-type epitaxial layer 141, a second-type epitaxial layer 143, and a light-emitting layer 142 located between them. The first-type epitaxial layer 141 is electrically connected to the conductive layer 130. The second-type epitaxial layer 143 is electrically connected to the upper electrode layer 150. In some embodiments, the light-emitting mesa of each micro-LED in the micro-LED array can be a micrometer-scale light-emitting mesa. In the three-layer structure, the first-type epitaxial layer 141 is closest to the driving backplane 110; the light-emitting layer 142 is located above the first-type epitaxial layer and further away from the driving backplane 110; the second-type epitaxial layer 143 is located above the light-emitting layer 142 and is furthest away from the driving backplane 110. In some embodiments, the light-emitting layer 142 is formed of a plurality of stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer 141 is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The primary substrate material of the first type epitaxial layer 141 may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the first type epitaxial layer 141 may, from top to bottom, include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; additionally, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer 143 is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary substrate material of the second type epitaxial layer 143 may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the second type epitaxial layer 143 may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0099] In some embodiments, the first type epitaxial layer 141 is an N-type GaN layer or an N-type AlGaN layer, and the second type epitaxial layer 143 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type epitaxial layer 143 can be a material layer of a second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first type epitaxial layer 141 can be a material layer of a first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 142 includes a multi-quantum well layer and an electron blocking layer. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 142 further includes an electron blocking layer disposed on a first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type epitaxial layer 141 may also be a P-type GaN layer or a P-type AlGaN layer, and the second type epitaxial layer 143 may be an N-type GaN layer or an N-type AlGaN layer.

[0100] In some embodiments, the light-emitting layer 142 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0101] In some embodiments, one of the first type epitaxial layer 141 and the second type epitaxial layer 143 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al. x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. Furthermore, in these embodiments, the thickness of the N-type cladding layer is no greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e⁻¹. 17 cm -3 up to 1e 18 cm -3The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e⁻¹. 18 cm -3 up to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm.

[0102] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al. x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such embodiments, the thickness of the P-type cladding layer is no greater than 380 nm, for example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0103] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first-doped P-type transition layer formed on the P-type cladding layer, and a second-doped P-type transition layer formed on the first-doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0104] In some embodiments, the material of the first doped P-type transition layer is (Al) x Ga 1-x ) y In 1-yP, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example, 30 nm.

[0105] In some embodiments, the material of the second doped P-type transition layer is Al. x Ga 1-x As, where x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0106] In some embodiments, the doping concentration of the second-doped P-type transition layer is greater than the doping density of the first-doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second-doped P-type transition layer.

[0107] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second-doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second-doped P-type transition layer is 2 to 4 times that of the first-doped P-type transition layer.

[0108] For example, the doping concentration of the first doped P-type transition layer is greater than 1e. 18 cm -3 The doping density of the second-doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 Within the range, the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0109] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first type epitaxial layer 141, while the electrode polarity of the upper electrode layer 150 is determined by the second type epitaxial layer 143. The electrode polarity of the conductive layer 130 is opposite to that of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 can be an electrode with a polarity opposite to that of the conductive layer 130, such as an N electrode or a cathode electrode, and vice versa.

[0110] In one embodiment, the light-emitting mesa 140 may be a platform with a trapezoidal cross-section, wherein the bottom lateral dimension of the light-emitting mesa is greater than the top lateral dimension. The sidewalls of the semiconductor light-emitting mesa 140 have an inclination angle with the bottom of the semiconductor light-emitting mesa, which is less than or equal to 90°. In one embodiment, the inclination angle of the sidewalls of the light-emitting mesa ranges from 45° to 90°. In one embodiment, the bottom lateral dimension of the light-emitting mesa exceeds 2 micrometers. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 micrometers. In one embodiment, the lateral dimension of the metal bonding composite layer is greater than the bottom lateral dimension of the light-emitting mesa.

[0111] In some embodiments, the light-emitting platform 140 may emit red, blue, green, or other colors of light.

[0112] In some embodiments, the passivation layer 160 covers the sides of the metal bonding composite layer 120, the conductive layer 130, and the light-emitting mesa 140. In some embodiments of the present invention, the passivation layer 160 may also cover a portion of the sides of the upper electrode layer 150, with a portion of the top surface of the upper electrode layer 150 exposed to form an electrical connection with the top electrode. In other embodiments of the present invention, the passivation layer 160 does not cover the top and sides of the upper electrode layer 150, allowing the upper electrode layers 150 of adjacent LED structures to be interconnected to form a common cathode or anode. In some embodiments of the present invention, the passivation layer 160 covers the sides of the metal bonding composite layer 120, the conductive layer 130, the first type epitaxial layer 141, the light-emitting layer 142, and a portion of the sides of the second type epitaxial layer 143.

[0113] In one embodiment, the passivation layer is made of a transparent insulating material, such as one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0114] In one embodiment, an insulating medium 180 fills the gaps between the light-emitting mesa 140. The insulating medium 180 is transparent to light emitted from the light-emitting mesa 140.

[0115] In some embodiments, the insulating medium 180 is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borosilicate glass, or any combination thereof. In some embodiments, the plastic material includes polymers such as SU-8, PermiNex, benzocyclobutene (BCB), or transparent plastics (resins) including spin-coated glass (SOG), or the adhesive Micro Resist BCL-1200, or any combination thereof. In some embodiments, the insulating medium 180 may facilitate the passage of light emitted from the LED structure.

[0116] In some embodiments, a microlens 170 is formed on top of the light-emitting platform 140. The lateral dimension of the bottom of the microlens 170 may be larger than the lateral dimension of the light-emitting area of ​​the micro-LED. In some embodiments, the lateral dimension of the bottom of the microlens 170 may be equal to the lateral dimension of the light-emitting area of ​​the micro-LED.

[0117] In some embodiments, a microlens 170 may cover multiple lensless micro-light-emitting diodes (LEDs). Multiple microlenses constitute a microlens array. The microlens array is disposed above the array of micro-light-emitting diodes, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro-light-emitting diodes, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-light-emitting diodes. The microlenses are primarily used to converge and / or collimate light rays; for example, the focal point of the microlens can be located within the light-emitting mesa of the micro-light-emitting diodes by adjusting parameters such as the thickness and curvature of the microlenses. The microlenses in the microlens array are typically identical. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. In one embodiment, typical shapes of the bottom cross-section of each microlens include circular, square, rectangular, and hexagonal. The individual microlenses in the microlens array of the display panel may be identical or different in terms of shape, curvature, optical power, size, base, and spacing.

[0118] In some embodiments, the microlens 170 may be a curved hemispherical or a regular hemispherical shape. In some embodiments, the height of the microlens 170 is no greater than 2 micrometers. In some embodiments, the height of the microlens 170 is no greater than 1 micrometer. In some embodiments, the height of the microlens 170 is no greater than 0.5 micrometers. In some embodiments, the width of the microlens 170 is no greater than 4 micrometers. In some embodiments, the width of the microlens 170 is no greater than 3 micrometers. In some embodiments, the width of the microlens 170 is no greater than 2 micrometers. In some embodiments, the width of the microlens 170 is no greater than 1 micrometer. In some embodiments, the width-to-height ratio of the microlens 170 is greater than 1.5.

[0119] In some embodiments, the microlens 170 may be made of various materials that are transparent to light of various wavelengths emitted by the micro-light-emitting diode. Exemplary transparent materials for the microlens 170 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 170 is made of photoresist. In some embodiments, the microlens is deposited directly on the surface of the micro-light-emitting diode using chemical vapor deposition (CVD) technology.

[0120] Figure 7 A cross-sectional schematic diagram of a micro light-emitting diode structure according to another embodiment of the present invention is shown. Figure 7 As shown, the micro light-emitting diode structure includes a pixel driving backplate 210, a lower electrode layer 220, a conductive layer 230, a light-emitting mesa 240, an upper electrode layer 250, a passivation layer 260, a microlens 270, an insulating dielectric 280, and a reflective layer 290.

[0121] The light-emitting mesa 240 includes a first-type epitaxial layer 241, a second-type epitaxial layer 243, and a light-emitting layer 242 located between the two. The first-type epitaxial layer 241 is electrically connected to the conductive layer 230. The second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250. Figure 7 The luminous platform 240 shown is... Figure 6 The difference between the illustrated light-emitting mesa 140 and the light-emitting mesa 240 is that the cross-sectional shape of the light-emitting mesa 240 is an inverted trapezoid. The bottom lateral dimension of the light-emitting mesa is smaller than the top lateral dimension. The sidewalls of the semiconductor light-emitting mesa 140 have an inclination angle with the bottom of the semiconductor light-emitting mesa, which is greater than or equal to 90°. In one embodiment, the inclination angle of the sidewalls of the light-emitting mesa ranges from 90° to 135°.

[0122] In some embodiments, the passivation layer 260 covers the conductive layer 230 and the side surface of the light-emitting mesa 240. In some embodiments of the present invention, the tops of the second type epitaxial layers 243 of adjacent light-emitting mesa 240 are connected to each other, and the passivation layer 260 covers the bottom surface of the connected portion of the second type epitaxial layers 243. At least a portion of the bottom surface of the light-emitting mesa 240 is not covered by the passivation layer 260, and the conductive layer 230 is located on the bottom surface of the light-emitting mesa 240 and forms an electrical connection thereto. The material of the passivation layer 260 is a transparent insulating material, such as one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0123] In some embodiments, a reflective layer 290 is formed on the surface of the passivation layer 260 and the conductive layer 230 that is away from the light-emitting mesa 240.

[0124] In some embodiments, the reflective layer 290 may be a metal layer with high reflectivity, including one or more metals such as Pt, Rh, Al, Au and Ag, a stacked DBR layer including TiO2 / SiO2 layers, or any other layer with total reflection properties, including a multilayer omnidirectional reflector (ODR), or a combination thereof.

[0125] In some embodiments, the reflective layer 290 may be one or more reflective coatings. One or more reflective coatings can reflect light emitted from the light-emitting area, thereby enhancing the brightness and luminous efficiency of the micro-LED panel or display. For example, light emitted from the light-emitting area may reach one or more reflective coatings and may be reflected upwards by one or more of these coatings.

[0126] Since the reflective layer can be made of conductive material, there is a gap 291 between the reflective layers of adjacent micro-mesa structures, thereby avoiding short circuits between adjacent light-emitting mesa.

[0127] In one embodiment, an insulating medium 280 fills the gaps between the light-emitting mesa 240. The insulating medium 280 is transparent to light emitted from the light-emitting mesa 240. The material of the insulating medium 280 is similar to that of the insulating medium 180, and will not be described again for the sake of simplicity.

[0128] In some embodiments, the light-emitting mesa 240 of the micro-LED can be bonded to the surface of the pixel driving backplane 210 using a hybrid bonding process. For example, in the hybrid bonding process, an oxide bonding layer is deposited at the bottom of the light-emitting mesa structure; a corresponding oxide bonding layer is deposited on the substrate 110. Through-holes can then be formed in the oxide bonding layer and filled with metal to form a lower electrode layer 220. A CMP process can be performed on the surface of the lower electrode layer 220 so that the surface of the lower electrode layer 220 is flush with the surface of the oxide bonding layer. The light-emitting mesa 240 is then bonded to the substrate 210 under high pressure and high temperature. In some embodiments, the lower electrode layer 220 is electrically connected between the contact 211 on the substrate 210 and the light-emitting mesa 240 above the lower electrode layer 220, serving as a P-electrode.

[0129] In one embodiment, an upper electrode layer 250 is formed on the top surface of the light-emitting mesa 240, and a second type epitaxial layer 243 is electrically connected to the upper electrode layer 250. The material of the upper electrode layer 250 is similar to that of the upper electrode layer 150, and will not be described again for the sake of simplicity. In some embodiments, a microlens 270 is formed on the top of the light-emitting mesa 240. The material of the microlens 270 is similar to that of the microlens 170, and will not be described again for the sake of simplicity.

[0130] In embodiments of the present invention, the micro light-emitting diodes or other similar micro light-emitting diodes described above constitute micro light-emitting diode pixels, and multiple micro light-emitting diode pixels are arranged in an array to constitute a micro light-emitting diode display chip.

[0131] It should be understood that in other embodiments of the present invention, the display module may also employ other common micro light-emitting diode array structures in the art, and the structure of the micro light-emitting diodes is not limited to the embodiments described above.

[0132] Figure 8 The diagram illustrates a flowchart of the control method for the microdisplay chip as described above. Based on the microdisplay chip architecture described above, the microdisplay chip can include multiple operating modes through register control and other methods: idle mode, sleep mode, power-saving mode (DPD), and multiple display modes. The control method mainly controls the switching and implementation between the various modes of the microdisplay chip based on the status of the host computer and / or the control commands sent by the host computer.

[0133] like Figure 8As shown, after the microdisplay chip is powered on / externally reset, it first performs an initialization flow to enter idle mode. In idle mode, the display module 002 is turned off and does not display anything. In one embodiment of the present invention, the initialization flow includes reading configuration parameters from a one-time programming storage module to configure the microdisplay chip. In another embodiment of the present invention, the initialization flow also includes reading compensation information from external flash memory through a flexible storage controller and storing the compensation information in a compensation cache component. As mentioned above, the compensation information mainly includes demura data and gamma data, which are stored in the demura cache and gamma cache respectively after being read. The demura data and gamma data are used to compensate and optimize the original image data.

[0134] like Figure 8 As shown, in one embodiment of the present invention, in idle mode, in response to the occurrence of a first event, the microdisplay chip will enter sleep mode. In one embodiment of the present invention, the first event may include, for example, the microdisplay chip not receiving display instructions and data sent by the host computer within a specified period of time after the microdisplay chip is powered on, or the microdisplay chip receiving a sleep instruction sent by the host computer, etc. The specified period of time can be configured according to actual needs.

[0135] In one embodiment of the present invention, the microdisplay chip is put into sleep mode primarily through register control. Specifically, the internal clock of the microdisplay chip is first turned off through register control, and the analog sub-modules in the microdisplay chip, including Efuse, OSC, PVT, and POR, are also turned off through register control. It can be seen that in sleep mode, some sub-modules are turned off, therefore the overall power consumption is lower than in idle mode.

[0136] like Figure 8 As shown, in one embodiment of the present invention, in sleep mode, in response to the occurrence of a second event, the microdisplay chip will exit sleep mode and re-enter idle mode. In one embodiment of the present invention, the second event may include, for example, the microdisplay chip receiving a display command or a sleep mode exit command sent by a host computer. When a display command is received from the host computer, the microdisplay chip first exits sleep mode and enters idle mode, and then enters display mode based on the display command.

[0137] Similarly, in one embodiment of the present invention, the microdisplay chip is mainly controlled to exit sleep mode via registers. Specifically, firstly, the various analog sub-modules that were previously disabled are activated via registers, and then the internal clock of the microdisplay chip is activated via registers to enter idle mode. It can be seen that some sub-modules remain powered on in sleep mode, so when it is necessary to re-enter the working state, only individual analog sub-modules need to be enabled, without needing to reconfigure all sub-modules. Compared to power-saving mode, this significantly improves the control efficiency of the host computer.

[0138] To further reduce system power consumption in certain specific scenarios, the microdisplay chip also supports a power-saving mode. Specifically, in idle or sleep mode, the microdisplay chip will enter power-saving mode in response to the occurrence of a third event. In one embodiment of the present invention, the third event may include, for example, the following: within a specified duration of the microdisplay chip entering sleep or idle mode, the microdisplay chip does not receive any display instructions or data sent by the host computer, or the microdisplay chip receives an instruction from the host computer to enter power-saving mode, etc. The specified duration can be configured according to actual needs.

[0139] In power-saving mode, except for the Power-On Reset (POR) submodule, all other components of the microdisplay chip and its submodules are powered off, resulting in the lowest overall system power consumption. However, because all submodules are powered off, when exiting power-saving mode and re-entering the working state, each submodule needs to be re-initialized and configured after being powered on again. Furthermore, exiting power-saving mode and entering the initialization and configuration process requires either a power-on restart controlled by a host computer or an external reset operation.

[0140] like Figure 8 As shown, in one embodiment of the present invention, in idle mode, an internal software reset instruction (soft reset) can be generated to re-initialize and configure the microdisplay chip, thereby restarting the microdisplay chip.

[0141] As mentioned earlier, in idle mode, the display signal DISP_ON is low and the display module does not display anything. If image display is required, the display signal DISP_ON needs to be raised to a high level. Then, according to the value of the display mode parameter VID_MODE, the specified display mode can be entered to display image information.

[0142] As previously described, in one embodiment of the present invention, the display mode includes a video display mode and an instruction display mode. When the value of VID_MODE is 1, the microdisplay chip uses the video display mode; when the value of VID_MODE is 0, the microdisplay chip uses the instruction display mode. In one embodiment of the present invention, the value of VID_MODE is 1 by default, meaning the microdisplay chip defaults to using the video display mode.

[0143] like Figure 8 As shown, in one embodiment of the present invention, in any display mode, setting the display signal DISP_ON to zero will exit the display mode and return to the idle mode. In the idle mode, the value of the display mode parameter VID_MODE can be modified to switch the display mode.

[0144] Based on the microdisplay chip and its control method described above, the present invention also provides an electronic device comprising the microdisplay chip described above. In one embodiment of the present invention, the electronic device further comprises a detection module and a control module. The detection module is used to detect the state of the electronic device. The control module is used to generate control commands based on the detection results of the detection module, etc., and send them to the microdisplay chip to control the mode switching of the microdisplay chip.

[0145] Taking AR glasses as an example, the detection module may include, for example, an orientation detection sensor and a temperature sensor, used to detect whether the AR glasses are being worn or picked up. Specifically, if the AR glasses are detected being removed from the user's face, i.e., exiting the wearing state, the control module will send a sleep command to the microdisplay chip to put it into sleep mode; if the AR glasses are detected being placed on a table for a period exceeding a first specified time, the control module will send a sleep command to the microdisplay chip to put it into sleep mode; if the AR glasses are detected being placed on a table for a period exceeding a second specified time, the control module will send a power-saving command to the microdisplay chip to put it into power-saving mode; if the AR glasses are detected being picked up or worn on the user's face, the control module will send a corresponding signal to the microdisplay chip, thereby causing it to exit sleep mode, etc. In addition, the control module can also send display commands, reset commands, etc., to the microdisplay chip to put it into display mode, perform restart operations, etc.

[0146] The addition of a sleep mode can effectively improve the control efficiency of the host computer and enhance the user experience.

[0147] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A control method for a microdisplay chip, characterized in that, Including the following steps: In response to the power-on of the microdisplay chip, the microdisplay chip is initialized and configured, causing the microdisplay chip to enter an idle mode; In response to the occurrence of the first event, the microdisplay chip is controlled to enter sleep mode; as well as When the microdisplay chip is in the sleep mode, in response to the occurrence of the second event, the microdisplay chip is controlled to exit the sleep mode and enter the idle mode.

2. The control method as described in claim 1, characterized in that, The first event includes: The microdisplay chip does not receive a display command within a first specified time period after it is powered on; or The microdisplay chip received a sleep command.

3. The control method as described in claim 1, characterized in that, When the microdisplay chip is in sleep mode, the internal clock and analog submodule of the microdisplay chip are turned off.

4. The control method as described in claim 3, characterized in that, The simulation submodule includes: A one-time programming storage module, configured to store some or all of the configuration parameters of the microdisplay chip; An internal oscillator is configured to generate the internal clock of the microdisplay chip; A temperature detection submodule is configured to acquire the temperature of the microdisplay chip; and The power-on reset submodule is configured to perform a power-on reset.

5. The control method as described in claim 1, characterized in that, The second event includes: The microdisplay chip receives a display command; or The microdisplay chip received a command to exit sleep mode.

6. The control method as described in claim 1, characterized in that, The microdisplay chip is controlled by registers to switch between the sleep mode and the idle mode.

7. The control method as described in claim 1, characterized in that, In response to the power-on of the microdisplay chip, the initialization configuration of the microdisplay chip includes the following steps: The configuration parameters are read from the one-time programming storage module to configure the microdisplay chip; The compensation information is read from the external flash memory by the flexible storage controller and stored in the compensation cache component.

8. The control method as described in claim 7, characterized in that, The compensation information includes demura data and gamma data, which are configured to compensate and optimize the original image data.

9. The control method as described in claim 1, characterized in that, It also includes the following steps: When the microdisplay chip is in the idle mode, in response to the display command sent by the host computer, the microdisplay chip is controlled to enter the display mode and display image information.

10. The control method as described in claim 9, characterized in that, Controlling the microdisplay chip to enter display mode includes the following steps: The control display signal DISP_ON is at a high level.

11. The control method as described in claim 9, characterized in that, It also includes the following steps: When the microdisplay chip is in the display mode, in response to the control display signal DISP_ON switching from a high level to a low level, the microdisplay chip switches from the display mode to the idle mode.

12. The control method as described in claim 1, characterized in that, It also includes the following steps: When the microdisplay chip is in the idle mode, in response to a change in the value of the display mode parameter, the microdisplay chip is controlled to switch between video display mode and instruction display mode.

13. The control method as described in claim 12, characterized in that, The display mode parameter has two values, 1 and 0. The default value of the display mode parameter is 1. When the display mode parameter is 1, the microdisplay chip is in video display mode; when the display mode parameter is 0, the microdisplay chip is in instruction display mode.

14. The control method as described in claim 1, characterized in that, It also includes the following steps: In response to the occurrence of a third event, the microdisplay chip is controlled to enter a power-saving mode.

15. The control method as described in claim 14, characterized in that, The third event includes: During a second specified period of time after the microdisplay chip enters the idle mode or sleep mode, the microdisplay chip does not receive a display command; or The microdisplay chip receives a command from the host computer to enter power-saving mode.

16. The control method as described in claim 14, characterized in that, It also includes the following steps: When the microdisplay chip is in the power-saving mode, in response to a power-on or external reset control signal, the microdisplay chip is controlled to re-initialize and configure itself.

17. The control method as described in claim 1, characterized in that, It also includes the following steps: When the microdisplay chip is in the idle mode, in response to a software reset command generated inside the microdisplay chip, the microdisplay chip is controlled to re-initialize and configure itself.

18. A microdisplay chip, characterized in that, Its working state is controlled by the control method described in any one of claims 1 to 17.

19. An electronic device, characterized in that, include: A detection module configured to detect the usage status of the electronic device; A control module, which is communicatively connected to the detection module, is configured to generate control commands based on the usage state and send them to the microdisplay chip; as well as The microdisplay chip as described in claim 18 is communicatively connected to the control module and operates based on the control commands.

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