A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The circuit comprises N cascaded gate driving units, the nth gate driving unit comprises: a pull-up module configured to charge a pull-up node; a stage transmission output module configured to output a stage transmission signal of a current stage under the action of a voltage on the pull-up node and a current stage clock signal; a local brushing control module configured to, in a local refreshing mode, if an nth-d stage is a non-refreshing row and the current stage is a refreshing row, control the electrical connection between the pull-up node and a driving control node in a non-overlapping period of the current stage clock signal; if the nth-d stage is a refreshing row and the current stage is a non-refreshing row, control the disconnection between the pull-up node and the driving control node in a pre-charging period of the current stage; and a driving output module configured to output a gate driving signal of the current stage under the action of a voltage on the driving control node. The application prevents the display abnormality of the edge of the local refreshing area.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display in the local refresh area of ​​the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel that solves the problem of abnormal edge display in the local refresh area.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit including N cascaded gate driving units, the nth gate driving unit including: a pull-up module connected to a pull-up node, configured to: charge the pull-up node in response to the output signal of the nith gate driving unit; a stage transmission output module connected to the pull-up node and the clock signal line of the current stage, configured to: output the stage transmission signal of the current stage under the action of the voltage on the pull-up node and the clock signal of the current stage; a local refresh control module connected to the pull-up node and a drive control node, configured to: in local refresh mode, if the ndth stage is a non-refresh line and the current stage is a refresh line, control the electrical connection between the pull-up node and the drive control node during the non-overlapping period of the clock signal of the current stage; if the ndth stage is a refresh line and the current stage is a non-refresh line, control the disconnection between the pull-up node and the drive control node during the pre-charge period of the current stage; wherein d is less than i; and a drive output module connected to the drive control node, configured to: output the gate driving signal of the current stage under the action of the voltage on the drive control node.

[0006] Optionally, the local refresh control module includes: a first control submodule connected to the local refresh control node, configured to: in the local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, generate a first switch control signal on the local refresh control node; a second control submodule connected to the local refresh control node, configured to: in the local refresh mode, if the nd-th level is a refresh line and the current level is a non-refresh line, generate a second switch control signal on the local refresh control node; and a switch submodule connected to the pull-up node, the local refresh control node, and the drive control node, respectively, configured to: control the electrical connection between the pull-up node and the drive control node according to the first switch control signal on the local refresh control node; and control the disconnection between the pull-up node and the drive control node according to the second switch control signal on the local refresh control node.

[0007] Optionally, the first control submodule includes: a first transistor; the control terminal of the first transistor is connected to a first local brush control terminal, the first terminal of the first transistor is connected to a pull-up node, and the second terminal of the first transistor is connected to the local brush control node.

[0008] Optionally, the second control submodule includes: a second transistor; the control terminal of the second transistor is connected to the second local brush control terminal, the first terminal of the second transistor is connected to the local brush control node, and the second terminal of the second transistor is connected to a low-level terminal.

[0009] Optionally, the switching submodule includes: a third transistor; the control terminal of the third transistor is connected to the local brush control node, the first terminal of the third transistor is connected to the pull-up node, and the second terminal of the third transistor is connected to the drive control node.

[0010] Optionally, the switching submodule includes a third transistor and a fourth transistor; the control terminal of the third transistor is connected to the local brush control node and the control terminal of the fourth transistor respectively; the first terminal of the third transistor is connected to the pull-up node; the second terminal of the third transistor is connected to the first terminal of the fourth transistor; and the second terminal of the fourth transistor is connected to the drive control node.

[0011] Optionally, the nth stage gate drive unit further includes: a coupling module, connected to the stage output module and the pull-up module respectively, configured to: when the pull-up node is disconnected from the drive control node, couple a coupling drive signal based on the stage transmission signal output by the stage output module; wherein, the pull-up module, connected to the nith stage output module, the nith stage drive output module and the nith stage coupling module, is configured to: charge the pull-up node based on the nith stage transmission signal and the nith stage gate drive signal, or charge the pull-up node based on the nith stage transmission signal and the nith stage coupling drive signal.

[0012] Optionally, the coupling module includes: a fifth transistor, a first capacitor, and a sixth transistor; the control terminal of the fifth transistor is connected to the control terminal of the second brush, the first terminal of the fifth transistor is connected to the stage output terminal of the stage output module, the second terminal of the fifth transistor is connected to the first terminal of the first capacitor; the second terminal of the first capacitor is connected to the first terminal of the sixth transistor; the control terminal of the sixth transistor is connected to the control terminal of the first brush, and the second terminal of the sixth transistor is connected to a low-level terminal.

[0013] Optionally, the pull-up module includes: a seventh transistor, an eighth transistor, and a ninth transistor; the control terminal and the first terminal of the seventh transistor are respectively connected to the ni-th stage drive output module, and the second terminal of the seventh transistor is respectively connected to the second terminal of the eighth transistor and the first terminal of the ninth transistor; the control terminal and the first terminal of the eighth transistor are respectively connected to the ni-th stage coupling module; the control terminal of the ninth transistor is connected to the ni-th stage transmission output module, and the second terminal of the ninth transistor is connected to the pull-up node.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the stage output module of the gate driving circuit being connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects: In this application, a local refresh control module is set between the pull-up node and the drive control node. In local refresh mode, if the nd level is a non-refreshing row and the current level is a refreshing row, the local refresh control module controls the electrical connection between the pull-up node and the drive control node during the non-overlapping period of the current level's clock signal. During the non-overlapping period, the clock signal of the nd level is a low-level signal, and the nd level will not output a gate drive signal. Therefore, when the current level outputs a gate drive signal to refresh the pixel, the nd level will not display any abnormalities. If the nd level is a refreshing row and the current level is a non-refreshing row, the local refresh control module controls the disconnection between the pull-up node and the drive control node during the pre-charge period of the current level. During the pre-charge period, the drive control node will not be charged. Therefore, the drive output module of the nd level is charged during the pre-charge period of the nd level, and when the nd level outputs a gate drive signal to refresh the pixel, the current level will not display any abnormalities. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 A schematic diagram of a gate drive circuit provided in this application is shown.

[0018] Figure 2 A timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0022] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 Local brush control module; 131 First control submodule; 132 Second control submodule; 133 Switching submodule; 140 Drive output module; 150 Coupling module; 160 Noise reduction module; 170 Pull-down module.

[0024] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, thirteenth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate drive signal is output. When switching between refresh lines and non-refresh lines, since there may be overlapping areas between the clock signals of adjacent gate drive lines, when the refresh line is controlled to output the gate drive signal, the non-refresh line will mistakenly output the gate drive signal, resulting in abnormal display of the edge area of ​​the partial refresh.

[0029] Figure 1 A schematic diagram of a gate drive circuit provided in this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate drive circuit includes N cascaded gate drive units 100. The nth gate drive unit 100 includes: a pull-up module 110, a stage output module 120, a local brush control module 130, and a drive output module 140. The pull-up module 110 is connected to the pull-up node An, the stage output module 120 is connected to the pull-up node An and the clock signal line CKm of the current stage, and the local brush control module 130 is connected to the pull-up node An and the drive control node Qn.

[0030] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, An represents the pull-up node of the current stage, Qn represents the drive control node of the current stage, Fn represents the output terminal of the nth stage transmission output module, Gn represents the output terminal of the nth stage drive output module 140, Fn-i represents the output terminal of the nith stage transmission output module 120, and Gn-i represents the output terminal of the nith stage drive output module 140.

[0031] In some embodiments, the pull-up module 110 is configured to charge the pull-up node An in response to the output signal of the nth gate drive unit 100.

[0032] For example, the output signal of the ni-th gate drive unit 100 can be a stage transmission signal. After receiving the ni-th stage transmission signal, the pull-up module 110 charges the pull-up node An to generate a voltage on the pull-up node An.

[0033] In some embodiments, the stage transmission output module 120 is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node An and the current stage clock signal.

[0034] For example, the stage transmission output module 120 is connected to the pull-up node An. When a voltage is generated on the pull-up node An and the clock signal of the current stage arrives, the stage transmission output module 120 will output the stage transmission signal of the current stage. The stage transmission signal acts on the gate drive unit 100 adjacent to the current stage. For example, the stage transmission signal can be a precharge signal acting on the (n+i)th stage or a pull-down signal acting on the njth stage, etc.; i can be 2 and j can be 3.

[0035] In some embodiments, the local refresh control module 130, connected to the pull-up node An and the drive control node Qn, is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the pull-up node An and the drive control node Qn to be electrically connected during the non-overlapping period of the current level's clock signal; if the nd-th level is a refresh line and the current level is a non-refresh line, control the pull-up node An and the drive control node Qn to be disconnected during the pre-charge period of the current level; where d is less than i.

[0036] For example, d can be 1. If the nd-th stage is a non-refresh line and the current stage is a refresh line, that is, the nd-th stage does not output the gate drive signal and the current stage outputs the gate drive signal, the non-overlapping period is the period when the clock signal of the n-th stage does not overlap with the clock signal of the nd-th stage. Figure 2 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the overlap period between CKm and CKm-1 is t4~t5, and the non-overlapping period between the current stage clock signal and the nd stage is t5~t6. During the non-overlapping period of the current stage clock signal, the pull-up node An and the drive control node Qn are directly electrically connected. For the current stage, the current stage clock signal is always at a high potential. After the pull-up node An and the drive control node Qn are electrically connected, the drive output module 140 will output a gate drive signal under the action of the voltage of the pull-up node An and the current stage clock signal, thereby refreshing the pixels of the current stage. At this time, for the nd stage, although the pull-up node An-d and the drive control node Qn-d of the nd stage are electrically connected, the clock signal of the nd stage is already at a low potential during the non-overlapping period. The nd stage will not output a gate drive signal, thus not refreshing the pixels of the nd stage, and will not cause display abnormalities in the nd stage.

[0037] For example, if the nd level is a refresh row and the current level is a non-refresh row, that is, the nd level outputs a gate drive signal and the current level does not output a gate drive signal, the pre-charge period is the period when the pull-up module 110 charges the pull-up node An. During the pre-charge period of the current level, the pull-up node An and the drive control node Qn are disconnected. For the nd level, the drive control node Qn-d of the nd level has completed the pre-charge during the pre-charge period of the nd level. The drive output module 140 of the nd level outputs the gate drive signal of the nd level under the action of the voltage on the drive node of the nd level and the clock signal of the nd level. For the current level, since the pull-up node An and the drive control node Qn have been disconnected during the pre-charge period, when the clock signal of the current level arrives, the voltage on the drive control node Qn is insufficient to drive the drive output module 140 of the current level. The drive output module 140 of the current level will not output a gate drive signal, so the pixels of the current level will not be refreshed, and the current level will not be abnormally displayed.

[0038] In some embodiments, the drive output module 140, connected to the drive control node Qn, is configured to output the gate drive signal of the current stage under the action of the voltage on the drive control node Qn.

[0039] For example, in normal refresh mode, the drive control node Qn will be precharged to generate voltage; in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, for the current level, the drive control node Qn has no precharge voltage, and during the non-overlapping period of the current level clock signal, the pull-up node An is directly electrically connected to the drive control node Qn, and the voltage of the pull-up node An will be transmitted to the drive control node Qn; if the nd level is a refresh line and the current level is a non-refresh line, for the nd level, the drive control node Qn-d of the nd level has completed precharging during the precharging period of the nd level, thereby generating voltage.

[0040] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the local brush control module 130 includes: a first control submodule 131 and a second control submodule 132. The first control submodule 131 is connected to the local brush control node Bn, and the second control submodule 132 is connected to the local brush control node Bn. The switch submodule 133 is connected to the pull-up node An, the local brush control node Bn, and the drive control node Qn, respectively. In the figure, Bn represents the local brush control node Bn.

[0041] In some embodiments, the first control submodule 131 is configured to generate a first switch control signal on the local refresh control node Bn if the nd level is a non-refresh line and the current level is a refresh line in the local refresh mode.

[0042] For example, when the nd level is a non-refresh line and the current level is a refresh line, a first switch control signal is generated on the local refresh control node Bn to control the switch submodule 133 to be turned on.

[0043] In some embodiments, the second control submodule 132 is configured to generate a second switch control signal at the local refresh control node Bn if the nd level is a refresh line and the current level is a non-refresh line in the local refresh mode.

[0044] For example, when the nd level is a refresh line and the current level is a non-refresh line, a second switch control signal is generated on the local refresh control node Bn to control the switch submodule 133 to be turned off.

[0045] In some embodiments, the switch submodule 133 is configured to: control the pull-up node An to be electrically connected to the drive control node Qn according to a first switch control signal on the local brush control node Bn; and control the pull-up node An to be disconnected from the drive control node Qn according to a second switch control signal on the local brush control node Bn.

[0046] For example, by setting the two ends of the switch submodule 133 to be connected to the pull-up node An and the drive control node Qn respectively, when the switch submodule 133 receives the first switch control signal on the local brush control node Bn, the switch submodule 133 is turned on, realizing the electrical connection between the pull-up node An and the drive control node Qn. When the switch submodule 133 receives the second switch control signal on the local brush control node Bn, the switch submodule 133 is turned off, and the connection between the pull-up node An and the drive control node Qn is disconnected.

[0047] In some embodiments, please refer to Figure 3 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the first local brush control terminal SW1, the first terminal of the first transistor T1 is connected to the pull-up node An, and the second terminal of the first transistor T1 is connected to the local brush control node Bn.

[0048] In some embodiments, please refer to Figure 3 As shown, the second control submodule 132 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the second local brush control terminal SW2, the first terminal of the second transistor T2 is connected to the local brush control node Bn, and the second terminal of the second transistor T2 is connected to the low-level terminal VSS.

[0049] In some embodiments, please refer to Figure 3 As shown, the switch submodule 133 includes: a third transistor T3; The control terminal of the third transistor T3 is connected to the local brush control node Bn, the first terminal of the third transistor T3 is connected to the pull-up node An, and the second terminal of the third transistor T3 is connected to the drive control node Qn.

[0050] For example, please refer to Figure 2 and Figure 3 As shown in the figure, the case where d is 1 and i is 2 is illustrated. If the nd-th level is a non-refreshing row and the current level is a refreshing row, from... Figure 2 It can be seen that during the pre-charge period (t1~t3) and the working period (t3~t5) of the nd stage, the first local refresh control terminal SW1 is a low-level signal, and the second local refresh control terminal SW2 is a high-level signal. The control terminal of the first transistor T1 will receive a low-level signal and be cut off, while the control terminal of the second transistor T2 will receive a high-level signal and be turned on, thereby pulling down the local refresh control node Bn to a low potential. The control terminal of the third transistor T3 will receive a low-level signal through the local refresh control node Bn, and the third transistor T3 will be cut off, thereby disconnecting the connection between the pull-up node An and the drive control node Qn. The nd stage will not output a gate drive signal and will not refresh the pixels of the nd stage.

[0051] For example, the first refresh control terminal SW1 is a high-level signal during the non-overlapping period (t5~t6) of the current stage clock signal, and the second refresh control terminal SW2 is a high-level signal during the non-overlapping period (t5~t7) of the current stage clock signal. At this time, there is a pre-charge voltage on the pull-up node An. The control terminal of the first transistor T1 receives a high-level signal and turns on. The first transistor T1 pulls the refresh control node Bn to a high potential. The control terminal of the second transistor T2 receives a low-level signal and turns off, and will not pull the refresh control node Bn to a low potential. The control terminal of the third transistor T3 receives a high-level signal and turns on, thereby controlling the electrical connection between the pull-up node An and the drive control node Qn. The drive output module 140 will output a gate drive signal under the voltage of the pull-up node An to refresh the pixels of the current stage. In the non-overlapping period (t5~t6), the clock signal of the nd stage is a low-level signal. When the pull-up node An and the drive control node Qn are electrically connected, the nd stage will not output a gate drive signal erroneously, thereby preventing the nd stage from displaying abnormally.

[0052] Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 4As shown, if level nd is a refresh row and the current level is a non-refresh row, during the pre-charge period (t2~t4), the first refresh control terminal SW1 is a low-level signal, and the second refresh control terminal SW2 is a high-level signal. The control terminal of the first transistor T1 will receive a low-level signal and be cut off, while the control terminal of the second transistor T2 will receive a high-level signal and be turned on. The second transistor T2 pulls down the refresh control node Bn to a low potential, and the control terminal of the third transistor T3 receives a low level and is turned on, thereby disconnecting the connection between the pull-up node An and the drive control node Qn. For level nd, the drive control node Qn-d of level nd has been fully charged during the pre-charge period of level nd. When the clock signal of level nd arrives, the gate drive signal will be output for refresh. For the current level, during the current level's working period (t4~t6), when the clock signal arrives, since there is no voltage on the drive control node Qn, the gate drive signal will not be output, thus the pixel will not be refreshed, and the current level will not display any abnormalities.

[0053] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the switch submodule 133 includes: a third transistor T3 and a fourth transistor T4; the control terminal of the third transistor T3 is connected to the local brush control node Bn and the control terminal of the fourth transistor T4 respectively; the first terminal of the third transistor T3 is connected to the pull-up node An; the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4; the second terminal of the fourth transistor T4 is connected to the drive control node Qn.

[0054] For example, by setting the third transistor T3 and the fourth transistor T4, the leakage path of the drive control node Qn can be increased, thereby ensuring the voltage of the drive control node Qn and improving the turn-on reliability of the drive output module 140.

[0055] In some embodiments, please refer to Figure 3 As shown, the pull-up module 110 includes an eighth transistor T8, the control terminal and the first terminal of the eighth transistor T8 are connected to the output terminal of the nith stage transmission output module 120, and the second terminal of the eighth transistor T8 is connected to the pull-up node An.

[0056] For example, when the control terminal and the first terminal of the eighth transistor T8 receive the stage transmission signal of the nith stage, the eighth transistor T8 will be turned on to precharge the pull-up node An.

[0057] In some embodiments, please refer to Figure 3As shown, the stage transmission output module 120 includes: a tenth transistor T10 and a second capacitor C2. The control terminal of the tenth transistor T10 is connected to the pull-up node An and the first terminal of the second capacitor C2. The first terminal of the tenth transistor T10 is connected to the clock signal line CKm of the current stage. The second terminal of the tenth transistor T10 is connected to the second terminal of the second capacitor C2 and serves as the stage transmission output terminal of the current stage.

[0058] For example, when the pull-up node An is pre-charged, that is, the second capacitor C2 is pre-charged to a certain voltage, when the clock signal of the current stage arrives, the tenth transistor T10 will be turned on, and the second capacitor C2 will bootstrap the tenth transistor T10 to ensure that the tenth transistor T10 outputs the stage transmission signal of the current stage.

[0059] In some embodiments, please refer to Figure 3 As shown, the drive output module 140 includes: an eleventh transistor T11, the control terminal of the eleventh transistor T11 is connected to the drive control node Qn and the first terminal of the third capacitor C3, the eleventh transistor T11 is connected to the clock signal line CKm of the current stage, and the second terminal of the eleventh transistor T11 is connected to the second terminal of the third capacitor C3 and serves as the drive output terminal.

[0060] For example, when the drive control node Qn is connected to the pull-up node An, the drive control node Qn can be pre-charged through the pull-up node An, that is, the third capacitor C3 can be pre-charged. When the current stage clock signal arrives, the eleventh transistor T11 is turned on, and the third capacitor C3 will bootstrap the eleventh transistor T11 to turn on, so as to ensure that the eleventh transistor T11 outputs the gate drive signal.

[0061] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 170, which includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected to the output terminal of the (n+j)th-stage transmission output module 120. The first terminal of the twelfth transistor T12 is connected to the pull-up node An, the first terminal of the thirteenth transistor T13 is connected to the drive control node Qn, the first terminal of the fourteenth transistor T14 is connected to the output terminal of the drive output module 140, and the second terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected to the low-level terminal VSS.

[0062] For example, j can be 3. When the (n+j)th stage drive output module 140 outputs a gate drive signal, it indicates that the current stage has already output a gate drive signal. When the control terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 of the current stage receive the (n+j)th stage transmission signal, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 will be turned on, pulling up the pull-up node An, the drive control node Qn, and the output terminal Gn of the drive output module 140 down to a low potential, so that when the next frame signal arrives, the pull-up node An and the drive control node Qn will be precharged again to output the gate drive signal.

[0063] In some embodiments, the nth gate driving unit 100 further includes a noise reduction module 160, which is connected to the pull-up node An, the drive control node Qn, the stage transmission output module 120, the drive output module 140 and the low-level terminal VSS. When the pull-up node An is a low-level signal, the pull-up node An, the drive control node Qn, the stage transmission output module 120 and the drive output module 140 are pulled down to a low potential to reduce noise in the pull-up node An, the drive control node Qn, the stage transmission output module 120 and the drive output module 140.

[0064] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 6 As shown, the nth-stage gate drive unit 100 further includes a coupling module 150, which is connected to the stage output module 120 and the pull-up module 110, respectively. The pull-up module 110 is connected to the stage output module 120, the drive output module 140, and the coupling module 150 of the nith stage. The coupling module 150 is configured to couple a coupling drive signal based on the stage transmission signal output by the stage output module 120 when the pull-up node An is disconnected from the drive control node Qn. The pull-up module 110 is configured to charge the pull-up node An based on the stage transmission signal and the nith-stage gate drive signal, or to charge the pull-up node An based on the stage transmission signal and the nith-stage coupling drive signal.

[0065] For example, when the pull-up module 110 is simultaneously connected to the nith stage transmission output module 120 and the nith stage drive output module 140 to charge the pull-up node An, when the drive control node Qn is disconnected from the pull-up node An, the drive output module 140 may not be able to output the gate drive signal. As a result, the pull-up module 110 will not be able to receive the gate drive signal to conduct and charge the pull-up node An. By setting the coupling module 150, the stage transmission output module 120 is coupled to obtain the coupling drive signal. When the pull-up module 110 cannot receive the gate drive signal, it receives the coupling drive signal to conduct.

[0066] In some embodiments, see Figure 6 As shown, the coupling module 150 includes: a fifth transistor T5, a first capacitor C1, and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the second brush control terminal SW2, the first terminal of the fifth transistor T5 is connected to the stage output terminal of the stage output module 120, the second terminal of the fifth transistor T5 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the first terminal of the sixth transistor T6; the control terminal of the sixth transistor is connected to the first brush control terminal SW1, and the second terminal of the sixth transistor T6 is connected to the low-level terminal VSS.

[0067] In some embodiments, the pull-up module 110 includes: a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; the control terminal and the first terminal of the seventh transistor T7 are respectively connected to the ni-th stage drive output module 140, and the second terminal of the seventh transistor T7 is respectively connected to the second terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9; the control terminal and the first terminal of the eighth transistor T8 are respectively connected to the ni-th stage coupling module 150; the control terminal of the ninth transistor T9 is connected to the ni-th stage transmission output module 120, and the second terminal of the ninth transistor T9 is connected to the pull-up node An.

[0068] For example, G n represents the output terminal of the nth stage coupling module 150. When the second brush control terminal SW2 is a high-level signal and the first brush control terminal SW1 is a low-level signal, the drive output module 140 will not output a gate drive signal, and the seventh transistor T7 of the (n+i)th stage will not receive the gate drive signal of the current stage. At this time, the fifth transistor T5 receives a high-level signal and is turned on, and the control terminal of the sixth transistor T6 receives a low-level signal and is turned off. The first terminal of the first capacitor C1 will receive the stage transmission signal of the current stage through the fifth transistor T5, and couple it through the first capacitor C1 to obtain the coupled drive signal, and then through G... The output drive signal is coupled to the control terminal of the eighth transistor T8 of the (n+i)th stage, and the eighth transistor T8 of the (n+i)th stage will be turned on to precharge the pull-up node An of the (n+i)th stage.

[0069] This application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output module 140 of the gate driving circuit is connected to at least one scan line.

[0070] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0071] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: A pull-up module, connected to a pull-up node, is configured to charge the pull-up node in response to the output signal of the nith gate drive unit. The stage transmission output module, connected to the pull-up node and the clock signal line of the current stage, is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node and the clock signal of the current stage. The local refresh control module, connected to the pull-up node and the drive control node, is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the electrical connection between the pull-up node and the drive control node during the non-overlapping period of the current level's clock signal; if the nd-th level is a refresh line and the current level is a non-refresh line, control the disconnection between the pull-up node and the drive control node during the pre-charge period of the current level; where d is less than i; The drive output module, connected to the drive control node, is configured to output the gate drive signal of the current stage under the action of the voltage on the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The local brush control module includes: The first control submodule, connected to the local refresh control node, is configured to generate a first switch control signal on the local refresh control node if the nd level is a non-refresh line and the current level is a refresh line in the local refresh mode. The second control submodule, connected to the local refresh control node, is configured to generate a second switch control signal at the local refresh control node if the nd level is a refresh line and the current level is a non-refresh line in the local refresh mode. The switch submodule, connected to the pull-up node, the local brush control node, and the drive control node respectively, is configured to: control the electrical connection between the pull-up node and the drive control node according to the first switch control signal on the local brush control node; and control the disconnection between the pull-up node and the drive control node according to the second switch control signal on the local brush control node.

3. The gate driving circuit according to claim 2, characterized in that, The first control submodule includes: a first transistor; The control terminal of the first transistor is connected to the first local brush control terminal, the first terminal of the first transistor is connected to the pull-up node, and the second terminal of the first transistor is connected to the local brush control node.

4. The gate driving circuit according to claim 2, characterized in that, The second control submodule includes: a second transistor; The control terminal of the second transistor is connected to the second local brush control terminal, the first terminal of the second transistor is connected to the local brush control node, and the second terminal of the second transistor is connected to the low-level terminal.

5. The gate driving circuit according to claim 2, characterized in that, The switching submodule includes: a third transistor; The control terminal of the third transistor is connected to the local brush control node, the first terminal of the third transistor is connected to the pull-up node, and the second terminal of the third transistor is connected to the drive control node.

6. The gate driving circuit according to claim 2, characterized in that, The switching submodule includes: a third transistor and a fourth transistor; The control terminal of the third transistor is connected to the local brush control node and the control terminal of the fourth transistor respectively. The first terminal of the third transistor is connected to the pull-up node, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor. The second terminal of the fourth transistor is connected to the drive control node.

7. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The coupling module, which is connected to the stage transmission output module and the pull-up module respectively, is configured to: when the pull-up node is disconnected from the drive control node, couple a driving signal is obtained by coupling the stage transmission signal output by the stage transmission output module. The pull-up module is connected to the stage output module, the drive output module, and the coupling module of the nith stage, and is configured to: charge the pull-up node according to the stage transmission signal and the gate drive signal of the nith stage, or charge the pull-up node according to the stage transmission signal and the coupling drive signal of the nith stage.

8. The gate driving circuit according to claim 7, characterized in that, The coupling module includes: a fifth transistor, a first capacitor, and a sixth transistor; The control terminal of the fifth transistor is connected to the control terminal of the second brush, the first terminal of the fifth transistor is connected to the stage transmission output terminal of the stage transmission output module, and the second terminal of the fifth transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the first terminal of the sixth transistor; The control terminal of the sixth transistor is connected to the control terminal of the first brush, and the second terminal of the sixth transistor is connected to the low-level terminal.

9. The gate driving circuit according to claim 7, characterized in that, The pull-up module includes: a seventh transistor, an eighth transistor, and a ninth transistor; The control terminal and the first terminal of the seventh transistor are respectively connected to the ni-th stage drive output module, and the second terminal of the seventh transistor is respectively connected to the second terminal of the eighth transistor and the first terminal of the ninth transistor. The control terminal and the first terminal of the eighth transistor are respectively connected to the ni-th coupling module; The control terminal of the ninth transistor is connected to the ni-th stage transmission output module, and the second terminal of the ninth transistor is connected to the pull-up node.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the stage output module of the gate driving circuit is connected to at least one of the scan lines.

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