A gate driving circuit and a display panel

Abstract

This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. The nth-stage gate driving unit in the gate driving circuit includes: a pull-up module configured to charge the pull-up node; a stage output module configured to output a stage transmission signal under the influence of the voltage on the pull-up node and the current stage clock signal; a partial refresh control module configured to, in partial refresh mode, if the (n-d)th stage is a non-refresh line and the current stage is a refresh line, control the electrical connection between the pull-up node and the drive control node at the start of the non-overlapping period of the current stage clock signal; if the (n-d)th stage is a refresh line and the current stage is a non-refresh line, control the disconnection between the pull-up node and the drive control node when the clock signal of the (n-i)th stage arrives; and a drive output module configured to output a gate driving signal under the influence of the voltage of the drive control node and the current stage clock signal. This application will avoid abnormal edge display in the partial refresh area of ​​the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display of local refresh areas in the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of how to prevent abnormal edge display in the local refresh area of ​​the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit comprising N cascaded gate driving units, wherein the nth gate driving unit comprises: a pull-up module connected to the pull-up node of the current stage, configured to: charge the pull-up node in response to the output signal of the nth gate driving unit; a stage transmission output module connected to the pull-up node and the clock signal line of the current stage respectively, configured to: output a stage transmission signal under the action of the voltage on the pull-up node and the clock signal of the current stage; and a partial refresh control module connected to the pull-up node and the drive control node of the current stage respectively, configured to: in partial refresh mode, if the nd stage is non-refreshing If the current level is a refresh row, and the non-overlapping period of the current level clock signal begins, the pull-up node is electrically connected to the drive control node; if the nd level is a refresh row and the current level is a non-refresh row, when the clock signal of the ni level arrives, the pull-up node is disconnected from the drive control node; wherein, d is less than i, and the non-overlapping period is the non-overlapping period of the current level clock signal and the nd level clock signal; the drive output module, connected to the clock signal lines of the drive control node and the current level respectively, is configured to output a gate drive signal under the action of the voltage of the drive control node and the current level clock signal.

[0006] Optionally, the local refresh control module includes: a first control submodule connected to the first local refresh control node, configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, generate a first switch signal on the first local refresh control node at the start of the non-overlapping period of the current level clock signal; if the nd-th level is a refresh line and the current level is a non-refresh line, generate a second switch signal on the first local refresh control node when the ni-th level clock signal arrives; a second control submodule connected to the first local refresh control node, the pull-up node, and the drive control node respectively, configured to: control the electrical connection between the pull-up node and the drive control node according to the first switch signal; and control the disconnection between the pull-up node and the drive control node according to the second switch signal.

[0007] Optionally, the first control submodule includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the control terminal of the first transistor is connected to a first brush control terminal, the first terminal of the first transistor and the first terminal of the second transistor are connected to a high-level terminal, and the second terminal of the first transistor is connected to the first terminal of the third transistor and the control terminal of the fourth transistor respectively to a first brush control node; the control terminal of the second transistor is connected to a second brush control terminal, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor respectively to a second brush control node; the second terminal of the third transistor and the second terminal of the fourth transistor are connected to a low-level terminal.

[0008] Optionally, the second control submodule includes: a fifth transistor; the control terminal of the fifth transistor is connected to the first local brush control node, the first terminal of the fifth transistor is connected to the pull-up node, and the second terminal of the fifth transistor is connected to the drive control node.

[0009] Optionally, the first control submodule further includes a second local brush control node, wherein the voltage polarity of the first local brush control node and the second local brush control node are opposite. The local brush control module further includes: a first reset submodule connected to the first local brush control node and configured to pull the first local brush control node down to a low potential during the vertical blanking period; and a second reset submodule connected to the second local brush control node and configured to pull the second local brush control node down to a low potential during the vertical blanking period.

[0010] Optionally, the first reset submodule includes: a sixth transistor; the control terminal of the sixth transistor is connected to the reset control terminal, the first terminal of the sixth transistor is connected to the first local brush control node, and the second terminal of the sixth transistor is connected to a low-level terminal; or, the second reset submodule includes: a seventh transistor; the control terminal of the seventh transistor is connected to the reset control terminal, the first terminal of the seventh transistor is connected to the second local brush control node, and the second terminal of the seventh transistor is connected to a low-level terminal.

[0011] Optionally, the first control submodule further includes: a first capacitor and / or a second capacitor; a first terminal of the first capacitor is connected to the control terminal of the first transistor, and a second terminal of the first capacitor is connected to the second terminal of the first transistor; a first terminal of the second capacitor is connected to the control terminal of the second transistor, and a second terminal of the second capacitor is connected to the second terminal of the second transistor.

[0012] Optionally, the drive output module includes: an eighth transistor, a ninth transistor, and a third capacitor; the control terminal of the eighth transistor is connected to the pull-up node, the first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor; the control terminal of the ninth transistor and the first terminal of the third capacitor are connected to the drive control node, and the second terminal of the ninth transistor and the second terminal of the third capacitor are connected and serve as the drive output terminal.

[0013] Optionally, the stage output module includes a tenth transistor and a fourth capacitor; the control terminal of the tenth transistor and the first terminal of the fourth capacitor are connected to the pull-up node, and the second terminal of the tenth transistor is connected to the second terminal of the fourth capacitor and serves as the stage output terminal.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that the non-display area includes a gate driving circuit as described in any one of the first aspects, and the driving output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, a partial refresh control module is set between the pull-up node and the drive control node. In partial refresh mode, if the nd level is a non-refreshing row and the current level is a refreshing row, the pull-up node and the drive control node are electrically connected at the beginning of the non-overlapping period of the current level's clock signal. For the current level, the voltage of the pull-up node will be transmitted to the drive control node at the beginning of the non-overlapping period of the current level's clock signal, and the drive output module will output the gate drive signal of the current level to refresh the pixel. For the nd level, the nd level's clock signal has ended during the non-overlapping period of the current level's clock signal, and no gate drive signal will be output to refresh the pixel of the nd level. If the nd-th level is a refresh row and the current level is a non-refresh row, when the ni-th level clock signal arrives, the connection between the pull-up node and the drive control node is disconnected. For the nd-th level, when the nd-th level clock signal arrives, the drive control node has completed pre-charging, and the drive output module will output a gate drive signal to refresh the pixel. For the current level, at the beginning of the ni-th level clock signal, the pull-up node and the drive control node are disconnected, there is no voltage on the drive control node, and no gate drive signal will be output to refresh the pixel. This enables partial refresh of the display panel, avoiding aging caused by frequent pixel refresh, and the edge of the refresh area will not output a gate drive signal, thus preventing abnormal display at the edge of the partial refresh area. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A first operating timing diagram of the gate drive circuit in the first embodiment provided in this application is shown.

[0020] Figure 3 This paper shows another schematic diagram of a gate drive circuit provided in an embodiment of the present application.

[0021] Figure 4 A circuit diagram of the gate driving unit in the first embodiment provided in this application is shown.

[0022] Figure 5 A second operating timing diagram of the gate drive circuit in the first embodiment provided in this application is shown.

[0023] Figure 6 A circuit diagram of the gate driving unit in the second embodiment provided in this application is shown.

[0024] Figure 7 A first operating timing diagram of the gate drive circuit in the second embodiment provided in this application is shown.

[0025] Figure 8 A second timing diagram of the gate drive circuit in the second embodiment provided in this application is shown.

[0026] Figure 9 A circuit diagram of the gate driving unit in the third embodiment provided in this application is shown.

[0027] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 Local brush control module; 131 First control submodule; 132 Second control submodule; 133 First reset submodule; 134 Second reset submodule; 140 Drive output module; 150 Pull-down module; 160 Noise reduction module.

[0028] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; VGH, high-level terminal; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal; Reset, reset control terminal. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0031] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0032] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a local brush control module 130, and a drive output module 140. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage output module 120 is connected to the pull-up node Qn and the clock signal line CKm of the current stage, respectively. The local brush control module 130 is connected to the pull-up node Qn and the drive control node Qsn of the current stage, respectively. The drive output module 140 is connected to the drive control node Qsn and the clock signal line CKm of the current stage, respectively.

[0033] It should be noted that in the figure, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the output terminal of the stage output module of the ni stage, Qn represents the pull-up node of the nth stage, Qsn represents the drive output node of the nth stage, and Gn represents the output terminal of the drive output module of the nth stage.

[0034] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn in response to the output signal of the nth gate drive unit 100.

[0035] For example, i can be 2, and the output signal of the ni-th gate drive unit 100 can be the ni-th stage transmission signal. When the pull-up module 110 receives the ni-th stage transmission signal, it will be turned on, thereby charging the pull-up node Qn.

[0036] In some embodiments, the stage output module 120 is configured to output a stage transmission signal under the influence of the voltage on the pull-up node Qn and the current stage clock signal.

[0037] For example, the stage transmission module 120 receives the voltage on the pull-up node Qn and will be turned on when the current stage clock signal arrives, outputting the stage transmission signal of the current stage, which acts on the gate drive unit 100 of the adjacent stage, for example, on the pull-up module 110 of the (n+i)th stage, to charge the pull-up node Qn+i of the (n+i)th stage.

[0038] In some embodiments, the local refresh control module 130 is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node Qn and the drive control node Qsn to be electrically connected; if the nd-th level is a refresh line and the current level is a non-refresh line, when the ni-th level clock signal arrives, control the pull-up node Qn and the drive control node Qsn to be disconnected; wherein, d is less than i, and the non-overlapping period is the non-overlapping period of the current level clock signal and the nd-th level clock signal.

[0039] It should be noted that the global refresh mode refreshes the pixels corresponding to each level in the display panel in one frame of the scan signal; the partial refresh mode refreshes the pixels corresponding to some levels in the display panel in one frame of the scan signal, while the pixels corresponding to other levels maintain the pixel voltage in the previous frame of the scan signal.

[0040] For example, i can be 2 and d can be 1. Figure 2 This paper shows a first operating timing diagram of the gate drive circuit in the first embodiment provided in this application. In this application, the clock signals of adjacent stages overlap during certain periods. For details, please refer to [link / reference needed]. Figure 2 As shown, the current level is level n. The overlapping period between the clock signal (CKm) of level n and the clock signal (CKm-1) of level nd is (t8~t9), and the non-overlapping period between the clock signal (CKm) of level n and the clock signal (CKm-1) of level nd is (t9~t10). In the figure, Fn-3 represents the level output terminal of the level-3 transmission module, Qn-1 represents the pull-up node of level n-1, Qsn-1 represents the drive control node of level n-1, An-1 represents the first brush control node of level n-1, Bn-1 represents the second brush control node of level n-1, Gn-1 represents the drive output terminal of the level-n-1 drive output module, An represents the first brush control node of level n, and Bn represents the second brush control node of level n.

[0041] For example, if the nd-th stage is a non-refresh line and the current stage is a refresh line, that is, when the non-refresh line switches to a refresh line, at the beginning of the non-overlapping period of the current stage's clock signal (t9), the control pull-up node Qn and the drive control node Qsn are electrically connected. For the current stage, i.e., the n-th stage, since the pull-up node Qn has a pre-charge voltage, the voltage of the pull-up node Qn will be transmitted to the drive control node Qsn. At the beginning of the non-overlapping period of the current stage's clock signal, the drive output module 140 will output the gate drive signal of the current stage, thereby refreshing the pixel; for the nd-th stage, when the pull-up node Qn-d... When the voltage is transmitted to the drive control node Qsn-d, during the non-overlapping period of the current stage clock signal, the nd stage clock signal has ended. The drive output module 140 of the nd stage will not output the gate drive signal, thus not charging the pull-up node Qn-d of the nd stage. When the clock signal of the nd stage arrives, the nd stage will not output the gate drive signal to refresh the pixels of the nd stage. This enables partial refresh of the display panel, avoiding aging caused by frequent pixel refresh. Furthermore, since the nd stage does not output the gate drive signal, it will not cause abnormal display in the edge area of ​​the partial refresh area.

[0042] For example, if the nd-th level is a refresh line and the current level is a non-refresh line, that is, when the refresh line switches to a non-refresh line, when the ni-th level clock signal arrives, the pull-up node Qn and the drive control node Qsn are disconnected. For the nd-th level, since the nid-th level clock signal and the ni-th level clock signal have a non-overlapping period, during the non-overlapping period of the transmission signal of the ndi-th level, the pull-up node Qn-d of the nd-th level and the drive control node Qsn-d of the nd-th level have been pre-charged. When the ni-th level clock signal arrives, the pull-up node Qn-d and the drive control node Qsn-d are disconnected. When the nd-th stage clock signal arrives, the drive output module 140 will still output a gate drive signal to refresh the pixel. For the current stage, at the beginning of the ni-th stage clock signal, the pull-up node Qn and the drive control node Qsn are disconnected, and there is no pre-charge voltage on the drive control node Qsn. When the current stage clock signal arrives, the gate drive signal will not be output to refresh the pixel, thereby realizing partial refresh of the display panel. This can avoid aging caused by frequent pixel refresh, and the current stage will not output a gate drive signal, so as not to cause abnormal display of the edge area of ​​the partial refresh area.

[0043] In some embodiments, the drive output module 140 is connected to the drive control node Qsn and the clock signal line CKm of the current stage, respectively, and is configured to output a gate drive signal under the action of the voltage of the drive control node Qsn and the clock signal of the current stage.

[0044] For example, when there is voltage at the drive control node Qsn and the current stage clock signal arrives, the drive output module 140 will output a gate drive signal to refresh the pixel. When there is voltage at the drive control node Qsn, the drive output module 140 will not be turned on, and thus will not output a gate drive signal.

[0045] Figure 3 This paper shows another schematic diagram of a gate drive circuit provided in an embodiment of this application. Please refer to [link / reference]. Figure 3 As shown, the local brush control module 130 includes: a first control submodule 131 and a second control submodule 132. The first control submodule 131 is connected to the first local brush control node An, and the second control submodule 132 is connected to the first local brush control node An, the pull-up node Qn, and the drive control node Qsn, respectively.

[0046] In some embodiments, the first control submodule 131 is configured to: in local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, generate a first switch signal on the first refresh control node An at the start of the non-overlapping period of the current level clock signal; if the nd level is a refresh line and the current level is a non-refresh line, generate a second switch signal on the first refresh control node An when the ni level clock signal arrives.

[0047] For example, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, a first switch signal is generated on the first refresh control node An to enable the second control submodule 132, thereby connecting the pull-up node Qn with the drive control node Qsn; if the nd-th level is a refresh line and the current level is a non-refresh line, when the ni-th level clock signal arrives, a second switch signal is generated on the first refresh control node An to disconnect the pull-up node Qn from the drive control node Qsn.

[0048] In some embodiments, the second control submodule 132 is configured to: control the electrical connection between the pull-up node Qn and the drive control node Qsn according to the first switch signal; and control the disconnection between the pull-up node Qn and the drive control node Qsn according to the second switch signal.

[0049] For example, if the nd-th level is a non-refreshing row and the current level is a refreshing row, for the current level, when the first switch signal controls the electrical connection between the pull-up node Qn and the drive control node Qsn, the voltage of the pull-up node Qn is transmitted to the drive control node Qsn, so that the drive output module 140 outputs a gate drive signal under the action of the voltage on the drive control node Qsn and the current level clock signal to refresh the pixel; for the nd-th level, the nd-th level clock signal has ended, and even if the voltage of the pull-up node Qn-d is transmitted to the drive control node Qsn-d, the drive output module 140 will not output a gate drive signal.

[0050] For example, if the nd-th stage is a refresh row and the current stage is a non-refresh row, for the current stage, when the second switch signal controls the pull-up node Qn to disconnect from the drive control node Qsn, the voltage of the pull-up node Qn stops being transmitted to the drive control node Qsn. When the clock signal of the current stage arrives, no gate drive signal will be output to refresh the pixel. For the nd-th stage, the drive control node Qsn-d has been pre-charged when the clock signal of the ndi-th stage arrives. When the pull-up node Qn-d is disconnected from the drive control node Qsn-d, there is still voltage on the drive control node Qsn. When the clock signal of the nd-th stage arrives, the gate drive signal can still be output to refresh the pixel.

[0051] Figure 4 A circuit diagram of the gate driving unit in the first embodiment provided in this application is shown. Please refer to [link / reference]. Figure 4 As shown, the first control submodule 131 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the control terminal of the first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first transistor T1 and the first terminal of the second transistor T2 are connected to the high-level terminal VGH, and the second terminal of the first transistor T1 is connected to the first terminal of the third transistor T3 and the control terminal of the fourth transistor T4 respectively to the first brush control node An; the control terminal of the second transistor T2 is connected to the second brush control terminal SW2, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3 and the first terminal of the fourth transistor T4 respectively to the second brush control node Bn; the second terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are connected to the low-level terminal VSS.

[0052] For example, in the diagram, Bn represents the second brush control node of the nth level, and Fn+3 represents the stage transmission output terminal of the (n+3)th stage transmission output module. When the control terminal of the first transistor T1 receives a high-level signal from the first brush control terminal SW1, and the second transistor T2 receives a low-level signal from the second brush control terminal SW2, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. This will generate a high-level signal (i.e., the first switching signal) at the first brush control node An, and a low-level signal at the second brush control node Bn. When the control terminal of the first transistor T1 receives a low-level signal from the first brush control node, and the control terminal of the second transistor T2 receives a high-level signal from the second brush control node Bn, this will generate a low-level signal (i.e., the second switching signal) at the first brush control node An, and a high-level signal at the second brush control node Bn.

[0053] In some embodiments, please refer to Figure 4 As shown, the second control submodule 132 includes: a fifth transistor T5; the control terminal of the fifth transistor T5 is connected to the first brush control node An, the first terminal of the fifth transistor T5 is connected to the pull-up node Qn, and the second terminal of the fifth transistor T5 is connected to the drive control node Qsn.

[0054] For example, when the control terminal of the fifth transistor T5 receives the first switch signal, the fifth transistor T5 will be turned on, thereby controlling the electrical connection between the pull-up node Qn and the drive control node Qsn; when the control terminal of the fifth transistor T5 receives the second switch signal, the fifth transistor T5 will be turned off, thereby disconnecting the connection between the pull-up node Qn and the drive control node Qsn.

[0055] For example, please refer to Figure 2 and Figure 4As shown, if the nd level is a non-refresh line and the current level is a refresh line, the first refresh control signal output by the first refresh control terminal SW1 at the start of the non-overlapping period of the current level clock signal (t9) is a high-level signal, and the second refresh control signal output by the second refresh control terminal SW2 at the start of the non-overlapping period of the current level clock signal (t9) is a low-level signal. This controls the first transistor T1 and the fourth transistor T4 to turn on, and controls the second transistor T2 and the third transistor T3 to turn off. The first switch signal is generated at the first refresh control node An, the fifth transistor T5 is turned on, and the precharge voltage on the pull-up node Qn is transmitted to the drive control node Qsn. For the nd stage, the clock signal of the nd stage has ended during the non-overlapping period of the current stage clock signal. Even if there is voltage on the drive control node Qsn-1, the drive output module 140 will not output the gate drive signal. For the current stage, during the non-overlapping period of the current stage clock signal, under the action of the current stage clock signal and the voltage on the drive control node Qsn, the drive output module 140 will output the gate drive signal of the current stage to refresh the pixel of the current stage.

[0056] For example, Figure 5 A second timing diagram of the gate drive circuit in the first embodiment provided in this application is shown. Please refer to [link / reference]. Figure 4 and Figure 5 As shown, if the nd level is a refresh row and the current level is a non-refresh row, the first refresh control signal output by the first refresh control terminal SW1 when the ni level clock signal arrives (t6) is a low-level signal, and the second refresh control signal output by the second refresh control terminal SW2 when the ni level clock signal arrives (t6) is a high-level signal. This controls the first transistor T1 and the fourth transistor T4 to be turned off, and controls the second transistor T2 and the third transistor T3 to be turned on. The second switch signal is generated at the first refresh control node An, the fifth transistor T5 is turned off, and the precharge voltage on the pull-up node Qn is stopped from being transmitted to the drive control node Qsn. For the nd stage, before the ni stage clock signal arrives, the eighth transistor T8 is in the on state, and the drive control node Qsn-1 completes pre-charging when the nid stage clock signal arrives. When the fifth transistor T5 arrives at the nd stage clock signal, there is a pre-charge voltage on the drive control node Qsn-1 of the nd stage, and the drive output module 140 will be turned on to output the nd stage gate drive signal to refresh the pixel. For the current stage, since the fifth transistor T5 is in the off state when the ni stage clock signal arrives, the pull-up node Qn and the drive control node Qsn are disconnected, and there is no pre-charge voltage on the drive control node Qsn. When the current stage clock signal arrives, the drive output module 140 will not output the gate drive signal to refresh the pixel.

[0057] Please see Figure 4As shown, the nth-stage gate drive unit 100 includes a pull-down module 150, which includes a sixth transistor T6, a seventh transistor T7, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminals of the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are respectively connected to the stage output terminals of the (n+j)th-stage drive output module 140. The first terminal of the sixth transistor T6 is connected to the first... The local brush control node An is connected. The second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7, the second terminal of the twelfth transistor T12, the second terminal of the thirteenth transistor T13, and the second terminal of the fourteenth transistor T14 to the low-level terminal VSS. The first terminal of the seventh transistor T7 is connected to the second local brush control node Bn. The first terminal of the twelfth transistor T12 is connected to the pull-up node Qn. The first terminal of the thirteenth transistor T13 is connected to the drive control node Qsn. The second terminal of the fourteenth transistor T14 is connected to the drive output module 140.

[0058] For example, j can be 3. When the control terminals of the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 receive the stage transmission signal output by the (n+j)th stage transmission module 120, the sixth transistor T6 turns on to pull down the first brush control node An to a low potential, the seventh transistor T7 turns on to pull down the second brush control node Bn to a low potential, the twelfth transistor T12 turns on to pull down the pull-up node Qn to a low potential, the thirteenth transistor T13 turns on to pull down the drive control node Qsn to a low potential, and the fourteenth transistor T14 turns on to pull down the drive output terminal of the drive output module 140 to a low potential. This ensures that the output gate drive signal is stopped after the current stage output gate drive signal, so that the pull-up node Qn and the drive control node Qsn can be precharged again when the next frame scan signal arrives.

[0059] Figure 6 A circuit diagram of the gate driving unit in the second embodiment provided in this application is shown. Please refer to [link / reference]. Figure 6 As shown, the first control submodule 131 also has a second local brush control node Bn. The voltage polarity of the first local brush control node An and the second local brush control node B is opposite. The local brush control module 130 also includes: a first reset submodule 133 and a second reset submodule 134. The first reset submodule 133 is connected to the first local brush control node An, and the second reset submodule 134 is connected to the second local brush control node Bn.

[0060] In some embodiments, the first reset submodule 133 is configured to pull down the first local brush control node An to a low potential during the vertical blanking period.

[0061] For example, when the first brush control terminal SW1 outputs a high-level signal for the first brush control signal, the first brush control node An will generate a high-level signal. By setting the first reset submodule 133 to pull down the first brush control node An to a low potential during the vertical blanking period, compared with the first embodiment using the n+j stage transmission signal to pull down the first brush control node An, the load of the n+j stage transmission signal can be reduced, and the output of the gate drive signal will not be affected.

[0062] In some embodiments, the second reset submodule 134 is configured to pull the second local brush control node Bn to a low potential during the vertical blanking period.

[0063] For example, when the second brush control terminal SW2 outputs a high-level signal for the second brush control signal, the second brush control node Bn will generate a high-level signal. By setting the second reset submodule 134 to pull down the second brush control node Bn to a low potential during the vertical blanking period, compared with the first embodiment which uses the n+j stage transmission signal to pull down the second brush control node Bn, the load of the n+j stage transmission signal can be reduced, and the output of the gate drive signal will not be affected.

[0064] In some embodiments, please refer to Figure 5 As shown, the first reset submodule 133 includes: a sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the reset control terminal Reset, the first terminal of the sixth transistor T6 is connected to the first local brush control node An, and the second terminal of the sixth transistor T6 is connected to the low-level terminal VSS.

[0065] For example, when the control terminal of the sixth transistor T6 receives the reset signal output by the reset control terminal Reset during the vertical blanking period, the sixth transistor T6 will be turned on, thereby pulling down the first brush control node An to a low potential. Figure 7 A first operating timing diagram of the gate drive circuit in the second embodiment provided in this application is shown. Please refer to [link / reference]. Figure 7 As shown, when the first brush control node An is at a high level, during the (n+i)th stage transmission signal output, the first brush control node An is not pulled down to a low potential, and the voltage on the first brush control node An continues until the vertical blanking period. Figure 7 The working timing of the vertical blanking period is not shown.

[0066] In some embodiments, the second reset submodule 134 includes: a seventh transistor T7; the control terminal of the seventh transistor T7 is connected to the reset control terminal Reset, the first terminal of the seventh transistor T7 is connected to the second local brush control node Bn, and the second terminal of the seventh transistor T7 is connected to the low-level terminal VSS.

[0067] For example, when the control terminal of the seventh transistor T7 receives the reset signal output by the reset control terminal Reset during the vertical blanking period, the seventh transistor T7 will be turned on, thereby pulling down the second brush control node Bn to a low potential. Figure 8 A second timing diagram of the gate drive circuit in the second embodiment provided in this application is shown. Please refer to [link / reference]. Figure 8 As shown, when the second brush control node Bn is at a high level, during the (n+i)th stage transmission signal output, the second brush control node Bn is not pulled down to a low potential, and the voltage on the second brush control node Bn continues until the vertical blanking period. Figure 8 The working timing of the vertical blanking period is not shown.

[0068] Figure 9 A circuit diagram of the gate driving unit in the third embodiment provided in this application is shown. Please refer to [link / reference]. Figure 9 As shown, the first control submodule 131 further includes: a first capacitor C1 and / or a second capacitor C2; the first terminal of the first capacitor C1 is connected to the control terminal of the first transistor T1, and the second terminal of the first capacitor C1 is connected to the second terminal of the first transistor T1; the first terminal of the second capacitor C2 is connected to the control terminal of the second transistor T2, and the second terminal of the second capacitor C2 is connected to the second terminal of the second transistor T2.

[0069] For example, by setting the first capacitor C1, when the first brush control signal output by the first brush control terminal SW1 is a high-level signal, the first transistor T1 is turned on, and the high-level signal output by the high-level terminal VGH will reach the first brush control node An. At the same time, the first brush control signal output by the first brush control terminal SW1 will also charge the first capacitor C1. The voltage on the first capacitor C1 will promote the first transistor T1 to turn on, and the high-level signal output by the high-level terminal VGH will reach the control terminal of the eighth transistor T8 more quickly, promoting the degree of turn-on of the eighth transistor T8.

[0070] For example, by setting the second capacitor C2, when the second brush terminal outputs a high-level second brush control signal, the second transistor T2 is turned on. The high-level signal output by the high-level terminal VGH will reach the second brush control node Bn. At the same time, the second brush control signal output by the second brush control terminal SW2 will also charge the second capacitor C2. The voltage on the second capacitor C2 will promote the second transistor T2 to turn on, and then promote the third transistor T3 to turn on. The low-level signal output by the low-level terminal VSS will reach the control terminal of the eighth transistor T8 more quickly, promoting the eighth transistor T8 to turn off.

[0071] It should be noted that the operating timing of the gate drive circuit in the third embodiment is the same as that in the second embodiment. The operating principles of the first control submodule 131 and the second control submodule 132 in the second and third embodiments are the same as those in the first embodiment, and will not be repeated here.

[0072] In some embodiments, please refer to Figure 6 and Figure 9 As shown, the pull-down module 150 includes: a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected to the output terminal of the (n+i)th stage output module 120. The control terminal of the tenth diode is connected to the pull-up node Qn. The second terminal of the twelfth transistor T12, the second terminal of the thirteenth transistor T13, and the second terminal of the fourteenth transistor T14 are connected to the low-level terminal VSS. The first terminal of the thirteenth transistor T13 is connected to the drive control node Qsn. The second terminal of the fourteenth transistor T14 is connected to the drive output terminal of the drive output module 140.

[0073] For example, when the control terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 receive the stage transmission signal output by the (n+j)th stage transmission output module 120, the twelfth transistor T12 turns on to pull the pull-up node Qn down to a low potential, the thirteenth transistor T13 turns on to pull the drive control node Qsn down to a low potential, and the fourteenth transistor T14 turns on to pull the drive output terminal of the drive output module 140 down to a low potential. This ensures that the output gate drive signal stops after the current stage outputs the gate drive signal, so that the pull-up node Qn and the drive control node Qsn can be precharged again when the next frame scan signal arrives.

[0074] In some embodiments, please refer to Figure 4 , Figure 6 and Figure 9As shown, the drive output module 140 includes: an eighth transistor T8, a ninth transistor T9, and a third capacitor C3; the control terminal of the eighth transistor T8 is connected to the pull-up node Qn, the first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage, and the second terminal of the eighth transistor T8 is connected to the first terminal of the ninth transistor T9; the control terminal of the ninth transistor T9 and the first terminal of the third capacitor C3 are connected to the drive control node Qsn, and the second terminal of the ninth transistor T9 is connected to the second terminal of the third capacitor C3 and serves as the drive output terminal.

[0075] For example, when there is voltage on the pull-up node Qn, the eighth transistor T8 will conduct; when there is voltage on the drive control node Qsn, the ninth transistor T9 will conduct, simultaneously charging the third capacitor C3. When the clock signal of the current stage arrives, the voltage of the third capacitor C3 will promote the conduction of the ninth transistor T9, and the gate drive signal will be output through the second terminal of the ninth transistor T9. By connecting the eighth transistor T8 to the pull-up node Qn of the current stage, and enabling the first terminal of the ninth transistor T9 to be connected to the clock signal line CKm of the current stage when there is voltage on the pull-up node Qn, crosstalk to the current stage when the same clock signal from other stages arrives can be avoided, thereby preventing the erroneous output of the gate drive signal.

[0076] In some embodiments, please refer to Figure 4 , Figure 6 and Figure 9 As shown, the stage output module 120 includes: a tenth transistor T10 and a fourth capacitor C4; the control terminal of the tenth transistor T10 and the first terminal of the fourth capacitor C4 are connected to the pull-up node Qn, and the second terminal of the tenth transistor T10 and the second terminal of the fourth capacitor C4 are connected and serve as the stage output terminal.

[0077] For example, when the pull-up node Qn of the current stage is precharged, the voltage of the pull-up node Qn is stored in the fourth capacitor C4. When the clock signal of the current stage arrives, the first capacitor C1 bootstraps the pull-up node Qn, promoting the conduction of the tenth transistor T10, so that the second terminal of the tenth transistor T10 will output the stage signal.

[0078] In some embodiments, please refer to Figure 4 , Figure 6 and Figure 9 As shown, the pull-up module 110 includes: an eleventh transistor T11, the control of the eleventh transistor T11 is connected to the stage output terminal of the nith stage output module 120, the first terminal of the eleventh transistor T11 is connected to the stage output terminal of the nith stage output module 120, and the second terminal of the eleventh transistor T11 is connected to the pull-up node Qn.

[0079] For example, when the control terminal and the first terminal of the eleventh transistor T11 receive the ni-th stage transmission signal, the eleventh transistor T11 will be turned on to charge the pull-up node Qn.

[0080] In some embodiments, the nth-stage gate driving unit 100 further includes a noise reduction module 160, which is connected to the drive control node Qsn, the pull-up node Qn, the stage output terminal of the stage output module 120, and the drive output terminal of the drive output module 140, respectively, and is configured to perform noise reduction on the pull-up node Qn, the stage output terminal of the stage output module 120, and the drive output terminal of the drive output module 140 when there is no voltage on the drive control node Qsn.

[0081] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output module 140 of the gate driving circuit is connected to at least one scan line.

[0082] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0083] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0084] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node in response to the output signal of the nith stage gate drive unit; The stage transmission module is connected to the pull-up node and the clock signal line of the current stage, respectively, and is configured to output the stage transmission signal under the action of the voltage on the pull-up node and the clock signal of the current stage; The local refresh control module, connected to both the pull-up node and the current-level drive control node, is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the pull-up node to electrically connect with the drive control node at the start of the non-overlapping period of the current-level clock signal; if the nd-th level is a refresh line and the current level is a non-refresh line, control the pull-up node to disconnect from the drive control node when the clock signal of the ni-th level arrives; wherein, d is less than i, and the non-overlapping period is the non-overlapping period between the current-level clock signal and the nd-th level clock signal; The drive output module, which is connected to the clock signal lines of the drive control node and the current stage respectively, is configured to output a gate drive signal under the action of the voltage of the drive control node and the clock signal of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The local brush control module includes: The first control submodule, connected to the first refresh control node, is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, generate a first switch signal on the first refresh control node at the start of the non-overlapping period of the current level clock signal; if the nd-th level is a refresh line and the current level is a non-refresh line, generate a second switch signal on the first refresh control node when the ni-th level clock signal arrives. The second control submodule, which is connected to the first local brush control node, the pull-up node, and the drive control node respectively, is configured to: control the electrical connection between the pull-up node and the drive control node according to the first switch signal; and control the disconnection between the pull-up node and the drive control node according to the second switch signal.

3. The gate driving circuit according to claim 2, characterized in that, The first control submodule includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is connected to the first brush control terminal, the first terminal of the first transistor and the first terminal of the second transistor are connected to the high-level terminal, and the second terminal of the first transistor is connected to the first terminal of the third transistor and the control terminal of the fourth transistor respectively to the first brush control node; The control terminal of the second transistor is connected to the control terminal of the second brush, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor respectively to the second brush control node; The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the low-level terminal.

4. The gate driving circuit according to claim 2, characterized in that, The second control submodule includes: a fifth transistor; The control terminal of the fifth transistor is connected to the first local brush control node, the first terminal of the fifth transistor is connected to the pull-up node, and the second terminal of the fifth transistor is connected to the drive control node.

5. The gate driving circuit according to claim 2, characterized in that, The first control submodule also has a second local brush control node, the voltage polarity of which is opposite to that of the second local brush control node. The local brush control module further includes: The first reset submodule, connected to the first local brush control node, is configured to pull the first local brush control node down to a low potential during the vertical blanking period. The second reset submodule, connected to the second local brush control node, is configured to pull the second local brush control node down to a low potential during the vertical blanking period.

6. The gate driving circuit according to claim 5, characterized in that, The first reset submodule includes: a sixth transistor; The control terminal of the sixth transistor is connected to the reset control terminal, the first terminal of the sixth transistor is connected to the first local brush control node, and the second terminal of the sixth transistor is connected to the low-level terminal. Alternatively, the second reset submodule includes: a seventh transistor; The control terminal of the seventh transistor is connected to the reset control terminal, the first terminal of the seventh transistor is connected to the second local brush control node, and the second terminal of the seventh transistor is connected to the low-level terminal.

7. The gate driving circuit according to claim 3, characterized in that, The first control submodule further includes: a first capacitor, and / or a second capacitor; The first terminal of the first capacitor is connected to the control terminal of the first transistor, and the second terminal of the first capacitor is connected to the second terminal of the first transistor. The first terminal of the second capacitor is connected to the control terminal of the second transistor, and the second terminal of the second capacitor is connected to the second terminal of the second transistor.

8. The gate driving circuit according to claim 1, characterized in that, The drive output module includes: an eighth transistor, a ninth transistor, and a third capacitor; The control terminal of the eighth transistor is connected to the pull-up node, the first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor. The control terminal of the ninth transistor is connected to the first terminal of the third capacitor at the drive control node, and the second terminal of the ninth transistor is connected to the second terminal of the third capacitor and serves as the drive output terminal.

9. The gate driving circuit according to claim 1, characterized in that, The stage transmission module includes: a tenth transistor and a fourth capacitor; The control terminal of the tenth transistor is connected to the first terminal of the fourth capacitor at the pull-up node, and the second terminal of the tenth transistor is connected to the second terminal of the fourth capacitor as the stage output terminal.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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