A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving units. The nth gate driving unit comprises a local brushing control module configured to, in a local brushing mode, if the nth-dth stage is a non-refresh row and the current stage is a refresh row, at the start of a non-overlapping period of a current stage clock signal, control the electrical connection between the pull-up node of the current stage and the driving control node of the current stage, and charge the driving control node of the current stage in the non-overlapping period of the current stage clock signal; if the current stage is a refresh row and the nth+dth stage is a non-refresh row, at the start period of an nth+d-i stage clock signal, control the disconnection between the pull-up node of the current stage and the driving control node of the current stage, and charge the driving control node of the current stage in the overlapping period of an nth-j stage clock signal. The application avoids the edge display abnormality of the local brushing area in the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display in the local refresh area of ​​the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of abnormal edge display in the local refresh area of ​​the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to the pull-up node of the current stage, configured to: charge the pull-up node of the current stage in response to the output signal of the nth gate driving unit; a stage transmission output module connected to the pull-up node of the current stage and the clock signal line of the current stage, configured to: output the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage; and a partial refresh control module connected to the pull-up node of the current stage and the drive control node of the current stage, configured to: in partial refresh mode, if the ndth stage is a non-refresh line and the current stage is a refresh line, at the start of the non-overlapping period of the clock signal of the current stage, control the electrical connection between the pull-up node of the current stage and the drive control node of the current stage, and During the non-overlapping period of the current level clock signal, the drive control node of the current level is charged; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the beginning of the (n+di)th level clock signal, the pull-up node of the current level is disconnected from the drive control node of the current level, and the drive control node of the current level is charged during the overlapping period of the (nj)th level clock signal; wherein, j is greater than i, and i is greater than d; each level clock signal includes overlapping and non-overlapping periods, and the non-overlapping period of the current level clock signal represents the period during which the nth level clock signal and the ndth level clock signal do not overlap; the drive output module, connected to the drive control node of the current level and the clock signal line of the current level, is configured to output the gate drive signal of the current level under the action of the voltage of the drive control node of the current level and the current level clock signal.

[0006] Optionally, the local refresh control module includes: a switch control submodule, connected to the pull-up node and the drive control node of the current level, configured to: in local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, control the pull-up node of the current level to be electrically connected to the drive control node of the current level at the start of the non-overlapping period of the current level clock signal; if the current level is a refresh line and the (n+d)th level is a non-refresh line, control the pull-up node of the current level to be disconnected from the drive control node of the current level at the start of the (n+di)th level clock signal; and a precharge submodule, connected to the stage output terminal of the (nj)th stage output module, the clock signal line of the nith stage, and the auxiliary stage of the current level. A control node is connected and configured to charge the auxiliary control node of the current level under the action of the nj-th level transmission signal and the ni-th level clock signal. A drive auxiliary submodule is connected to the drive control node and the auxiliary control node of the current level and configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the auxiliary control node of the current level to charge the drive control node of the current level during the non-overlapping period of the current level clock signal; in partial refresh mode, if the current level is a refresh line and the n+d-th level is a non-refresh line, control the auxiliary control node of the current level to charge the drive control node of the current level during the overlapping period of the nj-th level clock signal.

[0007] Optionally, the switch control submodule includes: a first transistor; the control terminal of the first transistor is connected to a first brush control terminal, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the drive control node of the current stage.

[0008] Optionally, the pre-charge submodule includes: a first pre-charge group, connected to the stage transmission output module of the nj stage, the pre-charge control node of the current stage, and the auxiliary control node of the current stage, configured to: generate a voltage at the pre-charge control node of the current stage under the action of the stage transmission signal of the nj stage, and charge the auxiliary control node of the current stage based on the voltage of the pre-charge control node of the current stage; and a second pre-charge group, connected to the clock signal line of the ni stage and the pre-charge control node of the current stage, configured to: increase the voltage of the pre-charge control node of the current stage under the action of the clock signal of the ni stage.

[0009] Optionally, the first precharge group includes: a second transistor, a third transistor, and a first capacitor; the control terminal of the second transistor is connected to the stage output module of the njth stage, the first terminal of the second transistor is connected to the stage output module of the njth stage, and the second terminal of the second transistor is connected to the precharge control node of the current stage; the control terminal of the third transistor is connected to the precharge control node of the current stage, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the first capacitor; the second terminal of the first capacitor is connected to the auxiliary control node of the current stage.

[0010] Optionally, the second precharge group includes: a fourth transistor, a second capacitor, and a fifth transistor; the control terminal of the fourth transistor and the first terminal of the second capacitor are connected to the precharge control node of the current stage, the first terminal of the fourth transistor is connected to the clock signal line of the ni-th stage, and the second terminal of the fourth transistor and the second terminal of the second capacitor are connected to the auxiliary pull-up node of the current stage; the control terminal of the fifth transistor is connected to the noise reduction control node of the ni-th stage, the first terminal of the fifth transistor is connected to the auxiliary pull-up node of the current stage, and the second terminal of the fifth transistor is connected to a low-level terminal.

[0011] Optionally, the drive auxiliary submodule includes: a sixth transistor; the control terminal of the sixth transistor is connected to the second brush control terminal, the first terminal of the sixth transistor is connected to the precharge control node of the current stage, and the second terminal of the sixth transistor is connected to the drive control node of the current stage.

[0012] Optionally, the local brush control module further includes: a pull-up auxiliary submodule, connected to the auxiliary pull-up node of the current stage, the auxiliary control node of the current stage, and the input terminal of the pull-up module, configured to: input the auxiliary pull-up signal of the current stage to the pull-up module under the action of the voltage of the auxiliary pull-up node of the current stage and the voltage of the auxiliary control node of the current stage, so that the pull-up module charges the drive control node of the current stage under the action of the output signal of the gate drive unit of the ni stage; wherein, the pre-charge submodule has the auxiliary pull-up node.

[0013] Optionally, the pull-up auxiliary submodule includes: a seventh transistor and a third capacitor; the control terminal of the seventh transistor is connected to the auxiliary pull-up node of the current stage, the first terminal of the seventh transistor is connected to the auxiliary control node of the current stage, the second terminal of the seventh transistor is connected to the first terminal of the third capacitor; the second terminal of the third capacitor is connected to the input terminal of the pull-up module.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the driving output module of the gate driving circuit being connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, by setting up a partial refresh control module, in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level's clock signal, the pull-up node of the current level is electrically connected to the drive control node of the current level, and the drive control node of the current level is charged during the non-overlapping period of the current level's clock signal. The drive control node of the nd-th level has no voltage, and the drive output module of the nd-th level will not output the gate drive signal, thus avoiding display abnormalities in the partial refresh area. The voltage of the pull-up node of the current level will be transmitted to the drive control node of the current level, and the drive output module of the current level will output the gate drive signal to realize partial refresh of the display line board. Furthermore, charging the drive control node of the current level during the non-overlapping period of the current level's clock signal can promote the conduction of the drive output module of the current level, making the gate drive signal of the current level more stable. If the current level is a refresh row and the (n+d)th level is a non-refresh row, the clock signal at the (n+di)th level controls the pull-up node of the current level to disconnect from the drive control node of the current level. The drive output module of the current level will then output a gate drive signal to achieve partial refresh of the display line board. Charging the drive control node of the current level during the overlapping period of the clock signal at the (nj)th level ensures the charging duration of the drive control node and makes the gate drive signal of the current level more stable. Since the drive control node of the (n+d)th level has no pre-charge voltage, the drive output module of the (n+d)th level will not output a gate drive signal, thus avoiding display abnormalities in the partial refresh area. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0021] Figure 4 A first operating timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A second timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0023] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0024] Explanation of reference numerals in the attached figures: 100. Gate drive unit; 110. Pull-up module; 120. Stage output module; 130. Local brush control module; 131. Switch control submodule; 132. Precharge submodule; 1321. First precharge group; 1322. Second precharge group; 133. Drive auxiliary submodule; 134. Pull-up auxiliary submodule; 140. Drive output module; 150. Noise reduction module; 160. Pull-down module; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; T17, seventeenth transistor; T18, eighteenth transistor; T19, nineteenth transistor; T20, twentieth transistor; T21, twenty-first transistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; C4, Fourth capacitor; C5, Fifth capacitor; SW1, First brush control terminal; SW2, Second brush control terminal; LC, Noise reduction control terminal; VSS, Low level terminal; Qn, Pull-up node of the current stage; Qsn, Drive control node of the current stage; An, Precharge control node of the current stage; Bn, Auxiliary control node of the current stage; Cn, Auxiliary pull-up node of the current stage; Pn, Noise reduction control node of the current stage. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a local brush control module 130, and a drive output module 140. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage output module 120 is connected to the pull-up node Qn of the current stage and the clock signal line CKm of the current stage. The local brush control module 130 is connected to the pull-up node Qn of the current stage and the drive control node Qsn of the current stage. The drive output module 140 is connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage.

[0029] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn of the current stage in response to the output signal of the nth stage gate drive unit 100.

[0030] For example, i can be 2, and the output signal of the ni-th gate drive unit 100 can be the stage transmission signal of the ni-th stage. When the pull-up module 110 receives the stage transmission signal of the ni-th stage, the pull-up module 110 is turned on to charge the pull-up node Qn of the current stage so as to generate a voltage on the pull-up node Qn of the current stage.

[0031] In some embodiments, the stage transmission module 120 is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node Qn of the current stage and the clock signal of the current stage.

[0032] For example, when there is a voltage on the pull-up node Qn of the current stage and the clock signal of the current stage arrives, the stage transmission module 120 will be turned on and output the stage transmission signal of the current stage for stage transmission, which will act on the gate drive unit 100 of the adjacent stage.

[0033] In some embodiments, the local refresh control module 130 is configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node Qn of the current level to be electrically connected to the drive control node Qsn of the current level, and charge the drive control node Qsn of the current level during the non-overlapping period of the current level clock signal; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, at the start of the (n+di)-th level clock signal, control the pull-up node Qn of the current level to be disconnected from the drive control node Qsn of the current level, and charge the drive control node Qsn of the current level during the overlapping period of the (nj)-th level clock signal; where j is greater than i, and i is greater than d.

[0034] It should be noted that in global refresh mode, the stage-by-stage signals in the display panel are transmitted normally, with each stage outputting a gate drive signal to refresh the pixels; in partial refresh mode, some gate drive units 100 in the display panel output gate drive signals to partially refresh the pixels, without each stage of gate drive unit 100 needing to output a gate drive signal to refresh the pixels. Each stage clock signal includes overlapping and non-overlapping periods. The non-overlapping period of the current stage clock signal represents the period during which the nth stage clock signal and the nd stage clock signal do not overlap.

[0035] For example, d can be 1. If the nd-th stage is a non-refresh line and the current stage is a refresh line, that is, when switching from a non-refresh line to a refresh line, at the beginning of the non-overlapping period of the current stage's clock signal, the pull-up node Qn of the current stage is electrically connected to the drive control node Qsn of the current stage, and the drive control node Qsn of the current stage is charged during the non-overlapping period of the current stage's clock signal. For the nd-th stage, the drive control node of the nd-th stage has no pre-charge voltage. When the clock signal of the nd-th stage arrives, the drive output module 140 of the nd-th stage will not output a gate drive signal, thus avoiding abnormal edge display of the local refresh area; for the current stage, the voltage of the pull-up node Qn of the current stage. The signal will be transmitted to the current stage's drive control node Qsn. At the start of the non-overlapping period of the current stage's clock signal, under the influence of the voltage of the current stage's drive control node Qsn and the current stage's clock signal, the drive output module 140 will output the current stage's gate drive signal to refresh the pixels, thereby achieving partial refresh of the display panel. Furthermore, the current stage charges the voltage of the current stage's drive control node Qsn during the non-overlapping period of the current stage's clock signal, increasing the drive voltage of the current stage's drive output module 140. This can promote the conduction of the current stage's drive output module 140, making the gate drive signal output by the drive output module 140 more stable.

[0036] For example, if the current level is a refresh line and the (n+d)th level is a non-refresh line (i.e., when switching from a refresh line to a non-refresh line), at the beginning of the (n+di)th level clock signal, the pull-up node Qn of the current level is disconnected from the drive control node Qsn of the current level. During the overlapping period of the (nj)th level clock signal, the drive control node Qsn of the current level is charged. For the current level, the (n+di)th level clock signal overlaps with the (ni)th level clock signal. The drive control node Qsn of the current level only pre-charges during the non-overlapping period of the (ni)th level clock signal. This results in a shorter voltage charging time for the drive control node Qsn of the current level. During the overlapping period of the (nj)th level clock signal, the (nj)th level will... The output stage transmits signals to charge the current stage's drive control node Qsn, which increases the voltage of Qsn and promotes the conduction of the drive output module 140. This makes the gate drive signal of the current stage output by the drive output module 140 more stable and refreshes the pixels of the current stage, thus achieving partial refresh of the display panel. For the (n+d)th stage, when the clock signal of the (n+d)th stage starts, the pull-up node of the (n+d)th stage is disconnected from the drive control node of the (n+d)th stage, and there is no voltage on the drive control node of the (n+d)th stage. When the clock signal of the (n+d)th stage arrives, the gate drive signal of the (n+d)th stage will not be output, thus avoiding abnormal edge display of the partial refresh area.

[0037] In some embodiments, the drive output module 140, connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node Qsn of the current stage and the clock signal of the current stage.

[0038] For example, when there is a voltage on the current stage's drive control node Qsn and the current stage's clock signal arrives, the drive output module 140 will be turned on to output the current stage's gate drive signal, thereby refreshing the current pixel.

[0039] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the local brush control module 130 includes: a switch control submodule 131, a precharge submodule 132, and a drive auxiliary submodule 133. The switch control submodule 131 is connected to the pull-up node Qn and the drive control node Qsn of the current stage. The precharge submodule 132 is connected to the stage output module 120 of the ni stage, the clock signal line CKm-i of the ni stage, and the auxiliary control node Bn of the current stage. The drive auxiliary submodule 133 is connected to the drive control node Qsn and the auxiliary control node Bn of the current stage.

[0040] In some embodiments, the switch control submodule 131 is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node Qn of the current level to be electrically connected to the drive control node Qsn of the current level; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, at the start of the (n+di)-th level clock signal, control the pull-up node Qn of the current level to be disconnected from the drive control node Qsn of the current level.

[0041] In some embodiments, the pre-charge submodule 132 is configured to charge the auxiliary control node Bn of the current level under the action of the nj-th stage transmission signal and the ni-th stage clock signal.

[0042] In some embodiments, the drive auxiliary submodule 133 is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, during the non-overlapping period of the current level clock signal, control the auxiliary control node Bn of the current level to charge the drive control node Qsn of the current level; in partial refresh mode, if the current level is a refresh line and the (n+d)-th level is a non-refresh line, during the overlapping period of the (nj)-th level clock signal, control the auxiliary control node Bn of the current level to charge the drive control node Qsn of the current level.

[0043] For example, d can be 1, i can be 2, and j can be 4. If the nd-th stage is a non-refresh line and the current stage is a refresh line, for the ni-th stage, when the clock signal of the current stage starts, the switch control submodule 131 controls the pull-up node of the nd-th stage to be electrically connected to the drive control node of the nd-th stage. There is no pre-charge voltage on the drive control node of the nd-th stage, and the clock signal of the nd-th stage has ended at this time. The drive output module 140 of the nd-th stage will not output the gate drive signal of the current stage. For the current stage, the switch control submodule 131 controls the pull-up node Qn of the current stage to be electrically connected to the drive node of the current stage. The voltage of the pull-up node Qn of the current stage will be transmitted to the current stage. During the non-overlapping period of the current stage clock signal, the driving control node Qsn will control the driving output module 140 to output the gate driving signal of the current stage, thereby refreshing the pixels of the current stage. The pre-charge submodule 132 charges the auxiliary control node Bn of the current stage under the action of the nj stage transmission signal. During the non-overlapping period of the current stage clock signal, the driving auxiliary submodule 133 controls the auxiliary control node Bn of the current stage to connect with the driving control node Qsn of the current stage, thereby charging the driving control node Qsn of the current stage, increasing the voltage of the driving control node Qsn of the current stage, promoting the conduction of the driving output module 140, and making the output gate driving signal more stable.

[0044] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, for the current level, the switch control submodule 131 controls the pull-up node Qn of the current level to disconnect from the drive control node Qsn of the current level during the initial period of the (n+di)th level clock signal. Since the (ni)th level signal and the (n+di)th level clock signal overlap, the pull-up node Qn of the current level will only be pre-charged during the non-overlapping period of the (ni)th level clock signal. This will result in a shorter voltage charging time for the drive control node Qsn of the current level. The pre-charging submodule 132 charges the auxiliary control node Bn of the current level under the action of the (nj)th level clock signal. The drive auxiliary submodule 133 controls the auxiliary control node Bn of the current level to charge with the drive control node Qsn of the current level during the overlapping period of the (nj)th level clock signal, which will increase the charging time of the drive control node Qsn of the current level and improve the voltage of the drive control node Qsn of the current level. The precharge voltage of stage n will output the gate drive signal of the current stage when the clock signal of the current stage arrives, thereby realizing partial refresh of the display panel. For stage n+d, the switch control submodule 131 controls the pull-up node of stage n+d to disconnect from the drive control node of stage n+d during the start period of the clock signal of stage n+di. The drive control node of stage n+d has no precharge voltage. During the overlapping period of the clock signal of stage nj, the stage transmission output module 120 of stage n+dj also does not output the stage transmission signal. The precharge submodule 132 of stage n+d will not control the auxiliary control node of stage n+d to charge. At this time, the drive auxiliary submodule 133 is turned on, and the auxiliary control node of stage n+d will not charge the drive control node of stage n+d. When the clock signal of stage n+d arrives, the gate drive signal of stage n+d will not be output, thus avoiding abnormal edge display of the partial refresh area.

[0045] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the switch control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first transistor T1 is connected to the pull-up node Qn of the current stage, and the second terminal of the first transistor T1 is connected to the drive control node Qsn of the current stage.

[0046] For example, when the control terminal of the first transistor T1 receives the first brush control signal output by the first brush control terminal SW1, the first transistor T1 is turned on, thereby controlling the pull-up node Qn of the current stage to be connected to the drive control node Qsn of the current stage.

[0047] In some embodiments, please refer to Figure 3As shown, the precharge submodule 132 includes: a first precharge group 1321 and a second precharge group 1322. The first precharge group 1321 is connected to the level transmission output module 120 of the njth level, the precharge control node An of the current level, and the auxiliary control node Bn of the current level. The second precharge group 1322 is connected to the clock signal line CKm-i of the nith level and the precharge control node An of the current level.

[0048] In some embodiments, the first precharge group 1321 is configured to: generate a voltage at the precharge control node An of the current stage under the action of the nj stage transmission signal, and charge the auxiliary control node Bn of the current stage based on the voltage of the precharge control node An of the current stage.

[0049] For example, when the first precharge group 1321 receives the njth stage transmission signal, the first precharge group 1321 will generate a voltage on the precharge control node An of the current stage. At the same time, the voltage of the precharge control node An of the current stage will be transmitted to the auxiliary control node Bn of the current stage for charging, so as to charge the drive control node Qsn of the current stage.

[0050] In some embodiments, the second precharge group 1322 is configured to increase the voltage of the precharge control node An of the current stage under the action of the ni-th stage clock signal.

[0051] For example, by setting the second precharge group 1322, when the clock signal of the ni stage arrives, the precharge control node An of the current stage will be bootstrapped, which will increase the voltage of the precharge control node An of the current stage, thereby increasing the voltage of the auxiliary control node Bn of the current stage. When the auxiliary control node Bn of the current stage is connected to the drive control node Qsn of the current stage, the voltage of the drive control node Qsn of the current stage will be higher, thereby promoting the conduction of the drive output module 140.

[0052] In some embodiments, please refer to Figure 3 As shown, the first precharge group 1321 includes: a second transistor T2, a third transistor T3, and a first capacitor C1; the control terminal of the second transistor T2 is connected to the stage transmission output module 120 of the njth stage, the first terminal of the second transistor T2 is connected to the stage transmission output module 120 of the njth stage, and the second terminal of the second transistor T2 is connected to the precharge control node An of the current stage; the control terminal of the third transistor T3 is connected to the precharge control node An of the current stage, the first terminal of the third transistor T3 is connected to the precharge control node An of the current stage, and the second terminal of the third transistor T3 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the auxiliary control node Bn of the current stage.

[0053] For example, when the control terminal of the second transistor T2 receives the stage transmission signal of the njth stage, and the first terminal of the second transistor T2 receives the stage transmission signal of the njth stage, the second transistor T2 is turned on, generating a voltage on the pre-charge control node An of the current stage; when the control terminal of the third transistor T3 receives the voltage of the pre-charge control node An of the current stage, and the first terminal of the third transistor T3 receives the voltage of the pre-charge control node An of the current stage, the third transistor T3 is turned on, charging the first capacitor C1, generating a voltage on the auxiliary control node Bn of the current stage.

[0054] In some embodiments, please refer to Figure 3 As shown, the second precharge group includes: a fourth transistor T4, a second capacitor C2, and a fifth transistor T5; the control terminal of the fourth transistor T4 and the first terminal of the second capacitor C2 are connected to the precharge control node An of the current stage, the first terminal of the fourth transistor T4 is connected to the clock signal line of the ni stage, and the second terminal of the fourth transistor T4 and the second terminal of the second capacitor C2 are connected to the auxiliary pull-up node Cn of the current stage; the control terminal of the fifth transistor T5 is connected to the noise reduction control node Pn-i of the ni stage, the first terminal of the fifth transistor T5 is connected to the auxiliary pull-up node Cn of the current stage, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS.

[0055] For example, the voltage of the current precharge control node will control the fourth transistor T4 to turn on and charge the second capacitor C2. When the clock signal of the ni stage arrives, the voltage output by the fourth transistor T4 will bootstrap the current stage precharge control node An through the second capacitor C2, thereby increasing the voltage of the current stage precharge control node An and thus increasing the voltage of the current stage auxiliary control node Bn.

[0056] For example, when the control terminal of the fifth transistor T5 receives the voltage of the noise reduction control node of the nith stage, the fifth transistor T5 turns on, pulls down the auxiliary pull-up node Cn of the current stage to a low potential, and discharges the voltage of the auxiliary pull-up node Cn of the current stage so that the pre-charge control node An of the current stage can be charged again in the next scan frame.

[0057] In some embodiments, the auxiliary submodule includes: a sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the second brush control terminal SW2, the first terminal of the sixth transistor T6 is connected to the precharge control node An of the current stage, and the second terminal of the sixth transistor T6 is connected to the drive control node Qsn of the current stage.

[0058] For example, when the control terminal of the sixth transistor T6 receives the second brush control signal output by the second brush control terminal SW2, the sixth transistor T6 is turned on, realizing the electrical connection between the current stage auxiliary control node Bn and the current stage drive control node Qsn, and the voltage of the current stage auxiliary control node Bn will be transmitted to the current stage drive control node Qsn.

[0059] Figure 4 This paper shows a first operating timing diagram of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, if the nd stage is a non-refresh line and the current stage is a refresh line, for the nd stage, the control terminal of the sixth transistor T6 charges the drive control node of the nd stage at the beginning of the non-overlapping period of the current stage clock signal (t9). The first transistor T1 receives the first refresh control signal at the beginning of the non-overlapping period of the current stage clock signal (t9), and the first transistor T1 turns on to charge the drive control node of the nd stage. However, at this time, the clock signal of the nd stage has ended, and the drive output module 140 will not output the gate drive signal of the nd stage.

[0060] For example, for the current stage, the first transistor T1 receives the first refresh control signal during the non-overlapping period of the current stage clock signal and turns on, controlling the electrical connection between the pull-up node Qn and the drive control node Qsn of the current stage. The pull-up node Qn of the current stage charges the drive control node Qsn of the current stage. The second transistor T2 turns on under the action of the njth stage clock signal and charges the precharge control node An of the current stage. The fourth transistor T4 turns on under the action of the precharge control node An of the current stage and the nith stage clock signal. 4 is turned on and boosts the pre-charge control node An of the current stage through the second capacitor C2. The third transistor T3 is turned on under the voltage of the pre-charge control node An of the current stage, charging the first capacitor C1 and generating a voltage on the auxiliary control node Bn of the current stage. The sixth transistor T6 receives the second brush control signal at the beginning of the non-overlapping period of the current stage clock signal (t9) and turns on to charge the drive control node Qsn of the current stage. During the non-overlapping period of the current stage clock signal, the drive output module 140 will output the current gate drive signal.

[0061] Figure 5 A second timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 5As shown, if the current level is a non-refresh line and the (n+d)th level is also a non-refresh line, for the current level, the control terminal of the first transistor T1 receives the first refresh control signal at the beginning of the (n+di)th level clock signal (t6) and turns on, controlling the electrical connection between the pull-up node Qn and the drive control node Qsn of the current level. For the current level, the drive control node Qsn of the current level is charged during the overlapping period (t4~t5) of the nith level clock signal. Compared with the pre-charge period of the normal level, the pre-charge duration is shorter. The control terminal of the second transistor T2 turns on under the action of the njth level clock signal, generating electricity on the pre-charge control node An of the current level. The voltage of the precharge control node An of the current stage will charge the first capacitor C1 and generate a voltage on the auxiliary control node Bn of the current stage. During the overlapping period of the clock signal of the njth stage (t3~t4), the control terminal of the sixth transistor T6 receives the second brush control signal and turns on, so that the auxiliary control node Bn of the current stage charges the drive control node Qsn of the current stage, thereby increasing the precharge period of the drive control node Qsn of the current stage, thereby increasing the voltage of the drive control node Qsn of the current stage, promoting the turn-on of the drive output module 140 of the current stage, and making the gate drive signal of the current stage output by the drive output module 140 more stable.

[0062] For example, for the (n+d)th stage, at the start of the (n+di)th stage clock signal (t6), the pull-up node of the (n+d)th stage is disconnected from the drive control node of the (n+d)th stage, and the pull-up node of the (n+d)th stage will not charge the drive control node of the (n+d)th stage. When the control terminal of the sixth transistor T6 receives the second brush control signal during the overlapping period of the (nj)th stage clock signal, the second transistor T2 of the (n+d)th stage has not yet received the stage transmission signal of the (n+dj)th stage. There is no pre-charge voltage on the pre-charge control node of the (n+d)th stage, and the auxiliary control node of the (n+d)th stage will not charge the drive control node of the (n+d)th stage. Since there is no pre-charge voltage on the drive control node of the (n+d)th stage, the gate drive signal of the (n+d)th stage will not be output when the (n+d)th stage clock signal arrives.

[0063] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 6As shown, the local brush control module 130 further includes a pull-up auxiliary submodule 134, which is connected to the current stage's auxiliary pull-up node Cn, the current stage's auxiliary control node Cn, and the input terminal of the pull-up module 110. It is configured to input the current stage's auxiliary pull-up signal to the pull-up module 110 under the action of the voltage of the current stage's auxiliary pull-up node and the voltage of the current stage's auxiliary control node Cn, so that the pull-up module 110 charges the current stage's drive control node Qsn under the action of the output signal of the ni-th stage gate drive unit 100 and the current stage's auxiliary pull-up signal. The pre-charge submodule 132 has an auxiliary pull-up node.

[0064] For example, by setting up the pull-up auxiliary submodule 134, the voltage of the auxiliary pull-up node Cn of the current stage is in the same timing as the stage transmission signal output of the ni stage. When there is voltage on the auxiliary pull-up node Cn of the current stage, the pull-up auxiliary submodule 134 is turned on, so that the voltage of the auxiliary control node Bn of the current stage is input to the pull-up module 110. At the same time as the pull-up module 110 receives the stage transmission signal of the ni stage, it also receives the voltage of the auxiliary control node Bn of the current stage. The pull-up module 110 charges the pull-up node Qn of the current stage so that the voltage of the drive control node Qsn of the current stage increases.

[0065] In some embodiments, please refer to Figure 6 As shown, the pull-up auxiliary submodule 134 includes: a seventh transistor T7 and a third capacitor C3; the control terminal of the seventh transistor T7 is connected to the auxiliary pull-up node Cn of the current stage, the first terminal of the seventh transistor T7 is connected to the auxiliary control node Bn of the current stage, the second terminal of the seventh transistor T7 is connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the input terminal of the pull-up module 110.

[0066] For example, when the control terminal of the seventh transistor T7 receives the voltage of the auxiliary pull-up node Cn of the current stage, the seventh transistor T7 is turned on, and the voltage of the auxiliary control node Bn of the current stage will charge the third capacitor C3. The voltage stored in the third capacitor C3 will be input to the input terminal of the pull-up module 110, so that the charging voltage of the pull-up module 110 to the pull-up node Qn of the current stage is increased.

[0067] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the pull-up module 110 includes: an eighth transistor T8, the control terminal of the eighth transistor T8 is connected to the stage output module 120 of the ni stage, the first terminal of the eighth transistor T8 is connected to the stage output module 120 of the ni stage, and the second terminal of the eighth transistor T8 is connected to the pull-up node Qn of the current stage.

[0068] For example, when the control terminal of the eighth transistor T8 receives the stage transmission signal of the nith stage output module 120, and the first terminal of the eighth transistor T8 receives the stage transmission signal of the nith stage, the eighth transistor T8 is turned on to charge the pull-up node Qn of the current stage.

[0069] In some embodiments, please refer to Figure 6 As shown, when the pull-up module 110 is connected to the pull-up auxiliary submodule 134, the first terminal of the eighth transistor T8 is also connected to the pull-up auxiliary submodule 134.

[0070] For example, the control terminal of the eighth transistor T8 receives the stage transmission signal of the ni stage. The first terminal of the eighth transistor T8 simultaneously receives the stage transmission signal of the ni stage and the voltage of the third capacitor C3. After the eighth transistor T8 is turned on, it will use the stage transmission signal of the ni stage and the voltage of the third capacitor C3 to charge the pull-up node Qn of the current stage, thereby increasing the voltage of the pull-up node Qn of the current stage.

[0071] In some embodiments, the stage output module 120 includes: a ninth transistor T9 and a fourth capacitor C4; the control terminal of the ninth transistor T9 and the first terminal of the fourth capacitor C4 are connected to the pull-up node Qn of the current stage, the first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage, and the second terminal of the ninth transistor T9 is connected to the second terminal of the fourth capacitor C4 and serves as the output terminal Fn.

[0072] For example, when there is a voltage at the pull-up node Qn of the current stage, the ninth transistor T9 is turned on and charges the fourth capacitor C4. When the first terminal of the ninth transistor T9 receives the clock signal of the current stage, it will bootstrap the voltage of the pull-up node Qn of the current stage through the fourth capacitor C4, promoting the turn-on of the ninth transistor T9. The second terminal of the ninth transistor T9 outputs the stage transmission signal of the current stage.

[0073] In some embodiments, the drive output module 140 includes a tenth transistor T10 and a fifth capacitor C5. The control terminal of the tenth transistor T10 and the first terminal of the fifth capacitor C5 are connected to the drive control node Qsn of the current stage. The first terminal of the tenth transistor T10 is connected to the clock signal line CKm of the current stage. The second terminal of the tenth transistor T10 is connected to the second terminal of the fifth capacitor C5 and serves as the output terminal Gn.

[0074] For example, when the control terminal of the tenth transistor T10 receives the voltage of the current stage's drive control node Qsn, the tenth transistor T10 turns on and charges the fifth capacitor C5. When the first terminal of the tenth transistor T10 receives the current stage's clock signal, the tenth transistor T10 will bootstrap the voltage of the current stage's drive control node Qsn through the fifth capacitor C5, promoting the conduction of the tenth transistor T10. The second terminal of the tenth transistor T10 outputs the current stage's gate drive signal.

[0075] In some embodiments, the noise reduction module 150 includes: an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18; the control terminal of the eleventh transistor T11 is connected to the first terminal of the eleventh transistor T11 and the first terminal of the twelfth transistor T12 to the noise reduction control terminal LC; the second terminal of the eleventh transistor T11 is connected to the control terminal of the twelfth transistor T12 and the first terminal of the thirteenth transistor T13; the second terminal of the twelfth transistor T12 is connected to the first terminal of the fourteenth transistor T14, the control terminal of the fifteenth transistor T15, the control terminal of the sixteenth transistor T16, the control terminal of the seventeenth transistor T17, and the control terminal of the eighteenth transistor T18. The noise reduction control node Pn of the current stage is connected. The control terminals of the thirteenth transistor T13 and the fourteenth transistor T14 are connected to the pull-up node Qn of the current stage. The second terminal of the thirteenth transistor T13, the second terminal of the fourteenth transistor T14, the second terminal of the fifteenth transistor T15, the second terminal of the sixteenth transistor T16, the second terminal of the seventeenth transistor T17, and the second terminal of the eighteenth transistor T18 are connected to the low-level terminal VSS. The first terminal of the fifteenth transistor T15 is connected to the pull-up control node Qn of the current stage. The first terminal of the sixteenth transistor T16 is connected to the drive control node Qsn of the current stage. The first terminal of the seventeenth transistor T17 is connected to the output terminal of the stage output module 120 of the current stage. The first terminal of the eighteenth transistor T18 is connected to the output terminal of the drive output module 140 of the current stage.

[0076] For example, the noise reduction control signal output by the LC terminal of the noise reduction control terminal is continuously high-level. When there is no voltage on the current stage's drive control node Qsn, the eleventh transistor T11 and the twelfth transistor T12 receive the high-level signal and turn on, generating a voltage on the current stage's noise reduction control node Pn. The current stage's noise reduction control node Pn will control the fifteenth transistor T15 to turn on, thereby pulling down the current stage's pull-up node Qn to a low potential, thus performing noise reduction on the current stage's pull-up node Qn; the sixteenth transistor... When transistor T16 is turned on, it pulls down the current stage's drive control node Qsn to a low potential, thus reducing noise at Qsn. Similarly, transistor T17 is turned on, pulling down the output of the current stage's stage output module 120 to a low potential, also reducing noise at its output. Finally, transistor T18 is turned on, pulling down the output of the current stage's drive output module 140 to a low potential, further reducing noise at its output. When there is voltage on the current stage's pull-up node Qn, transistors T13 and T14 will turn on, pulling down the current stage's noise reduction control node Pn to a low potential. Without voltage on Pn, transistors T15, T16, T17, and T18 will not turn on.

[0077] In some embodiments, the pull-down module 160 includes: a nineteenth transistor T19, a twentieth transistor T20, and a twenty-first transistor T21; the control terminals of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 are connected to the output terminal of the stage output module 120 of the (n+q)th stage; the first terminal of the nineteenth transistor T19 is connected to the pull-up node Qn of the current stage; the second terminal of the nineteenth transistor T19, the second terminal of the twentieth transistor T20, and the second terminal of the twenty-first transistor T21 are connected to the low-level terminal VSS; the first terminal of the twentieth transistor T20 is connected to the drive control node Qsn of the current stage; and the first terminal of the twenty-first transistor T21 is connected to the first terminal of the current stage and the output terminal of the drive output module 140 of the current stage.

[0078] For example, q can be 3. When the control terminals of the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 receive the stage transmission signal of the (n+q)th stage, they will all be turned on. The nineteenth transistor T19 pulls down the pull-up node Qn of the current stage to a low potential, the twentieth transistor T20 pulls down the drive control node Qsn of the current stage to a low potential, and the twenty-first transistor T21 pulls down the output terminal of the drive output module 140 to a low potential, so as to control the drive output module 140 of the current stage to stop outputting the gate drive signal of the current stage. When the next scan frame arrives, the pull-up node Qn of the current stage is charged again.

[0079] It should be noted that the first brush control terminal SW1, the second brush control terminal SW2, and the noise reduction control terminal LC can all be output terminals of the timing controller. Each gate drive unit is connected to the first brush control terminal SW1, the second brush control terminal SW2, and the noise reduction control terminal LC. When the first brush control terminal SW1 sends the first brush control signal, the second brush control terminal SW2 sends the second brush control signal, and the noise reduction control terminal LC sends the noise reduction control signal, each gate drive unit can receive it.

[0080] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit described above. The drive output module of the gate driving circuit is connected to at least one scan line.

[0081] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0082] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node of the current stage in response to the output signal of the nith stage gate drive unit. The stage transmission module is connected to the pull-up node of the current stage and the clock signal line of the current stage, and is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage. The local refresh control module, connected to the pull-up node and the drive control node of the current level, is configured to: in local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, at the start of the non-overlapping period of the current level clock signal, control the pull-up node of the current level to be electrically connected to the drive control node of the current level, and charge the drive control node of the current level during the non-overlapping period of the current level clock signal; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level clock signal, control the pull-up node of the current level to be disconnected from the drive control node of the current level, and charge the drive control node of the current level during the overlapping period of the (nj)th level clock signal; wherein, j is greater than i, and i is greater than d; each level clock signal includes overlapping and non-overlapping periods, and the non-overlapping period of the current level clock signal represents the period during which the nth level clock signal and the nd level clock signal do not overlap; The drive output module, connected to the drive control node and clock signal line of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The local brush control module includes: The switch control submodule, connected to the pull-up node and the drive control node of the current level, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, control the pull-up node of the current level to be electrically connected to the drive control node of the current level at the start of the non-overlapping period of the clock signal of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, control the pull-up node of the current level to be disconnected from the drive control node of the current level at the start of the clock signal of the (n+di)th level. The pre-charge submodule, connected to the stage output terminal of the nj-th stage output module, the clock signal line of the ni-th stage, and the auxiliary control node of the current stage, is configured to charge the auxiliary control node of the current stage under the action of the nj-th stage transmission signal and the ni-th stage clock signal. The drive auxiliary submodule, connected to the drive control node and the auxiliary control node of the current level, is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the auxiliary control node of the current level to charge the drive control node of the current level during the non-overlapping period of the clock signal of the current level; in partial refresh mode, if the current level is a refresh line and the (n+d)-th level is a non-refresh line, control the auxiliary control node of the current level to charge the drive control node of the current level during the overlapping period of the clock signal of the (nj)-th level.

3. The gate driving circuit according to claim 2, characterized in that, The switch control submodule includes: a first transistor; The control terminal of the first transistor is connected to the first brush control terminal, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the drive control node of the current stage.

4. The gate driving circuit according to claim 2, characterized in that, The pre-charge submodule includes: The first pre-charge group, connected to the stage transmission output module of the nj stage, the pre-charge control node of the current stage, and the auxiliary control node of the current stage, is configured to: generate a voltage in the pre-charge control node of the current stage under the action of the stage transmission signal of the nj stage, and charge the auxiliary control node of the current stage based on the voltage of the pre-charge control node of the current stage. The second precharge group, connected to the clock signal line of the ni-th stage and the precharge control node of the current stage, is configured to increase the voltage of the precharge control node of the current stage under the action of the clock signal of the ni-th stage.

5. The gate driving circuit according to claim 4, characterized in that, The first precharge group includes: a second transistor, a third transistor, and a first capacitor; The control terminal of the second transistor is connected to the stage output module of the njth stage, the first terminal of the second transistor is connected to the stage output module of the njth stage, and the second terminal of the second transistor is connected to the precharge control node of the current stage. The control terminal of the third transistor is connected to the precharge control node of the current stage, the first terminal of the third transistor is connected to the precharge control node of the current stage, and the second terminal of the third transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the auxiliary control node of the current level.

6. The gate driving circuit according to claim 4, characterized in that, The second precharge group includes: a fourth transistor, a second capacitor, and a fifth transistor; The control terminal of the fourth transistor and the first terminal of the second capacitor are connected to the precharge control node of the current stage. The first terminal of the fourth transistor is connected to the clock signal line of the ni stage. The second terminal of the fourth transistor and the second terminal of the second capacitor are connected to the auxiliary pull-up node of the current stage. The control terminal of the fifth transistor is connected to the noise reduction control node of the ni stage, the first terminal of the fifth transistor is connected to the auxiliary pull-up node of the current stage, and the second terminal of the fifth transistor is connected to the low-level terminal.

7. The gate driving circuit according to claim 3, characterized in that, The drive auxiliary submodule includes: a sixth transistor; The control terminal of the sixth transistor is connected to the control terminal of the second brush, the first terminal of the sixth transistor is connected to the precharge control node of the current stage, and the second terminal of the sixth transistor is connected to the drive control node of the current stage.

8. The gate driving circuit according to claim 2, characterized in that, The local refresh control module also includes: A pull-up auxiliary submodule, connected to the auxiliary pull-up node of the current stage, the auxiliary control node of the current stage, and the input terminal of the pull-up module, is configured to: input the auxiliary pull-up signal of the current stage to the pull-up module under the action of the voltage of the auxiliary pull-up node of the current stage and the voltage of the auxiliary control node of the current stage, so that the pull-up module charges the drive control node of the current stage under the action of the output signal of the gate drive unit of the ni stage; wherein, the pre-charge submodule has the auxiliary pull-up node.

9. The gate driving circuit according to claim 8, characterized in that, The pull-up auxiliary submodule includes: a seventh transistor and a third capacitor; The control terminal of the seventh transistor is connected to the auxiliary pull-up node of the current stage, the first terminal of the seventh transistor is connected to the auxiliary control node of the current stage, and the second terminal of the seventh transistor is connected to the first terminal of the third capacitor. The second terminal of the third capacitor is connected to the input terminal of the pull-up module.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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