A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises a first brush control module configured to: if the nth-d stage is a non-refresh row and the current stage is a refresh row, in a pre-charge period of the current stage, under the action of a stage transmission signal of the nth-j stage, a driving control node of the current stage is charged, and at the start of a non-overlapping period of a current stage clock signal, the connection between a pull-up node of the current stage and the driving control node of the current stage is controlled; if the current stage is a refresh row and the nth+d stage is a non-refresh row, before the pre-charge period of the current stage, under the action of the stage transmission signal of the nth-j stage, the driving control node of the current stage is charged, and at the start of a nth+d-i stage clock signal, the connection between the pull-up node of the current stage and the driving control node of the current stage is controlled. The application avoids edge display abnormalities in a local refresh area of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display in the local refresh area of ​​the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of abnormal edge display in the local refresh area of ​​the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to the pull-up node of the current stage, configured to: charge the pull-up node of the current stage in response to the output signal of the nth gate driving unit; a stage transmission output module connected to the pull-up node of the current stage and the clock signal line of the current stage, configured to: output the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage; and a first local refresh control module connected to the pull-up node of the current stage, the drive control node of the current stage, and the njth stage transmission output module, configured to: in local refresh mode, if the ndth stage is a non-refresh line and the current stage is a refresh line, during the pre-charge period of the current stage, charge the stage transmission signal of the njth stage. Under the action of the current stage's driving control node, the current stage's pull-up node is charged, and at the start of the non-overlapping period of the current stage's clock signal, the current stage's pull-up node is electrically connected to the current stage's driving control node; if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, before the current stage's pre-charge period, the current stage's driving control node is charged under the action of the stage transmission signal of the (nj)th stage, and at the start of the (n+di)th stage's clock signal, the pull-up node of the current stage is disconnected from the current stage's driving control node; wherein, j is greater than i, and i is greater than d; the driving output module, connected to the current stage's driving control node and the current stage's clock signal line, is configured to: output the current stage's gate driving signal under the action of the driving control node's voltage and the current stage's clock signal.

[0006] Optionally, the nth-level gate driving unit further includes: a second local refresh control module, connected to the driving control node of the current level, configured to: in local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, charge the driving control node of the current level during the non-overlapping period of the clock signal of the current level.

[0007] Optionally, the first refresh control module includes: a first control submodule, connected to the nj-th level transmission output module and the current level's drive control node, configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, charge the current level's drive control node under the action of the nj-th level's transmission signal during the current level's pre-charge period; if the current level is a refresh line and the n+d-th level is a non-refresh line, charge the current level's drive control node under the action of the nj-th level's transmission signal before the current level's pre-charge period. Line charging; the second control submodule, connected to the pull-up node and the drive control node of the current level, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, during the non-overlapping period of the current level clock signal, control the pull-up node of the current level to be electrically connected to the drive control node of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, at the start of the (n+di)th level clock signal, control the pull-up node of the current level to be disconnected from the drive control node of the current level.

[0008] Optionally, the first control submodule includes: a first transistor and a second transistor; the control terminal of the first transistor is connected to the njth stage transmission output module, the first terminal of the first transistor is connected to the first brush control terminal, the second terminal of the first transistor is connected to the current stage drive control node and the control terminal of the second transistor; the first terminal of the second transistor is connected to the current stage pull-up node, and the second terminal of the second transistor is connected to the current stage drive control node.

[0009] Optionally, the second control submodule includes: a third transistor; the control terminal of the third transistor is connected to the second brush control terminal, the first terminal of the third transistor is connected to the pull-up node of the current stage, and the second terminal of the third transistor is connected to the drive control node of the current stage.

[0010] Optionally, the first control submodule includes: a first transistor; the control terminal of the first transistor is connected to the nj-th level transmission output module, the first terminal of the first transistor is connected to the first local brush control terminal, and the second terminal of the first transistor is connected to the current level drive control node.

[0011] Optionally, the second refresh control module includes: a first pre-charge submodule, connected to the pre-charge control node of the current level, configured to: charge the pre-charge control node of the current level during the vertical blanking period of the previous scan frame; and a second pre-charge submodule, connected to the pre-charge control node and the drive control node of the current level, configured to: in partial refresh mode, if the current level is a non-refresh line and the (n+d)th level is a refresh line, during the non-overlapping period of the clock signal of the (n+d)th level, control the electrical connection between the pre-charge control node and the drive control node of the current level.

[0012] Optionally, the first precharge submodule includes: a fourth transistor and a first capacitor; the control terminal of the fourth transistor is connected to the control terminal of the third brush, the first terminal of the fourth transistor is connected to the control terminal of the third brush, and the second terminal of the fourth transistor is connected to the first terminal of the first capacitor; the second terminal of the first capacitor is connected to the precharge control node of the current stage.

[0013] Optionally, the second precharge submodule further includes: a fifth transistor; the control terminal of the fifth transistor is connected to the fourth brush control terminal, the first terminal of the fifth transistor is connected to the precharge control node of the current stage, and the second terminal of the fifth transistor is connected to the drive control node of the current stage.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the driving output module of the gate driving circuit being connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, a first-level refresh control module is configured. If the nd-th level is a refresh row, or if the nd-th level is a non-refresh row and the current level is a refresh row, during the pre-charge period of the current level, the drive control node of the current level is charged under the action of the stage transmission signal of the nj-th level. At the start of the non-overlapping period of the current level's clock signal, the pull-up node of the current level is electrically connected to the drive control node of the current level. This ensures that when the current level's clock signal arrives, the gate drive signal of the current level is output to refresh the pixels, thereby achieving partial refresh of the display panel. No gate drive signal is output in the nd-th level, avoiding partial refresh areas. The edge display is abnormal; if the current level is a refresh row and the n+d level is a non-refresh row, before the pre-charge period of the current level, the drive control node of the current level is charged under the action of the stage transmission signal of the nj level, and when the clock signal of the n+di level starts, the pull-up node of the current level is disconnected from the drive control node of the current level, so that when the clock signal of the current level arrives, the drive output module outputs the stage transmission signal of the current level to refresh the pixels of the current level, thereby realizing the partial refresh of the display panel. No gate drive signal is output in the n+d level to avoid the edge display abnormality of the local refresh area. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0021] Figure 4 A first operating timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A second timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0023] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0024] Figure 7 A third operating timing diagram of a gate driving unit provided in an embodiment of this application is shown.

[0025] Explanation of reference numerals in the attached figures: 100. Gate drive unit; 110. Pull-up module; 120. Stage output module; 130. First brush control module; 131. First control submodule; 132. Second control submodule; 140. Drive output module; 150. Second brush control module; 151. First precharge submodule; 152. Second precharge submodule; 153. Reset submodule; 160. Pull-down module; 170. Noise reduction module.

[0026] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; SW1, first brush control terminal; SW2, second brush control terminal; SW3, third brush control terminal; SW4, fourth brush control terminal; Reset, reset control terminal; VSS, low level terminal; Qn, pull-up node of the current stage; Qsn, drive control node of the current stage; An, precharge control node of the current stage. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0028] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0029] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0030] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth stage gate driving unit 100 includes: a pull-up module 110, a stage transmission output module 120, a first brush control module 130, and a drive output module 140. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage transmission output module 120 is connected to the pull-up node Qn of the current stage and the clock signal line CKm of the current stage. The first brush control module 130 is connected to the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, and the njth stage transmission output module 120. The drive output module 140 is connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage.

[0031] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the output terminal of the ni-th stage transmission module, Fn represents the output terminal of the current stage transmission module, and Gn represents the output terminal of the current stage drive output module.

[0032] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn of the current stage in response to the output signal of the nth stage gate drive unit 100.

[0033] For example, the output signal of the ni-th stage gate drive unit 100 can be the stage transmission signal of the ni-th stage. When the pull-up module 110 receives the stage transmission signal of the ni-th stage, it is turned on to charge the pull-up node Qn of the current stage to generate a voltage on the current pull-up node. i can be 2.

[0034] In some embodiments, the stage transmission module 120 is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node Qn of the current stage and the clock signal of the current stage.

[0035] For example, since there is a pre-charge voltage on the pull-up node Qn of the current stage, when the clock signal of the current stage arrives, the stage transmission module 120 will be turned on, outputting the stage transmission signal of the current stage for stage transmission, which will act on the gate drive unit 100 of the adjacent stage.

[0036] In some embodiments, the first refresh control module 130 is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, during the pre-charge period of the current level, under the action of the level transmission signal of the nj-th level, charge the drive control node Qsn of the current level, and at the start of the non-overlapping period of the clock signal of the current level, control the pull-up node Qn of the current level to be electrically connected to the drive control node Qsn of the current level; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, before the pre-charge period of the current level, under the action of the level transmission signal of the nj-th level, charge the drive control node Qsn of the current level, and at the start of the clock signal of the (n+di)-th level, control the pull-up node Qn of the current level to be disconnected from the drive control node Qsn of the current level; wherein, j is greater than i, and i is greater than d.

[0037] It should be noted that the display panel includes multiple gate driving units 100. In the global refresh mode, each gate driving unit 100 needs to output a gate driving signal to refresh each pixel. In the partial refresh mode, some gate driving units 100 in the display panel output gate driving signals to refresh the pixels locally, without each gate driving unit 100 needing to output a gate driving signal to refresh the pixels.

[0038] For example, d can be 1 and j can be 3. If the nd-th level is a non-refresh line and the current level is a refresh line, that is, when switching from a non-refresh line to a refresh line, since the pull-up node Qn of the current level is electrically connected to the drive control node Qsn of the current level at the beginning of the non-overlapping period of the current level clock signal; for the nd-th level, during the pre-charge period of the current level, which is the output period of the ni-th level clock signal, the ndj-th level transmission signal has been pulled down to a low potential, and the first refresh control module 130 will not be able to charge the drive control node of the nd-th level. Since there is no pre-charge voltage on the drive control node of the nd-th level, when the nd-th level clock signal arrives, the drive output module 140 of the nd-th level will not output the gate drive signal to refresh the pixel, which can avoid local refresh. The edge of the new area shows abnormalities; for the current level, during the pre-charge period of the current level, the drive control node Qsn of the current level is charged under the action of the stage transmission signal of the nj level. Even if the pull-up node Qn and the drive control node Qsn of the current level are only turned on during the non-overlapping period of the current level clock signal, the drive output module 140 can output the gate drive signal of the current level when the current level clock signal arrives, ensuring the stability of the gate drive signal of the current level. Moreover, the first refresh control module 130 controls the pull-up node Qn and the drive control node Qsn of the current level to be turned on during the non-overlapping period of the current level clock signal, which can ensure that the gate drive unit 100 after the current level can normally output the gate drive signal to refresh the pixel.

[0039] For example, if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, then when the refresh row switches to a non-refresh row, the drive control node Qsn of the current stage is charged before the pre-charge period of the current stage. At the start of the (n+di)th stage clock signal, the pull-up node Qn of the current stage is disconnected from the drive control node Qsn. For the current stage, the drive control node Qsn has already been pre-charged under the action of the stage transmission signal of the (nj)th stage before the pre-charge period, i.e., before the arrival of the (ni)th stage clock signal. When the current stage clock signal arrives, this ensures that the drive output module 140 outputs the gate drive signal of the current stage. To ensure the stability of the gate drive signal of the current stage; for the n+d stage, since the cascade signal of the n+dj stage is not output before the pre-charge period of the current stage, the first refresh control module 130 will not charge the drive control node of the n+d stage, and when the clock signal of the n+d stage arrives, the pull-up node of the n+d stage is disconnected from the drive control node of the n+d stage, and there is no pre-charge voltage on the drive control node of the n+d stage. When the clock signal of the n+d stage arrives, the drive output module 140 of the n+d stage will not output the gate drive signal to refresh the pixel, thereby avoiding abnormal display at the edge of the local refresh area of ​​the display panel.

[0040] In some embodiments, the drive output module 140, connected to the drive control node Qsn of the current stage and the clock signal line CKm of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

[0041] For example, when there is a voltage on the current stage's drive control node Qsn and the current stage's clock signal arrives, the drive output module 140 will be turned on to output the current stage's gate drive signal to refresh the current stage's pixels.

[0042] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the nth-stage gate drive unit 100 further includes a second local refresh control module 150, which is connected to the current stage drive control node Qsn and is configured to charge the current stage drive control node Qsn during the non-overlapping period of the current stage clock signal if the nd-th stage is a non-refresh line and the current stage is a refresh line in local refresh mode.

[0043] For example, each clock signal level includes overlapping and non-overlapping periods. The non-overlapping period represents the time when the current clock signal does not overlap with the previous clock signal. Since the pre-charge period of the current level (the output period of the ni-th clock signal) and the nj-th clock signal overlap, the charging time of the current level's drive control node Qsn is less than the charging time of the normal level during global refresh. By setting the second refresh control module 150 to charge the current level's drive control node Qsn during the non-overlapping period of the current level's clock signal, the voltage of the current level's drive control node Qsn will increase, promoting the conduction of the drive output module 140 and improving the stability of the current level's gate drive signal output. For the nd-th level, since the nd-th level's clock signal has ended during the non-overlapping period of the current level's clock signal, the second refresh control module 150 will charge the nd-th level's drive control node, and will not output the nd-th level's gate drive signal, thus avoiding abnormal display at the edges of the local refresh area of ​​the display region.

[0044] In some embodiments, please refer to Figure 2 As shown, the first control module 130 includes: a first control submodule 131 and a second control submodule 132. The first control submodule 131 is connected to the njth level transmission output module 120 and the current level drive control node Qsn. The second control submodule 132 is connected to the current level pull-up node Qn and the current level drive control node Qsn.

[0045] In some embodiments, the first control submodule 131 is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, charge the drive control node Qsn of the current level under the action of the level transmission signal of the nj level during the pre-charge period of the current level; if the current level is a refresh line and the n+d level is a non-refresh line, charge the drive control node Qsn of the current level under the action of the level transmission signal of the nj level before the pre-charge period of the current level.

[0046] In some embodiments, the second control submodule 132, connected to the pull-up node Qn of the current level and the drive control node Qsn of the current level, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, control the pull-up node Qn of the current level and the drive control node Qsn of the current level to be electrically connected during the non-overlapping period of the clock signal of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, control the pull-up node Qn of the current level and the drive control node Qsn of the current level to be disconnected when the clock signal of the (n+di)th level starts.

[0047] For example, if the nd-th stage is a non-refresh line and the current stage is a refresh line, i.e., when switching from a non-refresh line to a refresh line, the first control submodule 131 controls the charging of the current stage's drive control node Qsn under the action of the stage transmission signal of the nj-th stage during the pre-charge period of the current stage. Since the second control submodule 132 controls the electrical connection between the pull-up node Qn of the current stage and the drive control node Qsn of the current stage at the start of the non-overlapping period of the current stage's clock signal; for the nd-th stage, during the pre-charge period of the current stage, which is the output period of the ni-th stage's clock signal, the stage transmission signal of the ndj-th stage has been pulled down to a low potential, and the first control submodule 131 will be unable to charge the drive control node of the nd-th stage. Since there is no pre-charge voltage on the drive control node of the nd-th stage, the drive output module 140 of the nd-th stage will not output a gate drive signal when the clock signal of the nd-th stage arrives. Refreshing pixels can prevent abnormal display in local refresh areas of the display panel. For the current level, during the pre-charging period of the current level, the first control submodule 131 charges the drive control node Qsn of the current level under the action of the stage transmission signal of the nj level. Even if the second control submodule 132 controls the pull-up node Qn and the drive control node Qsn of the current level to be turned on only during the non-overlapping period of the current level clock signal, the drive output module 140 can still output the gate drive signal of the current level when the current level clock signal arrives, ensuring the stability of the gate drive signal of the current level. Furthermore, the second control submodule 132 controls the pull-up node Qn and the drive control node Qsn of the current level to be turned on during the non-overlapping period of the current level clock signal, which can ensure that the gate drive unit 100 after the current level can normally output the gate drive signal to refresh the pixels.

[0048] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, that is, when the refresh row switches to a non-refresh row, before the pre-charge period of the current level, the first control submodule 131 charges the drive control node Qsn of the current level under the action of the clock signal of the (nj)th level. When the clock signal of the (n+di)th level starts, the second control submodule 132 controls the pull-up node Qn of the current level to disconnect from the drive control node Qsn of the current level. For the current level, before the pre-charge period, that is, before the arrival of the clock signal of the (ni)th level, the drive control node Qsn of the current level has been pre-charged by the first control submodule 131 under the action of the stage transmission signal of the (nj)th level. When the clock signal of the current level arrives, it can ensure that the current level is charged. The drive output module 140 outputs the gate drive signal of the current stage, thereby ensuring the stability of the gate drive signal of the current stage. For the n+d stage, since the transmission signal of the n+dj stage is not output before the pre-charge period of the current stage, the first control submodule 131 will not charge the drive control node Qsn+d of the n+d stage. When the clock signal of the n+di stage arrives, the second control submodule 132 controls the pull-up node of the n+d stage to disconnect from the drive control node of the n+d stage. There is no pre-charge voltage on the drive control node Qsn+d of the n+d stage. When the clock signal of the n+d stage arrives, the n+d stage will not output the gate drive signal to refresh the pixel, thereby avoiding abnormal display of the edge of the local refresh area of ​​the display panel.

[0049] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the first control submodule 131 includes: a first transistor T1 and a second transistor T2; the control terminal of the first transistor T1 is connected to the njth stage transmission output module 120, the first terminal of the first transistor T1 is connected to the first brush control terminal SW1, the second terminal of the first transistor T1 is connected to the current stage drive control node Qsn and the control terminal of the second transistor T2; the first terminal of the second transistor T2 is connected to the current stage pull-up node Qn, and the second terminal of the second transistor T2 is connected to the current stage drive control node Qsn.

[0050] For example, when the control terminal of the first transistor T1 receives the stage transmission signal of the njth stage, and the first terminal of the first transistor T1 receives the first brush control signal output by the first brush control terminal SW1, the first transistor T1 will be turned on to charge the drive control node Qsn of the current stage; at the same time, the high-level signal output by the first transistor T1 will control the second transistor T2 to be turned on, and the second transistor T2 will control the pull-up node Qn of the current stage to be electrically connected to the drive control node Qsn of the current stage. When there is voltage in the pull-up node Qn of the current stage, it will charge the drive control node Qsn of the current stage.

[0051] In some embodiments, please refer to Figure 3 As shown, the second control submodule 132 includes: a third transistor T3; the control terminal of the third transistor T3 is connected to the second brush control terminal SW2, the first terminal of the third transistor T3 is connected to the pull-up node Qn of the current stage, and the second terminal of the third transistor T3 is connected to the drive control node Qsn of the current stage.

[0052] For example, when the control terminal of the third transistor T3 receives the second brush control signal output by the second brush control terminal SW2, the third transistor T3 will be turned on, realizing the electrical connection between the pull-up node Qn of the current stage and the drive control node Qsn of the current stage.

[0053] Figure 4 This paper shows a first operating timing diagram of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, if the nd level is a non-refresh line and the current level is a refresh line, that is, when the non-refresh line switches to the refresh line, for the nd level, during the overlapping period (t6~t7) of the pre-charge period of the current level, the ndj level transmission signal has not yet been output, and the first transistor T1 will not be turned on, so the drive control node of the nd level will not be charged; at the same time, during the non-overlapping period of the current level clock signal, the pull-up node of the nd level is electrically connected to the drive control node of the nd level, and there is no pre-charge voltage on the nd level. When the clock signal of the nd level arrives, the drive output module 140 of the nd level will not output the gate drive signal, thereby avoiding abnormal local refresh edges of the display panel.

[0054] For example, in the overlapping period (t6~t7) of the pre-charge period of the current stage, the first terminal of the first transistor T1 receives the first brush control signal, and at the same time, the control terminal of the first transistor T1 receives the stage transmission signal of the nj stage and turns on, which will charge the drive control node Qsn of the current stage. The high-level signal output by the first transistor T1 will control the second transistor T2 to turn on, thereby controlling the electrical connection between the pull-up node Qn of the current stage and the drive control node Qsn of the current stage. During the period t6~t7, there is voltage in the pull-up node Qn of the current stage, which will charge the drive control node Qsn of the current stage, making the pre-charge voltage of the current stage more sufficient, which will promote the drive output. Module 140 is turned on; when the current stage clock signal arrives (t8~t9), the drive output module 140 will output the gate drive signal of the current stage; at the beginning of the non-overlapping period of the current stage clock signal (t9), the second refresh control terminal SW2 outputs the second refresh control signal to control the third transistor T3 to turn on. The third transistor T3 controls the electrical connection between the pull-up node Qn of the current stage and the drive control node Qsn of the current stage. The pull-up node Qn of the current stage will further promote the turn-on of the drive output module 140, making the gate drive signal output by the drive output module 140 more stable. The pull-up nodes in the gate drive units 100 after the current stage will be connected to the drive control node to realize normal stage refresh.

[0055] Figure 5 A second timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 5 As shown, if the current level is a refresh line and the (n+d)th level is a non-refresh line, that is, when the refresh line switches to a non-refresh line, for the current level, before the pre-charge period of the current level (t4~t5), the control terminal of the first transistor T1 receives the stage transmission signal of the njth level, and the first terminal of the first transistor T1 receives the first brush control signal output by the first brush control terminal SW1 and turns on, which will charge the drive control node Qsn of the current level. When the control terminal of the fourth transistor T4 starts at the beginning of the clock signal of the (n+di)th level (t6), it controls the pull-up node Qn of the current level to disconnect from the drive control node Qsn of the current level. During the overlapping period of the nith level (t5~t6), the pull-up node Qn of the current level will charge the drive control node Qsn of the current level. When the clock signal of the current level arrives, the gate drive signal of the current level will be output for refresh.

[0056] For example, for the n+d stage, before the pre-charge period of the current stage (t4~t5), the output terminal (Fn-2) of the drive output module 140 of the n+di stage has not yet output the stage transmission signal, the first transistor T1 will not be turned on, and the first transistor T1 will not charge the drive control node of the n+d stage; at the same time, when the clock signal of the n+di stage starts (t6), the third transistor T3 controls the pull-up node of the n+d stage to disconnect from the drive control node of the n+d stage. There is no pre-charge voltage on the drive control node of the n+d stage, the drive output module 140 of the n+d stage will not be turned on, and will not output the gate drive signal, thus avoiding abnormal display of the edge of the local refresh area of ​​the display panel.

[0057] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 6 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the njth level transmission output module 120, the first terminal of the first transistor T1 is connected to the first local brush control terminal SW1, and the second terminal of the first transistor T1 is connected to the current level drive control node Qsn.

[0058] For example, when the control terminal of the first transistor T1 receives the stage transmission signal of the njth stage, and the first terminal of the first transistor T1 receives the first brush control signal output by the first brush control terminal SW1, the first transistor T1 will be turned on to charge the drive control node Qsn of the current stage.

[0059] It should be noted that, Figure 6 The first control submodule 131 and Figure 3 The difference in the working principle of the first control submodule 131 is that... Figure 6 When the first transistor T1 is turned on, it no longer controls the electrical connection between the pull-up node Qn and the drive control node Qsn of the current stage. When switching from a non-refresh line to a refresh line, during the pre-charge period (t6~t7) of the current stage, the pull-up node Qn of the current stage no longer charges the drive control node Qsn of the current stage, but the first transistor T1 charges the drive control node Qsn of the current stage. There is a voltage on the drive control node Qsn of the current stage, and the drive output module 140 can still be turned on when the clock signal of the current stage arrives. The working principle and timing of the rest are as follows. Figure 3 The embodiments described herein are the same; therefore, the working principle of the remaining parts will not be repeated here. Compared to Figure 3 In the Chinese embodiment, Figure 6 The first control submodule 131 can reduce the number of transistors, save costs, and reduce leakage paths.

[0060] In some embodiments, please refer to Figure 5 and Figure 6 As shown, the second pre-charge control module 150 includes: a first pre-charge sub-module 151 and a second pre-charge sub-module 152. The first pre-charge sub-module 151 is connected to the current level pre-charge control node An, and the second pre-charge sub-module 152 is connected to the current level pre-charge control node An and the current level drive control node Qsn.

[0061] In some embodiments, the first precharge submodule 151 is configured to charge the current level precharge control node An during the vertical blanking period of the previous scan frame.

[0062] For example, Figure 7 This paper illustrates a third timing diagram of a gate drive circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 7 As shown, each scan frame includes a scanning period (Blanking) and a vertical blanking period (Scanning). During the vertical blanking period of the previous scan frame, the precharge control node An of the current stage is charged so as to charge the drive control node Qsn of the current stage during the non-overlapping period of the clock signal of the n+d stage, and to avoid interference with the scanning period.

[0063] In some embodiments, the second precharge submodule 152 is configured to: in partial refresh mode, if the current level is a non-refresh line and the n+d level is a refresh line, during the non-overlapping period of the clock signal of the n+d level, control the voltage of the precharge control node An of the current level to be electrically connected with the drive control node Qsn of the current level.

[0064] For example, by setting the second precharge submodule 152, during the non-overlapping clock of the n+d level clock signal, the precharge control node An of the current level and the drive control node Qsn of the current level are electrically connected. The voltage of the precharge control node An of the current level will be transmitted to the current drive control node, increasing the voltage of the drive control node Qsn of the current level. During the non-overlapping period of the n+d level clock signal, the drive output module 140 is turned on, improving the stability of the gate drive signal of the current level.

[0065] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the first precharge submodule 151 includes: a fourth transistor T4 and a first capacitor C1; the control terminal of the fourth transistor T4 is connected to the third brush control terminal SW3, the first terminal of the fourth transistor T4 is connected to the third brush control terminal SW3, and the second terminal of the fourth transistor T4 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the precharge control node An of the current stage.

[0066] For example, please refer to Figure 7As shown, when the control terminal of the fourth transistor T4 receives the third brush control signal issued by the third brush control terminal SW3 in the previous scan frame during the vertical blanking period, the fourth transistor T4 will be turned on to charge the first capacitor C1 and generate a voltage at the pre-charge control node An of the current stage.

[0067] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the second precharge submodule 152 also includes: a fifth transistor T5; the control terminal of the fifth transistor T5 is connected to the fourth brush control terminal SW4, the first terminal of the fifth transistor T5 is connected to the precharge control node An of the current stage, and the second terminal of the fifth transistor T5 is connected to the drive control node Qsn of the current stage.

[0068] For example, please refer to Figure 4 As shown, when the control terminal of the fifth transistor T5 receives the non-overlapping period (t9~t10) of the clock signal of the fourth brush control terminal SW4 at the n+d level, the fifth transistor T5 will be turned on, and the precharge control node An of the current stage will be electrically connected to the drive control node Qsn of the current stage. The voltage of the precharge control node An of the current stage will be transmitted to the drive control node Qsn of the current stage to charge the drive control node Qsn of the current stage.

[0069] In some embodiments, please refer to Figure 3 and Figure 6 As shown, the second brush control module 150 also includes a reset submodule 153, which is connected to the precharge control node An of the current level and is configured to reset the precharge control node An of the current level during the vertical blanking period of the current level.

[0070] For example, by setting the reset submodule 153 to reset the precharge control node of the current stage during the vertical blanking period of the current stage, the precharge control node An of the current stage is charged again in the next scan frame.

[0071] In some embodiments, the reset submodule 153 includes: a sixth transistor T6, the control terminal of the sixth transistor T6 is connected to the reset control terminal Reset, the first terminal of the sixth transistor T6 is connected to the precharge control node An of the current stage, and the second terminal of the sixth transistor T6 is connected to the low-level terminal VSS.

[0072] For example, when the control terminal of the sixth transistor T6 receives the reset control signal issued by the reset control terminal Reset during the vertical blanking period, the sixth transistor T6 turns on and pulls down the precharge control node An of the current stage to a low potential, thereby resetting the precharge control node An of the current stage.

[0073] It should be noted that the effective frame period of the reset control signal is different from that of the third-round brush control signal, and the effective frame period of the reset control signal precedes that of the third-round brush control signal.

[0074] In some embodiments, the pull-up module 110 includes: a seventh transistor T7, the control terminal of the seventh transistor T7 is connected to the ni-th stage transmission output module 120, the first terminal of the seventh transistor T7 is connected to the ni-th stage transmission output module 120, and the second terminal of the seventh transistor T7 is connected to the pull-up node Qn of the current stage.

[0075] For example, when the control terminal of the seventh transistor T7 receives the stage transmission signal of the ni stage, the first terminal of the seventh transistor T7 receives the stage transmission signal of the ni stage, the seventh transistor T7 is turned on to charge the pull-up node Qn of the current stage.

[0076] In some embodiments, the stage output module 120 includes: an eighth transistor T8 and a second capacitor C2. The control terminal of the eighth transistor T8 is connected to the first terminal of the second capacitor C2. The first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage. The second terminal of the eighth transistor T8 is connected to the second terminal of the second capacitor C2 and serves as the stage output terminal of the current stage.

[0077] For example, when the control terminal of the eighth transistor T8 receives the voltage on the pull-up node Qn of the current stage, and the first terminal of the eighth transistor T8 receives the clock signal of the current stage, the second capacitor C2 will bootstrap the pull-up node Qn of the current stage, the eighth transistor T8 will be turned on, and the stage transmission signal of the current stage will be output through the second terminal of the eighth transistor T8.

[0078] In some embodiments, the drive output module 140 includes a ninth transistor T9 and a third capacitor C3. The control terminal of the ninth transistor T9 is connected to the first terminal of the third capacitor C3. The first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage. The second terminal of the ninth transistor T9 is connected to the second terminal of the third capacitor C3 and serves as the drive output terminal of the current stage.

[0079] For example, when the control terminal of the ninth transistor T9 receives the voltage on the current stage's drive control node Qsn, and the first terminal of the ninth transistor T9 receives the current stage's clock signal, the third capacitor C3 will bootstrap the current stage's drive control node Qsn, the ninth transistor T9 will be turned on, and the gate drive signal of the current stage will be output through the second terminal of the ninth transistor T9.

[0080] In some embodiments, the nth-stage gate drive unit 100 further includes a pull-down module 160, which includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The control terminals of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are connected to the output terminal of the stage output module 120 of the n+qth stage. The first terminal of the tenth transistor T10 is connected to the pull-up node Qn of the current stage. The second terminals of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are connected to the low-level segment. The first terminal of the eleventh transistor T11 is connected to the drive output module 140 of the current stage, and the first terminal of the twelfth transistor T12 is connected to the drive control node Qsn of the current stage.

[0081] For example, q can be 3. When the control terminals of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 receive the transmission signal of the (n+q)th stage, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 will be turned on. The tenth transistor T10 pulls down the pull-up node Qn of the current stage to a low potential, the eleventh transistor T11 pulls down the output terminal of the drive output module 140 of the current stage to a low potential, and the twelfth transistor T12 pulls down the drive control node Qsn of the current stage to a low potential, so that the current stage no longer outputs the gate drive signal, and the drive control node Qsn and the pull-up node Qn of the current stage are charged again in the next scan frame.

[0082] In some embodiments, the nth-stage gate driving unit 100 further includes a noise reduction module 170, which is connected to the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the output terminal of the stage transmission output module 120 of the current stage, and the output terminal of the drive output module 140 of the current stage, and is configured to perform noise reduction on the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the output terminal of the stage transmission output module 120 of the current stage, and the output terminal of the drive output module 140 of the current stage when there is no voltage on the pull-up node Qn of the current stage.

[0083] It should be noted that the first brush control terminal SW1, the second brush control terminal SW2, the third brush control terminal SW3, the fourth brush control terminal SW4, and the reset control terminal Reset can all be output terminals of the timing controller. Each stage of the gate drive unit is connected to the first brush control terminal SW1, the second brush control terminal SW2, the third brush control terminal SW3, the fourth brush control terminal SW4, and the reset control terminal Reset. When the first brush control terminal SW1 sends the first brush control signal, the second brush control terminal SW2 sends the second brush control signal, the third brush control terminal SW3 sends the third brush control signal, the fourth brush control terminal SW4 sends the fourth brush control signal, and the reset control terminal Reset sends the reset control signal, each stage of the gate drive unit can receive it.

[0084] In some embodiments, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit described above. The drive output module 140 of the gate driving circuit is connected to at least one scan line.

[0085] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0087] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node of the current stage in response to the output signal of the nith stage gate drive unit. The stage transmission module is connected to the pull-up node of the current stage and the clock signal line of the current stage, and is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node of the current stage and the clock signal of the current stage. The first refresh control module, connected to the pull-up node of the current level, the drive control node of the current level, and the transmission output module of the njth level, is configured as follows: In partial refresh mode, if the ndth level is a non-refresh line and the current level is a refresh line, during the pre-charge period of the current level, the drive control node of the current level is charged under the action of the transmission signal of the njth level, and at the start of the non-overlapping period of the clock signal of the current level, the pull-up node of the current level is electrically connected to the drive control node of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, before the pre-charge period of the current level, the drive control node of the current level is charged under the action of the transmission signal of the njth level, and at the start of the clock signal of the (n+di)th level, the pull-up node of the current level is disconnected from the drive control node of the current level; wherein, j is greater than i, and i is greater than d; The drive output module, connected to the drive control node and the clock signal line of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The second refresh control module, connected to the current level's drive control node, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, charge the current level's drive control node during the non-overlapping period of the current level's clock signal.

3. The gate driving circuit according to claim 1, characterized in that, The first refresh control module includes: The first control submodule, connected to the nj-th level transmission module and the current level's drive control node, is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, charge the current level's drive control node under the action of the nj-th level's transmission signal during the current level's pre-charge period; if the current level is a refresh line and the n+d-th level is a non-refresh line, charge the current level's drive control node under the action of the nj-th level's transmission signal before the current level's pre-charge period. The second control submodule, connected to the pull-up node and the drive control node of the current level, is configured to: in partial refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, control the pull-up node of the current level to be electrically connected to the drive control node of the current level during the non-overlapping period of the clock signal of the current level; if the current level is a refresh line and the (n+d)th level is a non-refresh line, control the pull-up node of the current level to be disconnected from the drive control node of the current level at the start of the clock signal of the (n+di)th level.

4. The gate driving circuit according to claim 3, characterized in that, The first control submodule includes: a first transistor and a second transistor; The control terminal of the first transistor is connected to the njth level transmission output module, the first terminal of the first transistor is connected to the first local brush control terminal, and the second terminal of the first transistor is connected to the current level drive control node and the control terminal of the second transistor. The first terminal of the second transistor is connected to the pull-up node of the current stage, and the second terminal of the second transistor is connected to the drive control node of the current stage.

5. The gate driving circuit according to claim 3, characterized in that, The second control submodule includes: a third transistor; The control terminal of the third transistor is connected to the control terminal of the second brush, the first terminal of the third transistor is connected to the pull-up node of the current stage, and the second terminal of the third transistor is connected to the drive control node of the current stage.

6. The gate driving circuit according to claim 3, characterized in that, The first control submodule includes: a first transistor; The control terminal of the first transistor is connected to the nj-th stage transmission output module, the first terminal of the first transistor is connected to the first local brush control terminal, and the second terminal of the first transistor is connected to the current stage drive control node.

7. The gate driving circuit according to claim 2, characterized in that, The second-round brush control module includes: The first pre-charge submodule, connected to the current level pre-charge control node, is configured to charge the current level pre-charge control node during the vertical blanking period of the previous scan frame. The second precharge submodule, connected to the precharge control node and the drive control node of the current level, is configured to: in partial refresh mode, if the current level is a non-refresh line and the (n+d)th level is a refresh line, during the non-overlapping period of the clock signal of the (n+d)th level, control the precharge control node and the drive control node of the current level to be electrically connected.

8. The gate driving circuit according to claim 7, characterized in that, The first pre-charge submodule includes: a fourth transistor and a first capacitor; The control terminal of the fourth transistor is connected to the control terminal of the third brush, the first terminal of the fourth transistor is connected to the control terminal of the third brush, and the second terminal of the fourth transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the precharge control node of the current stage.

9. The gate driving circuit according to claim 7, characterized in that, The second precharge submodule also includes: a fifth transistor; The control terminal of the fifth transistor is connected to the control terminal of the fourth brush, the first terminal of the fifth transistor is connected to the precharge control node of the current stage, and the second terminal of the fifth transistor is connected to the drive control node of the current stage.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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