Carrier synchronization control method and power conversion device

Abstract

The application discloses a carrier synchronization control method and a power conversion device. The method comprises the following steps: generating a synchronization pulse signal group, the synchronization pulse signal group comprising N pulse signals, the pulse widths of the pulse signals being different from each other, and the pulse widths of the pulse signals being associated with the identification information of each power sub-module; sending the synchronization pulse signal group to the power sub-modules; in response to the first edge of each pulse signal, controlling the power sub-module corresponding to the identification information to enter a pre-synchronization state; in response to the second edge of the pulse signal associated with the identification information of the power sub-module, controlling the corresponding power sub-module to synchronize and reset a locally generated carrier signal; and the carrier signals of adjacent power sub-modules have a preset phase difference after being synchronized and reset. Thus, the accurate synchronization of the carrier phase of each power sub-module can be realized under a distributed control architecture.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a carrier synchronization control method and a power conversion device. Background Technology

[0002] Existing power conversion systems typically consist of N cascaded power submodules, each generating switching control signals via carrier modulation. To achieve smooth multi-level output, the carrier signals of each power submodule usually need to maintain a specific phase relationship. Current power conversion systems typically employ a centralized control scheme, where all switching signals are generated by a central control chip. This chip can internally generate multiple carrier signals that satisfy the aforementioned phase difference and corresponding switching signals. However, the centralized scheme places high demands on the pulse width modulation (PWM) resources and pin count of the central controller, especially when the number of power submodules is large, making centralized control difficult to implement in terms of hardware resources. Therefore, a distributed control scheme has become an alternative. In a distributed scheme, each power submodule independently receives control signals and independently generates its own local carrier and switching signals. Under this distributed architecture, how to control the carrier phase relationship between the power submodules becomes a pressing technical problem to be solved. Summary of the Invention

[0003] The purpose of this application is to provide a carrier synchronization control method and a power conversion device that can achieve precise synchronization of the carrier phase of each power submodule under a distributed control architecture.

[0004] To achieve the above objectives: In a first aspect, embodiments of this application provide a carrier synchronization control method applied to a power conversion device, the power conversion device comprising N cascaded power sub-modules, the method comprising: A synchronization pulse signal group is generated, which includes N pulse signals, each pulse signal having a different pulse width, and the pulse width of each pulse signal is associated with the identification information of each power submodule. The synchronization pulse signal group is sent to the power submodule; In response to the first edge of each of the pulse signals, the power submodule corresponding to the identification information is controlled to enter the pre-synchronization state; In response to the second edge of the pulse signal associated with the power submodule identification information, the corresponding power submodule is controlled to synchronously reset the locally generated carrier signal; The carrier signals of adjacent power submodules have a preset phase difference after being synchronously reset.

[0005] In one embodiment, the preset phase difference is 180° / N.

[0006] In one embodiment, the first edge is a rising edge and the second edge is a falling edge.

[0007] In one embodiment, the signal period of each pulse signal is the same as the carrier period of the power submodule, and one pulse signal is transmitted within each carrier period.

[0008] In one embodiment, the difference in pulse width between adjacent pulse signals corresponds to the preset phase difference, and the pulse width of each pulse signal increases or decreases according to the transmission order.

[0009] In one embodiment, sending the synchronization pulse signal group to the power submodule includes: broadcasting the synchronization pulse signal group to all the power submodules via a bus.

[0010] In one embodiment, the power conversion device is an H-bridge cascaded multilevel converter, a half-bridge modular multilevel converter, or a full-bridge modular multilevel converter.

[0011] Secondly, embodiments of this application provide a power conversion device for implementing the carrier synchronization control method described above, the device comprising: The main control unit is used to generate a synchronization pulse signal group and send it to all power submodules. The synchronization pulse signal group includes N pulse signals, each pulse signal having a different pulse width, and the pulse width of each pulse signal is associated with the identification information of each power submodule. N cascaded power sub-modules, each of which is communicatively connected to the main control unit to receive the synchronization pulse signal group; Each of the power submodules includes a slave control unit, which generates a carrier signal and controls the locally generated carrier signal to be synchronously reset according to the synchronization pulse signal group, so that the carrier signals of adjacent power submodules have a preset phase difference.

[0012] In one embodiment, the main control unit is further configured to generate a modulation signal based on the target voltage; Each of the power submodules further includes a power switching unit, and the slave control unit is further configured to compare the carrier signal with the modulation signal to generate a pulse width modulation switching signal to control the power switching unit to turn on and off, thereby generating a target voltage.

[0013] In one embodiment, the power switching unit includes four power switching transistors that form an H-bridge topology.

[0014] The carrier synchronization control method and power conversion device provided in this application generate a synchronization pulse signal group including N pulse signals. The pulse widths of each pulse signal are different and associated with the identification information of the corresponding power sub-module. At the first edge of each pulse signal, the power sub-module with the corresponding identification information is controlled to enter a pre-synchronization state. At the second edge of the associated pulse signal, the corresponding power sub-module is controlled to synchronize and reset the locally generated carrier signal. In this way, the precise synchronization of the carrier phase of each power sub-module can be achieved under the distributed control architecture, so that the carriers of adjacent power sub-modules maintain a preset phase difference. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a carrier synchronization control method provided in an embodiment of this application.

[0017] Figure 2 This is a timing diagram of a synchronization pulse signal group provided in an embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the structure of a power conversion device provided in an embodiment of this application.

[0019] Figure 4 The circuit topology diagram of the H-bridge submodule provided in one embodiment of this application is shown.

[0020] Figure 5 This is a timing waveform diagram of an H-bridge submodule provided in an embodiment of this application.

[0021] Figure 6 This is a schematic diagram of the output voltage waveform of an H-bridge cascaded multilevel converter provided in an embodiment of this application. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0024] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0025] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0026] It should be noted that step designations such as S110 and S120 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S120 first and then S110, etc., but these should all be within the protection scope of this application.

[0027] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0028] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0029] Figure 1 This is a flowchart illustrating a carrier synchronization control method provided in one embodiment of this application. This application provides a carrier synchronization control method that can be executed by a power conversion device provided in this application. This power conversion device can be a distributed power conversion system such as an H-bridge cascaded multilevel converter, a half-bridge modular multilevel converter, or a full-bridge modular multilevel converter. This embodiment uses an H-bridge cascaded multilevel converter as an example to describe the carrier synchronization control method provided in this application in detail. Figure 1 As shown, the carrier synchronization control method provided in this application includes the following steps: Step S110: Generate a group of synchronization pulse signals.

[0030] Specifically, the power conversion device includes a main control unit and N cascaded power submodules. The main control unit generates a group of N synchronous pulse signals based on the number of power submodules N. The pulse widths of each pulse signal are different and are associated with the identification information of each power submodule. The identification information can be the address number or identification code of the power submodule; for example, the identification information of each power submodule is ID1, ID2, ID3, ..., IDN.

[0031] In this embodiment, the difference in pulse width between adjacent pulse signals corresponds to a preset phase difference. For example, when the preset phase difference is 180° / N, the difference in pulse width between adjacent pulse signals is 1 / (2N) of the carrier period. The pulse width of each pulse signal increases or decreases according to the transmission order; for example, the pulse width W of the i-th pulse signal... i = W0 + (i-1)×ΔT, where W0 is the reference pulse width, i is the identification information, and ΔT is the difference in pulse width between adjacent pulse signals.

[0032] In this embodiment, the signal period of each pulse signal is the same as the carrier period of the power submodule, and one pulse signal is transmitted within each carrier period. For example, the kth pulse signal (k=1, 2, ..., N) is transmitted in the kth carrier period, and the kth pulse signal is transmitted again in the k+Nth carrier period, and so on, to achieve periodic synchronization.

[0033] Step S120: Send the synchronization pulse signal group to the power submodule.

[0034] Specifically, the main control unit sends the generated synchronization pulse signal group to each power submodule. In one embodiment, the main control unit sends the synchronization pulse signal group to all power submodules via bus broadcast. The communication bus can be a Controller Area Network (CAN) bus, RS485 bus, or fiber optic communication link, etc. Each power submodule receives the synchronization pulse signal group through the communication bus and identifies the pulse signal associated with its own identification information.

[0035] S130: In response to the first edge of each pulse signal, control the power submodule with the corresponding identification information to enter the pre-synchronization state.

[0036] Specifically, after receiving a pulse signal from the synchronization pulse signal group, each power submodule detects the first edge of the pulse signal. When the first edge is detected, the power submodule enters a pre-synchronization state, preparing to perform subsequent carrier synchronization reset operations. In this embodiment, the first edge is a rising edge, meaning that each power submodule enters the pre-synchronization state in response to the rising edge of the pulse signal.

[0037] Step S140: In response to the second edge of the pulse signal associated with the power submodule identification information, control the corresponding power submodule to synchronously reset the locally generated carrier signal.

[0038] Specifically, in the pre-synchronization state, each power submodule continuously detects the second edge of the pulse signal associated with its own identification information. When the second edge of the pulse signal associated with its own identification information is detected, the power submodule performs a synchronization reset on the locally generated carrier signal. In one embodiment, the second edge is a falling edge, that is, the power submodule performs zeroing synchronization on the locally generated triangular carrier signal in response to the falling edge of the pulse signal associated with its own identification information.

[0039] Because the pulse widths of each pulse signal are different, the arrival times of their falling edges also differ. Therefore, the carrier zeroing times of each power submodule are also different, thus achieving precise control of the preset phase difference between the carriers of adjacent power submodules. For example, when the preset phase difference is 180° / N, the carrier signals of adjacent power submodules will have a phase difference of 180° / N after synchronous reset.

[0040] In one implementation, to prevent power submodules from erroneously responding to falling edges of non-corresponding pulse signals, each power submodule sets an effective time window in the pre-synchronization state, and only performs synchronization reset on falling edge signals falling within this time window. Specifically, the effective time window corresponding to the power submodule with identifier i is [i×180° / N -90° / N, i×180° / N + 90° / N], where i=1,2,...,N. For example, after receiving a rising edge signal and entering the pre-synchronization state, submodule 1 (i=1) only performs triangular carrier zeroing synchronization on falling edge signals whose time falls within the interval [180° / N - 90° / N, 180° / N + 90° / N]. Submodule 2 (i=2), after receiving a rising edge signal and entering the pre-synchronization state, only performs triangular carrier zeroing synchronization on falling edge signals whose time falls within the interval [2×180° / N - 90° / N, 2×180° / N + 90° / N]. This process continues. In this way, phase control of distributed submodules can be achieved, thus enabling smooth multi-level output.

[0041] The boundaries of the aforementioned effective time window can be adjusted according to the actual system characteristics. For example, in systems with low communication latency and high clock accuracy, the time window can be narrowed to improve synchronization accuracy; in systems with high communication latency and significant clock drift, the time window can be widened to enhance anti-interference capability. The width of the time window is usually set to half of the theoretical phase difference between adjacent sub-modules, i.e., 90° / N, to achieve a balance between synchronization accuracy and anti-interference capability.

[0042] Figure 2 is a timing diagram of a synchronous pulse signal group provided by an embodiment of the present application. As Figure 2 shown, the synchronous pulse signal group in the embodiment of the present application includes N pulse signals P1, P2, P3, ..., PN. Taking N=4 as an example, the pulse width of pulse signal P1 is T1, the pulse width of pulse signal P2 is T2, the pulse width of pulse signal P3 is T3, and the pulse width of pulse signal P4 is T4. Each pulse width satisfies T1<T2<T3<T4 (or T1>T2>T3>T4), the difference ΔT between the pulse widths of adjacent pulse signals is ΔT = Tc / (2N), where Tc is the carrier cycle.

[0043] Each pulse signal has the same signal period Ts, and Ts = Tc. One pulse signal is transmitted in each carrier cycle. Power sub-module 1 (ID1) enters a pre-synchronization state in response to the rising edge of pulse signal P1, and clears and synchronizes the local triangular carrier in response to the falling edge of pulse signal P1; power sub-module 2 (ID2) enters the pre-synchronization state in response to the rising edge of pulse signal P2, and clears and synchronizes the local triangular carrier in response to the falling edge of pulse signal P2; and so on.

[0044] The carrier synchronization method provided by the embodiment of the present application generates a synchronous pulse signal group including N pulse signals, wherein the pulse widths of the pulse signals are different from each other and are associated with the identification information of the corresponding power sub-module, controls the power sub-module with corresponding identification information to enter the pre-synchronization state at the first edge of each pulse signal, and controls the corresponding power sub-module to synchronously reset the locally generated carrier signal at the second edge of the associated pulse signal. In this way, accurate synchronization of the carrier phase of each power sub-module can be achieved under a distributed control architecture, so that the carrier signals of adjacent power sub-modules maintain a preset phase difference, thereby achieving multi-level smooth output of the cascaded power converter without relying on a large number of PWM resources and pins of a central controller.

[0045] Figure 3 is a schematic structural diagram of a power conversion device provided by an embodiment of the present application. As Figure 3 shown, the power conversion device 300 provided by the embodiment of the present application includes a main control unit 310 and N cascaded power sub-modules 320. The main control unit 310 is communicatively connected to each power sub-module 320 through a communication bus 330.

[0046] Specifically, the main control unit 310 is configured to generate a synchronous pulse signal group and send it to all power sub-modules 320. The synchronous pulse signal group includes N pulse signals, the pulse widths of the pulse signals are different from each other, and the pulse width of each pulse signal is associated with the identification information of each corresponding power sub-module.

[0047] Each power submodule 320 includes a slave control unit 321. The slave control unit 321 is used to generate a carrier signal and control the synchronous reset of the local carrier signal according to the synchronization pulse signal group sent by the master control unit 310, so that the carrier signals between adjacent power submodules 320 have a preset phase difference.

[0048] In this embodiment, the main control unit 310 is also used to generate a modulation signal based on the target voltage. Each power submodule 320 also includes a power switch unit 322. The slave control unit 321 is also used to compare the locally generated carrier signal with the modulation signal sent by the main control unit 310 to generate a pulse width modulation (PWM) switching signal to control the on and off of the power switch unit 322, thereby outputting the required target voltage.

[0049] Figure 4 This is a circuit topology diagram of an H-bridge submodule provided in one embodiment of this application. In one application scenario, the power submodule 320 employs an H-bridge module. Figure 4 As shown, the power switching unit 322 includes four power switching transistors S. 11 S 12 S 13 S 14 Four power switches form an H-bridge topology. The H-bridge submodule also includes a DC energy storage unit to provide a DC voltage Udc. By controlling the on and off states of the four power switches, the H-bridge submodule can output three voltage levels: 0, +Udc, or -Udc. In a cascaded H-bridge converter, N H-bridge submodules are connected in series, and the overall output voltage u... o The summation of the output voltages of each submodule is represented by values ​​of 0, ±Udc, ±2Udc, ..., ±NUdc. To achieve smooth multi-level output, the carrier signals of adjacent H-bridge submodules must maintain a phase difference of 180° / N.

[0050] Figure 5 This is a timing waveform diagram of an H-bridge submodule provided in an embodiment of this application. Taking a single H-bridge submodule as an example, a switching control signal is generated by comparing the triangular carrier signal generated by the control unit 321 with the modulation signal. In the actual control process, the power switch S... 11 and S 12 Complementary wave generation, S 13 and S 14 Complementary wave generation, therefore only S needs to be used. 11 and S 13 To implement control. 11 The corresponding triangular carrier and S 13 The corresponding triangular carrier waves exhibit a 180-degree phase difference. For example... Figure 5As shown, when the modulation ratio is 0.8, the final output voltage presents a high level of 0.8Ts and a zero level of 0.2Ts, with an equivalent output of 0.8Udc.

[0051] Figure 6 This is a schematic diagram of the output voltage waveform of an H-bridge cascaded multilevel converter provided in one embodiment of this application. In multilevel modulation, taking four sub-modules as an example, assuming the overall modulation ratio is a sinusoidal waveform, the modulating signal is compared with multiple carrier signals to generate corresponding switching signals. To achieve smooth multilevel output, the carriers of each sub-module maintain a 180° / N phase relationship. For example... Figure 6 As shown, the output voltage waveform of the cascaded H-bridge converter exhibits a multi-level stepped shape, close to a sine wave, with low harmonic content.

[0052] In summary, the carrier synchronization control method and power conversion device provided in this application achieve precise synchronization of the carrier phase of each power submodule under a distributed control architecture through the edge triggering mechanism of the synchronization pulse signal group and the pulse width differential allocation strategy. It does not rely on a large amount of PWM resources of the central controller and has good scalability and practicality.

[0053] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A carrier synchronization control method, characterized in that, Applied to a power conversion device, the power conversion device comprising N cascaded power sub-modules, the method includes: A synchronization pulse signal group is generated, which includes N pulse signals, each pulse signal having a different pulse width, and the pulse width of each pulse signal is associated with the identification information of each power submodule. The synchronization pulse signal group is sent to the power submodule; In response to the first edge of each of the pulse signals, the power submodule corresponding to the identification information is controlled to enter the pre-synchronization state; In response to the second edge of the pulse signal associated with the power submodule identification information, the corresponding power submodule is controlled to synchronously reset the locally generated carrier signal; The carrier signals of adjacent power submodules have a preset phase difference after being synchronously reset.

2. The carrier synchronization control method according to claim 1, characterized in that, The preset phase difference is 180° / N.

3. The carrier synchronization control method according to claim 1, characterized in that, The first edge is a rising edge, and the second edge is a falling edge.

4. The carrier synchronization control method according to claim 1, characterized in that, The signal period of each pulse signal is the same as the carrier period of the power submodule, and one pulse signal is sent within each carrier period.

5. The carrier synchronization control method according to claim 4, characterized in that, The difference in pulse width between adjacent pulse signals corresponds to the preset phase difference, and the pulse width of each pulse signal increases or decreases according to the transmission order.

6. The carrier synchronization control method according to claim 1, characterized in that, Sending the synchronization pulse signal group to the power submodule includes: broadcasting the synchronization pulse signal group to all the power submodules via a bus.

7. The carrier synchronization control method according to claim 1, characterized in that, The power conversion device is an H-bridge cascaded multilevel converter, a half-bridge modular multilevel converter, or a full-bridge modular multilevel converter.

8. A power conversion device, characterized in that, For implementing the carrier synchronization control method as described in any one of claims 1-7, the apparatus comprises: The main control unit is used to generate a synchronization pulse signal group and send it to all power submodules. The synchronization pulse signal group includes N pulse signals, each pulse signal having a different pulse width, and the pulse width of each pulse signal is associated with the identification information of each power submodule. N cascaded power sub-modules, each of which is communicatively connected to the main control unit to receive the synchronization pulse signal group; Each of the power submodules includes a slave control unit, which generates a carrier signal and controls the locally generated carrier signal to be synchronously reset according to the synchronization pulse signal group, so that the carrier signals of adjacent power submodules have a preset phase difference.

9. The power conversion device according to claim 8, characterized in that, The main control unit is also used to generate a modulation signal based on the target voltage; Each of the power submodules further includes a power switching unit, and the slave control unit is further configured to compare the carrier signal with the modulation signal to generate a pulse width modulation switching signal to control the power switching unit to turn on and off, thereby generating a target voltage.

10. The power conversion device according to claim 9, characterized in that, The power switching unit includes four power switching transistors, which form an H-bridge topology.

Images