High-precision low-offset signal amplification circuit for automotive electronic system

Abstract

This invention relates to a high-precision, low-offset signal amplifier circuit for automotive electronic systems, comprising a two-stage folded common-source common-gate operational amplifier circuit, a reference voltage and bias generation circuit, a programmable current source array, control logic, a high-precision voltage comparator CP, a startup circuit and an oscillator circuit OSC, and six signal selection switches K1~K6. Addressing the accuracy error problem caused by the long-term degradation of device characteristics in traditional laser trimming technology, this invention proposes a hybrid digital-analog compensation offset error calibration technique. The calibration process employs multiple calibration modes in combination and utilizes digital filtering to mitigate the impact of comparator offset voltage on calibration accuracy, reducing the accuracy requirements of the high-precision voltage comparator CP and lowering the overall circuit area overhead. Furthermore, this invention allows for on-the-fly offset calibration of the high-precision, low-offset signal amplifier circuit via a SET signal, improving the accuracy of the high-precision, low-offset signal amplifier circuit under different operating environments. The solution of this invention can be widely applied as a signal amplifier circuit in high-precision automotive electronic systems.

Description

Technical Field

[0001] This invention relates to a high-precision, low-offset signal amplification circuit for automotive electronic systems, belonging to the fields of integrated circuits and automotive electronics technology. Background Technology

[0002] In automotive electronic systems, high-precision operational amplifiers (op-amps) are an integral part of the safety system. They are used in vehicle audio, control systems, and safety systems to ensure driving safety. For example, in braking systems, the stability of precision op-amps ensures reliable braking performance. In battery management systems (BMS), high-precision op-amps are used for current detection, ensuring accurate monitoring of the battery's charge and discharge status. In motor control systems, high-precision op-amps process motor drive signals; for example, inverters and PWM modulation require real-time processing of rapidly changing current signals, necessitating op-amp bandwidths of at least 2MHz to ensure signal integrity. In sensor signal amplification systems, high-precision op-amps amplify signals, suitable for battery current monitoring and solenoid valve control (accuracy must reach ±1%). In circuit design, precision op-amps can serve as components in various circuits such as signal amplifiers, filters, and comparators, providing greater design options and flexibility. In automotive electronics, the offset voltage (Vos) of high-precision operational amplifiers directly affects the accuracy of signal measurements, especially in safety-critical scenarios where stringent performance requirements must be met. Calibration of the input offset voltage of high-precision operational amplifiers is crucial for ensuring measurement accuracy and system stability. Input offset voltage introduces systematic errors, causing output signal deviations. For example, in weak signal detection (such as bioelectrical signals at the microvolt level), if the op-amp offset voltage is at the millivolt level, the error signal may be much larger than the true signal, leading to measurement distortion. In feedback control systems, offset voltage can cause the output voltage to deviate from the setpoint, affecting system stability. For instance, in voltage regulation circuits, offset voltage can cause the output voltage to deviate from the reference value, inducing regulation errors. Modern high-precision operational amplifiers typically employ chopper stabilization and automatic zeroing calibration techniques, which introduce high-frequency EMI interference. Traditional laser trimming techniques, on the other hand, suffer from errors due to long-term degradation of device characteristics. Therefore, providing a high-precision operational amplifier offset voltage calibration technique based on digital compensation calibration is of significant practical importance for high-precision signal amplification circuits in automotive electronic systems. Summary of the Invention

[0003] Based on existing technology, this invention provides a high-precision, low-offset signal amplification circuit for automotive electronic systems, improving the overall efficiency and accuracy of DC-DC controllers. A high-precision, low-offset signal amplification circuit for automotive electronic systems includes a resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113, a reference voltage and bias generation circuit, a programmable current source array, control logic, a high-precision voltage comparator CP, a startup circuit and an oscillator circuit OSC, and six signal selection switches K1~K6. Specifically, the sources of PMOS transistors M100, M102, M104, M106, and M114 are all connected to the power supply voltage VCC; the sources of NMOS transistors M110, M112, and M113 are all connected to ground potential GND; the drain of PMOS transistor M100 is connected to the source of PMOS transistor M101; the gate of PMOS transistor M100 is connected to the bias voltage Vbp1; the gate of PMOS transistor M101 is connected to the bias voltage Vbp2; the gate of PMOS transistor M114 is connected to the bias voltage Vbp3; the gates of NMOS transistors M110 and M112 are connected to the bias voltage Vbn1; and the drain of PMOS transistor M101 is connected to PMOS transistors M107 and M108. The source of 8; the drain of PMOS transistor M102 and the source of PMOS transistor M103 are connected; the gate of PMOS transistor M102 is connected to the drain of PMOS transistor M103, the drain of PMOS transistor M106, the upper end of resistor R13 and the gate of PMOS transistor M104; the gate of PMOS transistor M103 is connected to the lower end of resistor R13 and the gate of PMOS transistor M105, and is also connected to the drain of NMOS transistor M109; the source of PMOS transistor M105 is connected to the drain of PMOS transistor M104; the drain Vtd of PMOS transistor M105 is connected to the drain of NMOS transistor M111, and the Vtd voltage is also connected to the gate of NMOS transistor M113; the drain of NMOS transistor M113 is connected to the drain of PMOS transistor M114 and the upper end of signal selection switch K5, and also serves as the output port Vout of the high-precision low-offset signal amplifier circuit of this invention; The gate AN of PMOS transistor M108 is simultaneously connected to the upper end of signal selection switch K4, the left end of signal selection switch K6, and the right end of signal selection switch K2. The left end of signal selection switch K2 is the differential negative input port VIN of the high-precision low-offset signal amplifier circuit of this invention. The gate AP of PMOS transistor M107 is simultaneously connected to the upper end of signal selection switch K3 and the right end of signal selection switch K1. The left end of signal selection switch K1 is the differential positive input port VIP of the high-precision low-offset signal amplifier circuit of this invention. The drain Aip of PMOS transistor M107 is connected to the positive compensation current Iajp port of the programmable current source array, the source of NMOS transistor M109, and the drain of NMOS transistor M110. The drain Ain of PMOS transistor M108 is connected to the negative compensation current Iajn port of the programmable current source array, the source of NMOS transistor M111, and the drain of NMOS transistor M112. The lower end of signal selection switch K5 is connected to the right end of signal selection switch K6 and the positive analog signal input of high-precision voltage comparator CP. The negative analog signal input of high-precision voltage comparator CP is connected to the comparison reference voltage Vrt. The output of high-precision voltage comparator CP inputs the error data Derr to the error data input of the control operation logic. The control operation logic generates comparator control clock CKcp and offset compensation code Daj based on the input clock OSC, reset signal SET, start signal EN and error data Derr, and respectively feeds them to high-precision voltage comparator CP and programmable current source array. After the chip is powered on, the startup circuit generates a startup signal EN and provides it to the reference voltage and bias generation circuit, the oscillator circuit OSC, and the gate of the PMOS transistor M116. After the startup signal EN is valid, the oscillator circuit OSC outputs the input clock OSC to the clock signal input terminal of the control logic. After the startup signal EN is valid, the reference voltage and bias generation circuit generates bias voltages Vbp3, Vbp2, Vbp1, Vbn1, comparison reference voltage Vrt, calibration positive reference voltage Vrp, calibration negative reference voltage Vrn, reference bias voltage Vrp1, and reference bias voltage Vrp2. Under the control of the offset compensation code Daj, the programmable current source array generates positive compensation current Iajp and negative compensation current Iajn based on the reference bias voltages Vrp1 and Vrp2. The calibration positive reference voltage Vrp and calibration negative reference voltage Vrn are respectively connected to the lower end of the signal selection switch K3. The resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113 constitute a two-stage folded cascode operational amplifier circuit. When the start signal EN is 1, the two-stage folded cascode operational amplifier circuit operates normally. The gates of PMOS transistors M107 and M108, i.e., AP and AN, are the differential input terminals of the two-stage folded cascode operational amplifier circuit. The output port Vout of the high-precision low-offset signal amplifier circuit is the output terminal of the two-stage folded cascode operational amplifier circuit. Furthermore, the high-precision low offset signal amplification circuit for automotive electronic systems includes three modes: standby mode, offset voltage adaptive calibration compensation mode, and normal operation mode. When the power supply voltage is applied, the power-on start signal EN changes from low to high and becomes effective. The reference voltage and bias generation circuit, the oscillator circuit OSC, and the two-stage folded common-source common-gate operational amplifier circuit begin to work normally. The control operation logic generates a set of uncalibrated initial offset compensation code Daj0 for the programmable current source array. The high-precision low offset signal amplification circuit is in standby mode at this time. When the reset signal SET experiences a high-level pulse for more than M OSC cycles, the high-precision low-offset signal amplifier circuit enters the offset voltage adaptive calibration compensation mode. The calibration mode control signal Cali generated internally by the control operation logic will be set to a high level, where M is an integer greater than 1. After Cali has been high for R cycles, the offset voltage adaptive calibration compensation mode is completed. The control operation logic will undergo J calibration compensations to obtain a calibrated offset compensation code Daj1(J), which remains unchanged. Simultaneously, the offset compensation code Daj1(J) is fed to the programmable current source array to generate a positive compensation current Iajp(J) and a negative compensation current Iajn(J), which are injected into Aip and Ain respectively, thereby adjusting the magnitude of the Vout signal and completing the offset voltage compensation for the high-precision low-offset signal amplifier circuit. J is a positive integer greater than 2. After the offset voltage adaptive calibration compensation mode is completed, the high-precision low offset signal amplification circuit enters the normal operation mode. At this time, signal selection switches K1 and K2 are turned on at the same time, and signal selection switches K3~K6 are kept off. The high-precision low offset signal amplification circuit amplifies the differential negative input port VIN and differential positive input port VIP signals with high precision. When the offset voltage adaptive calibration compensation mode is entered, the signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit is turned on, that is, AP is connected to the calibration positive reference voltage Vrp; the signal selection switches K5 and K6 connected to the output port Vout of the high-precision low offset signal amplifier circuit are turned on simultaneously, and the two-stage folded cascode op-amp circuit is connected as a unity-gain buffer circuit; at this time, the high-precision low offset signal amplifier circuit begins to enter the coarse calibration mode in the offset voltage adaptive calibration compensation mode. The control logic will output the comparator control clock CKcp, so that the high-precision voltage comparator CP performs the first comparison between the positive input terminal Vout of its analog signal and the comparison reference voltage Vrt of the negative input terminal of the analog signal. After the comparator control clock CKcp makes the high-precision voltage comparator CP complete a voltage comparison, the error data Derr (1) at the output terminal of the high-precision voltage comparator CP will be input to the error data input terminal of the control logic. The control logic generates a new offset compensation code Daj1 (1) according to the error data Derr (1) and gives it to the programmable current source array. Under the control of Daj1 (1), the programmable current source array generates a positive compensation current Iajp (1) and a negative compensation current Iajn (1) and injects them into the drain Aip of PMOS transistor M107 and the drain Ain of PMOS transistor M108, respectively, thereby adjusting the magnitude of the Vout signal and obtaining the output voltage Vout (1) after the first compensation, thus completing the first compensation of the offset voltage of the high-precision low offset signal amplifier circuit. When the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the Kth voltage comparison between its analog signal positive input terminal Vout(K-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, the error data Derr(K) is obtained and input to the error data input terminal of the control operation logic. Based on the error data Derr(K), the control operation logic generates a new offset compensation code Daj1(K) and feeds it to the programmable current source array to generate a positive compensation current Iajp(K) and a negative compensation current Iajn(K), obtaining the output voltage Vout(K) after the Kth compensation. After completing the Kth compensation of the offset voltage of the high-precision low-offset signal amplifier circuit, the high-precision low-offset signal amplifier circuit completes the coarse calibration mode in the offset voltage adaptive calibration compensation mode and begins to enter the fine calibration mode. K is a positive integer greater than 1 and less than J. The signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit remains on, and the signal selection switch K4 connected to the differential input terminal AN also remains on. That is, AP is connected to the positive calibration reference voltage Vrp, and AN is connected to the negative calibration reference voltage Vrn. The signal selection switch K5 connected to the output port Vout of the high-precision low-offset signal amplifier circuit remains on, while the signal selection switch K6 begins to turn off. The two-stage folded cascode op-amp circuit is connected in an open-loop amplification configuration. The comparator control clock CKcp controls the high-precision voltage comparator. The CP device performs the (K+1)th voltage comparison between its analog signal positive input terminal Vout(K) and the comparison reference voltage Vrt at its analog signal negative input terminal, obtaining error data Derr(K+1) and inputting it to the error data input terminal of the control operation logic. Based on the error data Derr(K+1), the control operation logic generates a new offset compensation code Daj1(K+1) and feeds it to the programmable current source array to obtain the output voltage Vout(K+1) after the (K+1)th compensation, thus completing the (K+1)th compensation of the offset voltage of the high-precision low offset signal amplifier circuit. When the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the J-th voltage comparison between its analog signal positive input terminal Vout(J-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, the error data Derr(J) is obtained and input to the error data input terminal of the control operation logic. Based on the error data Derr(J), the control operation logic generates a new offset compensation code Daj1(J) and sends it to the programmable current source array to obtain the output voltage Vout(J) after the J-th compensation, thus completing the J-th compensation of the offset voltage of the high-precision low-offset signal amplifier circuit. At this time, the high-precision low-offset signal amplifier circuit completes the fine calibration mode in the offset voltage adaptive calibration compensation mode, and simultaneously completes and ends the offset voltage adaptive calibration compensation mode. The high-precision low-offset signal amplifier circuit begins to enter the normal operation mode. At this time, signal selection switches K1 and K2 are simultaneously turned on, while signal selection switches K3~K6 are all turned off. The high-precision low-offset signal amplifier circuit performs high-precision amplification on the differential negative input port VIN and the differential positive input port VIP signals. Furthermore, in coarse calibration mode, the final output of any error data Derr is obtained by multiple comparisons by the comparator and then summed and averaged. The clock periods of the calibration control clock CKctrl and the comparator control clock CKcp used in the internal control logic have the following operational relationship: T CKctrl =L*T CKcp L is a positive integer greater than 1. Specifically, the operational control logic circuit includes: a reset counter, a calibration start control signal generation circuit, a switch selection signal generation circuit, a pulse data filtering circuit, a serial-to-parallel register conversion circuit, an error quantization circuit, a clock frequency divider circuit, a comparison clock generation circuit, an N-bit counter circuit, an N-bit shift register, and latch registers 1 to N, where N is a positive integer not less than J. The reset signal SET first enters the reset counter, is filtered, and then enters the reset signal port of the calibration start control signal generation circuit. The start signal EN is connected to the start signal port of the calibration start control signal generation circuit. The calibration start control signal generation circuit generates a calibration mode control signal Cali based on the reset signal SET and the start signal EN. The calibration mode control signal Cali will be simultaneously output to the calibration mode ports of the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the error quantization circuit, the clock divider circuit, the comparison clock generation circuit, the N-bit counter circuit, the N-bit shift register, and latch registers 1 to N. The circuit generates a calibration control clock CKctrl and a comparator clock source based on the input clock OSC; the calibration control clock CKctrl is output to the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the N-bit counter circuit, and the N-bit shift register; the comparator clock source enters the comparator clock generation circuit to generate the comparator control clock CKcp required by the high-precision comparator CP; the switch selection signal generation circuit generates control signals for the signal selection switches K1-K6 of the high-precision low-offset signal amplifier circuit in different operating modes based on the periodic cyclic reset signal Count output by the N-bit counter circuit and the calibration mode control signal Cali. Error data Derr is input to the pulse data filtering circuit, and after pulse filtering, error-weighted data Dev, arranged in a serial sequence, is obtained and input to the serial-to-parallel register conversion circuit. Under the control of the calibration control clock CKctrl, the serial-to-parallel register conversion circuit converts the error-weighted data Dev, arranged in a serial sequence, into N-bit parallel error-weighted data Devp. After being processed by the error quantization circuit, parallel calibration adjustment code Dajp is obtained. The parallel calibration adjustment code Dajp is simultaneously connected to the adjustment code input port of latch register 1 to latch register N. Under the control of the calibration control clock CKctrl and the calibration mode control signal Cali, the N-bit counter circuit generates the periodic cyclic reset signal Count required by the N-bit shift register. The cycle period of the reset signal is set by the N-bit counter circuit. The N-bit shift register generates a selection signal Sel according to the periodic reset signal provided by the N-bit counter circuit and connects to the selection signal input port of latch register 1 to latch register N respectively. At any time, one latch of latch register 1 to latch register N is selected to be valid. Furthermore, the programmable current source array circuit includes J groups of positive-terminal common-source cascode current sources and J groups of negative-terminal common-source cascode current sources, as well as J inverters; the external control input J-bit adjustment code Daj is daj1~dajJ, which adjusts the gates of the J switching-selection NMOS transistors M513p~M5J3p in the J groups of positive-terminal common-source cascode current sources to realize the adjustment of the positive compensation current Iajp of the programmable current source array; the external control input J-bit adjustment code Daj, after passing through the J inverters, yields adjustment codes daj1B~dajJB, which are opposite to daj1~dajJ, which adjust the gates of the J switching-selection NMOS transistors M513n~M5J3n in the J groups of negative-terminal common-source cascode current sources to realize the adjustment of the negative compensation current Iajn of the programmable current source array; When the high-precision low offset signal amplification circuit is in standby mode, the control operation logic generates a set of uncalibrated initial offset compensation codes Daj0 for the programmable current source array. At this time, the negative compensation current Iajn and the positive compensation current Iajp of the programmable current source array are equal and are at the center value within the current adjustment range. Since the adjustment codes daj1~dajJ are opposite to the adjustment codes daj1B~dajJB, the adjustment directions of the compensation currents Iajn and Iajp are opposite during the offset compensation process. This invention addresses the accuracy error problem caused by the long-term degradation of device characteristics in traditional laser trimming technology. It proposes a hybrid digital-analog offset error compensation calibration technique. The calibration process employs multiple calibration modes in combination and utilizes digital filtering to mitigate the impact of comparator offset voltage on calibration accuracy, reducing the accuracy requirements of the high-precision voltage comparator (CP) and lowering the overall circuit area overhead. Furthermore, this invention allows for on-the-fly offset calibration of the high-precision, low-offset signal amplifier circuit via a SET signal, improving its accuracy under various operating conditions. This solution can be widely applied as a signal amplifier circuit in high-precision automotive electronic systems. Attached Figure Description Figure 1 This is a block diagram of the high-precision, low-offset signal amplifier circuit of the present invention. Figure 2 This is a timing diagram of the high-precision, low-offset signal amplifier circuit of the present invention. Figure 3 This is a schematic diagram of the offset compensation in the coarse calibration mode of the present invention. Figure 4 This is a block diagram of the operational control logic circuit structure of the present invention. Figure 5 This is a schematic diagram of the programmable current source array circuit of the present invention. Detailed Implementation The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. Figure 1 This is a block diagram of a high-precision, low-offset signal amplification circuit for automotive electronic systems according to the present invention. The high-precision, low-offset signal amplification circuit for automotive electronic systems includes: resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113, a reference voltage and bias generation circuit, a programmable current source array, control logic, a high-precision voltage comparator CP, a startup circuit and an oscillator circuit OSC, and six signal selection switches K1~K6. Specifically, the sources of PMOS transistors M100, M102, M104, M106, and M114 are all connected to the power supply voltage VCC; the sources of NMOS transistors M110, M112, and M113 are all connected to ground potential GND; the drain of PMOS transistor M100 is connected to the source of PMOS transistor M101; the gate of PMOS transistor M100 is connected to the bias voltage Vbp1; the gate of PMOS transistor M101 is connected to the bias voltage Vbp2; the gate of PMOS transistor M114 is connected to the bias voltage Vbp3; the gates of NMOS transistors M110 and M112 are connected to the bias voltage Vbn1; and the drain of PMOS transistor M101 is connected to PMOS transistors M107 and M108. The source of 8; the drain of PMOS transistor M102 and the source of PMOS transistor M103 are connected; the gate of PMOS transistor M102 is connected to the drain of PMOS transistor M103, the drain of PMOS transistor M106, the upper end of resistor R13 and the gate of PMOS transistor M104; the gate of PMOS transistor M103 is connected to the lower end of resistor R13 and the gate of PMOS transistor M105, and is also connected to the drain of NMOS transistor M109; the source of PMOS transistor M105 is connected to the drain of PMOS transistor M104; the drain Vtd of PMOS transistor M105 is connected to the drain of NMOS transistor M111, and the Vtd voltage is also connected to the gate of NMOS transistor M113; the drain of NMOS transistor M113 is connected to the drain of PMOS transistor M114 and the upper end of signal selection switch K5, and also serves as the output port Vout of the high-precision low-offset signal amplifier circuit of this invention; The gate AN of PMOS transistor M108 is simultaneously connected to the upper end of signal selection switch K4, the left end of signal selection switch K6, and the right end of signal selection switch K2. The left end of signal selection switch K2 is the differential negative input port VIN of the high-precision low-offset signal amplifier circuit of this invention. The gate AP of PMOS transistor M107 is simultaneously connected to the upper end of signal selection switch K3 and the right end of signal selection switch K1. The left end of signal selection switch K1 is the differential positive input port VIP of the high-precision low-offset signal amplifier circuit of this invention. The drain Aip of PMOS transistor M107 is connected to the positive compensation current Iajp port of the programmable current source array, the source of NMOS transistor M109, and the drain of NMOS transistor M110. The drain Ain of PMOS transistor M108 is connected to the negative compensation current Iajn port of the programmable current source array, the source of NMOS transistor M111, and the drain of NMOS transistor M112. The lower end of signal selection switch K5 is connected to the right end of signal selection switch K6 and the positive analog signal input of high-precision voltage comparator CP. The negative analog signal input of high-precision voltage comparator CP is connected to the comparison reference voltage Vrt. The output of high-precision voltage comparator CP inputs the error data Derr to the error data input of the control operation logic. The control operation logic generates comparator control clock CKcp and offset compensation code Daj based on the input clock OSC, reset signal SET, start signal EN and error data Derr, and respectively feeds them to high-precision voltage comparator CP and programmable current source array. After the chip is powered on, the startup circuit generates a startup signal EN and provides it to the reference voltage and bias generation circuit, the oscillator circuit OSC, and the gate of the PMOS transistor M116. After the startup signal EN is valid, the oscillator circuit OSC outputs the input clock OSC to the clock signal input terminal of the control logic. After the startup signal EN is valid, the reference voltage and bias generation circuit generates bias voltages Vbp3, Vbp2, Vbp1, Vbn1, comparison reference voltage Vrt, calibration positive reference voltage Vrp, calibration negative reference voltage Vrn, reference bias voltage Vrp1, and reference bias voltage Vrp2. Under the control of the offset compensation code Daj, the programmable current source array generates positive compensation current Iajp and negative compensation current Iajn based on the reference bias voltages Vrp1 and Vrp2. The calibration positive reference voltage Vrp and calibration negative reference voltage Vrn are respectively connected to the lower end of the signal selection switch K3. The resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113 constitute a two-stage folded cascode operational amplifier circuit. When the start signal EN is 1, the two-stage folded cascode operational amplifier circuit operates normally. The gates of PMOS transistors M107 and M108, i.e., AP and AN, are the differential input terminals of the two-stage folded cascode operational amplifier circuit. The output port Vout of the high-precision low-offset signal amplifier circuit is the output terminal of the two-stage folded cascode operational amplifier circuit. Figure 1 In the embodiments of the present invention described herein, when the start signal EN is 1, the high-precision low-offset signal amplification circuit for automotive electronic systems includes three modes: a standby mode, an offset voltage adaptive calibration compensation mode, and a normal operating mode. The timing diagram of the high-precision low-offset signal amplification circuit described in the embodiments of the present invention is as follows: Figure 2 As shown. When the power supply voltage is applied, the power-on start signal EN changes from low to high and becomes effective. The reference voltage and bias generation circuit, the oscillator circuit OSC, and the two-stage folded common-source common-gate operational amplifier circuit begin to work normally. The control operation logic generates a set of uncalibrated initial offset compensation code Daj0 for the programmable current source array. The high-precision low offset signal amplification circuit is in standby mode at this time. When the reset signal SET experiences a high-level pulse for more than M OSC cycles, the high-precision low-offset signal amplifier circuit enters the offset voltage adaptive calibration compensation mode. The calibration mode control signal Cali generated internally by the control operation logic will be set to a high level, where M is an integer greater than 1. After Cali has been high for R cycles, the offset voltage adaptive calibration compensation mode is completed. The control operation logic will undergo J calibration compensations to obtain a calibrated offset compensation code Daj1(J), which remains unchanged. Simultaneously, the offset compensation code Daj1(J) is fed to the programmable current source array to generate a positive compensation current Iajp(J) and a negative compensation current Iajn(J), which are injected into Aip and Ain respectively, thereby adjusting the magnitude of the Vout signal and completing the offset voltage compensation for the high-precision low-offset signal amplifier circuit. J is a positive integer greater than 2. After the offset voltage adaptive calibration compensation mode is completed, the high-precision low offset signal amplification circuit enters the normal operation mode. At this time, signal selection switches K1 and K2 are turned on at the same time, and signal selection switches K3~K6 are kept off. The high-precision low offset signal amplification circuit amplifies the differential negative input port VIN and differential positive input port VIP signals with high precision. After the high-precision low-offset signal amplification circuit enters the offset voltage adaptive calibration compensation mode, the signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit is turned on, that is, AP is connected to the calibration positive reference voltage Vrp; the signal selection switches K5 and K6 connected to the output port Vout of the high-precision low-offset signal amplification circuit are turned on simultaneously, and the two-stage folded cascode op-amp circuit is connected as a unity-gain buffer circuit; at this time, the high-precision low-offset signal amplification circuit begins to enter the coarse calibration mode in the offset voltage adaptive calibration compensation mode. The control logic will output the comparator control clock CKcp, so that the high-precision voltage comparator CP performs the first comparison between the positive input terminal Vout of its analog signal and the comparison reference voltage Vrt of the negative input terminal of the analog signal. After the comparator control clock CKcp makes the high-precision voltage comparator CP complete a voltage comparison, the error data Derr (1) at the output terminal of the high-precision voltage comparator CP will be input to the error data input terminal of the control logic. The control logic generates a new offset compensation code Daj1 (1) according to the error data Derr (1) and gives it to the programmable current source array. Under the control of Daj1 (1), the programmable current source array generates a positive compensation current Iajp (1) and a negative compensation current Iajn (1) and injects them into the drain Aip of PMOS transistor M107 and the drain Ain of PMOS transistor M108, respectively, thereby adjusting the magnitude of the Vout signal and obtaining the output voltage Vout (1) after the first compensation, thus completing the first compensation of the offset voltage of the high-precision low offset signal amplifier circuit. Next, the comparator control clock CKcp controls the high-precision voltage comparator CP to perform a second voltage comparison between the analog signal positive input terminal Vout(1) and the comparison reference voltage Vrt at the analog signal negative input terminal, obtaining error data Derr(2) and inputting it to the error data input terminal of the control operation logic; the control operation logic generates a new offset compensation code Daj1(2) based on the error data Derr(2) and sends it to the programmable current source array to generate positive compensation current Iajp(2) and negative compensation current Iajn(2), thereby continuing to adjust the magnitude of the Vout signal to obtain the output voltage Vout(2) after the second compensation, completing the second compensation of the offset voltage of the high-precision low offset signal amplifier circuit; After the Tth OSC clock cycle, the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the Kth voltage comparison between its analog signal positive input terminal Vout(K-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, obtaining error data Derr(K) and inputting it to the error data input terminal of the control operation logic. Based on the error data Derr(K), the control operation logic generates a new offset compensation code Daj1(K) for the programmable current source array, generating a positive compensation current Iajp(K) and a negative compensation current Iajn(K), obtaining the output voltage Vout(K) after the Kth compensation. This completes the Kth compensation of the offset voltage of the high-precision low-offset signal amplifier circuit. At this point, the high-precision low-offset signal amplifier circuit completes the coarse calibration mode in the offset voltage adaptive calibration compensation mode and begins to enter the fine calibration mode; K is a positive integer greater than 1 and less than J. The signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit remains on, and the signal selection switch K4 connected to the differential input terminal AN also remains on. That is, AP is connected to the positive calibration reference voltage Vrp, and AN is connected to the negative calibration reference voltage Vrn. The signal selection switch K5 connected to the output port Vout of the high-precision low-offset signal amplifier circuit remains on, while the signal selection switch K6 begins to turn off. The two-stage folded cascode op-amp circuit is connected in an open-loop amplification configuration. The comparator control clock CKcp controls the high-precision voltage comparator. The CP device performs the (K+1)th voltage comparison between its analog signal positive input terminal Vout(K) and the comparison reference voltage Vrt at its analog signal negative input terminal, obtaining error data Derr(K+1) and inputting it to the error data input terminal of the control operation logic. Based on the error data Derr(K+1), the control operation logic generates a new offset compensation code Daj1(K+1) and feeds it to the programmable current source array to obtain the output voltage Vout(K+1) after the (K+1)th compensation, thus completing the (K+1)th compensation of the offset voltage of the high-precision low offset signal amplifier circuit. After the Rth OSC clock cycle, the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the Jth voltage comparison between its analog signal positive input terminal Vout(J-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, obtaining the error data Derr(J) and inputting it to the error data input terminal of the control logic. Based on the error data Derr(J), the control logic generates a new offset compensation code Daj1(J) and inputs it to the programmable current source array to obtain the Jth compensated output voltage Vout(J), thus completing the amplification of the high-precision low-offset signal. After the Jth compensation of the offset voltage of the large circuit; at this time, the high-precision low-offset signal amplification circuit completes the fine calibration mode in the offset voltage adaptive calibration compensation mode, and the high-precision low-offset signal amplification circuit completes and ends the offset voltage adaptive calibration compensation mode; the high-precision low-offset signal amplification circuit begins to enter the normal operation mode; at this time, signal selection switches K1 and K2 are turned on simultaneously, while signal selection switches K3~K6 are all turned off, and the high-precision low-offset signal amplification circuit performs high-precision amplification on the differential negative input port VIN and differential positive input port VIP signals. Figure 1 In the described embodiment, when the high-precision low-offset signal amplifier circuit enters the offset voltage adaptive calibration compensation mode, it first starts a coarse calibration mode, followed by a fine calibration mode. In the coarse calibration mode, the two-stage folded common-source cascode operational amplifier circuit is connected as a unity-gain buffer circuit. At this time, the offset voltage of the high-precision low-offset signal amplifier circuit has not been calibrated and has a relatively large offset voltage. By selecting a comparison reference voltage Vrt equal to the calibration positive reference voltage Vrp, the magnitude of the offset voltage Vout at the output port of the high-precision low-offset signal amplifier circuit can be determined. After the coarse calibration mode is completed, the offset voltage of the high-precision low-offset signal amplifier circuit, after coarse calibration, may have an offset voltage below 1mV between Vout and the comparison reference voltage Vrt. The high-precision voltage comparator CP will then find it difficult to further accurately distinguish offset voltages below 1mV in the high-precision low-offset signal amplifier circuit. To address the comparator accuracy limitation, this invention connects the two-stage folded cascode op-amp circuit into an open-loop amplification configuration. In this configuration, offset voltages below 1mV in the high-precision, low-offset signal amplification circuit are amplified and reflected in the output port Vout, resulting in an output voltage error greater than 100mV. This amplified offset error is more easily detected by the high-precision voltage comparator CP, allowing for more precise input offset voltage calibration. After the high-precision, low-offset signal amplification circuit enters fine calibration mode, the differential inputs of the two-stage folded cascode op-amp circuit are connected to the positive calibration reference voltage Vrp and the negative calibration reference voltage Vrn, respectively. Simultaneously, the bias point of the output port Vout changes, requiring corresponding adjustments to the comparison reference voltage Vrt. In practice, the comparison reference voltage Vrt is a pre-designed ideal voltage, typically located at the center of the offset of the output port Vout bias point. This invention employs a calibration method combining coarse and fine calibration modes, reducing the accuracy requirements of the high-precision voltage comparator CP and lowering the overall circuit area overhead. In addition, the present invention can perform offset calibration of the high-precision low-offset signal amplifier circuit at any time through the SET signal, thereby improving the accuracy of the high-precision low-offset signal amplifier circuit under different working environments. Figure 3 This is a schematic diagram of offset compensation in the coarse calibration mode of the present invention. The comparator control clock CKcp shown in the diagram is a 20kHz signal. The offset voltage present on the output Vout voltage of the high-precision low-offset signal amplifier circuit is 54mV. The coarse calibration mode requires six offset compensation operations. To improve the quantization accuracy of the comparator output Derr, in this embodiment of the invention, any error data Derr is ultimately calculated by multiple comparisons by the comparator and then summed and averaged. Therefore, the clock periods of the calibration control clock CKctrl and the comparator control clock CKcp used in the internal control logic have the following operational relationship: T CKctrl =L*T CKcp L is a positive integer greater than 1. Figure 3 In the given diagram, the calibration control clock CKctrl used internally by the control logic is a 4kHz signal with a value of L=5 and T. CKctrl =5*T CKcp . After the coarse calibration mode begins, the calibration control clock CKctrl and the comparator control clock CKcp will be turned on simultaneously. When the comparator control clock CKcp has passed 5 clock cycles, that is, at 0.2ms, the high-precision voltage comparator CP completes the first voltage comparison between the positive input terminal Vout(0) = 54mV of the analog signal and the reference voltage Vrt = 0 of the negative input terminal of the analog signal, and obtains the error data Derr(1) = 1 and inputs it to the control operation logic. The control operation logic generates the offset compensation code Daj1(1) = 100000 based on the error data Derr(1) and sends it to the programmable current source array, and generates the first error compensation code. The compensation amount Vcali = 40mV, and the output voltage Vout(1) = 14mV obtained after the first compensation; at 0.4ms, the high-precision voltage comparator CP completes the second voltage comparison between the positive input terminal Vout(1) = 14mV of the analog signal and the reference voltage Vrt = 0 of the negative input terminal of the analog signal, and obtains the error data Derr(2) = 1 and inputs it to the control operation logic; according to the error data Derr(2), the control operation logic generates the offset compensation code Daj1(2) = 110000 and sends it to the programmable current source array, and generates the second error compensation amount Vcali = 20mV, and the output voltage obtained after the second compensation. Vout(2) = -6mV; at 0.6ms, the high-precision voltage comparator CP completes the third voltage comparison between its analog signal positive input terminal Vout(2) = -6mV and the analog signal negative input terminal reference voltage Vrt = 0, obtaining error data Derr(3) = 0 and inputting it to the control operation logic; the control operation logic generates an offset compensation code Daj1(3) = 110000 based on the error data Derr(3) and sends it to the programmable current source array, and generates the third error compensation amount Vcali = -10mV. After the third compensation, the output voltage Vout(3) = 4mV is obtained; and so on, at 0.8ms The offset compensation code Daj1(4) = 110100 is generated, the fourth error compensation amount Vcali = 5mV, and the output voltage Vout(4) obtained after the fourth compensation is -1mV; at 1ms, the offset compensation code Daj1(5) = 110100 is generated, the fifth error compensation amount Vcali = -2.5mV, and the output voltage Vout(4) obtained after the fifth compensation is 1.5mV; at 1.2ms, the offset compensation code Daj1(6) = 110101 is generated, the sixth error compensation amount Vcali = 1.25mV, and the output voltage Vout(6) obtained after the sixth compensation is 0.25mV. In the calibration compensation process of the above embodiment of the present invention, the error compensation amount Vcali used for each compensation is different, and it is usually set that the error compensation amount of the later one is half of the error compensation amount of the previous one. The fine calibration mode described in the present invention adopts the same compensation and control method as the coarse calibration mode. Figure 4 This is a block diagram of the operational control logic circuit of the present invention. The operational control logic circuit includes: a reset counter, a calibration start control signal generation circuit, a switch selection signal generation circuit, a pulse data filtering circuit, a serial-to-parallel register conversion circuit, an error quantization circuit, a clock frequency divider circuit, a comparison clock generation circuit, an N-bit counter circuit, an N-bit shift register, and latch registers 1 to N, where N is a positive integer not less than J; The reset signal SET first enters the reset counter, is filtered, and then enters the reset signal port of the calibration start control signal generation circuit. The start signal EN is connected to the start signal port of the calibration start control signal generation circuit. The calibration start control signal generation circuit generates a calibration mode control signal Cali based on the reset signal SET and the start signal EN. The calibration mode control signal Cali will be simultaneously output to the calibration mode ports of the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the error quantization circuit, the clock divider circuit, the comparison clock generation circuit, the N-bit counter circuit, the N-bit shift register, and latch registers 1 to N. The circuit generates a calibration control clock CKctrl and a comparator clock source based on the input clock OSC; the calibration control clock CKctrl is output to the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the N-bit counter circuit, and the N-bit shift register; the comparator clock source enters the comparator clock generation circuit to generate the comparator control clock CKcp required by the high-precision comparator CP; the switch selection signal generation circuit generates control signals for the signal selection switches K1-K6 of the high-precision low-offset signal amplifier circuit in different operating modes based on the periodic cyclic reset signal Count output by the N-bit counter circuit and the calibration mode control signal Cali. Error data Derr is input to the pulse data filtering circuit, and after pulse filtering, error-weighted data Dev, arranged in a serial sequence, is obtained and input to the serial-to-parallel register conversion circuit. Under the control of the calibration control clock CKctrl, the serial-to-parallel register conversion circuit converts the error-weighted data Dev, arranged in a serial sequence, into N-bit parallel error-weighted data Devp. After being processed by the error quantization circuit, parallel calibration adjustment code Dajp is obtained. The parallel calibration adjustment code Dajp is simultaneously connected to the adjustment code input port of latch register 1 to latch register N. Under the control of the calibration control clock CKctrl and the calibration mode control signal Cali, the N-bit counter circuit generates the periodic cyclic reset signal Count required by the N-bit shift register. The cycle period of the reset signal is set by the N-bit counter circuit. The N-bit shift register generates a selection signal Sel according to the periodic reset signal provided by the N-bit counter circuit and connects to the selection signal input port of latch register 1 to latch register N respectively. At any time, one latch of latch register 1 to latch register N is selected to be valid. Figure 4 The operational control logic circuit of this invention controls the overall operating mode and offset error calibration process of the high-precision low-offset signal amplifier circuit. The number of calibrations in the coarse and fine calibration modes is determined by the periodic cyclic reset signal Count generated by the N-bit counter circuit, and can be flexibly set according to the application scenario. The reason for using the pulse data filtering circuit to filter the error data Derr is to improve the accuracy of the comparator output and reduce the influence of the comparator's own offset voltage. When the offset voltage of the high-precision low-offset signal amplifier circuit is below 1mV, the comparator's offset voltage has a certain bias error in the error data Derr. By weighting the results of multiple Derr calculations, interference from narrow pulse error signals can be filtered out, improving the accuracy of the comparator output and obtaining the weighted error data Dev. During the calibration process, the calculation method for the N-bit parallel error weighted data Devp by the error quantization circuit can be implemented using existing error lookup and calculation methods. After the error quantization circuit calculates the parallel calibration adjustment code Dajp, the selection signal Sel will sequentially select the selection signal input ports of latch registers 1 to N, causing latch registers 1 to N to output the offset compensation codes Daj(1) to Daj(N) sequentially. These are used to generate the error compensation amount Vcali value required for offset compensation in coarse and fine calibration modes, respectively. Obviously, the larger the value of N, the higher the offset compensation accuracy, but the calibration time and hardware overhead are relatively greater. Figure 5In the programmable current source array circuit of the present invention described herein, the positive compensation current Iajp and negative compensation current Iajn output by the programmable current source array are controlled by a J-bit adjustment code Daj. The programmable current source array circuit includes J groups of positive-terminal common-source cascode current sources and J groups of negative-terminal common-source cascode current sources, as well as J inverters. The externally controlled J-bit adjustment code Daj is daj1~dajJ. By adjusting the gates of the J switching-selection NMOS transistors M513p~M5J3p in the J groups of positive-terminal common-source cascode current sources, the positive compensation current Iajp of the programmable current source array can be adjusted. The externally controlled J-bit adjustment code Daj, after passing through the J inverters, yields adjustment codes daj1B~dajJB, which are opposite to daj1~dajJ. By adjusting the gates of the J switching-selection NMOS transistors M513n~M5J3n in the J groups of negative-terminal common-source cascode current sources, the negative compensation current Iajn of the programmable current source array can be adjusted. In practical implementation, when the high-precision low-offset signal amplification circuit is in standby mode, the control logic generates a set of uncalibrated initial offset compensation codes Daj0 for the programmable current source array. At this time, the negative compensation current Iajn and the positive compensation current Iajp of the programmable current source array are equal and at the center value of the current adjustment range. If the total current range of the compensation currents Iajn and Iajp is 0~1mA, then Iajn=Iajp=0.5mA can be set when the high-precision low-offset signal amplification circuit is in standby mode. Since the adjustment codes daj1~dajJ are opposite to the adjustment codes daj1B~dajJB, the adjustment directions of the compensation currents Iajn and Iajp are opposite during the offset compensation process. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-precision, low-offset signal amplification circuit for automotive electronic systems, characterized in that, Includes resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113, reference voltage and bias generation circuit, programmable current source array, control logic, high-precision voltage comparator CP, startup circuit and oscillator circuit OSC, and 6 signal selection switches K1~K6; Specifically, the sources of PMOS transistors M100, M102, M104, M106, and M114 are all connected to the power supply voltage VCC; the sources of NMOS transistors M110, M112, and M113 are all connected to ground potential GND; the drain of PMOS transistor M100 is connected to the source of PMOS transistor M101; the gate of PMOS transistor M100 is connected to the bias voltage Vbp1; the gate of PMOS transistor M101 is connected to the bias voltage Vbp2; the gate of PMOS transistor M114 is connected to the bias voltage Vbp3; the gates of NMOS transistors M110 and M112 are connected to the bias voltage Vbn1; and the drain of PMOS transistor M101 is connected to PMOS transistors M107 and M108. The source of 8; the drain of PMOS transistor M102 and the source of PMOS transistor M103 are connected; the gate of PMOS transistor M102 is connected to the drain of PMOS transistor M103, the drain of PMOS transistor M106, the upper end of resistor R13 and the gate of PMOS transistor M104; the gate of PMOS transistor M103 is connected to the lower end of resistor R13 and the gate of PMOS transistor M105, and is also connected to the drain of NMOS transistor M109; the source of PMOS transistor M105 is connected to the drain of PMOS transistor M104; the drain Vtd of PMOS transistor M105 is connected to the drain of NMOS transistor M111, and the Vtd voltage is also connected to the gate of NMOS transistor M113; the drain of NMOS transistor M113 is connected to the drain of PMOS transistor M114 and the upper end of signal selection switch K5, and also serves as the output port Vout of the high-precision low-offset signal amplifier circuit of this invention; The gate AN of PMOS transistor M108 is simultaneously connected to the upper end of signal selection switch K4, the left end of signal selection switch K6, and the right end of signal selection switch K2. The left end of signal selection switch K2 is the differential negative input port VIN of the high-precision low-offset signal amplifier circuit of this invention. The gate AP of PMOS transistor M107 is simultaneously connected to the upper end of signal selection switch K3 and the right end of signal selection switch K1. The left end of signal selection switch K1 is the differential positive input port VIP of the high-precision low-offset signal amplifier circuit of this invention. The drain Aip of PMOS transistor M107 is connected to the positive compensation current Iajp port of the programmable current source array, the source of NMOS transistor M109, and the drain of NMOS transistor M110. The drain Ain of PMOS transistor M108 is connected to the negative compensation current Iajn port of the programmable current source array, the source of NMOS transistor M111, and the drain of NMOS transistor M112. The lower end of signal selection switch K5 is connected to the right end of signal selection switch K6 and the positive analog signal input of high-precision voltage comparator CP. The negative analog signal input of high-precision voltage comparator CP is connected to the comparison reference voltage Vrt. The output of high-precision voltage comparator CP inputs the error data Derr to the error data input of the control operation logic. The control operation logic generates comparator control clock CKcp and offset compensation code Daj based on the input clock OSC, reset signal SET, start signal EN and error data Derr, and respectively feeds them to high-precision voltage comparator CP and programmable current source array. After the chip is powered on, the startup circuit generates a startup signal EN and provides it to the reference voltage and bias generation circuit, the oscillator circuit OSC, and the gate of the PMOS transistor M116. After the startup signal EN is valid, the oscillator circuit OSC outputs the input clock OSC to the clock signal input terminal of the control logic. After the startup signal EN is valid, the reference voltage and bias generation circuit generates bias voltages Vbp3, Vbp2, Vbp1, Vbn1, comparison reference voltage Vrt, calibration positive reference voltage Vrp, calibration negative reference voltage Vrn, reference bias voltage Vrp1, and reference bias voltage Vrp2. Under the control of the offset compensation code Daj, the programmable current source array generates positive compensation current Iajp and negative compensation current Iajn based on the reference bias voltages Vrp1 and Vrp2. The calibration positive reference voltage Vrp and calibration negative reference voltage Vrn are respectively connected to the lower end of the signal selection switch K3. The resistor R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, M114, NMOS transistors M109, M110, M111, M112, and M113 constitute a two-stage folded cascode operational amplifier circuit. When the start signal EN is 1, the two-stage folded cascode operational amplifier circuit operates normally. The gates of PMOS transistors M107 and M108, i.e., AP and AN, are the differential input terminals of the two-stage folded cascode operational amplifier circuit. The output port Vout of the high-precision low-offset signal amplifier circuit is the output terminal of the two-stage folded cascode operational amplifier circuit.

2. The high-precision, low-offset signal amplification circuit for automotive electronic systems according to claim 1, characterized in that, It includes three modes: standby mode, offset voltage adaptive calibration compensation mode, and normal operation mode; When the power supply voltage is applied, the power-on start signal EN changes from low to high and becomes effective. The reference voltage and bias generation circuit, the oscillator circuit OSC, and the two-stage folded common-source common-gate operational amplifier circuit begin to work normally. The control operation logic generates a set of uncalibrated initial offset compensation code Daj0 for the programmable current source array. The high-precision low offset signal amplification circuit is in standby mode at this time. When the reset signal SET has a high-level pulse for more than M OSC cycles, the high-precision low offset signal amplifier circuit starts to enter the offset voltage adaptive calibration compensation mode, and the calibration mode control signal Cali generated inside the control operation logic will be set to high level, where M is an integer greater than 1. After the Cali high level passes through R cycles, the offset voltage adaptive calibration compensation mode is completed. The control operation logic will undergo J calibration compensations to obtain a set of calibrated offset compensation code Daj1(J), which remains unchanged. At the same time, the offset compensation code Daj1(J) is given to the programmable current source array to generate positive compensation current Iajp(J) and negative compensation current Iajn(J), which are injected into Aip and Ain respectively, thereby adjusting the magnitude of the Vout signal and completing the offset voltage compensation of the high-precision low offset signal amplification circuit; J is a positive integer greater than 2. After the offset voltage adaptive calibration compensation mode is completed, the high-precision low offset signal amplification circuit enters the normal operation mode. At this time, signal selection switches K1 and K2 are turned on at the same time, and signal selection switches K3~K6 are kept off. The high-precision low offset signal amplification circuit amplifies the differential negative input port VIN and differential positive input port VIP signals with high precision.

3. The high-precision, low-offset signal amplification circuit for automotive electronic systems according to claim 2, characterized in that, After entering the offset voltage adaptive calibration compensation mode, the signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit is turned on, that is, AP is connected to the calibration positive reference voltage Vrp; the signal selection switches K5 and K6 connected to the output port Vout of the high-precision low offset signal amplifier circuit are turned on simultaneously, and the two-stage folded cascode op-amp circuit is connected as a unity-gain buffer circuit; at this time, the high-precision low offset signal amplifier circuit begins to enter the coarse calibration mode in the offset voltage adaptive calibration compensation mode. The control logic will output the comparator control clock CKcp, so that the high-precision voltage comparator CP performs the first comparison between the positive input terminal Vout of its analog signal and the comparison reference voltage Vrt of the negative input terminal of the analog signal. After the comparator control clock CKcp makes the high-precision voltage comparator CP complete a voltage comparison, the error data Derr (1) at the output terminal of the high-precision voltage comparator CP will be input to the error data input terminal of the control logic. The control logic generates a new offset compensation code Daj1 (1) according to the error data Derr (1) and gives it to the programmable current source array. Under the control of Daj1 (1), the programmable current source array generates a positive compensation current Iajp (1) and a negative compensation current Iajn (1) and injects them into the drain Aip of PMOS transistor M107 and the drain Ain of PMOS transistor M108, respectively, thereby adjusting the magnitude of the Vout signal and obtaining the output voltage Vout (1) after the first compensation, thus completing the first compensation of the offset voltage of the high-precision low offset signal amplifier circuit. When the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the Kth voltage comparison between its analog signal positive input terminal Vout(K-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, the error data Derr(K) is obtained and input to the error data input terminal of the control operation logic. Based on the error data Derr(K), the control operation logic generates a new offset compensation code Daj1(K) and feeds it to the programmable current source array to generate a positive compensation current Iajp(K) and a negative compensation current Iajn(K), obtaining the output voltage Vout(K) after the Kth compensation. After completing the Kth compensation of the offset voltage of the high-precision low-offset signal amplifier circuit, the high-precision low-offset signal amplifier circuit completes the coarse calibration mode in the offset voltage adaptive calibration compensation mode and begins to enter the fine calibration mode. K is a positive integer greater than 1 and less than J. The signal selection switch K3 connected to the differential input terminal AP of the two-stage folded cascode op-amp circuit remains on, and the signal selection switch K4 connected to the differential input terminal AN also remains on. That is, AP is connected to the positive calibration reference voltage Vrp, and AN is connected to the negative calibration reference voltage Vrn. The signal selection switch K5 connected to the output port Vout of the high-precision low-offset signal amplifier circuit remains on, while the signal selection switch K6 begins to turn off. The two-stage folded cascode op-amp circuit is connected in an open-loop amplification configuration. The comparator control clock CKcp controls the high-precision voltage comparator. The CP device performs the (K+1)th voltage comparison between its analog signal positive input terminal Vout(K) and the comparison reference voltage Vrt at its analog signal negative input terminal, obtaining error data Derr(K+1) and inputting it to the error data input terminal of the control operation logic. Based on the error data Derr(K+1), the control operation logic generates a new offset compensation code Daj1(K+1) and feeds it to the programmable current source array to obtain the output voltage Vout(K+1) after the (K+1)th compensation, thus completing the (K+1)th compensation of the offset voltage of the high-precision low offset signal amplifier circuit. When the comparator control clock CKcp controls the high-precision voltage comparator CP to perform the J-th voltage comparison between its analog signal positive input terminal Vout(J-1) and the comparison reference voltage Vrt at its analog signal negative input terminal, the error data Derr(J) is obtained and input to the error data input terminal of the control operation logic. Based on the error data Derr(J), the control operation logic generates a new offset compensation code Daj1(J) and sends it to the programmable current source array to obtain the output voltage Vout(J) after the J-th compensation, thus completing the J-th compensation of the offset voltage of the high-precision low-offset signal amplifier circuit. At this time, the high-precision low-offset signal amplifier circuit completes the fine calibration mode in the offset voltage adaptive calibration compensation mode, and simultaneously completes and ends the offset voltage adaptive calibration compensation mode. The high-precision low-offset signal amplifier circuit begins to enter the normal operation mode. At this time, signal selection switches K1 and K2 are simultaneously turned on, while signal selection switches K3~K6 are all turned off. The high-precision low-offset signal amplifier circuit performs high-precision amplification on the differential negative input port VIN and the differential positive input port VIP signals.

4. The high-precision, low-offset signal amplification circuit for automotive electronic systems according to claim 3, characterized in that, In coarse calibration mode, any error data Derr is ultimately compared multiple times by the comparator and then summed and averaged to obtain the final output. The clock periods of the calibration control clock CKctrl and the comparator control clock CKcp used internally by the control logic have the following operational relationship: T CKctrl =L*T CKcp L is a positive integer greater than 1.

5. The high-precision, low-offset signal amplification circuit for automotive electronic systems according to claim 1, characterized in that, The operational control logic circuit includes: a reset counter, a calibration start control signal generation circuit, a switch selection signal generation circuit, a pulse data filtering circuit, a serial-to-parallel register conversion circuit, an error quantization circuit, a clock frequency divider circuit, a comparison clock generation circuit, an N-bit counter circuit, an N-bit shift register, and latch registers 1 to N, where N is a positive integer not less than J. The reset signal SET first enters the reset counter, is filtered, and then enters the reset signal port of the calibration start control signal generation circuit. The start signal EN is connected to the start signal port of the calibration start control signal generation circuit. The calibration start control signal generation circuit generates a calibration mode control signal Cali based on the reset signal SET and the start signal EN. The calibration mode control signal Cali will be simultaneously output to the calibration mode ports of the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the error quantization circuit, the clock divider circuit, the comparison clock generation circuit, the N-bit counter circuit, the N-bit shift register, and latch registers 1 to N. The circuit generates a calibration control clock CKctrl and a comparator clock source based on the input clock OSC; the calibration control clock CKctrl is output to the pulse data filtering circuit, the serial-to-parallel register conversion circuit, the N-bit counter circuit, and the N-bit shift register; the comparator clock source enters the comparator clock generation circuit to generate the comparator control clock CKcp required by the high-precision comparator CP; the switch selection signal generation circuit generates control signals for the signal selection switches K1-K6 of the high-precision low-offset signal amplifier circuit in different operating modes based on the periodic cyclic reset signal Count output by the N-bit counter circuit and the calibration mode control signal Cali. Error data Derr is input to the pulse data filtering circuit. After pulse filtering, error weighted data Dev is obtained in a serial sequence and input to the serial-to-parallel register conversion circuit. Under the control of the calibration control clock CKctrl, the serial-to-parallel register conversion circuit converts the error weighted data Dev in a serial sequence into N-bit parallel error weighted data Devp. After the error quantization circuit calculates the parallel calibration adjustment code Dajp. The parallel calibration adjustment code Dajp is simultaneously connected to the adjustment code input ports of latch registers 1 to N; Under the control of the calibration control clock CKctrl and the calibration mode control signal Cali, the N-bit counter circuit generates the periodic cyclic reset signal Count required by the N-bit shift register. The cycle period of the reset signal is set by the N-bit counter circuit. The N-bit shift register generates a selection signal Sel according to the periodic reset signal provided by the N-bit counter circuit and connects it to the selection signal input port of latch register 1 to latch register N respectively. At any time, one latch from latch register 1 to latch register N is selected to be valid.

6. The high-precision, low-offset signal amplification circuit for automotive electronic systems according to claim 1, characterized in that, The programmable current source array circuit includes J groups of positive-terminal common-source cascode current sources and J groups of negative-terminal common-source cascode current sources, as well as J inverters. The external control input J-bit adjustment code Daj is daj1~dajJ. By adjusting the gates of the J switching-selection NMOS transistors M513p~M5J3p in the J groups of positive-terminal common-source cascode current sources, the positive compensation current Iajp of the programmable current source array is adjusted. The external control input J-bit adjustment code Daj, after passing through the J inverters, yields adjustment codes daj1B~dajJB, which are opposite to daj1~dajJ. By adjusting the gates of the J switching-selection NMOS transistors M513n~M5J3n in the J groups of negative-terminal common-source cascode current sources, the negative compensation current Iajn of the programmable current source array is adjusted. When the high-precision low offset signal amplification circuit is in standby mode, the control operation logic generates a set of uncalibrated initial offset compensation codes Daj0 for the programmable current source array. At this time, the negative compensation current Iajn and the positive compensation current Iajp of the programmable current source array are equal and are at the center value within the current adjustment range. Since the adjustment codes daj1~dajJ are opposite to the adjustment codes daj1B~dajJB, the adjustment directions of the compensation currents Iajn and Iajp are opposite during the offset compensation process.

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