A negative pressure direct drive silicon carbide JFET hybrid packaged device

Abstract

The application discloses a negative pressure direct drive silicon carbide JFET combined sealing device and belongs to the technical field of power semiconductor integrated devices. The device is composed of a normally open SiC JFET chip, a negative pressure direct drive chip, a low-voltage normally off MOSFET chip and a multi-pin package. The negative pressure direct drive chip integrates a negative pressure generation circuit and an overcurrent, overvoltage, under-voltage locking and over-temperature protection circuit, and does not have a Miller clamp circuit inside. The device can generate adjustable negative pressure of-5V to-20V only by relying on external 5V power supply. The combined sealing structure forms a sub-nanohen level parasitic inductance gate loop. When the device is turned off, the negative pressure is applied to stabilize the gate potential below the threshold voltage, thereby inhibiting the Miller effect mis-conduction. When the device is turned on, a bias voltage of-1V to+3V is applied to reduce the conduction loss. The low-voltage MOSFET provides a redundant hard-off path in the power-on, power supply abnormality and fault state, so that the device presents a normally off characteristic to the outside.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor integrated device technology, specifically to a negative voltage direct-drive silicon carbide JFET encapsulated device. Background Technology

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, has a critical breakdown field strength approximately ten times that of silicon and a thermal conductivity approximately three times that of silicon. This allows for higher operating voltages, higher switching frequencies, and lower conduction losses, giving it significant advantages in power electronics. SiC junction field-effect transistors (JFETs), by eliminating the MOS channel, have an on-resistance-to-chip area product (RDS·A) that is closer to the material's theoretical unipolar limit. At the same voltage rating, their on-state characteristics are far superior to SiC MOSFETs and silicon superjunction MOSFETs, making them the preferred devices for high-voltage, high-frequency applications.

[0003] Currently, most commercially available high-voltage SiC JFETs are normally-on depletion-type devices. Under zero gate-source bias, the source and drain are in a conducting state. Only when a sufficiently large reverse bias (negative voltage) is applied to the gate can the conductive channel be depleted to achieve turn-off. Because the threshold voltage of SiC JFETs is relatively low, they are susceptible to electromagnetic interference, which can lead to false turn-on. A negative voltage needs to be applied during turn-off to ensure stability. However, the normally-on characteristic does not conform to the safe operating habits of traditional power supply systems. During the initial power-on stage and when the drive circuit fails, the device will naturally conduct, which can easily cause serious safety accidents such as shoot-through short circuits.

[0004] To address the safe turn-off issue of normally open SiC JFETs, the mainstream industry solution employs a Cascode architecture, which encapsulates the normally open SiC JFET in series with a low-voltage silicon MOSFET. The entire device's turn-on and turn-off are indirectly controlled by controlling the low-voltage Si MOSFET; during power-on or in case of a fault, the low-voltage Si MOSFET remains off, giving the device a normally off characteristic. However, this architecture has significant drawbacks and struggles to meet the demands of high-frequency, high-power-density applications.

[0005] First, frequency characteristics are limited. SiCJFETs inherently possess excellent switching speed and high-frequency characteristics, but cascaded low-voltage SiMOSFETs have slow switching speeds and large parasitic parameters (Miller capacitance Cgd, output capacitance Coss), becoming the performance bottleneck of the entire device and severely weakening the high-frequency advantages of SiCJFETs. At the same time, in high-voltage, high-frequency applications, SiC devices have extremely high dV / dt change rates (reaching tens or even hundreds of kilovolts per microsecond), forming a significant Miller effect through gate-drain parasitic capacitance Cgd coupling. Low-voltage SiMOSFETs are susceptible to Miller current, generating voltage spikes that exceed the threshold voltage, leading to false turn-on, causing bridge arm shoot-through, device damage, and system failure. How to suppress the Miller effect and ensure normally-off characteristics under high-speed switching is a technical problem that urgently needs to be solved in this field.

[0006] Second, the system integration is low. Discrete drive solutions require multiple power rails, external negative voltage modules, and protection circuits, occupying a large PCB area and making it difficult to meet high power density requirements. Summary of the Invention

[0007] The present invention aims to solve the above-mentioned technical problems by providing a negative voltage direct-drive silicon carbide JFET encapsulated device. By encapsulating multiple chips, it realizes negative voltage direct drive of normally open silicon carbide JFET chip A, retains its extreme high-frequency characteristics, solves the safety problem of normally open conduction, and incorporates multiple protection mechanisms to ensure reliable operation of the device in high voltage, high frequency, and high power density applications, simplifying system design and improving power density.

[0008] To solve the above-mentioned technical problems, the technical solution provided by the present invention is as follows:

[0009] A negative voltage direct drive silicon carbide JFET encapsulated device includes a normally open silicon carbide JFET chip A, a negative voltage direct drive chip B, a low voltage normally closed MOSFET chip C, and a package.

[0010] Both the silicon carbide JFET chip A and the MOSFET chip C have a drain, a source, and a gate.

[0011] The negative pressure direct drive chip B integrates a negative pressure generation circuit, a drive stage output, an overcurrent protection circuit, an overvoltage protection circuit, an undervoltage lockout protection circuit, and an overtemperature protection circuit.

[0012] The OUT_G output of the driver stage is directly connected to the gate of the silicon carbide JFET chip A, and is used to provide a drive signal to control the turn-on and turn-off of the silicon carbide JFET chip A.

[0013] The drain of the MOSFET chip C is electrically connected to the source of the silicon carbide JFET chip A. The source of the MOSFET chip C is connected to the SENCE of the negative voltage generation circuit. The gate of the MOSFET chip C is electrically connected to LV_G output by the driver stage.

[0014] The package adopts a QFN or TOLL multi-pin package form, and encapsulates the silicon carbide JFET chip A, the negative voltage direct drive chip B, and the MOSFET chip C together. The package is provided with multiple external pins, including main power drain pin and source pin, 5V power supply input pin and ground pin, logic signal input pin, and at least one protection function related pin.

[0015] Preferably, the negative pressure direct drive chip B receives the 5V power supply and generates an adjustable negative pressure of -5V to -20V by its internal negative pressure generation circuit;

[0016] When the silicon carbide JFET chip A needs to be turned off, the negative voltage direct drive chip B applies a negative bias voltage of -10V to -18V to the gate of the silicon carbide JFET chip A in the off state;

[0017] When the silicon carbide JFET chip A needs to be turned on, the negative voltage direct drive chip B applies a bias voltage of -1V to +3V to the gate, so that the conductive channel is fully opened.

[0018] Preferably, the MOSFET chip C is turned on by the negative voltage direct drive chip B under at least one of the following conditions: during system power-on, when the 5V power supply drops below the undervoltage lockout threshold, or when an internal fault is detected; during normal operation, the MOSFET chip C is turned off, and the silicon carbide JFET chip A is controlled by the output of the drive stage.

[0019] Preferably, the silicon carbide JFET chip A is formed using silicon carbide material and is a normally open junction field-effect transistor with a vertical channel or lateral channel structure.

[0020] Preferably, the overcurrent protection circuit determines whether an overcurrent condition has occurred by detecting the drain-source voltage of the silicon carbide JFET chip A in the on state, or by detecting the voltage across the shunt resistor connected in series in the source circuit of the silicon carbide JFET chip A; when an overcurrent is detected, the negative voltage direct drive chip B controls the silicon carbide JFET chip A to safely turn off at a safe current decrease rate.

[0021] Preferably, the over-temperature protection circuit includes a temperature sensing element integrated inside the negative pressure direct drive chip B. The temperature sensing element indirectly senses the temperature of the silicon carbide JFET chip A through a thermal coupling path inside the package. When the over-temperature protection circuit detects that the temperature exceeds a preset over-temperature threshold, the negative pressure direct drive chip B forcibly shuts down the silicon carbide JFET chip A.

[0022] Preferably, the temperature sensing element is a diode temperature sensor or a positive temperature coefficient thermistor.

[0023] Preferably, the undervoltage lockout protection circuit monitors the power supply voltage of the negative voltage direct drive chip B in real time. When the power supply voltage is lower than the preset undervoltage lockout threshold, the negative voltage direct drive chip B places the gate of the silicon carbide JFET chip A in a negative voltage state to keep the silicon carbide JFET chip A off, preventing drive failure due to insufficient power supply voltage.

[0024] Preferably, the drive stage output adopts a push-pull drive topology. During the conduction phase, the on-side switch is closed, connecting the gate to the voltage terminal, so that the gate-source junction of the silicon carbide JFET chip A is in a bias voltage state, the conductive channel is fully opened, and the on-resistance is reduced to the minimum. During the turn-off phase, the turn-off side switch is closed, the on-side switch is open, connecting the gate to the negative voltage terminal output by the negative voltage generation circuit, so that the conductive channel is exhausted and the device is reliably turned off.

[0025] Preferably, the silicon carbide JFET chip A is a depletion-mode vertical channel JFET with a rated voltage of 650V, 750V, 1200V or 1700V.

[0026] With the above structure, the present invention has the following advantages:

[0027] 1. Fully leverage the high-frequency advantages of silicon carbide JFET chip A: The gate of silicon carbide JFET chip A is directly driven by negative voltage direct drive chip B, avoiding the limitation of switching speed by low-voltage MOSFET chip C in Cascode architecture. Silicon carbide JFET chip A can take advantage of its intrinsic high switching speed to achieve higher switching frequency and lower switching loss, eliminating the energy waste caused by driving low-voltage MOSFET chip C, and adapting to ultra-high frequency and high power density application scenarios.

[0028] 2. Effectively suppresses Miller effect-induced turn-on: In the off state, a deep negative voltage of -5V to -20V is applied to the gate, keeping the gate static potential far below the threshold voltage, which greatly improves the anti-interference margin; even under high dV / dt conditions, after the noise spikes of Miller capacitance coupling are superimposed, the net voltage is still difficult to reach the turn-on threshold, fundamentally reducing the risk of false turn-on.

[0029] 3. Optimize switching waveform and system efficiency: Negative voltage drive can accelerate gate charge extraction, shorten turn-off delay time and Miller plateau duration, and reduce turn-off losses; direct drive mode can precisely adjust gate drive strength and switching speed (dv / dt and di / dt), achieving the best balance between switching speed, switching losses and EMI characteristics, and improving overall system efficiency.

[0030] 4. Integrated multiple protections enhance reliability: The negative pressure direct drive chip B has built-in overcurrent, overvoltage, undervoltage lockout, and overtemperature protection functions. It can achieve self-protection in case of abnormal operation. Compared with external protection circuits, it has a faster response speed, stronger anti-interference ability, and occupies less PCB area, reducing the risk of system damage due to power device failure.

[0031] 5. Improved power density and simplified system design: Multi-chip co-packaging significantly reduces parasitic inductance in the drive and gate circuits, ensuring the integrity of high-frequency drive signals; it reduces the number of discrete components, lowers the complexity of circuit board layout and wiring, and a single 5V power supply can meet the requirements, eliminating the need for complex external isolation negative voltage power supplies, making it easier to realize high power density power modules.

[0032] 6. Solving the safety problem of normally open conduction: The internally integrated low-voltage auxiliary shutdown MOSFET chip C ensures that the silicon carbide JFET chip A is in the off state during the initial power-on stage and when the drive power supply is abnormal, so that the packaged device presents normally closed characteristics to the outside world, which meets the safety standards and usage habits of industrial applications.

[0033] 7. High application flexibility: The multi-pin package provides external interfaces such as fault indication, temperature monitoring, and soft shutdown time setting, which facilitates system-level health management and parameter adaptation to meet the needs of different application scenarios. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the principle of the present invention;

[0035] Figure 2 This is a block diagram of the internal functional modules of the negative pressure direct drive chip B of the present invention;

[0036] Figure 3 This is a schematic diagram of the QFN9*9 package outline of the present invention;

[0037] Figure 4 This is a schematic diagram of the internal packaging structure of an embodiment of the present invention;

[0038] Figure 5 It is a typical half-bridge application circuit. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the full text.

[0040] Combined with appendixFigures 1-5 As shown, a negative voltage direct-drive silicon carbide JFET packaged device includes:

[0041] Normally open silicon carbide JFET chip A has a drain, a source, and a gate;

[0042] Negative voltage direct drive chip B is used to provide drive signals to control the turn-on and turn-off of normally open silicon carbide JFET chip A. The drive output terminal OUT_G of negative voltage direct drive chip B is electrically connected to the gate of silicon carbide JFET chip A.

[0043] A low-voltage normally-off MOSFET chip is connected between the source of a silicon carbide JFET chip and an output node of a negative voltage generation circuit, and its gate is controlled by a negative voltage direct drive chip B.

[0044] The package is a QFN, TOLL or other multi-pin package, which encapsulates three chips: a silicon carbide JFET chip, a negative voltage direct drive chip B, and a low voltage normally off MOSFET chip.

[0045] The package has multiple external pins, including at least: a main power drain pin and a source pin, a 5V power supply input pin and a ground pin, a logic signal input pin, and at least one protection function related pin;

[0046] The negative pressure direct drive chip B receives a 5V power supply and generates an adjustable negative pressure from -5V to -20V through its internal negative pressure generation circuit.

[0047] When the silicon carbide JFET chip needs to be turned off, the negative voltage direct drive chip B applies a negative voltage to the gate through the drive output terminal, and utilizes the sub-Anahen low parasitic inductance gate circuit formed by the encapsulation structure, so that under the maximum rated dv / dt condition of the system, the voltage drop caused by the Miller capacitance coupling current in this circuit is far from sufficient to raise the gate potential from the negative voltage to the threshold voltage of the silicon carbide JFET, thereby achieving disturbance rejection turn-off without using Miller clamp;

[0048] When conduction is required, the negative voltage direct drive chip B applies a zero bias voltage or a small positive bias voltage of -1V to +3V to the gate, so that the conductive channel is fully opened.

[0049] When the low-voltage normally off MOSFET chip is powered on, when the 5V supply voltage drops below the undervoltage lockout threshold, or when the negative voltage direct drive chip B detects a serious internal fault, the negative voltage direct drive chip B controls its conduction, forcibly connecting the gate of the silicon carbide JFET chip to the negative voltage node, providing a redundant hard turn-off path; during normal operation, the low-voltage MOSFET is turned off, and the switching of the silicon carbide JFET chip is completely controlled by the drive output stage of the negative voltage direct drive chip B.

[0050] In specific implementation of this invention, such asFigure 1 and Figure 2 As shown, the negative pressure direct drive chip B integrates a negative pressure generation circuit and various protection circuits; the protection circuits include, but are not limited to, overcurrent protection circuit, overvoltage protection circuit, undervoltage lockout protection circuit and overtemperature protection circuit.

[0051] Specifically, when the negative voltage direct drive chip B is in the off state, the negative bias voltage applied to the gate of the silicon carbide JFET chip A is between -10V and -18V to meet the pinch-off voltage requirements of the SiC JFET.

[0052] Specifically, when the negative voltage direct drive chip B is in the on state, it applies a bias voltage of -1V to +3V (i.e., zero bias or a small positive bias) to the gate of the silicon carbide JFET chip A to reduce the on-resistance. Compared to zero bias drive, applying a small positive bias can further reduce the on-resistance by about 16% or more.

[0053] In specific implementation of this invention, such as Figure 1 and Figure 2 As shown, the encapsulated device includes a low-voltage normally-off MOSFET, whose drain is connected to the source of the silicon carbide JFET chip A, and whose gate is connected to an output of the negative voltage direct drive chip B. This low-voltage MOSFET acts as a safety shutdown auxiliary device, remaining off during the initial power-on phase of the system and before the power supply to the negative voltage direct drive chip B is established. By pulling down or blocking the gate-source circuit of the SiC JFET, it ensures that the SiC JFET is in a safe shutdown state. After the power supply to the negative voltage direct drive chip B is established, the low-voltage MOSFET is simultaneously controlled by the negative voltage direct drive chip B, keeping it in a normally-on state. Thereafter, the switching of the SiC JFET is directly controlled by the negative voltage drive signal output by the negative voltage direct drive chip B.

[0054] Specifically, the silicon carbide JFET chip A is formed using silicon carbide material and is a normally open junction field-effect transistor with a vertical channel or lateral channel structure. Its voltage rating includes, but is not limited to, 650V, 750V, 1200V and 1700V.

[0055] In specific implementation of this invention, such as Figure 4 As shown, the package has multiple external pins, including at least: main power drain pin and source pin, 5V power supply input pin and ground pin, logic signal input pin, and at least one protection function related pin; the negative voltage direct drive chip B, silicon carbide JFET chip A and Si LV-MOS are internally electrically interconnected by wire bonding, copper clips, aluminum strips or conductive pillars.

[0056] Specifically, the overcurrent protection circuit detects overcurrent conditions by monitoring the drain-source on-state voltage drop of the silicon carbide JFET chip A (i.e., desaturation detection) or by sampling the voltage across the shunt resistor connected in series in the power circuit (i.e., resistance sampling). When the detected current exceeds the preset overcurrent threshold, the negative voltage direct drive chip B actively controls the silicon carbide JFET chip A to enter a soft turn-off process, turning off the silicon carbide JFET chip A at a safe current decrease rate to avoid high di / dt and voltage overshoot caused by excessively fast turn-off.

[0057] In specific implementation of this invention, such as Figure 1 and Figure 2 As shown, the over-temperature protection circuit uses a temperature sensor (such as a diode temperature sensor or a positive temperature coefficient thermistor) integrated near the device to be protected to detect the real-time temperature close to the junction temperature of the silicon carbide JFET chip A. When the temperature exceeds the preset over-temperature threshold, the negative voltage direct drive chip B performs automatic shutdown control to prevent the device from failing due to overheating.

[0058] Specifically, the undervoltage lockout protection circuit monitors the power supply voltage of the negative voltage direct drive chip B in real time. When the power supply voltage is lower than the preset undervoltage lockout threshold, it will turn off the silicon carbide JFET chip A and keep it in a safe off state to prevent insufficient driving capability and runaway state caused by insufficient power supply voltage.

[0059] Example 1:

[0060] A 1200V SiC JFET co-packaged device with QFN packaging and no Miller clamp.

[0061] This embodiment provides an integrated device suitable for an 800V bus, 300kHz high-frequency phase-shifting full-bridge converter.

[0062] (a) The chip composition includes the following chips:

[0063] Chip A: Normally open SiC JFET chip.

[0064] The normally open 1000V (or 1200V) SiC JFET chip with a vertical channel structure has an on-resistance of approximately 25mΩ. The drain, source, and gate of this chip are led out to the corresponding pads on the package substrate through internal bonding wires. The drain and source serve as the electrodes of the main power circuit, and the gate is connected to the drive output terminal of the internal negative voltage direct drive chip.

[0065] Chip B: Negative pressure direct drive chip.

[0066] The negative pressure direct drive chip integrates the following functional modules:

[0067] (1) Negative voltage generation circuit module: This module receives an external power supply voltage (e.g., +5V to +20V) and generates an adjustable and stable negative voltage of -5V to -20V through an internally integrated negative voltage charge pump or switched capacitor circuit, which serves as the gate drive voltage source when the SiC JFET is turned off. The negative voltage amplitude can be set through an external resistor divider network or a digital interface (such as SPI) to adapt to the different pinch-off voltage requirements of different SiC JFET chip models.

[0068] (2) Output driver stage module: A push-pull driver topology is adopted. During the conduction phase, the conduction-side switch is closed, and the gate is connected to the 0V or +2V voltage terminal, so that the gate-source junction of the SiC JFET chip is in a zero-bias or slightly forward bias state, the conductive channel is fully opened, and the on-resistance is reduced to the minimum; during the turn-off phase, the turn-off-side switch is closed, the conduction-side switch is open, and the gate is connected to the negative voltage terminal (such as -15V) output by the negative voltage generation circuit, so that the conductive channel is exhausted and the device is reliably turned off.

[0069] In a preferred design, the off-side switch is implemented by an NMOS transistor with extremely low on-resistance, the on-side switch is implemented by a PMOS transistor, and an optional gate drive resistor Rg can be connected in series between the push-pull output stage and the gate to adjust the switching speed.

[0070] (3) Overcurrent Protection Circuit Module: This embodiment adopts the desaturation (DESAT) detection method. During the turn-on period of the SiC JFET chip, the overcurrent protection circuit detects the drain-source voltage Vds of the SiC JFET chip through a high-voltage diode and a current source. When Vds exceeds the preset desaturation threshold (which corresponds to the preset overcurrent value), the logic control module will trigger the overcurrent protection action, and the driver stage will enter the soft turn-off sequence to safely turn off the SiC JFET at a controlled current drop rate, preventing device damage caused by the superposition of overcurrent and inductive load voltage spikes.

[0071] (4) Over-temperature protection circuit module: A temperature sensing element (forward bias diode) is integrated inside the negative voltage direct drive chip. Since the negative voltage direct drive chip and the SiC JFET chip are tightly packaged in the same package, there is good thermal coupling between the two. The temperature sensing element indirectly reflects the junction temperature change of the SiC JFET chip through the heat conduction path inside the package. When the over-temperature protection circuit detects that the temperature exceeds the preset over-temperature threshold (e.g., 150°C), the negative voltage direct drive chip forcibly turns off the SiC JFET until the temperature drops below the hysteresis reduction recovery threshold, after which it is allowed to turn on again.

[0072] (5) Undervoltage Lockout Protection Circuit Module (UVLO): Real-time monitoring of the supply voltage VCC and negative voltage VEE of the negative voltage direct drive chip. During power-up, before VCC reaches the preset undervoltage lockout release threshold (e.g., VCC>4.5V), the UVLO circuit will force the drive output to remain in the negative voltage off state (or work with the auxiliary turn-off MOSFET to keep it off) to prevent the SiC JFET from being mis-turned due to insufficient drive capability. When VCC drops below the undervoltage lockout threshold due to a power supply failure, the UVLO circuit will immediately trigger the shutdown protection to ensure system safety.

[0073] (6) Overvoltage protection circuit module: During the turn-off period of the SiC JFET chip, the drain-source voltage is monitored. When Vds is detected to exceed a preset percentage of the rated breakdown voltage (e.g., 80%), the overvoltage protection circuit triggers an active clamping action, which limits Vds from rising further by slightly turning on the gate, or generates a fault signal to be transmitted to the logic control module.

[0074] Chip C: Low-voltage normally off auxiliary turn-off MOSFET.

[0075] A low-voltage (≤30V) normally-off N-channel MOSFET (a P-channel MOSFET can also be used to simplify the drive power supply) is placed inside the encapsulated device. The source of this low-voltage MOSFET is connected to the source of the SiC JFET chip, and its drain is connected to the gate of the SiC JFET chip through a resistor. At the initial moment of system power-on or before the power supply of the negative voltage direct drive chip is established, the low-voltage MOSFET remains in the off state. At this time, the gate-source circuit of the SiC JFET chip is blocked or clamped, ensuring that the SiC JFET is in the off state. After the power supply voltage of the negative voltage direct drive chip is established and the undervoltage lockout is released, the negative voltage direct drive chip switches the low-voltage MOSFET to the on state. Thereafter, the switching of the SiC JFET chip is controlled by the direct negative voltage pulse width modulation of the negative voltage direct drive chip, realizing high-frequency, low-loss switching operation.

[0076] (II) Package and Pin Definitions:

[0077] Uses a 9mm×9mm QFN package (e.g.) Figure 3 and Figure 4 The large heat dissipation pad on the bottom is connected to the source. The pin list is as follows:

[0078]

[0079] The internal gate drive circuit uses aluminum wire with a diameter of 0.2mm for bonding, and the length is controlled within 1mm. The measured parasitic inductance is less than 0.7nH.

[0080] (III) The normal working procedure is as follows:

[0081] Initial power-on phase: When the system powers on, the external auxiliary power supply provides the supply voltage VCC to the negative voltage direct drive chip. At this time, VCC has not yet reached the undervoltage lockout release threshold. The UVLO circuit of the negative voltage direct drive chip keeps all outputs in a safe state, the low-voltage auxiliary turn-off MOSFET remains off, the SiC JFET gate has no forward drive, the device is in the off state, and exhibits normally off characteristics.

[0082] Normal conduction control: When VCC rises above the undervoltage lockout release threshold, the low-voltage auxiliary shutdown MOSFET is turned on by the negative voltage direct drive chip. Subsequently, when the external control signal (PWM input) is high, the output drive stage of the negative voltage direct drive chip connects the gate of the SiC JFET to the 0V or +2V reference terminal, establishing a conductive channel between the source and drain of the SiC JFET, allowing the main power current to flow normally through the SiC JFET.

[0083] Normal shutdown control: When the PWM input signal flips to a low level, the output drive stage of the negative voltage direct drive chip quickly switches, connecting the SiC JFET gate to the -15V negative voltage terminal. The gate-source PN junction is reverse biased, the free carriers in the channel region are depleted, the conductive channel is pinched off, and the SiC JFET is reliably turned off.

[0084] Fault Protection: During device operation, overcurrent protection, overvoltage protection, overtemperature protection, and undervoltage lockout protection circuits continuously monitor the device's operating status in real time. Once any protection condition is triggered, the logic control module will immediately or according to a preset timing sequence shut down the SiC JFET (initiating a soft shutdown sequence if necessary) and output the fault status to the external controller via the feedback pin to ensure system safety.

[0085] The present invention and its embodiments have been described above. This description is not restrictive, and the embodiments shown throughout are only one of the embodiments of the present invention. The actual structure is not limited to this. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A negative voltage direct-drive silicon carbide JFET encapsulated device, characterized in that, It includes a normally open silicon carbide JFET chip A, a negative voltage direct drive chip B, a low voltage normally closed MOSFET chip C, and a package. Both the silicon carbide JFET chip A and the MOSFET chip C have a drain, a source, and a gate. The negative pressure direct drive chip B integrates a negative pressure generation circuit, a drive stage output, an overcurrent protection circuit, an overvoltage protection circuit, an undervoltage lockout protection circuit, and an overtemperature protection circuit. The OUT_G output of the driver stage is directly connected to the gate of the silicon carbide JFET chip A, and is used to provide a drive signal to control the turn-on and turn-off of the silicon carbide JFET chip A. The drain of the MOSFET chip C is electrically connected to the source of the silicon carbide JFET chip A. The source of the MOSFET chip C is connected to the SENCE of the negative voltage generation circuit. The gate of the MOSFET chip C is electrically connected to LV_G output by the driver stage. The package adopts a QFN or TOLL multi-pin package form, and encapsulates the silicon carbide JFET chip A, the negative voltage direct drive chip B, and the MOSFET chip C together. The package is provided with multiple external pins, including main power drain pin and source pin, 5V power supply input pin and ground pin, logic signal input pin, and at least one protection function related pin.

2. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The negative pressure direct drive chip B receives the 5V power supply and generates an adjustable negative pressure from -5V to -20V by its internal negative pressure generation circuit. When the silicon carbide JFET chip A needs to be turned off, the negative voltage direct drive chip B applies a negative bias voltage of -10V to -18V to the gate of the silicon carbide JFET chip A in the off state; When the silicon carbide JFET chip A needs to be turned on, the negative voltage direct drive chip B applies a bias voltage of -1V to +3V to the gate, so that the conductive channel is fully opened.

3. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The MOSFET chip C is turned on by the negative voltage direct drive chip B under at least one of the following conditions: during system power-on, when the 5V power supply drops below the undervoltage lockout threshold, or when an internal fault is detected; during normal operation, the MOSFET chip C is turned off, and the silicon carbide JFET chip A is controlled by the output of the drive stage.

4. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The silicon carbide JFET chip A is formed using silicon carbide material and is a normally open junction field-effect transistor with a vertical channel or lateral channel structure.

5. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The overcurrent protection circuit determines whether an overcurrent condition has occurred by detecting the drain-source voltage of the silicon carbide JFET chip A in the on state, or by detecting the voltage across the shunt resistor connected in series in the source circuit of the silicon carbide JFET chip A. When an overcurrent is detected, the negative voltage direct drive chip B controls the silicon carbide JFET chip A to safely turn off at a safe current decrease rate.

6. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The over-temperature protection circuit includes a temperature sensing element integrated inside the negative pressure direct drive chip B. The temperature sensing element indirectly senses the temperature of the silicon carbide JFET chip A through a thermal coupling path inside the package. When the over-temperature protection circuit detects that the temperature exceeds a preset over-temperature threshold, the negative pressure direct drive chip B forcibly shuts down the silicon carbide JFET chip A.

7. A negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 6, characterized in that: The temperature sensing element is a diode temperature sensor or a positive temperature coefficient thermistor.

8. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The undervoltage lockout protection circuit monitors the power supply voltage of the negative voltage direct drive chip B in real time. When the power supply voltage is lower than the preset undervoltage lockout threshold, the negative voltage direct drive chip B places the gate of the silicon carbide JFET chip A in a negative voltage state to keep the silicon carbide JFET chip A off, preventing drive failure due to insufficient power supply voltage.

9. The negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The drive stage output adopts a push-pull drive topology. During the conduction phase, the conduction side switch is closed, connecting the gate to the voltage terminal, so that the gate-source junction of the silicon carbide JFET chip A is in a bias voltage state, the conductive channel is fully opened, and the on-resistance is reduced to the minimum. During the turn-off phase, the turn-off side switch is closed and the conduction side switch is open, connecting the gate to the negative voltage terminal output by the negative voltage generation circuit, thus depleting the conductive channel and reliably turning off the device.

10. A negative voltage direct-drive silicon carbide JFET encapsulated device according to claim 1, characterized in that: The silicon carbide JFET chip A is a depletion-mode vertical channel JFET with a rated voltage of 650V, 750V, 1200V or 1700V.

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