Source follower based gate voltage bootstrap sampling switch and source follower based gate voltage bootstrap sampling control method

Abstract

This application relates to the field of analog integrated circuits and discloses a source follower-based gate voltage bootstrap sampling switch and a source follower-based gate voltage bootstrap sampling control method. The sampling switch includes a sampling switch transistor connected between the input node and the output node, a bootstrap capacitor, and a local source follower structure. The control terminal of the source follower transistor is coupled to the output node of the sampling switch transistor, and the output terminal drives the reference node of the bootstrap capacitor, so that the charging and discharging of the bootstrap capacitor is locally supplied by the local source follower structure. A bias transistor uses a bias voltage higher than ground potential as a control low level, providing bias current in a weakly inverted state in the sampling phase and approximately turning off in the holding phase. This application helps to reduce the equivalent fan-out load at the input, improve the effective overdrive voltage of the sampling switch, and shorten the gate voltage settling time.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuits, and in particular to a gate voltage bootstrap sampling switch technology for the front end of an analog-to-digital converter. Background Technology

[0002] In the front-end circuitry of high-speed analog-to-digital converters (ADCs), especially time-interleaved ADCs, the performance of the sampling switch directly affects the system's effective resolution and input bandwidth. Typical applications include: in high-speed communication systems, the receiver front-end needs to discretize broadband RF signals at sampling rates of tens of gigahertz; in high-energy physics experiments or optical communication systems, multiple time-interleaved ADCs are required to capture transient signal characteristics at extremely high equivalent sampling rates; and in on-chip self-test systems, multiple parallel sampling channels share the same input distribution network. In these applications, the on-resistance of the sampling switch needs to be sufficiently low to ensure sampling bandwidth, its gate drive voltage needs to build up in a very short time to meet the high-speed clock cycle, and the equivalent load seen by the front-end input node needs to be as small as possible to maintain signal integrity.

[0003] Gate voltage bootstrapping technology is a common method to improve the effective gate-source overdrive of sampling switches under low supply voltage conditions. Traditional gate voltage bootstrapping structures typically connect the reference terminal of the bootstrap capacitor directly to the input node to maintain an approximately constant gate-source voltage in the sampling phase. However, with increasing sampling rates and the number of time-interleaving paths, this traditional structure has the following limitations: the dynamic charging and discharging current of the bootstrap capacitor flows directly through the input distribution path, significantly increasing the equivalent fan-out load of the input node with the increase in the number of interleaving channels and the size of the bootstrap capacitor; the direct loading of the bootstrap capacitor on the input node creates an irreconcilable constraint between input bandwidth and bootstrap driving capability; under low supply voltage process conditions, the high gate potential after bootstrapping creates voltage stress on internal devices, requiring a balance between improving overdrive and ensuring device reliability. Therefore, a gate voltage bootstrapping sampling switch technology is needed that can maintain rapid gate voltage establishment while reducing the direct load on the input bootstrap capacitor and taking into account the reliability constraints of low-voltage devices. Summary of the Invention

[0004] The purpose of this application is to provide a source follower-based gate voltage bootstrap sampling switch and a source follower-based gate voltage bootstrap sampling control method to solve the problems mentioned in the background art.

[0005] This application discloses a gate voltage bootstrap sampling switch based on a source follower, including: a sampling switch transistor M7 connected between an input node Vop and an output node Vsp, wherein the output node Vsp is coupled to a sample-and-hold capacitor; A bootstrap capacitor is coupled between the first node N1 and the second node N2; the second node N2 is coupled to the gate of the sampling switch M7; The local source follower structure includes a source follower transistor M8 and a bias transistor M1; the control terminal of the source follower transistor M8 is coupled to the output node Vsp, and the output terminal of the source follower transistor M8 is coupled to the first node N1; the bias transistor M1 is disposed in the bias path powered by the second power supply voltage VDDH, and cooperates with the source follower transistor M8 to provide bias current to the source follower transistor M8 in the sampling phase; In the holding phase, the first node N1 is discharged to a low potential, the second node N2 is precharged to the first power supply voltage VDD, the gate of the sampling switch M7 is pulled to ground potential, and the bias transistor M1 is approximately turned off. In the sampling phase, the source follower transistor M8 follows the potential of the output node Vsp and drives the first node N1. The bootstrap capacitor raises the gate potential of the second node N2 and the sampling switch transistor M7, making the gate-source voltage of the sampling switch transistor M7 higher than the first power supply voltage VDD. The bias transistor M1 provides bias current to the source follower transistor M8 in a weak inversion state. The control low level of the bias transistor M1 is a bias voltage VSSH higher than the ground potential, so that the bias transistor M1 is near the weak inversion region at the end of the holding phase, thereby providing an initial bias current for the local source follower structure when entering the sampling phase.

[0006] In a preferred embodiment, the source follower transistor M8 is a PMOS transistor, the gate of the PMOS transistor is coupled to the output node Vsp, and the source of the PMOS transistor is coupled to the first node N1 as the output terminal of the source follower transistor M8.

[0007] In a preferred embodiment, in the steady state after the sampling switch M7 is turned on in the sampling phase, the potential of the output node Vsp approaches the potential of the input node Vop, and the gate-source voltage of the sampling switch M7 satisfies: in, The gate-source voltage of the sampling switch M7. The first power supply voltage is... The absolute value of the gate-source voltage when the source follower transistor M8 is in the on-follower state; thus, the sampling switch transistor M7 obtains a voltage higher than... Overdrive voltage.

[0008] In a preferred embodiment, the bias voltage VSSH is higher than the ground potential and configured to keep the maximum voltage stress between the relevant terminals of the bias transistor M1 below the process reliability limit, while keeping the bias transistor M1 in a biased state near the weak inversion region at the end of the holding phase rather than completely turned off, so that it does not need to recover from the deep cutoff state when entering the sampling phase.

[0009] In a preferred embodiment, a clock control network is also included, the clock control network comprising: The third transistor M3 is configured to discharge the first node N1 to a low potential in the holding phase; The second transistor M2 is configured to precharge the second node N2 to the first power supply voltage VDD in the holding phase; The fifth transistor M5 and the sixth transistor M6 are configured to pull the gate of the sampling switch M7 to ground potential in the holding phase.

[0010] In a preferred embodiment, during the sampling phase, the fourth transistor M4 and the fifth transistor M5 are turned off, causing the first node N1 of the bootstrap capacitor to be driven by the local source follower structure, and the second node N2 to float up and drive the gate potential of the sampling switch M7 to rise.

[0011] In a preferred embodiment, the local source follower structure is powered by a second power supply voltage VDDH, which is higher than the first power supply voltage VDD; the bias transistor M1 is coupled via an enable switch between the power supply node providing the second power supply voltage VDDH and the first node N1.

[0012] In a preferred embodiment, the fifth transistor M5 and the sixth transistor M6 are connected in series between the gate of the sampling switch M7 and the ground terminal; in the sampling phase, when the gate of the sampling switch M7 is raised to a high potential, the fifth transistor M5 is turned off to isolate the voltage stress of the high potential on the sixth transistor M6 which is on the low potential side.

[0013] In a preferred embodiment, the control terminal of the bias transistor M1 receives a control signal that switches between the bias voltage VSSH and a high control level; the control signal is at a level in the sampling phase that turns on the bias transistor M1 to provide bias current, and at the bias voltage VSSH in the holding phase that makes the bias transistor M1 approximately turn off; the low level of the control signal is the bias voltage VSSH and not ground potential.

[0014] This application also provides a gate voltage bootstrap sampling control method based on a source follower, applied to a bootstrap sampling switch circuit including a sampling switch transistor M7, a bootstrap capacitor, and a local source follower structure. The local source follower structure includes a source follower transistor M8 and a bias transistor M1. The control terminal of the source follower transistor M8 is coupled to the output node Vsp of the sampling switch transistor M7. The method includes: In the holding phase, the first node N1 of the bootstrap capacitor is discharged to a low potential, the second node N2 of the bootstrap capacitor is precharged to the first power supply voltage VDD, and the gate of the sampling switch M7 is pulled to the ground potential; at the same time, a bias voltage VSSH higher than the ground potential is used as the control low level of the bias transistor M1, so that the bias transistor M1 is approximately turned off but maintained near the weak inversion region. When entering the sampling phase, the source follower transistor M8 is started using the initial bias current provided by the bias transistor M1 when it is near the weak inversion region; In the sampling phase, after startup, the source follower transistor M8 follows the potential of the output node Vsp and drives the first node N1. The bootstrap capacitor raises the gate potential of the second node N2 and the sampling switch transistor M7, so that the gate-source voltage of the sampling switch transistor M7 is higher than the first power supply voltage VDD and turns on. After the sampling switch transistor M7 turns on, the output node Vsp follows the potential of the input node Vop and continues to serve as the following reference for the source follower transistor M8.

[0015] In a preferred embodiment, in the sampling phase, the dynamic charging and discharging current of the bootstrap capacitor is locally supplied via the local source follower structure and does not flow directly through the input distribution path where the input node Vop is located.

[0016] In a preferred embodiment, the source follower transistor M8 is a PMOS transistor; in the steady state of the sampling phase, the voltage of the gate of the sampling switch M7 relative to the output node Vsp is approximately equal to the absolute value of the first power supply voltage VDD and the gate-source voltage of the source follower transistor M8. The sum of these values ​​allows the sampling switch M7 to achieve a higher value than the given value. Effective overdrive voltage to reduce on-resistance.

[0017] In a preferred embodiment, the bias voltage VSSH is higher than the ground potential and is configured to simultaneously achieve: limiting the voltage stress between the relevant terminals of the bias transistor M1 to below the upper limit of process reliability; and maintaining the bias transistor M1 near the weak inversion region rather than completely turning it off at the end of the holding phase, so as to shorten the setup time of the local source follower structure when entering the sampling phase.

[0018] This application also provides an analog-to-digital converter, including the aforementioned gate voltage bootstrap sampling switch.

[0019] In a preferred embodiment, the analog-to-digital converter is a time-interleaved analog-to-digital converter, including the gate voltage bootstrap sampling switch configured in multiple parallel paths.

[0020] The gate voltage bootstrap sampling switch provided in this application establishes the reference drive relationship of the bootstrap capacitor between the output node Vsp of the sampling switch transistor M7 and the local source follower structure, rather than directly associating it with the input node Vop in the traditional scheme. This allows the dynamic current of the bootstrap capacitor charging and discharging in the sampling phase to be mainly supplied locally through the local source follower structure, and not to flow directly through the input distribution path where the input node Vop is located. This helps to reduce the equivalent fan-out capacitive load on the input node in high-speed sampling scenarios and improve the bandwidth burden of the input signal path.

[0021] In the embodiment where the source follower transistor M8 is a PMOS transistor, since the source (i.e., output terminal) potential of the PMOS source follower transistor is higher than its gate potential in the on-follower state, the first node N1 not only follows the potential of the output node Vsp in the sampling phase, but also forms a potential boost relative to Vsp that is related to the absolute value of the gate-source voltage of the PMOS source follower transistor. This boost is transferred to the second node N2 and the gate of the sampling switch transistor M7 through the bootstrap capacitor, so that the gate-source voltage of the sampling switch transistor M7 approximately satisfies the following in the steady state after it is turned on. Compared to the gate-source overdrive of approximately the first power supply voltage VDD in the traditional bootstrap structure, this application enables the sampling switch M7 to obtain an additional overdrive voltage increment, which is beneficial to reduce its on-resistance and improve the signal tracking characteristics during the high-speed sampling setup process.

[0022] The control low level of bias transistor M1 is set to a bias voltage VSSH higher than the ground potential instead of dropping directly to ground. This biasing strategy has two interrelated effects: First, because the control low level of bias transistor M1 does not drop to ground, the maximum voltage difference between the relevant terminals of M1 is limited, helping to keep the device voltage stress within the upper limit of process reliability. Second, this bias voltage VSSH keeps M1 in a bias state near the weak inversion region at the end of the hold phase instead of being deeply cut off. When the circuit switches to the sampling phase, M1 can quickly provide initial bias current to the source follower transistor M8 without recovering from a completely current-free cutoff state, thereby helping to shorten the startup time of the local source follower structure and reduce the gate voltage build-up delay. These two effects are achieved through the same bias voltage VSSH, forming an integrated synergy between device reliability protection and fast startup.

[0023] In the clock control network, the third transistor M3 discharges the first node N1 to a low potential in the holding phase, the second transistor M2 precharges the second node N2 to the first power supply voltage VDD, and the fifth transistor M5 and the sixth transistor M6 pull the gate of the sampling switch M7 to ground. This allows the bootstrap capacitor to form a defined initial state related to the first power supply voltage VDD before entering the next sampling phase, which helps reduce sampling errors caused by residual charge or uncertain node potentials and provides a defined starting condition for the bootstrap capacitor's rise process in the next sampling phase. In the sampling phase, the fourth transistor M4 and the fifth transistor M5 are turned off, allowing the first node N1 to be driven by the local source follower structure without being restrained by the holding phase reset branch. The second node N2 is unclamped and rises with the action of the bootstrap capacitor, thus allowing the gate potential of M7 to be bootstrap raised.

[0024] The fifth transistor M5 and the sixth transistor M6 are connected in series between the gate of the sampling switch M7 and the ground terminal. In the sampling phase, when the gate of M7 is raised to a high potential by the bootstrap capacitor, M5 is turned off, isolating the high potential above M5. This prevents the sixth transistor M6, which is on the low potential side, from directly experiencing the high voltage stress from the gate of M7. This series structure balances the functional requirement of grounding and resetting the gate of M7 in the holding phase with the reliability requirement of providing high-voltage isolation protection for the low-potential side devices in the sampling phase.

[0025] The local source follower structure is powered by a second power supply voltage VDDH that is higher than the first power supply voltage VDD, enabling the source follower transistor M8 to obtain sufficient current supply capability in the sampling phase to drive the first node N1 to follow the dynamic potential change of the output node Vsp. This helps to improve the following capability and setup speed of the local source follower structure under large signal swing input conditions.

[0026] The aforementioned technical methods work synergistically in terms of timing: maintaining the bias transistor M1 near the weak inversion state due to VSSH at the end of the phase provides the conditions for the rapid startup of the local source follower structure after entering the sampling phase; after the source follower transistor M8 starts, it drives the first node N1 with the output node Vsp as the reference, and the bootstrap capacitor enables the gate of M7 to obtain an overdrive voltage higher than VDD and quickly turn on; after M7 turns on, Vsp quickly follows Vop, thus providing a more stable following reference for M8, forming a rapid establishment chain of "gate voltage boost - M7 turn-on - Vsp following - source follower reference stabilization". The functional connection of each device in this chain enables this application to achieve the generation of bootstrap reference, the transfer of input fan-out load and the rapid establishment of sampling gate voltage with the local structural resources of the sampling switch without adding a global input replication drive path.

[0027] When the aforementioned gate voltage bootstrap sampling switch is used in a time-interleaved analog-to-digital converter with multiple parallel sampling channels, the charging and discharging of the bootstrap capacitors of each channel are no longer directly applied to the common input distribution network. This helps to slow down the linear superposition trend of the equivalent load of the input node when the number of interleaved paths increases, and improves the bandwidth and signal integrity of the input signal path in the high-speed time-interleaved sampling system.

[0028] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the circuit structure of a source follower-based gate voltage bootstrap sampling switch according to an embodiment of this application. It shows the connection relationship of the sampling switch transistor M7, the local source follower structure (including source follower transistor M8 and bias transistor M1), the bootstrap capacitor (coupled between the first node N1 and the second node N2), the clock control network (including the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6), the input node Vop, the output node Vsp, and the clock bootstrap unit.

[0030] Figure 2 This is a schematic diagram of the working timing of the bootstrap sample-and-hold circuit provided in an embodiment of the present invention. Detailed Implementation

[0031] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] Explanation of some concepts: Input node Vop refers to a node used to receive the analog input signal to be sampled. In a time-interleaved analog-to-digital converter, it can provide signals to the corresponding sampling channel for the preceding input buffer or RF input distribution network.

[0033] The output node Vsp refers to the local sampling node located on the output side of the sampling switch M7 and coupled to the sample-and-hold capacitor. In the sampling phase, the sampling switch M7 follows the potential of the input node Vop, and in the holding phase, it holds the sampled voltage.

[0034] A sampling switch is a MOS transistor used in analog-to-digital converters or sample-and-hold circuits. It is connected between the input node and the sample-and-hold capacitor and uses its on and off states to sample and hold the input signal.

[0035] A bootstrap capacitor is a capacitor element in a gate voltage bootstrap sampling switch that is coupled between the first node N1 and the second node N2. It is used to raise the gate potential of the sampling switch relative to the reference node in the sampling phase, so that the sampling switch can obtain an effective gate-source drive voltage higher than the power supply voltage.

[0036] A local source follower structure refers to a voltage follower unit formed by the cooperation of a source follower transistor and a bias transistor, which is set locally in the sampling switch. Its control terminal is coupled to the output node Vsp, and the output terminal drives the reference node of the bootstrap capacitor. It is used to generate a bootstrap reference related to the output node potential locally in the sampling switch.

[0037] The weak inversion region refers to the operating region of a MOS transistor when the gate-source voltage is below its threshold voltage but above the voltage required to completely turn off the transistor. In this region, the transistor conducts a small amount of subthreshold current.

[0038] The sampling phase refers to the clock phase in which the sampling switch is turned on and the output node Vsp follows the potential of the input node Vop through the sampling switch to achieve signal sampling.

[0039] The hold phase refers to the clock phase in which the sample-and-hold capacitor on the output node Vsp maintains the sampled voltage value when the sampling switch is turned off.

[0040] Fan-out refers to the total number of loads connected to an input node and their equivalent capacitive load in an input distribution network. The larger the fan-out, the larger the equivalent load seen by the input node.

[0041] Overdrive voltage refers to the portion of the gate-source voltage of the sampling switch that exceeds its threshold voltage. The larger this voltage is, the lower the on-resistance of the sampling switch.

[0042] The following is a brief summary of some of the innovative aspects of this application: In summary, in the front-end sampling scenario of high-speed time-interleaved analog-to-digital converters, traditional input-referenced gate-voltage bootstrap switches directly associate the reference terminal of the bootstrap capacitor with the input node Vop. This forces the dynamic charging and discharging current of the bootstrap capacitor to be borne by the input distribution network—this coupling relationship creates a mutual constraint between the equivalent fan-out capacitance at the input and the sampling bandwidth. The technical solution of this application does not simply add a buffer or a second input drive path between the bootstrap capacitor and the input. Instead, it transfers the bootstrap reference node to the output node Vsp of the sampling switch M7, and drives the first node N1 through a local PMOS source follower M8 whose gate is coupled to this output node Vsp. This creates a bootstrap reference generation path locally associated with the actual sampling output node in the sampling switch. The non-obvious aspect of this concept is that Vsp, being a dynamic node after the sampling switch, is affected by the holding capacitor and the turn-on process. Using it as the control reference for the local source follower structure means altering the load distribution and reference signal source of the bootstrap control loop—this is not an equivalent replacement of the traditional input reference node, but a structural reconstruction based on the insight that Vsp approaches Vop in the steady state of the sampling phase. Furthermore, to enable the local source follower structure to quickly establish itself at the beginning of the sampling phase rather than recovering from a deep cutoff state, the bias transistor M1 is configured to provide bias current in a weakly inverted state during the sampling phase and be approximately off during the holding phase. The key to achieving this dual-function state switching is that the control low level of M1 is set to a bias voltage VSSH higher than the ground potential. It is the existence of this bias voltage that limits the voltage stress between the relevant terminals of M1 within the upper limit of process reliability and keeps M1 near the weakly inverted region at the end of the holding phase rather than being completely off, thus achieving synergy between device reliability protection and rapid start-up of the source follower structure with the same bias level configuration. The aforementioned Vsp reference, local PMOS source follower M8 isolation, bias transistor M1's weak inversion dual function, and VSSH bias strategy are interdependent and synergistic: Because the bootstrap reference is taken from the output-side node Vsp rather than the global input path, it is necessary to set up a local source follower structure for local driving; because of the local source follower structure, bias transistor M1 needs to provide a phase-controlled bias current; and because M1 needs to switch between weak inversion and near-off states, VSSH is needed as a third level between ground potential and supply voltage to handle both reliability constraints and integrated startup state settings. This mutually constraining structural cooperation ultimately ensures that the gate-source voltage of the sampling switch M7 satisfies the following in near-steady state: This means that the bootstrap overdrive increases the voltage by an order of |VGS(M8)| compared to the traditional VDD – a result that cannot be directly derived by simply superimposing or transplanting any single known method in the prior art.

[0043] Furthermore, through long-term in-depth research, the inventors of this application discovered that the contradiction between input fan-out and sampling bandwidth faced by traditional gate-voltage bootstrap sampling switches in high-speed time-interleaved analog-to-digital converters stems not merely from the capacitance value of the bootstrap capacitor itself, but from the direct charging and discharging current path between the reference terminal of the bootstrap capacitor and the input node Vop. In the sampling phase, the bootstrap capacitor needs to continuously charge and discharge in response to the dynamic changes in the input signal. This current must be supplied through the distribution path where the input node Vop is located, thus imposing a dynamic load on the common input network in each sampling channel. The inventors further recognized that while the dual-input structure or buffer isolation scheme proposed in the prior art can separate the sampling signal path and the bootstrap drive path to a certain extent, the cost is often the need to additionally set up a global input replication drive branch or a system-level dual-output buffer. This not only increases power consumption and area overhead, but more importantly, it does not fundamentally eliminate the dependence of the bootstrap reference signal on the driving capability of the preceding stage.

[0044] Through in-depth analysis of the potential relationship between the input and output terminals when the sampling switch is on, the inventors discovered that in the steady-state or near-steady-state phase when the sampling switch M7 is fully on, the potential of the output node Vsp is essentially close to that of the input node Vop. Therefore, if the reference drive of the bootstrap capacitor is changed from the input node Vop to be taken from the output node Vsp and isolated and driven by the local source follower structure of the sampling switch, the dynamic current of the bootstrap capacitor can be closed locally in the sampling switch without having to flow through the common input distribution path. However, the implementation of this scheme is not as simple as changing the reference terminal connection—the inventors also discovered a key problem in practice: the local source follower structure faces a startup process at the beginning of each sampling phase, recovering from an unbiased or weakly biased state to normal following operation. If this startup process is too slow, the establishment of the bootstrap gate voltage will be significantly delayed, and the effective sampling window will be compressed. After repeated refinement, the inventors proposed that by setting the control low level of the bias transistor M1 to a bias voltage VSSH higher than the ground potential, M1 is not in deep cutoff at the end of the holding phase but is maintained near the weak inversion region. This allows the initial current to be provided to the source follower transistor M8 at the instant the sampling phase is switched in. Simultaneously, this bias voltage VSSH also limits the voltage stress between the relevant terminals of M1 within the process reliability threshold, achieving a combination of fast startup and device protection. Based on the above in-depth research, the inventors proposed a gate voltage bootstrap sampling switch scheme that uses the sampling output node Vsp as the local source follower reference, combines the weak inversion dual function of the bias transistor M1, and VSSH lift-off bias. The implementation process of this scheme is described in detail below through specific embodiments.

[0045] The specific embodiments of this application are described below with reference to the accompanying drawings. It should be noted that the following embodiments are used to explain the technical solutions of this application and should not be construed as limiting the scope of protection of this application; without departing from the technical concept of this application, those skilled in the art can make adaptive adjustments to some device dimensions, control signal names or bias voltages according to specific processes, power domains, device thresholds and clock implementation methods.

[0046] In this embodiment, a gate voltage bootstrap sampling switch based on a source follower includes a sampling switch M7, a bootstrap capacitor, a local source follower structure, and a clock control network. The sampling switch M7 is connected between the input node Vop and the output node Vsp, and the output node Vsp is coupled to the sample-and-hold capacitor. The input node Vop can be the input node of the corresponding sampling channel in a pre-stage input buffer, an RF input distribution network, or a time-interleaved analog-to-digital converter; the output node Vsp can be understood as the output-side node of the sampling switch M7, or as a local sampling node on the holding capacitor side. Unlike the traditional structure that directly associates the bootstrap capacitor reference terminal with the input node Vop, this embodiment enables the output node Vsp to participate in forming the bootstrap reference, so that the dynamic charging and discharging current of the bootstrap capacitor is mainly supplied by the local source follower structure of the sampling switch, rather than directly by the input distribution path where the input node Vop is located.

[0047] Specifically, a bootstrap capacitor is coupled between the first node N1 and the second node N2. The first node N1 serves as a bootstrap reference node driven by a local source follower structure, and the second node N2 is used to participate in raising the gate potential of the sampling switch M7. In the hold phase, the two ends of the bootstrap capacitor are set to a defined initial state; in the sampling phase, the first node N1 is raised by the local source follower structure as the potential of the output node Vsp changes, and the second node N2 floats due to the charge retention effect of the bootstrap capacitor, thereby enabling the gate of the sampling switch M7 to obtain a driving voltage higher than the first power supply voltage VDD.

[0048] The local source follower structure includes a source follower transistor M8 and a bias transistor M1. The control terminal of the source follower transistor M8 is coupled to the output node Vsp, and the output terminal of the source follower transistor M8 is coupled to the first node N1. In other words, the source follower transistor M8 does not directly use the input node Vop as the following reference, but rather uses the output node Vsp on the output side of the sampling switch transistor M7 as the following reference, thereby forming a bootstrap reference locally related to the actual sampling output node in the sampling switch. The bias transistor M1 cooperates with the source follower transistor M8 to form a bias path, enabling the source follower transistor M8 to obtain a bias current in the sampling phase and enter the source follower operation state.

[0049] In one specific embodiment, the source follower transistor M8 is a PMOS source follower transistor. The gate of this PMOS source follower transistor is coupled to the output node Vsp, and its output terminal is coupled to the first node N1. Since the output potential of the PMOS source follower transistor M8 is higher than its gate potential when it is in the follower state, the first node N1 can follow the output node Vsp in the sampling phase and form a certain potential boost relative to the output node Vsp. To avoid inconsistencies caused by the sign of the gate-source voltage of the PMOS transistor, this paper uniformly uses the absolute value of the gate-source voltage of the PMOS source follower transistor M8 to represent this potential boost.

[0050] In the sampling phase, let (V_{N1}) represent the potential of the first node N1, (V_{sp}) represent the potential of the output node Vsp, and (|V_{GS}(M8)|) represent the absolute value of the gate-source voltage of the source follower transistor M8 when it is in the on-follower state. Then the potential of the first node N1 can be approximately expressed as: (Formula 1) Where (V_{N1}) is the potential of the first node N1, (V_{sp}) is the potential of the output node Vsp, and (|V_{GS}(M8)|) is the absolute value of the gate-source voltage when the PMOS source follower transistor M8 is in the on-follower state. This formula indicates that when M8 operates as a source follower with the output node Vsp as the control reference, the first node N1 is not directly driven by the input node Vop, but is locally raised by the local PMOS source follower structure.

[0051] In the holding phase, the first node N1 is discharged to a low potential, and the second node N2 is pre-charged to the first power supply voltage VDD. Thus, the bootstrap capacitor forms an initial voltage difference related to the first power supply voltage VDD before entering the sampling phase. After entering the sampling phase, the first node N1 is raised by the source follower transistor M8, and the second node N2 floats up along with the first node N1; when the second node N2 is coupled to the gate drive node of the sampling switch transistor M7, the gate potential of the sampling switch transistor M7 also increases. Let (V_G(M7)) represent the gate potential of the sampling switch transistor M7, (V_{N2}) represent the potential of the second node N2, and (V_{DD}) represent the first power supply voltage, then under the ideal bootstrap approximation, it can be expressed as: (Formula 2) Where (V_G(M7)) is the gate potential of sampling switch M7, (V_{N2}) is the potential of the second node N2, (V_{DD}) is the first power supply voltage, (V_{sp}) is the potential of output node Vsp, and (|V_{GS}(M8)|) is the absolute value of the gate-source voltage of PMOS source follower M8 when it is in the on-follower state. This approximation is based on the premise that the bootstrap capacitor has been pre-charged to an initial state related to VDD in the holding phase, and that the first node N1 is driven to rise by the local source follower structure in the sampling phase.

[0052] Furthermore, in the steady-state or near-steady-state phase after the sampling switch M7 is turned on, the potential of the output node Vsp approaches the potential of the input node Vop. When explaining this by approximating the potential of the signal terminal of the sampling switch M7 as the potential of the output node Vsp, let (V_{GS}(M7)) represent the gate-source voltage of the sampling switch M7, which can then be approximately expressed as: (Formula 3) Where (V_{GS}(M7)) is the gate-source voltage of sampling switch M7, (V_G(M7)) is the gate potential of sampling switch M7, (V_{sp}) is the potential of output node Vsp, (V_{DD}) is the first power supply voltage, and (|V_{GS}(M8)|) is the absolute value of the gate-source voltage of PMOS source follower M8. Therefore, when sampling switch M7 is in a conduction state suitable for transmitting the sampling signal, this embodiment enables M7 to obtain a higher effective gate-source overdrive voltage than the conventional approximately VDD bootstrap drive, which helps to reduce the on-resistance and shorten the gate voltage build-up process in the sampling phase. This effect is the result of the synergistic effect of the local source follower structure, the output node Vsp reference, and the bootstrap capacitor, rather than being generated by a single device in isolation.

[0053] Furthermore, in the holding phase, the clock control network causes each critical node to enter a defined reset and precharge state. Specifically, the third transistor M3 is turned on in the holding phase to discharge the first node N1 to a low potential; the second transistor M2 is turned on in the holding phase to precharge the second node N2 to the first power supply voltage VDD; the fifth transistor M5 and the sixth transistor M6 are turned on in the holding phase to pull the gate of the sampling switch M7 to ground potential. Through the above actions, the first node N1, the second node N2, and the gate of the sampling switch M7 are in a relatively defined initial state before entering the next sampling phase, which helps to reduce sampling errors caused by residual charge or uncertain node potentials.

[0054] During the hold phase, the bias transistor M1 is approximately off. It should be noted that "approximately off" as described herein does not mean that bias transistor M1 is in a deep cutoff state throughout the entire hold phase. The control low level of bias transistor M1 is a bias voltage VSSH higher than ground potential. This bias voltage VSSH reduces residual drive in the main body of the hold phase, while maintaining a bias state near the weak inversion region at the end of the hold phase or near the beginning of the sampling phase. Thus, when the circuit switches from the hold phase to the sampling phase, bias transistor M1 does not need to completely recover from the deep cutoff state, but can instead provide initial bias current to the source follower transistor M8, which helps to shorten the startup time of the local source follower structure.

[0055] Optionally, in this embodiment, the first power supply voltage VDD can be a power supply voltage adapted to the low-voltage sampling switch, the second power supply voltage VDDH can be a power supply voltage higher than the first power supply voltage VDD, and the bias voltage VSSH can be a control low level higher than the ground potential. For example, in a specific process implementation, VDD can be approximately 0.9V, VDDH can be approximately 1.2V, and VSSH can be approximately 0.4V. The above values ​​are only examples related to specific processes and should not be construed as limiting the scope of protection of this application. VDDH can be provided by an external power supply, and VSSH can be generated by an existing on-chip bias structure; under other process or power conditions, VDDH and VSSH can be adapted according to the upper limit of device reliability, threshold voltage, and the startup requirements of the source follower structure.

[0056] Furthermore, the control terminal of the bias transistor M1 receives a control signal that switches between the bias voltage VSSH and a high control level. This control signal is at a level that turns on the bias transistor M1 to provide bias current during the sampling phase, and at the bias voltage VSSH during the holding phase, so that the bias transistor M1 is approximately turned off and its control low level does not drop directly to ground potential. Since the control low level of the bias transistor M1 is VSSH rather than ground potential, this helps to limit the voltage stress between the relevant terminals of M1 and maintain M1 in the vicinity of the weak inversion region at the end of the holding phase. This combines device reliability management with the fast startup of the source follower structure in the same bias strategy.

[0057] In the sampling phase, the fourth transistor M4 and the fifth transistor M5 are turned off. Turning off the fourth transistor M4 prevents the first node N1 from being constrained by the reset or auxiliary control branch in the holding phase, thus allowing it to be driven by the local source follower structure. Turning off the fifth transistor M5 removes the ground clamping of the gate of the sampling switch M7, allowing the second node N2 and the gate of M7 to float up due to the bootstrap capacitor. The fifth transistor M5 and the sixth transistor M6 are connected in series between the gate of the sampling switch M7 and the ground terminal. When the gate of M7 in the sampling phase is raised to a high potential, M5 is turned off, isolating the high potential from the voltage stress on the sixth transistor M6, which is on the low potential side. Thus, the series structure of M5 and M6 balances gate reset in the holding phase and high-voltage isolation in the sampling phase, avoiding simply exposing the gate reset branch to the high potential after bootstrapping.

[0058] In this embodiment, the clock control network can be controlled by complementary or interlocked clock signals. For example, the clock signals used for switching between the hold phase and the sampling phase may include signals such as QS, QSb, QSI, and QBSTb, and these signals can be generated by existing clock bootstrap units or clock generation units. The clock bootstrap unit in the form of cross-coupled transistors and dual capacitors shown in the figures can be used to provide the corresponding clock control level, but its specific structure can adopt existing structures in the art and is not the main improvement point of this application. The improvement focus of this application is: using the output node Vsp as the control reference of the local source follower structure, and combining the weak inversion / approximate turn-off dual function of the bias transistor M1 and the VSSH bias level, to achieve local generation of the bootstrap reference, rapid establishment of the sampling gate voltage, and overdrive improvement under device reliability constraints.

[0059] The working process of this embodiment is further explained as follows. In the hold phase, the gate of the sampling switch M7 is pulled to ground potential by M5 and M6, and M7 is turned off; M3 discharges the first node N1 to a low potential, and M2 precharges the second node N2 to the first power supply voltage VDD, so that the bootstrap capacitor forms a defined initial voltage; the control terminal of the bias transistor M1 receives the bias voltage VSSH, so that M1 is approximately turned off, but not completely enters the deep cutoff state. At the end of the hold phase, since the gates of N1, N2 and M7 are all in a controlled state, the circuit does not need to recover from the unknown node potential at the beginning of the next sampling phase.

[0060] When the sampling phase begins, the control signal for bias transistor M1 switches to a level that enables it to conduct and provide bias current. Since M1 has been maintained near the weak inversion region at the end of the holding phase, it can quickly provide the initial bias current to the local source follower structure. Source follower transistor M8 enters the follower state under the influence of the bias current. Its control terminal receives the potential of output node Vsp, and its output terminal drives the first node N1. As the first node N1 is boosted, the bootstrap capacitor causes the gate of the second node N2 and the sampling switch M7 to float up accordingly. M7 obtains an effective gate-source overdrive voltage higher than VDD and turns on.

[0061] It should be noted that at the beginning of the sampling phase, the sampling switch M7 is not yet fully turned on, and the output node Vsp may not yet fully follow the input node Vop. At this time, the source follower transistor M8 will have a brief setup process using Vsp as the following reference. This process does not affect the basic working logic of this embodiment: on the one hand, the bootstrap capacitor has formed a pre-charge state related to VDD in the holding phase; on the other hand, the rise of N1 after the start of the sampling phase causes N2 and the gate of M7 to rise rapidly, thereby allowing M7 to enter the conducting state more quickly. As M7 turns on, the output node Vsp quickly follows the input node Vop, the source follower transistor M8 obtains a more stable reference, and the gate potentials of N1 and M7 are further stabilized. This forms a rapid setup chain of "gate voltage rise - M7 turn on - Vsp follow - source follower reference stabilization".

[0062] After M7 is turned on, the output node Vsp follows the input node Vop through M7. Since the control terminal of M8 is coupled to the output node Vsp, the dynamic potential of the output node Vsp continues to serve as a reference for the local source follower structure, causing the gate potentials of the first node N1 and M7 to change in tandem with the sampling output node. In this way, the dynamic charging and discharging of the bootstrap capacitor does not need to be directly applied to the input distribution path where the input node Vop is located. The input path mainly bears the transmission of the sampled signal, while the local source follower structure bears the local driving of the bootstrap reference node. This operating mode is beneficial for reducing the equivalent fan-out load at the input end in high-speed sampling scenarios, and makes the gate voltage establishment of the sampling switch M7 more directly serve the actual potential change of the output sampling node.

[0063] This application can also be implemented as a gate voltage bootstrap sampling control method based on a source follower. This method is applied to a bootstrap sampling switch circuit that includes a sampling switch transistor M7, a bootstrap capacitor, and a local source follower structure, wherein the local source follower structure includes a source follower transistor M8 and a bias transistor M1, and the control terminal of the source follower transistor M8 is coupled to the output node Vsp of the sampling switch transistor M7.

[0064] In step 100, the circuit enters the holding phase. The third transistor M3 discharges the first node N1 of the bootstrap capacitor to a low potential, the second transistor M2 precharges the second node N2 of the bootstrap capacitor to the first power supply voltage VDD, and the fifth transistor M5 and the sixth transistor M6 pull the gate of the sampling switch M7 to ground potential. Simultaneously, a bias voltage VSSH higher than ground potential is used as the control low level for the bias transistor M1, keeping it in a near-off state and maintaining it near the weak inversion region at the end of the holding phase. Through step 100, the circuit establishes a defined bootstrap initial state and bias initial state before entering the next sampling phase.

[0065] In step 200, the circuit switches from the holding phase to the sampling phase. The control signal for the bias transistor M1 is switched from the bias voltage VSSH to a level that turns M1 on to provide bias current. Since M1 is not in a deeply cut-off state at the end of the holding phase, it can provide initial bias current to the source follower transistor M8, allowing the source follower transistor M8 to enter the following working state more quickly. The purpose of this step is to reduce the recovery time required for the local source follower structure to start from a completely unbiased state.

[0066] In step 300, the source follower transistor M8 follows the potential of the output node Vsp and drives the first node N1. Since the control terminal of the source follower transistor M8 is coupled to the output node Vsp, and its output terminal is coupled to the first node N1, the potential of the first node N1 can change with the potential of the output node Vsp, and a potential boost related to the absolute value of the gate-source voltage of M8 is superimposed in the PMOS source follower structure. At the same time, the fourth transistor M4 and the fifth transistor M5 are turned off in the sampling phase, so that the first node N1 is driven by the local source follower structure, and the gate of M7 is disengaged from the ground clamp of the holding phase.

[0067] In step 400, the bootstrap capacitor transfers the boost from the first node N1 to the second node N2 and the gate of the sampling switch M7, raising the gate potential of the sampling switch M7 and turning it on. After M7 is turned on, the output node Vsp follows the potential of the input node Vop and continues to serve as the following reference for the source follower transistor M8. Thus, the dynamic charging and discharging current of the bootstrap capacitor is locally supplied through the local source follower structure, instead of flowing directly through the input distribution path where the input node Vop is located.

[0068] In step 500, when the sampling phase ends and the holding phase begins again, the clock control network re-discharges the first node N1, pre-charges the second node N2 to the first power supply voltage VDD, pulls the gate of the sampling switch M7 to ground, and switches the control low level of the bias transistor M1 to the bias voltage VSSH. Through this repeated process, the sampling switch can maintain a relatively certain reset state and a relatively fast sampling phase start-up state during continuous sampling cycles.

[0069] The aforementioned gate voltage bootstrap sampling switch can be used in analog-to-digital converters (ADCs), particularly in time-interleaved ADCs. A time-interleaved ADC can include multiple parallel sampling channels, each with its own gate voltage bootstrap sampling switch. Since each sampling channel is sensitive to the equivalent load of the input distribution network and the gate voltage build-up speed of the sampling switch during high-speed interleaving, the output reference-type local source follower structure of this embodiment helps reduce the direct burden on the bootstrap capacitors in the input path and locally forms a gate voltage bootstrap drive for each sampling channel.

[0070] The above embodiments have the following technical effects: First, by transferring the bootstrap reference from the input node Vop to the local source follower structure related to the output node Vsp, the direct load effect of the dynamic current of the bootstrap capacitor charging and discharging on the input distribution path can be reduced, which is beneficial to improving the bandwidth burden of the high-speed input signal path; Second, by using the source follower transistor M8 to drive the first node N1 with the output node Vsp as the control reference, the bootstrap reference can be made closer to the actual dynamic node on the output side of the sampling switch, thereby assisting the sampling switch transistor M7 to quickly establish the gate voltage in the sampling phase; Third, by using the bias transistor M1 to provide bias current in the sampling phase, approximately turn off in the holding phase, and control it to a low level, the bias transistor M1 provides bias current in the sampling phase, approximately turns off in the holding phase, and controls it to a low level. Setting VSSH to be higher than the ground potential can shorten the startup process of the local source follower structure under the constraints of device reliability; fourth, through the absolute value of the gate-source voltage introduced by the PMOS source follower transistor M8, the sampling switch transistor M7 can obtain an effective gate-source overdrive higher than the first power supply voltage VDD, which is beneficial to reduce the on-resistance in the appropriate operating area; fifth, by using M3, M2, M5 and M6 to achieve N1 discharge, N2 precharge and M7 gate ground in the holding phase respectively, and by using the series connection of M5 / M6 to achieve high voltage isolation of the sampling phase, a more certain initial node state can be provided for the next sampling phase, and the voltage stress of high gate voltage on the low potential reset branch can be reduced.

[0071] The embodiments of this application will be further explained and illustrated by example below.

[0072] In the embodiments of this application, the bias transistor M1 is a PMOS transistor, and the source follower transistor M8 is a PMOS source follower transistor. One end of the bias transistor M1 is coupled to the bias node powered by the second power supply voltage VDDH, and the other end is directly or normally coupled to the local source follower bias path of the first node N1 through a common source cascode transistor. The control terminal of the source follower transistor M8 is coupled to the output node Vsp, and the output terminal of the source follower transistor M8 is coupled to the first node N1. The control terminal of the bias transistor M1 receives a bias control signal that switches between the bias voltage VSSH and the first power supply voltage VDD; wherein VSSH is the low level of the bias control signal, and VDD is the high level of the bias control signal.

[0073] Since the bias transistor M1 is a PMOS transistor, in the sampling phase, the bias control signal is at a low level VSSH, which increases the absolute value of the gate-source voltage of the bias transistor M1, thereby turning on the PMOS bias transistor M1 and providing bias current to the source follower transistor M8, causing the source follower transistor M8 to enter the source follower operating state with the output node Vsp as the control reference. In the hold phase, the bias control signal is at a high level VDD, which decreases the absolute value of the gate-source voltage of the bias transistor M1, thereby putting the PMOS bias transistor M1 in a near-off state. Furthermore, since the low level of the bias control signal uses a bias voltage VSSH higher than the ground potential instead of the ground potential, it is beneficial to limit the maximum voltage difference between the relevant terminals of the bias transistor M1. At the same time, the bias transistor M1 can be maintained near the weak inversion region rather than in a deep cutoff state at the end of the hold phase, which is beneficial for the local source follower structure to quickly establish its operating state when switching from the hold phase to the sampling phase.

[0074] In the embodiments of this application, the clock control network can receive control signals such as QS, QSb, QSI, and QBSTb. QS and QSb can be complementary clock signals, wherein QS is high in the sampling phase and low in the holding phase; QSb is high in the holding phase and low in the sampling phase; QSI is high (VDD) in the holding phase and low (VSSH) in the sampling phase; and QBSTb is high in the holding phase and low in the sampling phase. Further, the high level of QBSTb can be VDD+0.5V, and the low level can be VDD, and QBSTb can be determined by… Figure 1 The clock bootstrap circuit shown in the lower right corner generates the clock; the low level of QSI can be about 0.4V, i.e., the bias voltage VSSH, and the high level can be VDD; the high level of QS and QSb can be VDD, and the low level can be ground potential.

[0075] Specifically, in the holding phase, the control signal QSb is high, turning on the third transistor M3 to discharge the first node N1 to a low potential, and turning on the fifth transistor M5 and the sixth transistor M6 to pull the gate of the sampling switch M7 to ground potential; the control signal QBSTb is high, turning on the second transistor M2 to precharge the second node N2 to the first power supply voltage VDD; the control signal QSI is high, turning off the PMOS switch controlled by QSI, thereby isolating the second node N2 from the gate of the sampling switch M7. Through the above holding phase operation, the first node N1, the second node N2, and the gate of the sampling switch M7 form a defined reset and precharge state before entering the next sampling phase.

[0076] In the sampling phase, control signals QBSTb and QSb switch to low level VDD, turning off the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5. This removes the constraint of the holding phase reset branch on the first node N1, allowing it to be driven by the local source follower structure. Simultaneously, the gate of the sampling switch M7 is released from ground clamping. At this time, control signal QSI switches to low level VSSH, causing bias transistor M1 to provide bias current to the source follower transistor M8, and enabling the gates of the second node N2 and the sampling switch M7 to enter a state where they can float with the bootstrap capacitor. The source follower transistor M8 drives the first node N1 with the output node Vsp as the control reference. After the potential of the first node N1 rises, the bootstrap capacitor drives the gate potentials of the second node N2 and the sampling switch M7 to rise, thereby enabling the sampling switch M7 to obtain an effective gate-source overdrive voltage higher than the first power supply voltage VDD.

[0077] Furthermore, setting the high level of QBSTb to VDD+0.5V in the holding phase facilitates the full conduction of the second transistor M2 in the holding phase, thereby pre-charging the second node N2 to the first power supply voltage VDD. Setting the low level of QBSTb to VDD in the sampling phase facilitates the turn-off of the second transistor M2, allowing the second node N2 to float to a potential higher than VDD due to the bootstrap capacitor. Thus, the high and low level settings of QBSTb are used not only for pre-charge control in the holding phase but also to release the pre-charge clamping of the second node N2 in the sampling phase, in conjunction with the bootstrap capacitor to raise the gate potential of the sampling switch M7.

[0078] In a specific example, the first power supply voltage VDD can be approximately 0.9V, the second power supply voltage VDDH can be approximately 1.2V and is provided by an external power supply, and the bias voltage VSSH can be approximately 0.4V and is generated by an existing on-chip bias structure; the low level of QBSTb can be VDD, and the high level can be VDD+0.5V, which can be generated by a clock bootstrap circuit. The above values ​​are only used to illustrate an implementation under a specific process condition. Under other process nodes, device thresholds, power supply configurations, and reliability requirements, the high and low levels of VDD, VDDH, VSSH, and QBSTb can be adaptively adjusted, which does not constitute a limitation on the scope of protection of this application.

[0079] Under the same process, power supply, sampling frequency, input amplitude, and sample-and-hold capacitor conditions, compared with the conventional input reference type bootstrap structure, the embodiments of this application can reduce the direct load of the bootstrap capacitor seen by the input node Vop by transferring the bootstrap reference from the input node Vop to the local source follower structure related to the output node Vsp; by driving the first node N1 through the source follower transistor M8 and raising the gate of the sampling switch transistor M7 through the bootstrap capacitor, the effective operating bandwidth of the sampling switch can be increased; by reducing the dynamic loading at the input end and increasing the effective gate-source overdrive of the sampling switch transistor M7, the sampling linearity of the sampling switch can be improved; by making the dynamic charging and discharging of the bootstrap capacitor mainly complete in the local path where the local source follower structure is located, the feedthrough effect of the clock signal on the input node Vop can also be reduced.

[0080] Compared to solutions that only employ a source follower structure to reduce the input load seen at the input node Vop, the embodiments of this application further combine the PMOS bias structure of the bias transistor M1, the weak inversion current supply and hold-related disconnection control formed by the switching of QSI between VSSH and VDD, the consideration of VSSH for device voltage stress and fast startup operating point, the reset precharge timing of the first node N1 and the second node N2, and the series gate reset protection structure of the fifth transistor M5 and the sixth transistor M6. These structures and timings together form a complete operating chain from hold-phase reset, sampling-phase startup, source follower drive, bootstrap to gate protection, rather than achieving input load isolation solely through a single source follower.

[0081] This application preferably describes a local source follower structure using a PMOS source follower transistor M8. However, other equivalent local source follower structures can be used while maintaining the local follower relationship where the control terminal receives the output node Vsp potential, the output terminal drives the first node N1, and the bootstrap capacitor is not directly driven by the input node Vop. For cases using different device types or different source follower implementations, the potential relationship of the first node N1, the floating relationship of the bootstrap capacitor, and the gate-source voltage relationship of the sampling switch transistor M7 can be redefined based on the specific device type, power domain, and bias method.

[0082] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0083] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A gate voltage bootstrap sampling switch based on a source follower, characterized in that, include: The sampling switch M7 is connected between the input node Vop and the output node Vsp, and the output node Vsp is coupled to the sample-and-hold capacitor; A bootstrap capacitor is coupled between the first node N1 and the second node N2; the second node N2 is coupled to the gate of the sampling switch M7; The local source follower structure includes a source follower transistor M8 and a bias transistor M1; the control terminal of the source follower transistor M8 is coupled to the output node Vsp, and the output terminal of the source follower transistor M8 is coupled to the first node N1; the bias transistor M1 is disposed in a bias path powered by a second power supply voltage VDDH, and cooperates with the source follower transistor M8 to provide a bias current to the source follower transistor M8 in the sampling phase; In the holding phase, the first node N1 is discharged to a low potential, the second node N2 is precharged to the first power supply voltage VDD, the gate of the sampling switch M7 is pulled to ground potential, and the bias switch M1 is approximately turned off. In the sampling phase, the source follower transistor M8 follows the potential of the output node Vsp and drives the first node N1. Through the bootstrap capacitor, it raises the gate potential of the second node N2 and the sampling switch transistor M7, so that the gate-source voltage of the sampling switch transistor M7 is higher than the first power supply voltage VDD. The bias transistor M1 provides bias current to the source follower transistor M8 in a weakly inverted state. The control low level of the bias transistor M1 is a bias voltage VSSH higher than the ground potential, so that the bias transistor M1 is near the weak inversion region at the end of the holding phase, thereby providing an initial bias current for the local source follower structure when entering the sampling phase.

2. The gate voltage bootstrap sampling switch according to claim 1, characterized in that, The source follower transistor M8 is a PMOS transistor, the gate of which is coupled to the output node Vsp, and the source of which serves as the output terminal of the source follower transistor M8 and is coupled to the first node N1.

3. The gate voltage bootstrap sampling switch according to claim 2, characterized in that, In the steady state after the sampling switch M7 is turned on in the sampling phase, the potential of the output node Vsp approaches the potential of the input node Vop, and the gate-source voltage of the sampling switch M7 satisfies: in, The gate-source voltage of the sampling switch M7. The first power supply voltage is... The absolute value of the gate-source voltage when the source follower transistor M8 is in the on-follower state; thus, the sampling switch transistor M7 obtains a voltage higher than... The overdrive voltage is used to reduce the on-resistance.

4. The gate voltage bootstrap sampling switch according to claim 1, characterized in that, It also includes a clock control network, which comprises: The third transistor M3 is configured to discharge the first node N1 to a low potential in the holding phase; The second transistor M2 is configured to precharge the second node N2 to the first power supply voltage VDD in the holding phase; The fifth transistor M5 and the sixth transistor M6 are configured to pull the gate of the sampling switch M7 to ground potential in the holding phase.

5. The gate voltage bootstrap sampling switch according to claim 1, characterized in that, The local source follower structure is powered by a second power supply voltage VDDH, which is higher than the first power supply voltage VDD; the bias transistor M1 is coupled via an enable switch between the power supply node providing the second power supply voltage VDDH and the first node N1.

6. The gate voltage bootstrap sampling switch according to claim 4, characterized in that, The fifth transistor M5 and the sixth transistor M6 are connected in series between the gate of the sampling switch M7 and the ground terminal; in the sampling phase, when the gate of the sampling switch M7 is raised to a high potential, the fifth transistor M5 is turned off to isolate the voltage stress of the high potential on the sixth transistor M6 which is on the low potential side.

7. The gate voltage bootstrap sampling switch according to claim 1, characterized in that, The control terminal of the bias transistor M1 receives a control signal that switches between the bias voltage VSSH and a high control level; the control signal is at a level that turns on the bias transistor M1 to provide bias current in the sampling phase, and at the bias voltage VSSH that makes the bias transistor M1 approximately turn off in the holding phase; the low level of the control signal is the bias voltage VSSH rather than ground potential, so that the maximum voltage stress between the relevant terminals of the bias transistor M1 is lower than the upper limit of process reliability.

8. A gate voltage bootstrap sampling control method based on a source follower, applied to a bootstrap sampling switch circuit including a sampling switch transistor M7, a bootstrap capacitor, and a local source follower structure, wherein the local source follower structure includes a source follower transistor M8 and a bias transistor M1, and the control terminal of the source follower transistor M8 is coupled to the output node Vsp of the sampling switch transistor M7, characterized in that, The method includes: In the holding phase, the first node N1 of the bootstrap capacitor is discharged to a low potential, the second node N2 of the bootstrap capacitor is precharged to the first power supply voltage VDD, and the gate of the sampling switch M7 is pulled to ground potential; at the same time, a bias voltage VSSH higher than the ground potential is used as the control low level of the bias transistor M1, so that the bias transistor M1 is approximately turned off but maintained near the weak inversion region; When entering the sampling phase, the source follower transistor M8 is started using the initial bias current provided by the bias transistor M1 when it is near the weak inversion region; In the sampling phase, after startup, the source follower transistor M8 follows the potential of the output node Vsp and drives the first node N1. Through the bootstrap capacitor, it raises the gate potential of the second node N2 and the sampling switch transistor M7, so that the gate-source voltage of the sampling switch transistor M7 is higher than the first power supply voltage VDD and turns on. After the sampling switch transistor M7 turns on, the output node Vsp follows the potential of the input node Vop and continues to serve as the following reference for the source follower transistor M8.

9. The method according to claim 8, characterized in that, In the sampling phase, the dynamic charging and discharging current of the bootstrap capacitor is locally supplied via the local source follower structure and does not flow directly through the input distribution path where the input node Vop is located.

10. A time-interleaved analog-to-digital converter, characterized in that, The gate voltage bootstrap sampling switch, as described in any one of claims 1 to 7, includes a multi-channel parallel configuration.

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