A temperature-robust wideband phase-locked loop circuit and method

Abstract

This invention provides a temperature-robust broadband phase-locked loop (PLL) circuit and method. The circuit includes: a frequency phase detector; a charge pump; a loop filter; a mode selector; a voltage-controlled oscillator (VCO); a frequency divider; a temperature-compensated voltage generator; a temperature-compensated reference voltage generator; and a temperature-compensated tail current generation circuit. The temperature-robust broadband PLL circuit has an open-loop frequency band selection mode and a closed-loop phase-locked operation mode. In the open-loop frequency band selection mode, the temperature-compensated voltage generator is connected to the VCO to ensure that the adjustment voltage at the control terminal of the VCO is within a preset range. In the closed-loop phase-locked operation mode, the reference voltage is applied to part of the VCO's voltage-controlled capacitor to compensate for capacitor drift caused by temperature changes, and a positive temperature coefficient current is introduced into the tail current. This invention reduces the probability of PLL lockout under extreme temperatures.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and communication technology, and in particular to a temperature-robust broadband phase-locked loop circuit and method. Background Technology

[0002] Phase-locked loop (PLL) circuits are widely used in various electronic devices, such as telecommunications systems, on-chip clock generation circuits, and transceiver local oscillator circuits, because they can generate clock signals with controllable frequency and phase. In high-performance wireless communication and high-frequency signal processing systems, PLL circuits, as the core module providing high-precision, low-jitter local oscillation signals, directly determine the communication quality and operational reliability of the entire system due to their frequency stability and temperature robustness.

[0003] However, the oscillation frequency of the voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) circuit is significantly affected by changes in operating temperature. When the operating temperature changes, the physical characteristics of components such as the inductor's parasitic resistance, variable capacitor, and fixed capacitor within the VCO drift, causing a shift in the VCO's output frequency. This temperature drift is particularly pronounced in wideband PLL circuits. Temperature drift can cause the loop control voltage of the PLL circuit to approach or exceed the power supply voltage range, leading to a deterioration in the PLL circuit's performance and even functional failures such as lockout. Summary of the Invention

[0004] This invention provides a temperature-robust broadband phase-locked loop circuit and method to solve the problem of frequency drift in voltage-controlled oscillators caused by temperature changes.

[0005] This invention provides a temperature-robust broadband phase-locked loop circuit, comprising: a frequency phase detector for comparing the phase difference between a reference clock and a feedback clock and outputting a phase difference signal; a charge pump for converting the phase difference signal into a current signal; a loop filter for filtering the current signal to generate a loop control voltage; a mode selector for selectively outputting the loop control voltage or a correction voltage; a voltage-controlled oscillator for generating an output clock signal based on the output of the mode selector; a frequency divider for dividing the output clock signal to generate the feedback clock; a temperature-compensated correction voltage generator for generating the temperature-dependent correction voltage; and a temperature-compensated reference clock. A voltage generator is provided to generate a reference voltage that dynamically varies with temperature; and a temperature-compensated tail current generation circuit is provided to supply a tail current to the voltage-controlled oscillator (VCO). The temperature-robust broadband phase-locked loop (PLL) circuit has an open-loop frequency band selection mode and a closed-loop phase-locked operation mode. In the open-loop frequency band selection mode, the temperature-compensated voltage generator is connected to the VCO to ensure that the regulated voltage input to the control terminal of the VCO is within a preset range. In the closed-loop phase-locked operation mode, the reference voltage is applied to a portion of the VCO's voltage-controlled capacitor to compensate for capacitor drift caused by temperature changes, while a positive temperature coefficient current is introduced into the tail current.

[0006] In one embodiment of the present invention, the voltage-controlled oscillator includes an inductor, a fixed capacitor, a selection switch, a cross-coupled positive feedback differential pair, a tail current source, and a voltage-controlled variable capacitor array composed of multiple voltage-controlled capacitors; wherein, the first terminal of each voltage-controlled capacitor is connected to the power supply voltage through an inductor, and the second terminal is connected to the selection switch; the selection switch performs a three-way selection according to a configuration signal to selectively connect the second terminal to the reference voltage, the power supply voltage, or the regulating voltage; if the selection switch selects to connect to the reference voltage, the corresponding voltage-controlled capacitor serves as a temperature correction compensation capacitor; if the selection switch selects to connect to the power supply voltage, the corresponding voltage-controlled capacitor serves as a fixed capacitor; if the selection switch selects to connect to the regulating voltage, the corresponding voltage-controlled capacitor is connected to the closed-loop circuit.

[0007] In one embodiment of the present invention, the temperature-robust broadband phase-locked loop circuit further includes an automatic amplitude control circuit and an automatic frequency band selection circuit. If in the open-loop frequency band selection mode, the output clock signal is sent to the automatic amplitude control circuit to perform amplitude detection and compare the detection result with a preset amplitude, so as to adjust the tail current control codeword based on the comparison result, thereby adjusting the tail current. The frequency divider divides the output clock signal to obtain a feedback clock, and the automatic frequency band selection circuit generates a frequency band selection signal by comparing the frequencies of the feedback clock and the reference clock to configure the voltage-controlled variable capacitor array. In the calibration process, automatic amplitude control is performed first, and automatic frequency band selection is performed after the amplitude of the output clock signal stabilizes.

[0008] In one embodiment of the present invention, the temperature-compensated voltage generator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a first operational amplifier, a zero-temperature coefficient current source, a positive temperature coefficient current source, a reference voltage source, and a first 2-to-1 analog switch; the non-inverting input terminal of the first operational amplifier is connected to the reference voltage source, and the inverting input terminal is connected to the midpoint between the first resistor and the second resistor and clamped at the reference voltage; the first 2-to-1 analog switch selects the voltage at the end of the first resistor furthest from the midpoint or the voltage at the end of the second resistor furthest from the midpoint as the correction voltage output according to a polarity selection signal; wherein, the temperature-compensated current flowing through the first resistor and the second resistor is formed by mixing the zero-temperature coefficient current source and the positive temperature coefficient current source in proportions of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.

[0009] In one embodiment of the present invention, the slope of the correction voltage as a function of temperature is adjusted by changing the positive temperature coefficient current component injected into the first resistor and the second resistor by adjusting the width-to-length ratio of the second PMOS transistor and the second NMOS transistor; and the temperature compensation reference point of the correction voltage is changed by adjusting the size of the second PMOS transistor.

[0010] In one embodiment of the present invention, the temperature-robust broadband phase-locked loop circuit further includes a positive temperature coefficient current generating circuit, which includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and a third resistor; the width-to-length ratio of the seventh NMOS transistor is K times that of the sixth NMOS transistor, where K is a positive integer; the eighth PMOS transistor and the ninth PMOS transistor have the same dimensions so that the current flowing through the sixth NMOS transistor and the seventh NMOS transistor is equal; the gate-source voltage difference between the sixth NMOS transistor and the seventh NMOS transistor acts on the third resistor to generate a positive temperature coefficient current, which is then mirrored and output through the tenth PMOS transistor.

[0011] In one embodiment of the present invention, the temperature-compensated reference voltage generator includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fourth resistor, a fifth resistor, a bias current source, a positive temperature current source, a zero temperature current source, a second operational amplifier, and a second 2-to-1 analog switch; the non-inverting input terminal of the second operational amplifier is connected to a fixed voltage, and the inverting input terminal is connected to the midpoint between the fourth resistor and the fifth resistor and clamped to the fixed voltage; the second 2-to-1 analog switch selects the end of the fourth resistor furthest from the midpoint or the drain of the ninth NMOS transistor as the reference voltage output according to a polarity control signal; wherein the current flowing through the fourth resistor and the fifth resistor is a mirror image of the temperature-compensated mixed current of the branch of the eighth NMOS transistor.

[0012] In one embodiment of the present invention, the eighth NMOS transistor and the eleventh PMOS transistor constitute a low-dropout current mirror; the source of the eleventh PMOS transistor is connected to the power supply voltage, the gate is connected to the drain of the eighth NMOS transistor, and the drain is connected to the gate of the eighth NMOS transistor to introduce negative feedback, thereby stabilizing the drain voltage of the eighth NMOS transistor at the saturation drop.

[0013] In one embodiment of the present invention, the temperature-compensated tail current generating circuit includes a fifteenth PMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; a zero-temperature coefficient current and a positive temperature coefficient current are connected in parallel at the input terminal and then injected into the drain of the twelfth NMOS transistor; the gate of the thirteenth NMOS transistor is connected to the gate of the twelfth NMOS transistor to form a current mirror, and the drain of the thirteenth NMOS transistor is connected to the tail node of the voltage-controlled oscillator to provide the tail current.

[0014] This invention also provides a temperature compensation method applied to the temperature-robust broadband phase-locked loop circuit. The method includes: obtaining the current operating mode of the temperature-robust broadband phase-locked loop circuit, wherein the current operating mode includes an open-loop frequency band selection mode and a closed-loop phase-locked operating mode; if in the open-loop frequency band selection mode, a temperature-compensated correction voltage generator is connected to the voltage-controlled oscillator (VCO) to ensure that the adjustment voltage input to the control terminal of the VCO is within a preset range; if in the closed-loop phase-locked operating mode, the reference voltage is applied to the VCO's voltage-controlled capacitor to compensate for capacitor drift caused by temperature changes, and a positive temperature coefficient current is introduced into the tail current. The beneficial effects of this invention: The temperature-robust broadband phase-locked loop (PLL) circuit and method proposed in this invention greatly expands the operating temperature range of the PLL circuit through a triple temperature compensation synergy mechanism of open-loop correction voltage, closed-loop reference voltage, and closed-loop tail current. In the open-loop stage, sufficient voltage drift margin is reserved through the temperature-related correction voltage. In the closed-loop stage, capacitor temperature drift is compensated through the dynamic reference voltage, and the decrease in inductor quality factor is compensated through the positive temperature coefficient tail current. This achieves extremely high frequency stability and locking robustness across the entire temperature range, reducing the probability of PLL lockout under extreme temperatures. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the attached diagram: Figure 1 This is a schematic diagram of the overall structure of an optional temperature-robust broadband phase-locked loop circuit provided in an optional embodiment of the present invention; Figure 2 This is a schematic diagram of an optional circuit connection in open-loop frequency band selection mode provided in an optional embodiment of the present invention; Figure 3 This is a schematic diagram of an optional circuit connection in closed-loop phase-locked mode provided in an optional embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of an optional voltage-controlled oscillator provided in an optional embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit principle of an optional temperature-compensated correction voltage generation circuit provided in an optional embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit principle of an optional positive temperature current generating circuit provided in an optional embodiment of the present invention; Figure 7 This is a schematic diagram of the characteristic curve of the voltage-controlled capacitor as a function of temperature in an optional voltage-controlled oscillator provided in an optional embodiment of the present invention; Figure 8 This is a schematic diagram of the characteristic curve of an optional variable capacitor as a function of a reference voltage, provided in an optional embodiment of the present invention. Figure 9 This is a schematic diagram of an optional temperature-compensated reference voltage generation circuit provided in an optional embodiment of the present invention. Figure 10 This is a schematic diagram of the circuit principle of an optional voltage-controlled oscillator tail current temperature correction circuit provided in an optional embodiment of the present invention; Figure 11 This is a schematic flowchart of a temperature compensation method provided in an optional embodiment of the present invention. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0018] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0019] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0020] To facilitate understanding of the technical solutions provided in the embodiments of the present invention, the technical terms and custom concepts involved in the present invention will first be clearly defined and explained.

[0021] Temperature robustness refers to the ability of a circuit or system to maintain its core operating parameters (such as the output frequency, phase noise, loop bandwidth, and internal control voltage of the phase-locked loop) within a preset stable operating range when the external ambient temperature changes drastically (e.g., within a wide temperature range of -40℃ to 125℃), without experiencing severe performance degradation or functional failures such as loop lockout due to temperature drift.

[0022] A wideband phase-locked loop (PLL) is a type of loop that can output frequencies covering a wide range (e.g., spanning multiple octaves). to This is a phase-locked loop circuit for the local oscillation signal. Due to its extremely wide operating frequency band, the capacitor array and inductor of its internal voltage-controlled oscillator exhibit significant differences in temperature sensitivity at different frequency bands.

[0023] A low-headroom current mirror is a device that can operate at extremely low supply voltages (e.g., ...). to It operates normally under these conditions, and the drain-source voltage of its input or output transistor can be reduced to the saturation voltage drop. (usually) to An improved current mirror structure is described. This structure introduces an active feedback loop to decouple the transistor's drain voltage from its gate voltage, thereby greatly reducing the requirements on the transistor's drain voltage and making it suitable for low-voltage, low-power applications.

[0024] Positive temperature coefficient current (PTAT current) refers to current whose amplitude varies with absolute temperature. A current signal that changes proportionally. In semiconductor circuits, it is typically generated by applying the gate-source voltage difference of a bipolar transistor or a metal-oxide-semiconductor transistor operating at different current densities to a resistor.

[0025] Zero-temperature coefficient current (ZTAT current) refers to a current signal whose amplitude remains essentially constant within the designed operating temperature range and does not drift significantly with temperature changes. It is typically synthesized by superimposing a current with a positive temperature coefficient and a current with a negative temperature coefficient in a specific ratio.

[0026] Through in-depth research, the inventors discovered that in conventional inductor-capacitor (LC) type voltage-controlled oscillators, the inductors, variable capacitors, and fixed capacitors inside the resonant cavity all exhibit significant temperature coefficients. As the operating temperature increases, the carrier mobility of the semiconductor material decreases. A decrease in resistance leads to an increase in the on-resistance of the transistor; simultaneously, an increase in the resistivity of the metal coil of the integrated inductor leads to a decrease in the inductor's quality factor. The value decreased significantly. Inductance quality factor A decrease in the value will directly lead to a decrease in the equivalent parallel resistance of the resonant cavity. Reduced. Under the action of a constant tail current, the output signal swing of the voltage-controlled oscillator decreases. (It approximately satisfies) The phase noise level will decrease significantly, which will not only severely degrade the phase noise performance of the voltage-controlled oscillator, but may even cause the voltage-controlled oscillator to stop oscillating at extreme high temperatures.

[0027] Furthermore, due to the decrease in equivalent inductance and capacitance within the voltage-controlled oscillator (VCO) caused by increased temperature, the natural oscillation frequency of the VCO typically increases with rising temperature, assuming constant control voltage and tail current. In closed-loop locked state, to maintain a constant output frequency, the negative feedback loop of the phase-locked loop (PLL) must compensate for this frequency drift by adjusting the loop control voltage. Specifically, when the temperature increases, the loop control voltage must drift in a direction greater than the initial correction voltage; when the temperature decreases, the loop control voltage must drift in a direction less than the initial correction voltage. For high-performance broadband PLLs, due to the frequency control gain of the VCO… Typically designed to be small to reduce noise injection into the control lines, the adjustment range of the loop control voltage can easily exceed the power supply voltage when the operating temperature changes drastically over a wide temperature range. or below This leads to the phase-locked loop circuit losing its lock.

[0028] To address the aforementioned technical deficiencies, this invention provides a temperature-robust broadband phase-locked loop (PLL) circuit and method. The core inventive concept lies in introducing multiple, comprehensive temperature compensation mechanisms into the PLL. These include providing a temperature-dependent correction voltage in open-loop frequency band selection mode, providing a temperature-dynamically varying reference voltage applied to a portion of the voltage-controlled capacitor within the voltage-controlled oscillator (VCO) in closed-loop phase-locked mode, and introducing a positive temperature coefficient current into the tail current of the VCO. Through the coordinated operation of these three temperature compensation mechanisms throughout the open-loop correction and closed-loop locking processes, the problems of control voltage saturation and lockout due to temperature drift in conventional PLLs under wide-temperature operating environments, as well as signal swing attenuation at high temperatures, are completely solved. This achieves high-reliability locking across the entire temperature range and excellent phase noise performance.

[0029] The overall architecture of the temperature-robust broadband phase-locked loop circuit provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Please see Figure 1 This invention provides a temperature-robust broadband phase-locked loop circuit. The temperature-robust broadband phase-locked loop circuit includes: a frequency phase detector, a charge pump, a loop filter, a mode selector, a voltage-controlled oscillator (VCO), a frequency divider, a temperature-compensated correction voltage generator, a temperature-compensated reference voltage generator, and a temperature-compensated tail current generation circuit.

[0031] In one embodiment, a frequency phase detector is used to compare a reference clock. With feedback clock The phase difference is calculated and output as a phase difference signal. A charge pump connected to a frequency phase detector converts the phase difference signal into a current signal. A loop filter connected to the charge pump filters the current signal to generate the loop control voltage. The mode selector is connected to the loop filter. The voltage-controlled oscillator is connected to the mode selector to generate the output clock signal. The frequency divider connects the output of the voltage-controlled oscillator (VCO) and the feedback input of the frequency and phase detector, and is used to control the output clock signal. Frequency division is performed to generate a feedback clock. .

[0032] In one embodiment, a temperature-compensated correction voltage generator is connected to a mode selector for generating a temperature-dependent correction voltage. A temperature-compensated reference voltage generator is connected to a voltage-controlled oscillator to generate a reference voltage that dynamically varies with temperature. A temperature-compensated tail current generation circuit is connected to the voltage-controlled oscillator (VCO) to provide tail current to the VCO. .

[0033] In this embodiment, the temperature-robust broadband phase-locked loop circuit has an open-loop frequency band selection mode and a closed-loop phase-locked operating mode.

[0034] Please see Figure 2 If in open-loop frequency band selection mode (also known as calibration operating mode), the mode selector disconnects the closed-loop circuit. At this time, the temperature-compensated calibration voltage generator produces a temperature-dependent calibration voltage. The voltage-controlled oscillator (VCO) is input via a mode selector as its initial control voltage. This correction voltage... It exhibits temperature-dependent characteristics, automatically adjusting the initial control level based on the ambient temperature during calibration. This provides sufficient voltage drift margin for temperature changes after closed-loop operation, ensuring the regulated voltage at the control terminal of the voltage-controlled oscillator after closed-loop operation. It always stays within the preset voltage range, which basically avoids lockout caused by control voltage saturation.

[0035] Please see Figure 3 If in closed-loop phase-locked operation mode, the mode selector closes the closed-loop circuit, connecting the output of the loop filter to the control terminal of the voltage-controlled oscillator. At this time, the temperature-compensated reference voltage generator produces a reference voltage that dynamically changes with temperature. This is applied to part of the voltage-controlled capacitor of the voltage-controlled oscillator to compensate for capacitor drift caused by temperature changes in real time. Simultaneously, the temperature-compensated tail current generation circuit generates tail current... A positive temperature coefficient current is introduced to overcome the quality factor of the internal inductance of the voltage-controlled oscillator at high temperatures. The problem of reduced swing amplitude due to the decrease in value.

[0036] Through the triple synergistic mechanism of open-loop correction voltage temperature compensation, closed-loop reference voltage temperature compensation, and closed-loop tail current temperature compensation, this embodiment achieves extremely high frequency stability and lockout robustness across the entire temperature range.

[0037] The internal capacitor reuse structure of the voltage-controlled oscillator is described in detail below with reference to the accompanying drawings.

[0038] Please see Figure 4 In some alternative embodiments, the voltage-controlled oscillator includes an inductor and a fixed capacitor. Select switch The system consists of a cross-coupled positive feedback differential pair, a tail current source, and a voltage-controlled variable capacitor array composed of multiple voltage-controlled capacitors. The voltage-controlled variable capacitor array includes voltage-controlled variable capacitors... Each voltage-controlled variable capacitor has its first terminal connected to the power supply voltage VDD via an inductor, and its second terminal connected to a selector switch. .

[0039] Select switch According to the configuration signal Perform a three-way selection to selectively connect the second terminal to the reference voltage. Power supply voltage Or adjust the voltage .

[0040] Specifically, if you select a switch According to the configuration signal Select to connect to the reference voltage The corresponding voltage-controlled variable capacitor serves as the temperature correction compensation capacitor, and its capacitance value dynamically changes with the reference voltage. Continuous fine-tuning is performed to compensate for capacitor drift caused by temperature; if the selector switch is connected to the power supply voltage... The corresponding voltage-controlled variable capacitor acts as a regular fixed capacitor, providing the basic resonant capacitance value; if the selector switch is connected to the regulating voltage... The corresponding voltage-controlled variable capacitor is then connected to the closed-loop circuit for real-time phase locking. Since the parasitic resistance of the inductor, the variable capacitor, and the fixed capacitor constituting the VCO change with temperature, the voltage regulation... and tail current Under constant conditions, the oscillation frequency of the VCO increases with increasing temperature. In closed-loop phase-locked operation mode, the voltage is adjusted to maintain the output frequency. This will change with temperature; for example, when the temperature rises, the regulating voltage in Figure 3 will change. The voltage needs to be reduced to keep the phase-locked loop locked; as the temperature decreases, the adjustment voltage in Figure 3... The gain needs to be increased to keep the phase-locked loop locked. When the phase-locked loop is a high-performance broadband phase-locked loop, the VCO gain... k VCO Typically small. Therefore, when the temperature changes, the voltage is adjusted. It is easy to exceed the power supply voltage VDD or fall below 0, which can lead to the phase-locked loop losing lock.

[0041] In contrast, traditional phase-locked loops (PLLs) either lack temperature compensation circuitry or have overly complex compensation circuits. Overly complex compensation circuits not only significantly increase the chip's layout area but also severely degrade the phase noise performance of the voltage-controlled oscillator (VCO) due to the introduction of excessive parasitic capacitances. This embodiment addresses this by introducing a selection switch. and configuration signals This achieves the control of the same voltage-controlled variable capacitor array. This highly flexible capacitor configuration perfectly balances frequency band selection, temperature compensation, and closed-loop locking without adding an extra capacitor array, greatly saving chip area and significantly improving phase noise performance.

[0042] The calibration process in open-loop frequency band selection mode will be explained in detail below with reference to the accompanying diagram.

[0043] Please see Figure 2 In some alternative embodiments, the temperature-robust broadband phase-locked loop circuit further includes an automatic amplitude control circuit and an automatic band selection circuit. If in open-loop band selection mode, the output clock signal of the voltage-controlled oscillator... The signal is fed into the automatic amplitude control circuit. The automatic amplitude control circuit outputs the clock signal. Amplitude detection is performed and compared with a set amplitude. The tail current control codeword is adjusted using a binary search algorithm or a traversal algorithm. To change the tail current of the voltage-controlled oscillator The frequency divider outputs a clock signal. Frequency division is performed to obtain the feedback clock. Automatic band selection circuit 7: Comparison feedback clock and reference clock The frequency is used to generate a frequency band selection signal based on the comparison results. A voltage-controlled variable capacitor array is configured for the voltage-controlled oscillator. During the calibration process, automatic amplitude control is first performed; once the output signal amplitude stabilizes, the tail current control codeword is used. After latching, perform automatic frequency band selection.

[0044] In contrast, if amplitude control and frequency band selection are performed simultaneously during the calibration process, or if frequency band selection is performed first and then amplitude control is performed, the tail current will change. This directly affects the bias state of the cross-coupled transistors inside the voltage-controlled oscillator (VCO), thereby changing its parasitic capacitance. This leads to a fine-tuning of the VCO's oscillation frequency. Such a frequency adjustment can cause a shift in the selected frequency band and may even prevent the correction algorithm from converging.

[0045] To overcome this technical deficiency, this embodiment strictly limits the calibration timing: during the calibration process, automatic amplitude control is performed first, and automatic frequency band selection is performed only after the amplitude of the output signal stabilizes. This timing control method completely eliminates the secondary interference of tail current fine-tuning on frequency band selection, ensuring that the open-loop calibration process can converge quickly and with high precision, laying an extremely stable initial state for subsequent closed-loop locking.

[0046] The specific circuit structure of the temperature-compensated voltage generator is described in detail below with reference to the accompanying drawings.

[0047] Please see Figure 5 In some alternative embodiments, the temperature-compensated voltage generator includes a first PMOS transistor. Second PMOS transistor Third PMOS transistor First NMOS transistor Second NMOS transistor Third NMOS transistor Fourth NMOS transistor First resistor Second resistor First operational amplifier 1. Zero temperature coefficient current source, positive temperature coefficient current source, reference voltage source, and first / second dual-choice analog switch 1.

[0048] In one embodiment, the first operational amplifier The non-inverting input terminal is connected to a reference voltage source. The inverting input terminal is connected to the first resistor. With the second resistor The intermediate node is clamped to the reference voltage. First and second selector analog switch Signal selection based on polarity Select the first resistor Voltage at the end furthest from the intermediate node, or the second resistor The voltage at the end furthest from the intermediate node is used as the correction voltage. Output.

[0049] Among them, the current flows through the first resistor Second resistor Temperature compensation current A zero-temperature-coefficient current source and a positive-temperature-coefficient current source pass through the first PMOS transistor. Second PMOS transistor Third PMOS transistor and the first NMOS transistor Second NMOS transistor Third NMOS transistor Fourth NMOS transistor It is a mixture in a specific ratio. Specifically, the first PMOS transistor... The gate and drain of the transistor are connected together, and then connected to the second PMOS transistor. The gate of the first PMOS transistor The source of the second PMOS transistor The source and the third PMOS transistor The source is connected to the power supply voltage, the first PMOS transistor The drain is connected to a zero temperature coefficient current source, the second PMOS transistor The drains of the two transistors are connected to the second NMOS transistor. The drain of the third NMOS transistor The drain of the second NMOS transistor; The gates are respectively connected to a positive temperature coefficient current source and the first NMOS transistor. The gate and the first NMOS transistor The source; the first NMOS transistor The source of the second NMOS transistor The source of the third NMOS transistor The source and the fourth NMOS transistor The sources of all three are grounded; the third NMOS transistor The drain and gate are connected, and then connected to the fourth NMOS transistor. The gate of the fourth NMOS transistor; The drain electrode is the second resistor. One end and the first two-to-one analog switch One of the input terminals, the second resistor The other end is connected to the first resistor One end is connected, and this connection point is the midpoint connecting the two resistors. The first resistor... The other end is connected to the third PMOS transistor. The drain and the first two-to-one analog switch The other input terminal is a two-to-one analog switch. Control terminal polarity selection signal First operational amplifier The non-inverting input is connected to a reference voltage source, and the inverting input is connected to the first resistor. Second resistor The intermediate node, with the output terminal connected to the third PMOS transistor. The gate.

[0050] In one embodiment, if the first two-to-one analog switch Signal selection based on polarity Select the first resistor The voltage at the end furthest from the intermediate node is affected by the temperature-compensated current. The output correction voltage, flowing into this terminal, satisfies:

[0051] If the first or second choice analog switch MUX1 Polarity is selected by choosing the second resistor R1. I flows out from this terminal, and the output correction voltage satisfies:

[0052] Due to current Having a positive temperature coefficient, this embodiment can easily generate correction voltages with positive and negative temperature coefficients by switching the polarity of the first two-to-one analog switch MUX1. This perfectly adapts to the temperature compensation requirements of the initial voltage during the open-loop correction stage for different frequency bands.

[0053] In some alternative embodiments, by adjusting the second PMOS transistor Second NMOS transistor The aspect ratio is adjusted to change the injected first resistor. Second resistor The positive temperature coefficient current component is used to adjust the correction voltage. The slope of the temperature change. Simultaneously, by adjusting the second PMOS transistor... The size of the voltage is used to change the correction voltage. Temperature compensation reference point.

[0054] Specifically, by adjusting the second PMOS transistor Second NMOS transistor The aspect ratio can be precisely adjusted to change the injected first resistor. Second resistor Positive temperature coefficient current The magnitude of the component. When the second NMOS transistor When the aspect ratio increases, the positive temperature coefficient current component of the injected resistor network increases, resulting in a higher output correction voltage. The slope of the temperature change (i.e., temperature sensitivity) increases; conversely, when the second NMOS transistor is reduced... When the aspect ratio is 5, the correction voltage is 10. The slope decreases with temperature change.

[0055] In addition, by adjusting the second PMOS transistor The size can change the correction voltage. Temperature compensation reference point. When the second PMOS transistor... As the size increases, the compensation reference temperature rises; when the second PMOS transistor... As the size decreases, the temperature of the compensation reference point decreases.

[0056] In contrast, traditional correction voltage generation circuits, once fabricated, have a fixed temperature coefficient and reference point, making them unable to adapt to the significant differences in temperature sensitivity of broadband phase-locked loops operating at different frequency bands. This embodiment, by fine-tuning the physical dimensions of the aforementioned transistors, enables the correction voltage generator to possess strong programmability and wide adaptability, providing the most accurate temperature compensation curves for different operating frequency bands, significantly improving the overall robustness of the broadband phase-locked loop.

[0057] In one embodiment, it is generally relatively easy to obtain a zero temperature coefficient current I within a broadband phase-locked loop circuit. ZTAT Inside the circuit, there is usually a bandgap reference source that can generate a voltage that remains constant with temperature. This voltage can then be used to easily generate a temperature-independent current I with zero temperature coefficient. ZTAT .

[0058] The specific circuit structure of the positive temperature coefficient current generating circuit will be described in detail below with reference to the accompanying drawings.

[0059] Please see Figure 6 In some alternative embodiments, the temperature-robust broadband phase-locked loop circuit further includes a positive temperature coefficient current generation circuit. The positive temperature coefficient current generation circuit includes a fifth NMOS transistor. The sixth NMOS transistor 7th NMOS transistor Fourth PMOS transistor Fifth PMOS transistor The sixth PMOS transistor 7th PMOS transistor Eighth PMOS transistor Ninth PMOS transistor 10th PMOS transistor and the third resistor Fifth NMOS transistor The source of the sixth NMOS transistor The source and the seventh NMOS transistor The source is grounded, and the fifth NMOS transistor The gates are connected to one end of the third resistor R2 and the sixth NMOS transistor, respectively. The gate of the sixth NMOS transistor; The drains are connected to the other end of the third resistor R2 and the seventh NMOS transistor, respectively. The gate of the fifth NMOS transistor; The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor; the fourth PMOS transistor After the gate and drain of the first transistor are shorted, they are connected to the fifth PMOS transistor. The gate of the sixth PMOS transistor The gate and the seventh PMOS transistor The gate of the fourth PMOS transistor; The source of the eighth PMOS transistor The source of the ninth PMOS transistor The source and the tenth PMOS transistor The sources of the five PMOS transistors are connected to the power supply voltage respectively; The drain of the sixth NMOS transistor is connected. The gate of the fifth PMOS transistor The source and the eighth PMOS transistor Drain connection; sixth PMOS transistor The source and the ninth PMOS transistor The drain connection of the seventh PMOS transistor The source and the tenth PMOS transistor Drain connection; Eighth PMOS transistor The gates of the transistors are respectively connected to the ninth PMOS transistor. The gate of the tenth PMOS transistor Gate of the seventh NMOS transistor The drain and the sixth PMOS transistor The drain of the seventh NMOS transistor. The drain is also connected to the sixth PMOS transistor. Drain connection; seventh PMOS transistor The drain is used as the output terminal to output a positive temperature coefficient current. .

[0060] Seventh NMOS transistor The aspect ratio is that of the sixth NMOS transistor. of The eighth PMOS transistor (K is a positive integer) and the ninth PMOS transistor The dimensions are the same, so that the current flows through the sixth NMOS transistor. and the seventh NMOS transistor The currents are equal. The sixth NMOS transistor and the seventh NMOS transistor The gate-source voltage difference acts on the third resistor To generate positive temperature coefficient current And through the tenth PMOS transistor Mirror output.

[0061] Specifically, the width-to-length ratio of NMOS transistor MN6 is K times that of MN5, and MP7 and MP8 have the same dimensions. Because MP7 and MP8 have the same dimensions, the current flowing through MP7 / MN5 and MP8 / MN6 is the same. Therefore:

[0062]

[0063]

[0064] Therefore, we get:

[0065] in, This is the gate-source voltage of the sixth NMOS transistor. is the gate-source voltage of the seventh NMOS transistor. is the aspect ratio of the transistor. This is the capacitance per unit area of ​​the transistor's gate oxide layer. Due to the carrier velocity... ,so T represents absolute temperature (usually in Kelvin), and m is the temperature mobility index (a dimensionless constant, typically around 1.5–2.0). Therefore, the current flowing through resistor R2 is approximately a positive temperature coefficient current. Thus, the current flowing through the tenth PMOS transistor... Mirror output positive temperature coefficient current It exhibits extremely excellent and linear positive temperature coefficient characteristics, providing a highly reliable temperature-compensated current reference for the entire phase-locked loop circuit.

[0066] To further reduce the temperature robustness of the phase-locked loop (PLL), this patent proposes a second temperature correction scheme. The voltage-controlled capacitor of the VCO is connected to a reference voltage, vref. When the VCO changes with temperature, vref also changes with temperature, thereby altering the size of the pneumatic capacitor connected to vref and changing the oscillation frequency of the VCO.

[0067] Figure 7 shows the temperature-dependent capacitance (VCO) curve in the VCO. As the temperature increases, the capacitances Ctune, Cref, and CVDD connected to the VCO gradually decrease, causing an increase in the VCO oscillation frequency. Under this condition, the loop voltage decreases under loop control, which can easily lead to lockout.

[0068] Figure 8 shows the curve of the voltage-controlled capacitor as a function of voltage. As can be seen from the figure, the capacitance gradually decreases as the voltage increases.

[0069] Therefore, to prevent unlocking caused by temperature changes, the capacitance change due to temperature can be overcome by altering the VCO's reference voltage, Vref. When the temperature rises, the capacitance decreases; therefore, the reference voltage Vref can be decreased, thereby increasing Cref; thus, the total capacitance can be kept constant. Conversely, when the temperature decreases, the reference voltage Vref can be increased, keeping the total capacitance constant.

[0070] The specific circuit structure of the temperature-compensated reference voltage generator is described in detail below with reference to the accompanying drawings.

[0071] Please see Figure 9 In some alternative embodiments, the temperature-compensated reference voltage generator includes an eighth NMOS transistor. Ninth NMOS transistor The tenth NMOS transistor Eleventh NMOS transistor Eleventh PMOS transistor 12th PMOS transistor Thirteenth PMOS transistor Fourteenth PMOS transistor Fourth resistor Fifth resistor Bias current source Positive temperature coefficient current source, zero temperature coefficient current source, second operational amplifier 2 and the second two-to-one analog switch Specifically, the tenth NMOS transistor The source of the eleventh NMOS transistor The source, the eleventh PMOS transistor The drain of the eighth NMOS transistor The source and the ninth NMOS transistor The sources of the transistors are grounded; the tenth NMOS transistor After shorting the gate and drain, they are connected to the eleventh NMOS transistor. The gate and positive temperature coefficient current source, the eleventh NMOS transistor The drains of the transistors are connected to the eighth NMOS transistor. The drain of the eleventh PMOS transistor MP10, the gate of the eleventh PMOS transistor MP10, and the drain of the thirteenth PMOS transistor are connected to each other. The gate and drain of the twelfth PMOS transistor MP11 are shorted and then connected to the gate of the thirteenth PMOS transistor MP12 and a zero-temperature coefficient current source, respectively. The sources of the twelfth PMOS transistor MP11, the thirteenth PMOS transistor MP12, and the fourteenth PMOS transistor MP13 are connected to the power supply voltage. The eleventh PMOS transistor... The source of each is connected to a bias voltage and the eighth NMOS transistor, respectively. The gate and the ninth NMOS transistor The gate of the ninth NMOS transistor. The drain of the first PMOS transistor is connected to one end of the fifth resistor R4 and one of the input terminals of the second 2-to-1 analog switch MUX2. The node connecting the other end of the fifth resistor R4 and one end of the fourth resistor R3 is the intermediate node of the two resistor connections, which is also connected to the inverting input terminal of the second operational amplifier A2. The non-inverting input terminal of the second operational amplifier A2 is connected to a reference voltage source, and its output terminal is connected to the gate of the fourteenth PMOS transistor MP13. The drain of the fourteenth PMOS transistor MP13 is connected to the other end of the fourth resistor R3 and the other input terminal of the second 2-to-1 analog switch MUX2. The output terminal of the second 2-to-1 analog switch MUX2 outputs a reference voltage. .

[0072] For example, the second operational amplifier The non-inverting input of 2 is connected to a fixed voltage. The inverting input terminal is connected to the fourth resistor. With the fifth resistor The intermediate node is clamped to a fixed voltage. Second-to-second analog switch Select the fourth resistor based on the polarity control signal polarity. The end furthest from the middle node, or the ninth NMOS transistor. The drain is used as the reference voltage. Output. The current flows through the fourth resistor. and the fifth resistor current Mirror image from the eighth NMOS transistor Temperature-compensated mixed current of the branch.

[0073] Specifically, if the second two-to-one analog switch Select the fourth resistor The end furthest from the corresponding intermediate node, due to the current The input voltage flows into this terminal, and the output reference voltage satisfies:

[0074] If the second option is an analog switch Choosing the drain of the ninth NMOS transistor, due to the current... The reference voltage flowing out from this terminal satisfies:

[0075] By properly configuring the ratio of the positive temperature coefficient current and the zero temperature coefficient current at the input terminal, the current can have a specific temperature coefficient, thereby achieving precise reverse compensation of the reference voltage as the temperature rises and falls, and dynamically maintaining the constant total capacitance inside the voltage-controlled oscillator.

[0076] In some alternative embodiments, the eighth NMOS transistor and the eleventh PMOS transistor This forms a low-dropout current mirror. Eleventh PMOS transistor. The source is connected to the power supply voltage, and the gate is connected to the eighth NMOS transistor. The drain of the transistor is connected to the eighth NMOS transistor. The gate of the eighth NMOS transistor is used to introduce negative feedback, thereby enabling the eighth NMOS transistor to... The drain voltage stabilizes at the saturation voltage drop. saturation pressure drop The range is to .

[0077] In contrast, in a traditional diode connected current mirror, the drain and gate of the input diode are directly connected, forcing the drain voltage to equal the gate-source voltage. This requires a voltage greater than a threshold voltage in low-voltage designs. (usually) This greatly limits the reduction of power supply voltage.

[0078] This embodiment introduces an eleventh PMOS transistor. The active feedback effect will enable the eighth NMOS transistor to... The drain voltage and gate voltage are decoupled, making the eighth NMOS transistor... The drain voltage can operate at a minimum of the saturation voltage drop. (usually only) This low-dropout design significantly reduces the circuit's headroom requirements, allowing the entire reference voltage generator to operate within a safe range. It can maintain extremely high current mirror accuracy even in ultra-low voltage environments, making it very suitable for low-voltage, low-power integrated circuit applications.

[0079] The specific circuit structure of the temperature-compensated tail current generation circuit is described in detail below with reference to the attached diagram.

[0080] Please see Figure 10 In some alternative embodiments, the temperature-compensated tail current generation circuit includes a fifteenth PMOS transistor. 12th NMOS transistor and the thirteenth NMOS transistor Specifically, the source of the twelfth NMOS transistor MN11, the source of the thirteenth NMOS transistor MN12, and the drain of the fifteenth PMOS transistor MP14 are grounded respectively; the gate of the twelfth NMOS transistor MN11 is connected to the drain of the fifteenth PMOS transistor and the bias voltage I. BIAS And the gate of the thirteenth NMOS transistor MN12; the gate of the fifteenth PMOS transistor MP14 is connected to the drain of the twelfth NMOS transistor MN11 and the zero temperature coefficient current, respectively. and positive temperature coefficient current The drain of the thirteenth NMOS transistor MN12 serves as the output terminal to provide the tail current. .

[0081] In one embodiment, zero temperature coefficient current With positive temperature coefficient current After being added in parallel at the input terminals, the twelfth NMOS transistor is injected. The drain of 54. The thirteenth NMOS transistor. The gate of 55 is connected to the twelfth NMOS transistor. The gate of the 54 is used to form a current mirror, the thirteenth NMOS transistor. The drain of the 55 is connected to the tail node of the voltage-controlled oscillator to provide tail current. .

[0082] In contrast, traditional voltage-controlled oscillators (VCOs) use a constant tail current source. As the operating temperature rises, the parasitic resistance of the inductor inside the chip increases, thus affecting the inductor's quality factor. The value will decrease significantly, leading to a reduction in the equivalent parallel resistance of the resonant cavity. Under the influence of a constant tail current, the output signal swing of the voltage-controlled oscillator will decrease dramatically, resulting in a sharp drift in the oscillation frequency or even oscillation stopping.

[0083] This embodiment uses a positive temperature coefficient current. Introducing tail current When the operating temperature rises, due to The current increases significantly, and the total current injected into the twelfth NMOS transistor MN11 increases. Through the current mirror effect, the tail current output by the thirteenth NMOS transistor MN12 increases. It automatically increases proportionally with rising temperature. The increase in tail current perfectly compensates for the inductance. The loss caused by the decrease in value maintains the constant swing of the voltage-controlled oscillator output signal, thereby significantly improving the temperature robustness of the phase-locked loop.

[0084] In some alternative embodiments, the thirteenth NMOS transistor It is a size-adjustable NMOS transistor, whose gate is connected to the twelfth NMOS transistor via a switch array. The gate of the thirteenth NMOS transistor The effective width-to-length ratio is dynamically adjusted based on the control code output by the automatic amplitude control circuit. If the operating temperature rises, the twelfth NMOS transistor is injected. Positive temperature coefficient current of drain Increase the current to allow the thirteenth NMOS transistor to pass through the current mirror. Output tail current The VCO current automatically increases as the temperature rises, thus overcoming the problem of reduced swing amplitude caused by increased temperature.

[0085] This embodiment organically and deeply integrates digital calibration algorithms with analog temperature compensation circuits: in the open-loop calibration stage, the automatic amplitude control circuit determines the optimal control codeword through a binary search algorithm. Thus, the thirteenth NMOS transistor was coarsely adjusted. The effective size lays the foundation for the tail current magnitude; during the closed-loop operation phase, the control codeword... Maintain latch-up; if the operating temperature rises during this time, inject into the twelfth NMOS transistor. Positive temperature coefficient current of drain Automatically increased, through the action of a current mirror, causing the thirteenth NMOS transistor to... Output tail current The circuit continuously increases the analog amplitude based on a predetermined baseline level. This dual control mechanism, combining digital coarse adjustment and analog fine adjustment, ensures the consistency of the initial amplitude of the phase-locked loop (PLL) across different frequency bands and achieves real-time, smooth compensation for temperature changes during closed-loop operation, greatly improving the reliability of the circuit.

[0086] Please see Figure 11 The present invention provides a temperature compensation method applied to a temperature-robust broadband phase-locked loop circuit as described above. The method includes: Step S1100: Obtain the current operating mode of the temperature-robust broadband phase-locked loop circuit, wherein the current operating mode includes open-loop frequency band selection mode and closed-loop phase-locked operating mode.

[0087] Step S1110: If in open-loop frequency band selection mode, the temperature-compensated voltage generator is connected to the voltage-controlled oscillator so that the adjustment voltage at the control terminal of the voltage-controlled oscillator is within the preset range.

[0088] In step S1120, if the open-loop frequency band selection mode is in effect, the temperature-compensated voltage generator is connected to the voltage-controlled oscillator so that the adjustment voltage at the control terminal of the voltage-controlled oscillator is within a preset range.

[0089] The specific execution process of the method has been described in detail in the aforementioned circuit embodiments, and will not be repeated here.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A temperature-robust broadband phase-locked loop circuit, characterized in that, include: A frequency phase detector is used to compare the phase difference between a reference clock and a feedback clock and output a phase difference signal. A charge pump is used to convert the phase difference signal into a current signal; A loop filter is used to filter the current signal to generate a loop control voltage; A mode selector is used to selectively output the loop control voltage or the correction voltage; A voltage-controlled oscillator is used to generate an output clock signal based on the output of the mode selector; A frequency divider is used to divide the output clock signal to generate the feedback clock; A temperature-compensated correction voltage generator is used to generate the temperature-dependent correction voltage; A temperature-compensated reference voltage generator is used to generate a reference voltage that dynamically changes with temperature. as well as, A temperature-compensated tail current generation circuit is used to provide tail current for the voltage-controlled oscillator; The broadband phase-locked loop circuit has an open-loop frequency band selection mode and a closed-loop phase-locked operating mode. When in the open-loop frequency band selection mode, the temperature-compensated voltage generator is connected to the voltage-controlled oscillator so that the adjustment voltage input to the control terminal of the voltage-controlled oscillator is within a preset range. If the closed-loop phase-locked operating mode is in effect, the reference voltage is applied to part of the voltage-controlled capacitor of the voltage-controlled oscillator to compensate for capacitor drift caused by temperature changes, and a positive temperature coefficient current is introduced into the tail current.

2. The temperature-robust broadband phase-locked loop circuit according to claim 1, characterized in that, The voltage-controlled oscillator includes an inductor, a fixed capacitor, a selection switch, a cross-coupled positive feedback differential pair, a tail current source, and a voltage-controlled variable capacitor array composed of multiple voltage-controlled capacitors. Each voltage-controlled capacitor has its first terminal connected to the power supply voltage via an inductor, and its second terminal connected to the selection switch. The selection switch performs a three-way selection based on a configuration signal, selectively connecting the second terminal to the reference voltage, the power supply voltage, or the regulated voltage. If the selection switch connects to the reference voltage, the corresponding voltage-controlled capacitor acts as a temperature correction compensation capacitor. If the selection switch connects to the power supply voltage, the corresponding voltage-controlled capacitor acts as a fixed capacitor. If the selection switch connects to the regulated voltage, the corresponding voltage-controlled capacitor is connected to the closed-loop circuit.

3. The temperature-robust broadband phase-locked loop circuit according to claim 2, characterized in that, The temperature-robust broadband phase-locked loop circuit also includes an automatic amplitude control circuit and an automatic frequency band selection circuit. If the open-loop frequency band selection mode is in effect, the output clock signal is sent to the automatic amplitude control circuit to perform amplitude detection and compare the detection result with the preset amplitude, so as to adjust the tail current control code based on the comparison result, thereby adjusting the tail current. The frequency divider divides the output clock signal to obtain a feedback clock. The automatic frequency band selection circuit generates a frequency band selection signal to configure the voltage-controlled variable capacitor array by comparing the frequencies of the feedback clock and the reference clock. During the calibration process, automatic amplitude control is performed first, and automatic frequency band selection is performed after the amplitude of the output clock signal stabilizes.

4. The temperature-robust broadband phase-locked loop circuit according to claim 1, characterized in that, The temperature-compensated voltage generator includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a first operational amplifier, a zero temperature coefficient current source, a positive temperature coefficient current source, a reference voltage source, and a first two-to-one analog switch. The non-inverting input of the first operational amplifier is connected to the reference voltage source, and the inverting input is connected to the midpoint between the first resistor and the second resistor and clamped to the reference voltage. The first two-to-one analog switch selects the voltage at the end of the first resistor furthest from the midpoint or the voltage at the end of the second resistor furthest from the midpoint as the correction voltage output according to the polarity selection signal. The temperature-compensated current flowing through the first resistor and the second resistor is formed by mixing the zero temperature coefficient current source and the positive temperature coefficient current source through the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor in a certain proportion.

5. The temperature-robust broadband phase-locked loop circuit according to claim 4, characterized in that, By adjusting the width-to-length ratio of the second PMOS transistor and the second NMOS transistor, the positive temperature coefficient current component injected into the first resistor and the second resistor is changed, thereby adjusting the slope of the correction voltage as a function of temperature; by adjusting the size of the second PMOS transistor, the temperature compensation reference point of the correction voltage is changed.

6. The temperature-robust broadband phase-locked loop circuit according to claim 1, characterized in that, The temperature-robust broadband phase-locked loop circuit further includes a positive temperature coefficient current generation circuit, which includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and a third resistor. The width-to-length ratio of the seventh NMOS transistor is K times that of the sixth NMOS transistor, where K is a positive integer. The eighth and ninth PMOS transistors have the same dimensions so that the current flowing through the sixth and seventh NMOS transistors is equal. The gate-source voltage difference between the sixth and seventh NMOS transistors acts on the third resistor to generate a positive temperature coefficient current, which is then mirrored and output through the tenth PMOS transistor.

7. The temperature-robust broadband phase-locked loop circuit according to claim 1, characterized in that, The temperature-compensated reference voltage generator includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fourth resistor, a fifth resistor, a bias current source, a positive temperature current source, a zero temperature current source, a second operational amplifier, and a second 2-to-1 analog switch. The non-inverting input of the second operational amplifier is connected to a fixed voltage, and the inverting input is connected to the midpoint between the fourth and fifth resistors and clamped to the fixed voltage. The second 2-to-1 analog switch selects the end of the fourth resistor furthest from the midpoint or the drain of the ninth NMOS transistor as the reference voltage output according to a polarity control signal. The current flowing through the fourth and fifth resistors is a mirror image of the temperature-compensated mixed current from the branch of the eighth NMOS transistor.

8. The temperature-robust broadband phase-locked loop circuit according to claim 7, characterized in that, The eighth NMOS transistor and the eleventh PMOS transistor form a low-dropout current mirror; the source of the eleventh PMOS transistor is connected to the power supply voltage, the gate is connected to the drain of the eighth NMOS transistor, and the drain is connected to the gate of the eighth NMOS transistor to introduce negative feedback, thereby stabilizing the drain voltage of the eighth NMOS transistor at the saturation drop.

9. The temperature-robust broadband phase-locked loop circuit according to claim 1, characterized in that, The temperature-compensated tail current generation circuit includes a tenth PMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; the zero temperature coefficient current and the positive temperature coefficient current are connected in parallel at the input terminal and then injected into the drain of the twelfth NMOS transistor; the gate of the thirteenth NMOS transistor is connected to the gate of the twelfth NMOS transistor to form a current mirror, and the drain of the thirteenth NMOS transistor is connected to the tail node of the voltage-controlled oscillator to provide the tail current.

10. A temperature compensation method, characterized in that, The method, applied to a temperature-robust broadband phase-locked loop circuit as described in any one of claims 1 to 9, comprises: Obtain the current operating mode of the temperature-robust broadband phase-locked loop circuit, wherein the current operating mode includes an open-loop frequency band selection mode and a closed-loop phase-locked operating mode; If the open-loop frequency band selection mode is in effect, the temperature-compensated voltage generator is connected to the voltage-controlled oscillator so that the adjustment voltage input to the control terminal of the voltage-controlled oscillator is within a preset range. If the closed-loop phase-locked operating mode is in effect, the reference voltage is applied to part of the voltage-controlled capacitor of the voltage-controlled oscillator to compensate for capacitor drift caused by temperature changes, and a positive temperature coefficient current is introduced into the tail current.

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