A fast-locking fractional-frequency division all-digital phase-locked loop

Abstract

This invention discloses a fast-locking fractional-frequency division all-digital phase-locked loop (PLL). The PLL comprises: a digitally controlled oscillator (DCO), a variable-phase accumulator (VPA), a reference-phase accumulator (RPA), a digital phase detector (DPD), a digital-time converter (DTC), a time-to-digital converter (TDC), a digital loop filter (DLF), a Delta-sigma modulator (DSM), a frequency modulation data generation module, a delay module, a first adder, and a second adder. This invention achieves decoupling of speed and noise performance by simultaneously injecting data into the NTW and FCW nodes, and features extremely low digital overhead and a simple structure requiring no complex switching.

Description

Technical Field

[0001] This invention relates to a fully digital phase-locked loop, specifically a fast-locking fractional-frequency fully digital phase-locked loop. Background Technology

[0002] An all-digital phase-locked loop (ADPLL) is a closed-loop negative feedback system where all module interfaces are digital signals. With its excellent process compatibility, flexible loop parameter programmability, and architecture that facilitates system integration, it has become a core frequency synthesis solution for modern wireless communication systems. From the ultra-low jitter local oscillator required for 5G millimeter-wave communication to low-power frequency synthesis in IoT devices, ADPLL not only provides high-precision clock signals, but its digital nature also makes it easier to implement complex calibration algorithms and dynamic performance optimization. This meets the fundamental requirements of advanced systems such as software-defined radio for frequency agility and multi-mode operation, making it a key technological foundation for the performance evolution of communication equipment.

[0003] As communication technology evolves towards higher spectral efficiency and energy efficiency, the dynamic performance of ADPLLs is being placed on systems with unprecedented demands. In scenarios involving rapid time-slot switching such as carrier aggregation, frequency hopping, and dynamic spectrum sharing, the transmit channel needs to complete frequency switching and phase stabilization within microseconds or even nanoseconds. Traditional locking processes have become a bottleneck limiting system throughput efficiency and real-time response capabilities. Especially in high-efficiency architectures such as polarized transmitters, the locking speed of the ADPLL directly determines the synchronization accuracy of the power amplifier envelope path and phase path, thus affecting the linearity and efficiency of the entire transmit link. Therefore, achieving fast and accurate frequency locking is a key technical indicator for ensuring the functional integrity of modern communication systems.

[0004] There is a direct contradiction between the locking time and the loop bandwidth of a phase-locked loop: a fast locking time requires a wide loop bandwidth, while excellent in-band phase noise requires a narrow loop bandwidth. At present, in order to achieve fast locking of a fully digital phase-locked loop, a number of technical solutions have been proposed: (1) Variable loop bandwidth method: by using a wide bandwidth during the acquisition stage and switching to a narrow bandwidth after locking, the locking is accelerated. Its advantages are simple implementation and low digital overhead, but the improvement in locking time is limited, and the timing of bandwidth switching is difficult to control precisely, which can easily introduce phase disturbance (Research and design of fast locking fully digital phase-locked loop based on piecewise tuned codeword estimation [D]. South China University of Technology, 2022); (2) Frequency preset or lookup table method: by pre-measuring and storing the DCO tuning curve, the DCO is directly set near the target frequency before locking, which can significantly reduce the initial frequency difference. However, this method is severely affected by PVT changes and requires frequent calibration. Moreover, the nonlinearity of DCO will lead to the preset Limited accuracy (Analysis and design of fast locking all-digital phase-locked loop [D]. Tsinghua University, 2011); (3) Auxiliary locking method (such as FLL auxiliary) adds an independent frequency locking loop to quickly bring the frequency closer, and then the main PLL locks the phase. It has a significant effect on frequency hopping with large frequency difference, but it will increase the additional loop and switching logic, increase the system complexity, and the smooth switching of the main and auxiliary loops is challenging; (4) Digital algorithm optimization method uses algorithms such as least squares or gradient descent to directly calculate the DCO control word through a small number of frequency measurements. The digital implementation is flexible, but the algorithm requires multiple measurement and calculation cycles, and has high requirements for frequency measurement accuracy and DCO gain linearity (Research on low-noise fast locking fractional frequency division DPLL [D]. Dalian University of Technology, 2023).

[0005] In summary, existing ADPLL fast locking methods are still inherently limited by the finite response speed of the closed loop, making it difficult to achieve single-cycle frequency jumps while maintaining low jitter.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a fast-locking fractional-frequency division fully digital phase-locked loop, which solves the contradiction between the locking speed and phase noise in the prior art. This invention achieves decoupling of speed and noise performance by simultaneously injecting data into the NTW node and FCW node, and has extremely low digital overhead and a simple structure that does not require complex switching.

[0008] To achieve the above objectives, this invention provides a fast-locking fractional-frequency division all-digital phase-locked loop (PLL). This PLL comprises: a digitally controlled oscillator (DCO), a variable phase accumulator (VPA), a reference phase accumulator (RPA), a digital phase detector (DPD), a digital time converter (DTC), a time-to-digital converter (TDC), a digital loop filter (DLF), a Delta-sigma modulator (DSM), a frequency modulation data generation module, a delay module, a first adder, and a second adder. The DCO, VPA, DPD, DTC, TDC, DLF, DSM, first adder, and DSM are sequentially connected, and the output of the DSM is connected to the fine-tuning section of the DCO, forming a loop. The second adder, RPA, and... The digital phase detectors (DPDs) are connected in sequence; the output of the frequency modulation data generation module is connected to both the delay module and the second adder, and the output of the delay module is connected to the first adder; the output of the digitally controlled oscillator (DCO) is also connected to the time-to-digital converter (TDC); the frequency modulation data generation module is used to generate frequency modulation data, which is divided into two paths and simultaneously injected with frequency control information into the frequency control word (FCW) node and the digital tuning word (NTW) node; the frequency control word (FCW) is input to the second adder, added to one path of frequency modulation data in the second adder, and then sent to the reference phase accumulator (RPA); the other path of frequency modulation data is input to the delay module, and after being delayed and calibrated by the delay module, it is injected into the digital tuning word (NTW) node, added to the digital tuning word (NTW) output by the digital loop filter (DLF) in the first adder, and then sent to the Delta-sigma modulator (DSM).

[0009] Preferably, the numerically controlled oscillator (DCO) is used to generate a high-frequency output clock CKV as a feedback clock; the variable phase accumulator (VPA) is used to obtain the integer phase of the high-frequency output clock CKV. and integer phase The digital phase detector (DPD) is input; the reference phase accumulator (RPA) is used to accumulate the reference phase to obtain the accumulated reference phase. The digital phase detector (DPD) is used to determine the integer phase. and accumulated reference phase Obtain the fractional phase to be compensated and the fractional phase value to be compensated ε The input digital time converter (DTC) will convert the input fractional phase value. εThe input reference clock REF is converted into a delay and then delayed. The time-to-digital converter TDC compares the phase of the delayed reference clock REF_DLY with the feedback clock CKV. The digital loop filter DLF is used to filter and generate a digital control word. This word is added to the frequency modulation data after delay calibration by the second adder, and then the digital tuning word NTW is jittered by the Delta-sigma modulator DSM to regulate the output frequency of the digitally controlled oscillator DCO, thereby achieving frequency locking and phase locking.

[0010] More preferably, the reference phase includes an integer phase and a fractional phase.

[0011] Preferably, the method used by the digital time converter (DTC) to perform the delay includes gain calibration.

[0012] More preferably, the gain calibration uses the LMS algorithm to iteratively adjust the gain error.

[0013] Preferably, the time-to-digital converter (TDC) is used to compare whether the rising edges of the delayed reference clock REF_DLY and the feedback clock CKV are aligned.

[0014] More preferably, the time-to-digital converter (TDC) includes: a TDC main circuit and a decoder, wherein the decoder is used to decode the thermometer code output by the TDC main circuit and convert it into binary code.

[0015] Preferably, the digital loop filter (DLF) is a proportional-integral digital filter or a high-order digital filter to attenuate and filter the input.

[0016] Preferably, the frequency modulation data generation module is used to store frequency control data. The frequency control information is injected into the frequency control word (FCW) node and the digital tuning word (NTW) node simultaneously through the frequency modulation data generation module, and all-pass transmission is achieved through gain calibration and delay calibration.

[0017] Preferably, the delay module adopts... The module performs delay calibration on the data injected into the digital tuning word NTW node.

[0018] The fast-locking fractional-frequency division all-digital phase-locked loop of the present invention solves the contradiction between the locking speed and phase noise in the prior art, and has the following advantages: (1) Regarding the locking time, the existing technology is limited by the loop bandwidth and usually requires tens to hundreds of reference cycles. However, the present invention injects data into the digital tuning word NTW node and the frequency control word FCW node at the same time, and the theoretical locking time is only 1 to 2 reference cycles, which is an order of magnitude improvement. (2) Regarding the decoupling of loop bandwidth and locking speed, existing fast locking methods must use wide bandwidth, but wide bandwidth will degrade noise performance. This invention ensures speed by adjusting the digital tuning word NTW and ensures accuracy and noise by adjusting the frequency control word FCW, thus achieving decoupling of speed and noise performance. It can simultaneously obtain fast locking and low output jitter, breaking through the traditional compromise. (3) In terms of hardware overhead, this invention only requires adding an adder to the feedforward path, resulting in minimal digital overhead. In terms of implementation complexity, this invention is implemented entirely digitally, with the two nodes (the digital tuning word NTW node and the frequency control word FCW node) working in parallel according to the input, requiring no state switching, making the design simple and reliable;

[0019] (4) In terms of applicable scenarios, existing technologies are mostly applicable to continuous locking or slow frequency hopping, while the present invention can be applied to scenarios such as arbitrary large frequency difference frequency hopping, burst mode and dynamic frequency scaling. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the fast-locking fractional frequency division all-digital phase-locked loop of the present invention.

[0021] Figure 2 The transfer function frequency domain characteristic curve of the fast-locking fractional-frequency-division all-digital phase-locked loop of the present invention; the horizontal axis freq represents frequency; the vertical axis... This represents the magnitude of the transfer function.

[0022] Figure 3 This invention provides an s-domain model for a fast-locking fractional-frequency-division all-digital phase-locked loop.

[0023] Figure 4 The simulation results of the single-point and two-point input of the fast-locking fractional frequency division all-digital phase-locked loop of the present invention are shown; (A) is the phase difference curve over time; (B) is the Δf curve over time.

[0024] Symbol explanations in the diagram: TDC: Time-to-Digital Converter; DLF: Digital Loop Filter; DCO: Digitally Controlled Oscillator; DSM: Delta-Sigma Modulator; VPA: Variable Phase Accumulator; RPA: Reference Phase Accumulator; DPD: Digital Phase Detector; DTC: Digital-Time Converter; FM: Frequency Modulation Data Generation Module; Z -1 Delay module; Adder; CKV: High-frequency output clock; : Accumulate reference phase; : Integer phase of the high-frequency output clock CKV; ε : The fractional phase value to be compensated; REF_DLY: The reference clock after delay; REF: Reference clock; FCW: Frequency control word; NTW: Digital control word; Indicates the frequency division ratio; LSB represents the least significant bit; φ out Indicates the output phase; φ data Indicates the input phase. Detailed Implementation

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It should be noted that the features mentioned in this invention can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification, as long as there is no contradiction in the combination of these features. Each feature disclosed in the specification can be replaced by any alternative feature that provides the same, equivalent, or similar purpose. Therefore, unless otherwise specified, the disclosed features are merely general examples of equivalent or similar features.

[0027] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0028] This invention provides a fast-locking fractional-frequency division all-digital phase-locked loop (PLL). The PLL includes: a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a Delta-Sigma modulator (DSM), a variable phase accumulator (VPA), a reference phase accumulator (RPA), a digital phase detector (DPD), a digital-to-time converter (DTC), a modulation data generator (FM module), a delay module, a first adder, and a second adder. The PLL achieves fast locking by inputting the frequency-modulated data generated by the FM data generator to both the low-frequency path (FCW path) and the high-frequency path (NTW path).

[0029] See Figure 1 The signal transmission relationships of each structure in the fast-locking fractional-frequency-division all-digital phase-locked loop of the present invention are as follows: The frequency modulation data generation module is used to generate frequency modulation data, which is divided into two channels: 1) High-frequency path: One FM data input is sent to the delay module. After the input FM data is delayed and calibrated by the delay module, it is injected into the digital tuning word NTW node. It is added to the digital control word NTW output by the digital loop filter DLF and then sent to the Delta-sigma modulator DSM. The delay module compensates for the inherent delay of the FCW path relative to the NTW path to ensure that the timing of the two injected signals is aligned when they arrive at the corresponding nodes. 2) Low-frequency path: The other frequency modulation data is added to the frequency control word FCW input at the frequency control word FCW node in the second adder and then sent to the reference phase accumulator RPA.

[0030] The Reference Phase Accumulator (RPA) is used to accumulate the reference phase FCW (including integer and fractional phases) to obtain the accumulated reference phase. .

[0031] The numerically controlled oscillator (DCO) is used to generate a high-frequency output clock CKV as a feedback clock. The output of the DCO is connected to a variable phase accumulator (VPA) and a time-to-digital converter (TDC). The input of the VPA is connected to the output of the DCO, counting the periods of the high-frequency output clock CKV to obtain the integer phase of the CKV. The digitally controlled oscillator (DCO) transmits the feedback clock CKV signal to the time-to-digital converter (TDC), which performs a phase comparison between the input CKV and REF_DLYTDC.

[0032] The output of the reference phase accumulator (RPA) is connected to the input of the digital phase detector (DPD). The RPA accumulates the reference phase. Input the digital phase detector (DPD). The output of the variable phase accumulator (VPA) is connected to the input of the DPD. The VPA will then input the integer phase. Input a digital phase detector (DPD). The phase difference between the two input signals is quantized by the DPD. The subtraction operation yields the fractional phase to be compensated. (Binary number), the fractional phase value to be compensated ε The input digital time converter (DTC) will convert the input fractional phase value. ε The input reference clock REF is converted into a delay, and the rising edge of the delayed reference clock REF_DLY is very close to that of the feedback clock CKV. They are then sent to the time-to-digital converter TDC for comparison, achieving fractional phase alignment and reducing the measurement range of TDC, thereby reducing the performance requirements and power consumption of TDC.

[0033] The output of the time-to-digital converter (TDC) is connected to the input of the digital loop filter (DLF). The TDC quantizes the phase difference between the rising edges of two clocks (the delayed reference clock REF_DLY and the feedback clock CKV) into a digital value and outputs it to the DLF. After filtering by the DLF, a digital control word NTW (i.e., the output decimal value, which is the digital tuning word and directly determines the output frequency of the phase-locked loop) is generated. The output of the DLF is connected to the first adder. The NTW is input to the first adder and added to the frequency-modulated data after delay calibration. The result is then sent to the Delta-Sigma modulator (DSM).

[0034] The Delta-sigma modulator (DSM) jitters the digital tuning word (NTW), transforming a small value into a series of integers (the average of which equals the small value). This further reduces the frequency quantization step size of the digitally controlled oscillator (DCO), shaping the DCO noise to a higher frequency. The output of the DSM is connected to the input of the DCO, which takes binary digital values ​​as input and outputs a high-frequency oscillating sine wave. The DCO consists of three parts: coarse tuning, intermediate tuning, and fine tuning, with the tuning step size decreasing sequentially. The fine tuning step size determines the DCO quantization noise. The fine tuning part is connected to a phase-locked loop (PLL). The output of the DSM drives the fine tuning port. The control words for the coarse and intermediate tuning parts are generated by an algorithm, specifically an AFC algorithm. The DSM controls the output frequency of the DCO, thus achieving frequency locking and phase locking.

[0035] This invention injects frequency control information simultaneously into the forward and feedback paths, allowing frequency modulation data to be transmitted simultaneously through the NTW high-frequency path and the FCW low-frequency path. The NTW path corresponds to high-pass characteristics, while the FCW path corresponds to low-pass characteristics. Through precise gain matching, the theoretical transfer function of the frequency control signal is not limited by the loop bandwidth, thereby achieving a frequency locking speed far exceeding the loop bandwidth constraint while maintaining an extremely narrow loop bandwidth to optimize phase noise.

[0036] According to a specific embodiment of the present invention, the method used by the digital time converter (DTC) to perform delay includes gain calibration using the LMS (Least Mean Squares) algorithm.

[0037] According to a specific embodiment of the present invention, a time-to-digital converter (TDC) is used to compare whether the rising edges of a delayed reference clock REF_DLY and a feedback clock CKV are aligned. The TDC includes a main circuit and a temperature code to binary code decoder. The signal input to the TDC first passes through the main circuit and then through the decoder. The decoder is used to convert the temperature code into a binary code for output.

[0038] According to a specific embodiment of the present invention, the digital loop filter (DLF) employs a proportional-integral digital filter or a high-order digital filter to attenuate and filter the input.

[0039] According to a specific embodiment of the present invention, the frequency modulation data generation module is used to store frequency control data and achieve fast locking. The frequency modulation data generation module simultaneously injects frequency control information into the FCW end and the NTW end, and achieves full-pass (low-pass and high-pass) transmission through gain calibration and delay calibration, thereby achieving fast locking.

[0040] According to a specific embodiment of the present invention, the delay module adopts The module performs delay calibration for data injected into the Qualcomm path, i.e., the NTW node.

[0041] The working principle of the fast-locking fractional-frequency division all-digital phase-locked loop of the present invention is as follows: (1) When only in the Frequency Controlled Word (FCW), At the node, data output from the frequency modulation data generation module is injected. When no signal is injected into the Number Tuning Word (NTW) node, the integer phase of the feedback obtained by the variable phase accumulator VPA is subtracted from the reference phase (containing integer and fractional phases) obtained by the reference phase accumulator RPA to obtain the fractional phase difference. The reference clock REF is delayed by sending it to the digital time converter DTC. The delayed reference clock REF_DLY (representing the reference phase) and the feedback clock CKV (representing the feedback phase) are compared in phase by the time-to-digital converter TDC. The comparison result is used by the digital loop filter DLF to regulate the output frequency of the digitally controlled oscillator DCO until the frequency and phase are locked. (2) When frequency control information is input at both the digital tuning word NTW node and the frequency control word FCW node, the fastest locking speed supported by the frequency control information input from the frequency control word FCW node is limited by the loop bandwidth. The frequency control information input from the digital tuning word NTW node directly acts on the input terminal of the digitally controlled oscillator (DCO). By selecting an appropriate gain, it can just compensate for the loop bandwidth limitation of the input data of the frequency control word FCW node, thereby achieving full-pass transmission and achieving a locking speed higher than the loop bandwidth.

[0042] The fractional frequency division of this invention is mainly achieved through the time-to-digital converter (DTC) and the time-to-digital converter (TDC) module. The VPA accumulates the integer phase of the feedback clock CKV, and the DTC compensates for the fractional phase. By separating the integer phase and the fractional phase, and locking them, the digital phase detector (DPD) obtains the fractional phase difference value to be compensated for each reference cycle. The rising edge of the corresponding value of the reference clock delay is aligned with the rising edge of the feedback clock. At this time, the comparison result of the time difference between the two input signals by the time-to-digital converter (TDC) is 0, and the result is output to the digital loop filter (DLF). At this time, the digital loop filter (DLF) no longer adjusts the frequency of the digitally controlled oscillator (DCO), and the loop is locked.

[0043] When injecting data along the two paths of the loop, the gain of the data injected by the digital tuning word (NTW) node is appropriately configured so that the high-frequency components reaching the output through the NTW node can precisely compensate for the information lost in the data injected by the frequency control word (FCW) node, thus achieving... Figure 2 The illustrated all-through transmission achieves a locking speed higher than the loop bandwidth.

[0044] See Figure 3 This paper presents the s-domain model of the fast locking ADPLL proposed in this invention, including the transfer functions of each module. , This indicates the output frequency of the digitally controlled oscillator (DCO). Indicates the reference clock frequency. This indicates the target frequency division ratio.

[0045] When the DCO normalization module accurately estimates the DCO gain of the numerically controlled oscillator, the specific functions for the low-pass and high-pass paths are as follows: (1) For low-pass paths, Open-loop transfer function: (1) In equation (1), Represent the open-loop transfer function; Indicates DTC gain; Indicates TDC gain; Indicates the proportionality coefficient; Indicates the integral coefficient; Indicates the reference frequency; Indicates DCO gain; This represents the estimated DCO gain. s This represents the Laplace transform factor.

[0046] Feedback coefficient: (2) In equation (2), This represents the feedback coefficient.

[0047] make Closed-loop transfer function: (3) In equation (3), The closed-loop transfer function represents the low-pass path; Represent the open-loop transfer function; Indicates the feedback coefficient; This indicates the frequency division ratio.

[0048] (2) For the high-pass path Open-loop transfer function: (4) In equation (4), This represents the open-loop transfer function.

[0049] Feedback coefficient: (5) In equation (5), This represents the feedback coefficient.

[0050] but Closed-loop transfer function: (6) In equation (6), The closed-loop transfer function represents the high-pass path; This represents the gain value to be compensated for in the high-pass path.

[0051] (3) Total transfer function (7) In equation (7), This represents the total transfer function.

[0052] If it is a fully connected network, then , It represents an arbitrary constant.

[0053] So need .

[0054] Therefore, when the frequency control information injected into the digital tuning word NTW node has the same meaning as the frequency control information input into the frequency control word FCW node, the loop is a fully open network, and the frequency regulation bandwidth can exceed the phase-locked loop bandwidth.

[0055] See Figure 4 The simulation results of the fast locking ADPLL proposed in this invention are shown using the visualization simulation tool Simulink. It can be seen that when the target frequency changes again after the loop is locked, the locking speed of injecting data from both the digital tuning word NTW and the frequency control word FCW simultaneously is much greater than the locking speed of single-point injection, thus achieving fast locking.

[0056] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A fast-locking fractional-frequency division all-digital phase-locked loop, characterized in that, The phase-locked loop includes: a digitally controlled oscillator (DCO), a variable phase accumulator (VPA), a reference phase accumulator (RPA), a digital phase detector (DPD), a digital time converter (DTC), a time-to-digital converter (TDC), a digital loop filter (DLF), a Delta-sigma modulator (DSM), a frequency modulation data generation module, a delay module, a first adder, and a second adder. The numerically controlled oscillator (DCO), variable phase accumulator (VPA), digital phase detector (DPD), digital time converter (DTC), time-to-digital converter (TDC), digital loop filter (DLF), first adder, and Delta-sigma modulator (DSM) are connected in sequence, with the output of the Delta-sigma modulator (DSM) connected to the fine-tuning section of the numerically controlled oscillator (DCO) to form a loop. The second adder, reference phase accumulator (RPA), and digital phase detector (DPD) are connected in sequence. The output of the frequency modulation data generation module is connected to both the delay module and the second adder, and the output of the delay module is connected to the first adder. The output of the numerically controlled oscillator (DCO) is also connected to the time-to-digital converter (TDC). The frequency modulation data generation module is used to generate frequency modulation data. The generated frequency modulation data is divided into two channels and frequency control information is injected into the frequency control word FCW node and the digital tuning word NTW node at the same time. The frequency control word FCW is input to the second adder, and after being added to one channel of frequency modulation data in the second adder, it is sent to the reference phase accumulator RPA; another channel of frequency modulation data is input to the delay module, and after being delayed and calibrated by the delay module, the input frequency modulation data is injected into the digital tuning word NTW node, and after being added to the digital tuning word NTW output by the digital loop filter DLF in the first adder, it is sent to the Delta-sigma modulator DSM.

2. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The numerically controlled oscillator (DCO) is used to generate a high-frequency output clock CKV as a feedback clock; the variable phase accumulator (VPA) is used to obtain the integer phase of the high-frequency output clock CKV. and integer phase Input the digital phase detector (DPD); The reference phase accumulator (RPA) is used to accumulate the reference phase to obtain the accumulated reference phase. ; The digital phase detector (DPD) is used to determine the integer phase. and accumulated reference phase Obtain the fractional phase to be compensated and the fractional phase value to be compensated ε The input digital time converter (DTC) will convert the input fractional phase value. ε The input reference clock REF is converted into a delay and then delayed. The time-to-digital converter TDC compares the phase of the delayed reference clock REF_DLY with the feedback clock CKV. The digital loop filter DLF is used to filter and generate a digital control word. This word is added to the frequency modulation data after delay calibration by the second adder, and then the digital tuning word NTW is jittered by the Delta-sigma modulator DSM to regulate the output frequency of the digitally controlled oscillator DCO, thereby achieving frequency locking and phase locking.

3. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 2, characterized in that, The reference phase includes integer phase and fractional phase.

4. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The method used by the digital time converter (DTC) to perform delay includes gain calibration.

5. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 4, characterized in that, The gain calibration uses the LMS algorithm to iteratively adjust the gain error.

6. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The time-to-digital converter (TDC) is used to compare whether the rising edges of the delayed reference clock REF_DLY and the feedback clock CKV are aligned.

7. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The time-to-digital converter (TDC) includes a TDC main circuit and a decoder. The decoder is used to decode the thermometer code output by the TDC main circuit and convert it into binary code.

8. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The digital loop filter (DLF) uses a proportional-integral digital filter or a high-order digital filter to attenuate and filter the input.

9. The fast-locking fractional-frequency division all-digital phase-locked loop according to claim 1, characterized in that, The frequency modulation data generation module is used to store frequency control data. It simultaneously injects frequency control information into the frequency control word (FCW) node and the digital tuning word (NTW) node, and achieves full-pass transmission through gain calibration and delay calibration.

10. The fast-locking fractional-frequency division all-digital phase-locked loop according to any one of claims 1 to 9, characterized in that, The delay module adopts The module performs delay calibration on the data injected into the digital tuning word NTW node.

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