Cross-domain communication apparatus, method and switch chip

Abstract

The application discloses a cross-domain communication device, method and switching chip, and belongs to the technical field of computer communication. The cross-domain communication device comprises an address decoding module, a non-transparent bridge unicast module, a doorbell interrupt module and a non-transparent bridge multicast module. The address decoding module sends a data message to the non-transparent bridge unicast module, the doorbell interrupt module, the non-transparent bridge multicast module or a system on chip according to a base address register window type and an address space of the data message, carries out corresponding message conversion, and forwards the converted message to a target virtual switch domain, thereby realizing communication between different virtual switch domains. The application realizes cross-domain communication with high performance, low overhead and sequence guarantee.

Description

Technical Field

[0001] This invention relates to the field of computer communication technology, and in particular to a cross-domain communication device, method, and switching chip. Background Technology

[0002] In existing Peripheral Component Interconnect Express (PCIe) multi-host systems, each host is typically isolated within an independent Virtual Switch (VS) domain. Direct memory access or interrupt propagation between domains is impossible, necessitating the use of a Non-Transparent Bridge (NTB) for inter-domain communication. Traditional non-transparent bridge solutions for cross-domain communication suffer from the following technical problems: Hardware-wise, each non-transparent bridge endpoint requires independent Base Address Register (BAR) decoding and address translation, resulting in hardware redundancy and increased chip area; address translation flexibility is insufficient, with address windows typically fixed or only supporting linear offsets, making it difficult to adapt to dynamic resource configurations; the identifier (ID) translation table has a small depth and is not scalable, easily leading to table overflow in multi-host concurrent scenarios; in terms of communication efficiency, doorbell interrupts are sent separately from data, and multi-queue scheduling within the switch can cause doorbell interrupts to arrive before data, forcing the receiving software to insert additional synchronization overhead; and the lack of a native multicast mechanism means that multi-host synchronous communication requires per-unicast replication, resulting in low bandwidth utilization.

[0003] Therefore, how to optimize the implementation of non-transparent bridges in PCIe multi-host systems, and solve problems such as hardware redundancy, insufficient flexibility, and low communication efficiency, remains an urgent issue to be addressed in existing PCIe multi-host interconnect technologies. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of the prior art and provide a cross-domain communication device, method and switching chip.

[0005] In a first aspect, this application provides a cross-domain communication device applied to a switching chip, comprising: The address decoding module stores the base address information of the base address registers of all non-transparent endpoints during the enumeration phase and generates a base address register decoding table. During the runtime phase, it receives data packets, looks up the base address register decoding table according to the target address of the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space. The non-transparent bridge unicast module receives data packets from the address decoding module that hit the first address space of the first base address register window type, performs address translation and identifier translation on the data packets to obtain the translated first packet, and sends the first packet to the target host corresponding to the target virtual switch domain. The doorbell interrupt module receives data packets from the address decoding module that hit the third address space of the second base address register window type. Based on the doorbell interrupt offset in the data packet, it determines the corresponding target virtual switch domain and interrupt packet format, converts the data packet into the corresponding second packet, sends the second packet to the target host corresponding to the target virtual switch domain, and stores the address space corresponding to the doorbell interrupt function in the current switching chip, the base address of the target virtual switch domain, and the information corresponding to the second packet. The non-transparent bridge multicast module receives data packets from the address decoding module that hit the second address space of the first base address register window type. Based on the multicast group identifier in the data packet, it determines all target virtual switch domains that need to receive the data packet. It copies the data packet into multiple copies, performs address translation and identifier translation on each copy, and sends it to the target host of the corresponding target virtual switch domain. It also stores and records the address space and multicast forwarding records corresponding to the non-transparent bridge multicast.

[0006] Optionally, the non-transparent bridge unicast module includes: The address translation unit, based on the source address and address window index of the received data packet, looks up the address translation table, determines the corresponding target base address and address mask, and outputs them to the target host corresponding to the target virtual switch domain; The identifier conversion unit searches the identifier conversion table based on the source identifier of the received data packet, determines the converted target identifier and the corresponding table entry, and outputs it to the target host corresponding to the target virtual switch domain.

[0007] Optionally, the address translation unit supports two address translation modes: direct address translation mode and lookup table address translation mode; in the direct address translation mode, the converted target address is the source address plus an offset; in the lookup table address translation mode, the address translation is implemented through an address lookup table or a tri-state content-addressable memory.

[0008] Optionally, the conversion process of the address lookup table is as follows: The base address information of the base address register, after removing the first preset bit from the source address, is used to obtain the internal offset address of the base address register; the address space of the base address register is divided into M equal address windows; the first preset bit of the internal offset address of the base address register is used as the window index; the address lookup table is queried using the window index to output the converted target base address; the converted target base address is concatenated with the second preset bit of the internal offset address of the base address register to form a new target address.

[0009] Optionally, the conversion process of the three-state content addressing memory is as follows: During the initialization phase of the cross-domain communication device, the source virtual switch domain number, the base address of the source address, and the address mask corresponding to each entry are written into the three-state content addressing memory. When address conversion is required, the source virtual switch domain number and source address of the message to be converted are input into the three-state content addressing memory. Each row of the three-state content addressing memory performs the following operations: First, the input source address is bitwise ANDed with the address mask stored in this row to obtain the mask result; then, the mask result is compared with the base address of the source address stored in this row, and the source virtual switch domain number stored in this row is compared with the input source virtual switch domain number. When both comparison results are equal, the row is hit, and the corresponding row index is output; using the row index as the address, a static random access memory with the same depth as the three-state content addressing memory is accessed to read the corresponding target source virtual switch domain number, the base address of the target address, and the address mask; the converted target address is calculated based on the source address, address mask, and base address of the target address.

[0010] Optionally, the identifier conversion unit is equipped with a bus number extension mechanism, and a source segment field is set in the identifier conversion table.

[0011] Optionally, the doorbell interrupt module includes: The doorbell interrupt table is used to store the address space corresponding to the doorbell interrupt function in this switching chip and to record the base address of the target switching chip. The MSI / MSIX table is used to store the MSI / MSIX address and MSI / MSIX data corresponding to each doorbell interrupt offset, and to convert the doorbell interrupt write message into the corresponding MSI / MSIX interrupt message. During operation, when the cross-domain communication device receives a data packet that hits the third address space, it looks up the doorbell interrupt table according to the source virtual switch domain number to obtain the corresponding address space and the base address of the target switching chip; at the same time, it looks up the MSI / MSIX table according to the doorbell interrupt offset in the data packet to obtain the corresponding MSI / MSIX address and MSI / MSIX data.

[0012] Optionally, the cross-domain communication device determines whether a data packet hits a doorbell interrupt write operation based on a first judgment condition: when the first judgment condition is true, the doorbell interrupt address accessed by the data packet is subtracted from the doorbell base address to obtain the doorbell interrupt offset, and the doorbell interrupt offset is used as an index to query the MSI / MSIX table to obtain the corresponding MSI / MSIX payload data, including the MSI / MSIX address and MSI / MSIX data; when the first judgment condition is false, it is treated as an invalid access and an error is returned; the first judgment condition is: the result of a bitwise AND operation between the doorbell interrupt address and the doorbell address mask is equal to the doorbell base address.

[0013] Secondly, this application also provides a switching chip, comprising: a cross-domain communication device as described in any one of the first aspects.

[0014] Thirdly, this application also provides a cross-domain communication method, applied to a cross-domain communication device as described in any one of the first aspects, comprising the following steps: The on-chip system intercepts the configuration request sent by the host or device, constructs multiple non-transparent endpoints according to the configuration request, writes the base address information of the base address register of each non-transparent endpoint into the base address register decoding table of the cross-domain communication device, writes the bus information into the identifier conversion unit of the cross-domain communication device, and completes the enumeration. The host or device receives the configuration space read response from the on-chip system and sends a data packet. The cross-domain communication device receives the data packet, looks up the base address register decoding table according to the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space. If the data packet hits the first address space, address translation and identifier translation are performed to obtain the first packet, and the first packet is sent to the target host of the corresponding target virtual switch domain; If the data packet hits the second address space, then all target virtual switch domains that need to receive the data packet are determined according to the multicast group identifier in the data packet. The data packet is copied into multiple copies, and address translation and identifier translation are performed on each copy before being sent to the target host of the corresponding target virtual switch domain. If the data packet hits the third address space, the corresponding target virtual switch domain is determined according to the doorbell interrupt offset in the data packet, the data packet is converted into a second packet, and the second packet is sent to the target host corresponding to the target virtual switch domain. If the data packet hits the fourth address space, the data packet is sent to the system on-chip, and the system on-chip reads and writes the corresponding non-transparent endpoint.

[0015] The cross-domain communication device, method, and switching chip of this application integrate base address register decoding, address translation, identifier translation, doorbell interrupt, and multicast functions into a single cross-domain communication device. The address decoding module stores the base address information of the base address registers of all non-transparent endpoints and generates a shared base address register decoding table. The non-transparent bridge unicast module, doorbell interrupt module, and non-transparent bridge multicast module access the base address register decoding table in parallel to perform their respective message translation and forwarding operations. This eliminates the hardware redundancy caused by each non-transparent endpoint independently implementing the above functions in traditional solutions at the architectural level, significantly reducing the chip area. At the same time, the doorbell interrupt module converts data packets that hit the doorbell interrupt address space into message signal interrupts or message signal interrupt extended packets, so that interrupt packets and data packets are transmitted in the same virtual channel. This eliminates the out-of-order problem of interrupts arriving before data caused by doorbell interrupts and data being separated into different queues in traditional solutions at the hardware level. The receiving end does not need to insert additional synchronization overhead, ensuring the correct order of interrupt responses. This application solves the problems of fixed address window, identifier conflict, and out-of-order interruption in existing non-transparent bridges in multi-domain scenarios, and realizes high-performance, low-overhead, and order-guaranteed cross-domain communication.

[0016] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the cross-domain communication device provided in one embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of a cross-domain communication device provided in another embodiment of this application.

[0020] Figure 3 This is a flowchart of a cross-domain communication method provided in one embodiment of this application. Detailed Implementation

[0021] To make the objectives and technical solutions of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In one embodiment, see Figure 1 This application provides a cross-domain communication device 11, applied to a virtual switch domain 1, which is integrated into a switching chip. The cross-domain communication device 11 is connected to a system-on-a-chip 2. The system-on-a-chip 2 intercepts configuration requests sent by a host or device, constructs a non-transparent endpoint according to the configuration request, writes the base address information and bus information of the base address register (BAR) of the non-transparent endpoint into the cross-domain communication device 11, returns to the configuration space to read the response to the host or device, and completes enumeration. The cross-domain communication device 11 also receives data packets sent by a host or device, performs corresponding packet conversion according to the base address register window type hit by the target address of the data packet, and forwards the converted packet to the target virtual switch domain, thereby realizing communication between different virtual switch domains.

[0023] As an example, the address space of the base address register of the cross-domain communication device 11 is divided into multiple address windows, each address window is uniquely mapped to a virtual switch domain, constituting the cross-domain communication entry point of the virtual switch domain to the outside.

[0024] As an example, during the runtime phase, a host or device within the source virtual switch domain triggers the cross-domain communication device 11 to perform cross-domain address translation and forwarding by initiating a data packet pointing to the address window assigned to the target virtual switch domain.

[0025] As an example, during the enumeration phase, the System-on-Chip 2 dynamically virtualizes a corresponding non-transparent endpoint (NT endpoint) for each virtual switch domain participating in cross-domain communication. This NT endpoint serves as the non-transparent bridge functional logic interface visible to the outside world for that virtual switch domain. All NT endpoints share a shared memory area maintained by the System-on-Chip, which is the Scratch Pad. Each NT endpoint maps this shared memory area to a private address space accessible independently by its own virtual switch domain through the address space of its base address register. This private address space is used to temporarily store control information, status information, or user-defined data that needs to be exchanged between different virtual switch domains.

[0026] As an example, when a host in any source virtual switch domain performs a write operation on the address mapped by the whiteboard register through the address space of the base address register of its corresponding non-transparent endpoint, data is written to the shared memory area. Hosts in other target virtual switch domains can then read the data in the shared memory area through the address space of the base address register of their respective non-transparent endpoints, thereby achieving lightweight data sharing and communication across virtual switch domains via memory read / write.

[0027] As an example, from the perspective of each virtual switch domain, the whiteboard register access space provided by its corresponding non-transparent endpoint is logically independent and does not interfere with each other. This ensures the isolation and reliability of each domain when accessing the whiteboard register and avoids data conflicts when multiple hosts concurrently access the same logical address space.

[0028] As an example, one implementation of a non-transparent endpoint is to simplify its functionality to provide only whiteboard register access, which is exposed to the virtual switch domain through the address space of a base address register of the non-transparent endpoint. During operation, when a data packet received by the cross-domain communication device 11 does not hit the first, second, and third address spaces, the packet is considered a non-transparent bridge function-independent access. In this case, under the PCIe unicast routing mechanism, the packet will be automatically matched to the default routing window defined by the memory base address or restricted address space of the data path port (DP) where the non-transparent endpoint is located, and will eventually be forwarded to the on-chip system 2 for processing.

[0029] For example, please refer to Figure 1The cross-domain communication device 11 provided in this application is applied to virtual switch domain 1. The cross-domain communication device 11 includes: a non-transparent bridge unicast module 111, a doorbell interrupt module 112, a non-transparent bridge multicast module 113, and an address decoding module 114. The address decoding module 114 stores the base address information of the base address registers of all non-transparent endpoints during the enumeration phase, generates a base address register decoding table, receives data packets during the operation phase, searches the base address register decoding table according to the target address of the data packet, and determines the base address register window type and address space hit by the data packet. The register window types include a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space, and the second base address register window type includes a third address space and a fourth address space. Based on the base address register window type and address space, the data packet is sent to the non-transparent bridge unicast module 111, the doorbell interrupt module 112, the non-transparent bridge multicast module 113, or the system-on-a-chip 2. The non-transparent bridge unicast module 111 receives data from the address decoding module 114 that hits the first address in the first base address register window type. The data packet in the space is processed by address translation and identifier translation to obtain a first packet, which is then sent to the target host corresponding to the target virtual switch domain. The doorbell interrupt module 112 receives a data packet from the address decoding module 114 that hits the third address space in the second base address register window type. Based on the doorbell interrupt offset in the data packet, it determines the corresponding target virtual switch domain and interrupt packet format, converts the data packet into a corresponding second packet, sends the second packet to the target host corresponding to the target virtual switch domain, and stores it in the current switching chip. The address space corresponding to the doorbell interrupt function, the base address of the target virtual switch domain, and the information corresponding to the second packet are included. The non-transparent bridge multicast module 113 receives data packets from the address decoding module 114 that hit the second address space in the first base address register window type. Based on the multicast group identifier in the data packet, it determines all target virtual switch domains that need to receive the data packet, copies the data packet into multiple copies, performs address translation and identifier translation on each copy, and sends it to the target host of the corresponding target virtual switch domain. It also stores and records the address space corresponding to the non-transparent bridge multicast and the multicast forwarding record.

[0030] As an example, the non-transparent bridge unicast module 111, the doorbell interrupt module 112, and the non-transparent bridge multicast module 113 are in a parallel access relationship, and the same data packet will only hit the address space corresponding to any one of the modules.

[0031] As an example, the address space may include a base address, an address mask, etc.

[0032] As an example, the second message is a Message Signaled Interrupt (MSI) message or a Message Signaled Interrupt eXtended (MSIX) message.

[0033] As an example, the doorbell interrupt module 112 converts the received data packets into message signal interruption packets or message signal interruption extension packets for the target virtual switch domain.

[0034] As an example, the doorbell interrupt module 112 includes a doorbell interrupt table and an MSI / MSIX table. The doorbell interrupt table stores the address space corresponding to the doorbell interrupt function within the current switching chip and records the base address of the target switching chip. The MSI / MSIX table stores the MSI / MSIX address and MSI / MSIX data corresponding to each doorbell interrupt offset (Doorbell_offset) to convert doorbell interrupt write messages into corresponding MSI / MSIX interrupt messages. During operation, when the cross-domain communication device 11 receives a data packet that hits the third address space, it searches the doorbell interrupt table according to the source virtual switch domain number to obtain the corresponding address space and the base address of the target switching chip; simultaneously, it searches the MSI / MSIX table according to the doorbell interrupt offset (Doorbell_offset) in the data packet to obtain the corresponding MSI / MSIX address and MSI / MSIX data.

[0035] As an example, the non-transparent bridge unicast module 111 includes: an address translation unit 1111 and an identifier translation unit 1112. The address translation unit 1111 searches the address translation table according to the source address and address window index of the received data packet, determines the corresponding target base address and address mask, and outputs them to the target host corresponding to the target virtual switch. The identifier translation unit 1112 searches the identifier translation table according to the source identifier of the received data packet, determines the converted target identifier and the corresponding table entry, and outputs it to the target host corresponding to the target virtual switch domain.

[0036] As an example, the address translation unit 1111 is also used to store the address space corresponding to the non-transparent bridge unicast in the current switching chip, and output the target virtual switch base address after address translation.

[0037] As an example, the identifier conversion unit 1112 is also used to store the bus information (BDF) of each device.

[0038] As an example, the bus information is scalable.

[0039] As an example, the bus information may include the PCIe bus number (Bus), device number (Device), and function number (Function).

[0040] As an example, both the address translation unit 1111 and the identifier translation unit 1112 integrate an input / output memory management unit (IOMMU) loading interface, which has IOMMU functionality and can realize dynamic mapping and isolation of the device address space, thereby enhancing the security and flexibility of the system.

[0041] As an example, the address translation unit 1111 supports two address translation modes, including: direct address translation mode and table lookup address translation mode.

[0042] As an example, in direct address translation mode, the translated target address is the source address plus the offset.

[0043] As an example, in lookup table address translation mode, address translation can be achieved using an address lookup table (A-LUT) or a tri-state content-addressable memory (TCAM).

[0044] Taking an address lookup table as an example, the conversion process is as follows: Remove the high-order base address information from the source address to obtain the internal offset address of the base address register; divide the address space of the base address register into M equal-sized address windows, specifying the size and alignment of each window; use the high-order bits of the internal offset address of the base address register as the window index; query the address lookup table using the window index to output the translated target base address; concatenate the target base address with the low-order bits of the internal offset address of the base address register to form a new target address.

[0045] It should be noted that the address lookup table is applicable to a single cross-domain communication device 11. When multiple cross-domain communication devices 11 in multiple virtual switch domains share the same address translation table, and the address space of the base address register is not divided into address windows in an equal manner, a tri-state content addressing memory is used to implement table lookup address translation.

[0046] Specifically, the conversion process of the tri-state content addressing memory is as follows: During the initialization phase of the cross-domain communication device 11, the source virtual switch domain number, the base address of the source address (src_addr_base), and the address mask (addr_mask) corresponding to each entry are written into the tri-state content addressing memory. When address conversion is required, the source virtual switch domain number and the source address (src_addr) of the message to be converted are input into the tri-state content addressing memory. Each row of the tri-state content addressing memory performs the following operations: First, a masking operation is performed on the input source address (src_addr), that is, a bitwise AND operation is performed between the input source address (src_addr) and the address mask (addr_mask) stored in this row to mask the low-order offset in the source address; then, the masking result is compared with the base address of the source address (src_addr_base) stored in this row, and the source virtual switch domain number stored in this row is compared with the input source virtual switch domain number. When both comparison results are equal, the row is a match, and the corresponding row index is output. Using the row index as the address, access the static random access memory (SRAM) with the same depth as the tri-state content addressing memory, and read out the corresponding target source virtual switch domain number dst_vcs, the base address of the target address dst_addr_base, and the address mask addr_mask; finally, calculate the transformed target address Translated_addr based on the source address src_addr, the address mask addr_mask, and the base address of the target address dst_addr_base, with the expression: Here, & represents bitwise AND, and ~ represents bitwise NOT.

[0047] As an example, the identifier conversion performed by the identifier conversion unit 1112 includes two types of conversion: requester ID conversion and completion ID conversion.

[0048] The following example uses a PCIe Switch as the switching chip, with the source host0 and the target host1 belonging to different virtual switch domains, to illustrate the cross-domain communication process in detail.

[0049] Please see Figure 2During the enumeration phase, the source host 0 sends a configuration request. The system on-chip 2 intercepts the configuration request and constructs a first non-transparent endpoint 21 and a second non-transparent endpoint 22 based on the configuration request. The first non-transparent endpoint 21 corresponds to the source virtual switch domain 1 where the source host 0 is located, and the second non-transparent endpoint 22 corresponds to the target virtual switch domain 3 where the target host 1 is located. The system on-chip 2 returns valid configuration information to the source host 0, completes the enumeration, and enters the normal operation phase.

[0050] As an example, the valid configuration information may include Vendor ID, Device ID, Header Type, address space of the base address register, etc.

[0051] Furthermore, the system-on-chip 2 writes the base address information of the base address registers of the first non-transparent endpoint 21 and the second non-transparent endpoint 22 into the base address register decoding table of the address decoding module 114, and writes the bus information of the first non-transparent endpoint 21 and the second non-transparent endpoint 22 into the identifier conversion unit 1112, so that the source host host0 can trigger the cross-domain communication device 11 to perform message conversion by accessing the address space corresponding to the base address register decoding table of the address decoding module 114, and send the converted message to the target host host1, thereby realizing cross-domain virtual switch domain communication.

[0052] During the operation phase, the source host host0 sends a data packet, and the address decoding module 114 receives the data packet. Based on the target address of the data packet, the address decoding module 114 looks up the base address register decoding table to determine the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space.

[0053] As an example, BAR2 to BAR5 are the first base address register window types, and BAR0 to BAR1 are the second base address register window types; the first address space is the address range in BAR2 to BAR5 used for non-transparent bridge unicast, the second address space is the address range in BAR2 to BAR5 used for non-transparent bridge multicast, the third address space is the address range in BAR0 to BAR1 used for doorbell interrupts, and the fourth address space is the address range in BAR0 to BAR1 used for whiteboard registers.

[0054] Further, if the data packet hits the first address space, the data packet is sent to the non-transparent bridge unicast module 111, where address translation and identifier translation are performed according to the packet type to obtain the translated first packet; if the data packet hits the second address space, all target virtual switch domains that need to receive the data packet are determined according to the multicast group identifier in the data packet, the data packet is copied into multiple copies, and address translation and identifier translation are performed on each copy before being sent to the target host of the corresponding target virtual switch domain; if the data packet hits the third address space, the corresponding target virtual switch domain is determined according to the doorbell interrupt offset in the data packet, the data packet is converted into a second packet, and the second packet is sent to the target host corresponding to the target virtual switch domain; if the data packet hits the fourth address space, the data packet is sent to the system on-chip 2, where the system on-chip 2 reads and writes the corresponding whiteboard register.

[0055] As an example, if the source host0 and the target host1 belong to different virtual switch domains, regardless of whether the two hosts are located in the same switching chip, there will always be a boundary switching chip (switchx) in the entire PCIe interconnect topology that is divided into two ports belonging to the two virtual switch domains respectively. The address translation of the cross-domain communication device 11 occurs in this boundary switching chip. The source host0 realizes mutual access between the two virtual switch domains by operating the cross-domain communication device 11 on the boundary switching chip.

[0056] For example, source host0 belongs to source virtual switch domain 1, and target host1 belongs to target virtual switch domain 3. Source host0 sends a read or write request data packet with a target address falling within the unicast range of BAR2 to BAR5 to the cross-domain communication device 11. Address decoding module 114 determines that the data packet hits the first address space and sends the data packet to address translation unit 1111 and identifier translation unit 1112 respectively. Address translation unit 1111 looks up the address translation table according to the source address and address window index of the received data packet to determine the corresponding target base address and address mask. Identifier translation unit 1112 looks up the identifier translation table according to the source identifier of the received data packet to determine the converted target identifier and the corresponding table entry, and at the same time obtains the target bus number of target virtual switch domain 3.

[0057] As an example, the address translation table is a non-transparent bridge memory / virtual switch mapping table (NTB Mem / VCSmapping table), which is used to store the address space mapping relationship corresponding to each virtual switch domain.

[0058] In one embodiment, the PCIe switching chip can be configured to include eight virtual switch domains, each corresponding to a cross-domain communication device. The BAR2 to BAR5 address spaces of each cross-domain communication device are used for address translation, totaling 32 base address register address spaces. The address translation table is configured to support the loading of the Input / Output Memory Management Unit (IOMMU) function, with an entry depth of 512, implemented using tri-state content-addressable memory. To save switching chip area, the target address base address dst_addr_base and the target virtual switch domain number are stored in static random access memory. Table 1 shows the address translation table in a specific embodiment.

[0059] Table 1 Address translation table in a specific embodiment As an example, the identifier translation table is a non-transparent bridge identifier / virtual switch domain mapping table (NTB ID / VSmapping table), used to store the identifier mapping relationship and bus information (BDF) of each device. The bus information includes bus number, device number, and function number.

[0060] As an example, the identifier translation table is implemented using registers.

[0061] As an example, the identifier translation table is a global table, meaning that all virtual switch domains in a cross-domain communication device share the same identifier translation table.

[0062] As an example, each entry in the identifier translation table is uniquely identified by the virtual switch domain number, bus number, device number, and function number, and each host or device has one and only one corresponding entry in the identifier translation table.

[0063] As an example, the Direct Memory Access (DMA) engine or endpoint (EP) can also communicate across virtual switch domains through the cross-domain communication device 11.

[0064] As an example, a Direct Memory Access (DMI) engine is typically integrated into a host or device to perform bulk data transfers without CPU intervention. It can initiate cross-virtual switch domain transfers based on a location with non-transparent functionality. When a DMI engine needs to access memory or a device in another target virtual switch domain, its read or write request is sent to the address space of the base address register of the local cross-domain communication device 11. The cross-domain communication device 11 performs address and identifier translation on the read or write request, routing it to the target virtual switch domain. Since each DMI engine endpoint has independent bus information, it occupies one entry in the identifier translation table.

[0065] As an example, since the identifier translation table is global, the identifier translation table content is the same for all virtual switch domains, and the System-on-Chip 2 can automatically fill in any missing entries. The address translation table, on the other hand, is manually filled in by each host or device, and the content filled in by different hosts or devices may differ.

[0066] For example, when the cross-domain communication device 11 receives a data packet that matches the address translation table but not the identifier translation table, the cross-domain communication device 11 forwards the data packet to the system-on-a-chip 2. The system-on-a-chip 2 extracts bus information from the requester identifier of the data packet and fills the bus information into the corresponding entry in the identifier translation table. Subsequently, the system-on-a-chip 2 routes the data packet to the egress point. Afterward, subsequent data packets with the same requester identifier can directly match the identifier translation table.

[0067] In one embodiment, the identifier translation table can be configured to include 128 entries. Limited by the index width, it can support a maximum of 128 devices simultaneously transmitting across virtual switch domains. The identifier translation table supports both index lookup and bus information lookup. Considering that virtual switch domain numbers and bus information may be duplicated across different hosts, a host identifier (Host_ID) field is added to the identifier translation table to uniquely distinguish different hosts or devices. Table 2 shows an identifier translation table in a specific embodiment.

[0068] Table 2. Identifier conversion table in a specific embodiment. As an example, considering that PCIe bus numbers may have duplicate or extended requirements, this embodiment also sets up a bus number extension mechanism, and correspondingly sets the source segment (Src Segment) field in the identifier conversion table.

[0069] Specifically, the host allocates a 16-bit segment to each virtual switch domain. Each segment can contain 256 buses, thus expanding the number of buses and allowing the secondary bus number (SecBus) and slave bus number (SubBus) routing mechanisms to continue to be used. The memory address space between multiple segments under the same host uses unified addressing, and addressing can be completed without segment information.

[0070] As an example, whether or not comparison of source segment fields is enabled is controlled by a global register inside the cross-domain communication device 11.

[0071] For example, source host0 sends a data packet. The identifier translation table is looked up using the source virtual switch domain number, bus number, device number, and function number corresponding to source host0. If a match is found, the corresponding index is output. This index replaces the device number and function number fields in the original requester identifier, and the bus number field in the original requester identifier is replaced with the target bus number output from the identifier translation table, thus obtaining the translated requester identifier. Subsequently, a route lookup is performed using the translated requester identifier and the translated address. The packet is ultimately routed to the exit corresponding to the target virtual switch domain number and then routed according to the address in the target virtual switch domain to reach the target host1.

[0072] Further, the target host 'host1' returns a read response message. The completer identifier of the read response message is the bus number, device number, and function number corresponding to the target host 'host1'. The requester identifier in the read response message is the converted requester identifier carried in the request message. The read response message uses the converted requester identifier for routing. When the read response message is routed to a border switch chip (Switch X), and the bus number in the converted requester identifier is equal to the bus number of the cross-domain communication device on the border switch chip, it indicates that it has reached a border switch chip that can return to the source virtual switch domain 1. At this time, the identifier translation table is looked up in reverse using the index in the converted requester identifier to obtain the bus number, device number, function number, and source bus number of the source virtual switch domain 1. Then, the requester identifier in the read response message is replaced with the bus number, device number, and function number of the source virtual switch domain 1, and the completer identifier is replaced with the source bus number, with the device number and function number equal to zero. Finally, the read response message is sent to the ingress processing stage, where the exit point is found based on the bus number, device number, and function number of the source virtual switch domain 1. The message then returns to the source virtual switch domain 1 and is routed to the source host host0 via the requester identifier.

[0073] As an example, in existing cross-domain communication devices, out-of-order processing can occur between doorbell interrupts and cross-domain communication data packets. For instance, source host0 first sends a cross-domain communication data packet to target host1. Immediately after sending the data packet, it is written to the doorbell interrupt register. The cross-domain communication data packet is directly routed to the first switch output queue buffer (SW OQ buffer0) at the exit of target host1, while the doorbell interrupt is routed to the Synthetic Subsystem NT. The interrupt packet generated by the Synthetic Subsystem NT is sent to the second switch output queue buffer (SW OQ buffer1) at the exit of target host1. Although both switch output queue buffers go to the same exit, their scheduling cannot guarantee the order. It is possible that the doorbell interrupt in the second switch output queue buffer is processed before the interrupt packet in the first switch output queue buffer, leading to operational errors.

[0074] As an example, this application sets up multiple doorbell interrupt registers during the entry processing phase, with each doorbell interrupt register corresponding to multiple MSI / MSIX registers. During the enumeration phase, the corresponding MSI / MSIX addresses are pre-filled by the on-chip system. When the host writes to the doorbell interrupt register, a special MSI / MSIX payload data is generated. The doorbell interrupt message is converted into an MSI / MSIX message, which is then constructed and sent out by the switch chip's output.

[0075] As an example, the doorbell interrupt function occupies a contiguous third address space from BAR0 to BAR1. Each virtual switch domain requires only one doorbell base address register and one doorbell address mask register. The cross-domain communication device 11 determines whether a data packet hits a doorbell interrupt write operation based on a first condition: when the first condition is met, the doorbell interrupt address Doorbell_addr accessed by the data packet is subtracted from the doorbell base address Doorbell_base to obtain the doorbell interrupt offset Doorbell_offset. Then, the doorbell interrupt offset Doorbell_offset is used as an index to query the MSI / MSIX table to obtain the corresponding MSI / MSIX payload data, including the MSI / MSIX address and MSI / MSIX data; when the first condition is not met, it is treated as an invalid access and an error is returned.

[0076] As an example, the first judgment condition is: the result of the bitwise AND operation between the doorbell interrupt address Doorbell_addr and the doorbell address mask Doorbell_mask is equal to the doorbell base address Doorbell_base.

[0077] Specifically, the doorbell interrupt table is queried based on the source virtual switch domain number to obtain the doorbell interrupt address Doorbell_addr, doorbell address mask Doorbell_mask, doorbell interrupt offset Doorbell_offset, and doorbell base address Doorbell_base. It is then determined whether the doorbell interrupt address Doorbell_addr, doorbell address mask Doorbell_mask, and doorbell base address Doorbell_base satisfy the first judgment condition. If they do, it indicates that the current data packet is a doorbell write packet.

[0078] Further, the doorbell interrupt offset Doorbell_offset is calculated based on the doorbell interrupt address Doorbell_addr and the doorbell base address Doorbell_base. If the depth of the MSI / MSIX table is 256, the lower 8 bits of the doorbell interrupt offset Doorbell_offset[7:0] are taken as the index. The lower 8 bits of the doorbell interrupt offset Doorbell_offset[7:0] are added to the base address msi_table_base of the MSI / MSIX table to obtain the corresponding table entry address. The MSI / MSIX table is queried according to the table entry address to obtain the corresponding MSI / MSIX address and MSI / MSIX data. The converted MSI / MSIX payload data is generated according to the MSI / MSIX address and MSI / MSIX data.

[0079] For example, to save on switch chip area, the target address base address dst_addr_base and the target virtual switch domain can be implemented using static random access memory (SRAM).

[0080] In the aforementioned cross-domain communication device, by integrating the address translation unit, identifier translation unit, doorbell interrupt module, non-transparent bridge multicast module, and address decoding module into a single cross-domain communication device, hardware duplication can be significantly reduced. It supports dual-mode address translation, including direct address translation and lookup table address translation, adapting to different application scenarios. It also supports flexible non-uniform window mapping and automatic filling of missed entries, significantly reducing configuration overhead and improving the flexibility of cross-domain address translation and identifier translation. The address translation module supports multiple mapping methods, including direct offset, address lookup table equal-division window, and tri-state content-addressable memory non-uniform-division window, and, in conjunction with the multicast module's single-message copying mechanism, maximizes the utilization of PCIe's effective bandwidth. By converting doorbell interrupt writes into MSI / MSIX interrupt messages and integrating them with data messages, it achieves optimal performance. The virtual channel eliminates doorbell interrupts and out-of-order data packet issues, ensuring the correct sequence of interrupt responses. It isolates the whiteboard register from the cross-domain communication device's translation path, exposing it only through the base address register's address space and processing it via the on-chip system, simplifying shared data access logic. Through the cross-domain communication device and virtual port architecture, address and identifier translation are performed at the hardware level, eliminating the need for CPU forwarding and significantly reducing communication latency. A parallel module access mechanism allows data packets to pass quickly through the cross-domain communication device, reducing processing time. Direct PCIe routing and optimized data transmission paths avoid external network bandwidth bottlenecks. An integrated input / output memory management unit loading interface enables dynamic mapping and isolation of device address spaces, enhancing system security and flexibility. It is PCIe 6.0 compatible, supports bus segment expansion, and increases the bus number from 8 bits to 24 bits, meeting the needs of 256+ host topologies.

[0081] In another embodiment, please refer to Figure 3 This application also provides a cross-domain communication method, integrated into the cross-domain communication device described in the above embodiments, including the following steps: steps S1 to S6.

[0082] Step S1: The on-chip system intercepts the configuration request sent by the host or device, constructs multiple non-transparent endpoints according to the configuration request, writes the base address information of the base address register of each non-transparent endpoint into the base address register decoding table of the cross-domain communication device, writes the bus information into the identifier conversion unit of the cross-domain communication device, and completes the enumeration.

[0083] Step S2: The host or device receives the configuration space read response from the on-chip system and sends a data packet. The cross-domain communication device receives the data packet, looks up the base address register decoding table according to the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space.

[0084] Step S3: If the data packet hits the first address space, then address translation and identifier translation are performed to obtain the first packet, and the first packet is sent to the target host of the corresponding target virtual switch domain.

[0085] Step S4: If the data packet hits the second address space, determine all target virtual switch domains that need to receive the data packet based on the multicast group identifier in the data packet, copy the data packet into multiple copies, perform address translation and identifier translation on each copy, and then send it to the target host of the corresponding target virtual switch domain.

[0086] Step S5: If the data packet hits the third address space, the corresponding target virtual switch domain is determined according to the doorbell interrupt offset in the data packet, the data packet is converted into a second packet, and the second packet is sent to the target host corresponding to the target virtual switch domain.

[0087] Step S6: If the data packet hits the fourth address space, the data packet is sent to the on-chip system, and the on-chip system reads and writes the corresponding non-transparent endpoint.

[0088] In step S1, please refer to Figure 3 In step S1, the on-chip system intercepts the configuration request sent by the host or device, constructs multiple non-transparent endpoints according to the configuration request, writes the base address information of the base address register of each non-transparent endpoint into the base address register decoding table of the cross-domain communication device, writes the bus information into the identifier conversion unit of the cross-domain communication device, and completes the enumeration.

[0089] Specifically, when the switching chip is powered on, the host or device sends a configuration request. The on-chip system in the switching chip intercepts the configuration request sent by the host or device, constructs multiple non-transparent endpoints according to the configuration request, writes the base address information of the base address register of each non-transparent endpoint into the base address register decoding table of the cross-domain communication device, writes the bus information into the identifier conversion unit of the cross-domain communication device, returns to the configuration space to read the response to the host or device, and completes the enumeration.

[0090] In step S2, please refer to Figure 3 In step S2, the host or device receives the configuration space read response of the on-chip system and sends a data packet. The cross-domain communication device receives the data packet, looks up the base address register decoding table according to the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space.

[0091] Specifically, the host or device receives the configuration space read response from the on-chip system and issues a read request or write request. The cross-domain communication device receives the data packet corresponding to the read request or write request, looks up the base address register decoding table according to the target address of the data packet, and determines the base address register window type and address space hit by the data packet.

[0092] As an example, the address space of the base address register of the cross-domain communication device is divided into multiple address blocks, each address block corresponding to a target virtual switch domain and the cross-domain communication device corresponding to that target virtual switch domain.

[0093] As an example, BAR2 to BAR5 are the first base address register window types, and BAR0 to BAR1 are the second base address register window types. The first address space is the address range in BAR2 to BAR5 used for non-transparent bridge unicast, the second address space is the address range in BAR2 to BAR5 used for non-transparent bridge multicast, the third address space is the address range in BAR0 to BAR1 used for doorbell interrupts, and the fourth address space is the address range in BAR0 to BAR1 used for whiteboard registers.

[0094] In step S3, please refer to Figure 3 In step S3, if the data packet hits the first address space, address translation and identifier translation are performed to obtain the first packet, and the first packet is sent to the target host of the corresponding target virtual switch domain.

[0095] Specifically, if the data packet hits the first address space, the non-transparent bridge unicast module 111 receives the data packet and sends it to the address translation unit 1111 and the identifier translation unit 1112 respectively for address translation and identifier translation. The address translation unit 1111 looks up the address translation table based on the source address and address window index of the received data packet, performs address translation, and obtains the corresponding target base address and address mask; the identifier translation unit 1112 looks up the identifier translation table based on the source identifier of the received data packet, performs identifier translation, and obtains the converted target identifier and the corresponding table entry.

[0096] As an example, address translation can include direct address translation and table lookup address translation.

[0097] As an example, in direct address translation mode, the translated target address is the source address plus the offset.

[0098] As an example, in lookup table address translation mode, address translation can be implemented using an address lookup table (A-LUT) or a tri-state content-addressable memory (TCAM). Address lookup tables are suitable for single cross-domain communication devices. When multiple cross-domain communication devices across multiple virtual switch domains share the same address translation table, and the address space of the base address register is not equally divided, a tri-state content-addressable memory is used.

[0099] As an example, the conversion process of the address lookup table is as follows: Remove the high-order base address information of the base address register from the source address to obtain the internal offset address of the base address register; divide the address space of the base address register into M equal address windows of the same size, specify the size and alignment of each address window, use the high-order bits of the internal offset address of the base address register as the window index, query the address lookup table using the window index, and output the translated target base address; concatenate the target base address with the low-order bits of the internal offset address of the base address register to form a new target address.

[0100] As an example, the conversion process of the tri-state content-addressable memory is as follows: During the initialization phase of the cross-domain communication device 11, the source virtual switch domain number, the base address of the source address (src_addr_base), and the address mask (addr_mask) corresponding to each entry are written into the tri-state content-addressable memory. When address conversion is required, the source virtual switch domain number and the source address (src_addr) of the message to be converted are input into the tri-state content-addressable memory. Each row of the tri-state content-addressable memory performs the following operations: First, a masking operation is performed on the input source address (src_addr), that is, a bitwise AND operation is performed between the input source address (src_addr) and the address mask (addr_mask) stored in this row to mask the low-order offset in the source address; then, the masking result is compared with the base address of the source address (src_addr_base) stored in this row, and the source virtual switch domain number stored in this row is compared with the input source virtual switch domain number. When both comparison results are equal, the row is a match, and the corresponding row index is output. Using the row index as the address, access the static random access memory (SRAM) with the same depth as the tri-state content addressing memory, and read out the corresponding target source virtual switch domain number dst_vcs, the base address of the target address dst_addr_base, and the address mask addr_mask; finally, calculate the transformed target address Translated_addr based on the source address src_addr, the address mask addr_mask, and the base address of the target address dst_addr_base, with the expression: Here, & represents bitwise AND, and ~ represents bitwise NOT.

[0101] As an example, identifier transformations include: requester ID transformation and completion ID transformation.

[0102] For example, the identifier translation table is searched using the virtual switch domain number, bus number, device number, and function number in the data packet. If a match is found, the corresponding index is output. This index replaces the device number and function number fields in the original requester identifier, and the bus number field in the original requester identifier is replaced with the target bus number output from the identifier translation table, thus obtaining the translated requester identifier. Subsequently, a route lookup is performed using the translated requester identifier and the translated address. The requester is ultimately routed to the exit corresponding to the target virtual switch domain number, and then routed to the target host according to the address in the target virtual switch domain.

[0103] Further, the target host returns a read response message. The completer identifier of the read response message is the bus number, device number, and function number corresponding to the target host. The requester identifier in the read response message is the converted requester identifier carried in the request message. This read response message uses the converted requester identifier for routing. When the read response message is routed to a border switch chip (Switch X), and the bus number in the converted requester identifier is equal to the bus number of the cross-domain communication device on the border switch chip, it indicates that a border switch chip capable of returning to the source virtual switch domain has been reached. At this time, the identifier translation table is looked up in reverse using the index in the converted requester identifier to obtain the bus number, device number, function number of the source virtual switch domain, and the source bus number. Then, the requester identifier in the read response message is replaced with the bus number, device number, and function number of the source virtual switch domain, and the completer identifier is replaced with the source bus number with the device number and function number equal to zero. Finally, the read response message is sent to the Ingress stage, where the exit point is found based on the bus number, device number, and function number of the source virtual switch domain. The message then returns to the source virtual switch domain and is routed to the source host via the requester identifier.

[0104] In step S4, please refer to Figure 3 In step S4, if the data packet hits the second address space, then all target virtual switch domains that need to receive the data packet are determined according to the multicast group identifier in the data packet. The data packet is copied into multiple copies, and address translation and identifier translation are performed on each copy before being sent to the target host of the corresponding target virtual switch domain.

[0105] As an example, the specific methods for each execution of address translation and identifier translation can be found in step S3, and will not be repeated here.

[0106] In step S5, please refer to Figure 3 In step S5, if the data packet hits the third address space, the corresponding target virtual switch domain is determined according to the doorbell interrupt offset in the data packet, the data packet is converted into a second packet, and the second packet is sent to the target host corresponding to the target virtual switch domain.

[0107] Specifically, if the data packet hits the third address space, a special MSI / MSIX payload data will be generated. The doorbell interrupt module of the cross-domain communication device determines whether the host is performing a doorbell interrupt write operation through a first judgment condition. When the first judgment condition is true, the doorbell interrupt address Doorbell_addr accessed by the data packet is subtracted from the doorbell base address Doorbell_base to obtain the doorbell interrupt offset Doorbell_offset. Then, the doorbell interrupt offset Doorbell_offset is used as an index to query the MSI / MSIX table to obtain the corresponding MSI / MSIX payload data, including the MSI / MSIX address and MSI / MSIX data. When the first judgment condition is false, it is treated as an invalid access and an error is returned.

[0108] As an example, the first judgment condition is: the result of the bitwise AND operation between the doorbell interrupt address Doorbell_addr and the doorbell address mask Doorbell_mask is equal to the doorbell base address Doorbell_base.

[0109] In step S6, please refer to Figure 3 In step S6, if the data packet hits the fourth address space, the data packet is sent to the on-chip system, and the on-chip system reads and writes the corresponding non-transparent endpoint.

[0110] As an example, when the data packet received by the cross-domain communication device does not hit the first address space, the second address space, and the third address space, it will hit the memory base address or restricted address space of the data path port (DP) where the non-transparent endpoint is located during the PCIe unicast routing process. The data packet is eventually routed to the system on chip, and the system on chip reads and writes the whiteboard register of the corresponding non-transparent endpoint.

[0111] As an example, the whiteboard register is a shared storage space. Each non-transparent endpoint maps the whiteboard register to a private address space that can be accessed independently by its own virtual switch domain through the address space of its own base address register. This private address space is used to temporarily store control information, status information, or user-defined data exchanged between different virtual switch domains.

[0112] As an example, when a host in any virtual switch domain performs a write operation on the address mapped by the whiteboard register through the address space of the base address register of its corresponding non-transparent endpoint, data is written to the shared memory area. Hosts in other target virtual switch domains can then read the data in the shared memory area through the address space of the base address register of their respective non-transparent endpoints, thereby achieving lightweight data sharing and communication across virtual switch domains via memory read / write.

[0113] In the cross-domain communication method of this application, data packets from the source host to the destination host do not need to be forwarded by the CPU software. Instead, the cross-domain communication device directly performs address translation and identifier translation before routing to the exit. Simultaneously, address translation, identifier translation, doorbell interrupt, and multicast employ a parallel access mechanism, allowing data packets to pass quickly as long as they hit only one address space. This significantly reduces the depth of the processing pipeline and latency, achieving extremely low-latency point-to-point communication between different virtual switch domains within the same switching chip. By centrally integrating the base address register decoding logic into the link layer of the cross-domain communication device for unified processing, the functional limitations of virtual endpoints can be broken, allowing for flexible adjustment of the cross-domain communication device. At the deployment level, it adapts to networking scenarios with multiple ports and multiple domains, improving the overall compatibility and scalability of the architecture. Utilizing the direct routing feature of PCIe, all cross-domain communication is kept at the PCIe link layer, avoiding the protocol conversion overhead and bandwidth bottlenecks caused by forwarding through external networks. By copying unicast packets multiple times and converting them separately to achieve multicast, it significantly improves the efficiency of multi-domain broadcasting. By being compatible with both direct offset translation and tri-state content addressing memory lookup table address translation mechanisms, it can take into account both simple single-domain communication and complex address mapping requirements of multiple virtual switch domains, adapting to application scenarios where multiple devices share mapping tables, and greatly improving the accuracy and adaptability of address translation.

[0114] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0115] In another embodiment, this application also provides a switching chip, comprising: a cross-domain communication device as described in the above embodiments; a control device; and a storage device for storing one or more programs; wherein when the one or more programs are executed by the control device, the control device controls the cross-domain communication device to perform the steps of the cross-domain communication method as described in any one of the above embodiments.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this application.

Claims

1. A cross-domain communication device, characterized in that, Applications in switching chips include: The address decoding module stores the base address information of the base address registers of all non-transparent endpoints during the enumeration phase and generates a base address register decoding table. During the runtime phase, it receives data packets, looks up the base address register decoding table according to the target address of the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space. The non-transparent bridge unicast module receives data packets from the address decoding module that hit the first address space in the first base address register window type, performs address translation and identifier translation on the data packets to obtain the translated first packet, and sends the first packet to the target host corresponding to the target virtual switch domain. The doorbell interrupt module receives data packets from the address decoding module that hit the third address space in the second base address register window type. Based on the doorbell interrupt offset in the data packet, it determines the corresponding target virtual switch domain and interrupt packet format, converts the data packet into the corresponding second packet, sends the second packet to the target host corresponding to the target virtual switch domain, and stores the address space corresponding to the doorbell interrupt function in the current switching chip, the base address of the target virtual switch domain, and the information corresponding to the second packet. The non-transparent bridge multicast module receives data packets from the address decoding module that hit the second address space in the first base address register window type. Based on the multicast group identifier in the data packet, it determines all target virtual switch domains that need to receive the data packet. It copies the data packet into multiple copies, performs address translation and identifier translation on each copy, and sends it to the target host of the corresponding target virtual switch domain. It also stores and records the address space and multicast forwarding records corresponding to the non-transparent bridge multicast. The non-transparent bridge unicast module includes: The address translation unit, based on the source address and address window index of the received data packet, looks up the address translation table, determines the corresponding target base address and address mask, and outputs them to the target host corresponding to the target virtual switch domain; The identifier conversion unit searches the identifier conversion table based on the source identifier of the received data packet, determines the converted target identifier and the corresponding table entry, and outputs it to the target host corresponding to the target virtual switch domain.

2. The cross-domain communication device according to claim 1, characterized in that, The address translation unit supports two address translation modes: direct address translation mode and lookup table address translation mode. In the direct address translation mode, the converted target address is the source address plus an offset. In the lookup table address translation mode, the address translation is implemented through an address lookup table or a tri-state content-addressable memory.

3. The cross-domain communication device according to claim 2, characterized in that, The conversion process of the address lookup table is as follows: The base address information of the base address register, after removing the first preset bit from the source address, is used to obtain the internal offset address of the base address register; the address space of the base address register is divided into M equal address windows; the first preset bit of the internal offset address of the base address register is used as the window index; the address lookup table is queried using the window index to output the converted target base address; the converted target base address is concatenated with the second preset bit of the internal offset address of the base address register to form a new target address.

4. The cross-domain communication device according to claim 2, characterized in that, The conversion process of the three-state content addressing memory is as follows: during the initialization phase of the cross-domain communication device, the source virtual switch domain number, the base address of the source address, and the address mask corresponding to each entry are written into the three-state content addressing memory. When address translation is required, the source virtual switch domain number and source address of the message to be translated are input into the tri-state content addressing memory. Each row of the tri-state content addressing memory performs the following operations: First, the input source address is bitwise ANDed with the address mask stored in this row to obtain the mask result; then, the mask result is compared with the base address of the source address stored in this row, and the source virtual switch domain number stored in this row is compared with the input source virtual switch domain number. When both comparison results are equal, the row is hit, and the corresponding row index is output; using the row index as the address, a static random access memory with the same depth as the tri-state content addressing memory is accessed to read the corresponding target source virtual switch domain number, the base address of the target address, and the address mask; the translated target address is calculated based on the source address, address mask, and base address of the target address.

5. The cross-domain communication device according to claim 1, characterized in that, The identifier conversion unit is equipped with a bus number extension mechanism and sets the source segment field in the identifier conversion table.

6. The cross-domain communication device according to claim 1, characterized in that, The doorbell interrupt module includes: The doorbell interrupt table is used to store the address space corresponding to the doorbell interrupt function in this switching chip and to record the base address of the target switching chip. The MSI / MSIX table is used to store the MSI / MSIX address and MSI / MSIX data corresponding to each doorbell interrupt offset, and to convert the doorbell interrupt write message into the corresponding MSI / MSIX interrupt message. During operation, when the cross-domain communication device receives a data packet that hits the third address space, it looks up the doorbell interrupt table according to the source virtual switch domain number to obtain the corresponding address space and the base address of the target switching chip; at the same time, it looks up the MSI / MSIX table according to the doorbell interrupt offset in the data packet to obtain the corresponding MSI / MSIX address and MSI / MSIX data.

7. The cross-domain communication device according to claim 6, characterized in that, The cross-domain communication device determines whether a data packet hits a doorbell interrupt write operation based on a first condition: when the first condition is met, the doorbell interrupt address accessed by the data packet is subtracted from the doorbell base address to obtain the doorbell interrupt offset. The doorbell interrupt offset is then used as an index to query the MSI / MSIX table to obtain the corresponding MSI / MSIX payload data, including the MSI / MSIX address and MSI / MSIX data. When the first condition is not met, the access is treated as invalid, and an error is returned. The first condition is that the bitwise AND operation between the doorbell interrupt address and the doorbell address mask equals the doorbell base address.

8. A switching chip, characterized in that, include: The cross-domain communication device as described in any one of claims 1 to 7.

9. A cross-domain communication method, characterized in that, An application to a cross-domain communication device as described in any one of claims 1 to 7 includes the following steps: The on-chip system intercepts the configuration request sent by the host or device, constructs multiple non-transparent endpoints according to the configuration request, writes the base address information of the base address register of each non-transparent endpoint into the base address register decoding table of the cross-domain communication device, writes the bus information into the identifier conversion unit of the cross-domain communication device, and completes the enumeration. The host or device receives the configuration space read response from the on-chip system and sends a data packet. The cross-domain communication device receives the data packet, looks up the base address register decoding table according to the data packet, and determines the base address register window type and address space hit by the data packet. The base address register window type includes a first base address register window type and a second base address register window type. The first base address register window type includes a first address space and a second address space. The second base address register window type includes a third address space and a fourth address space. If the data packet hits the first address space, address translation and identifier translation are performed to obtain the first packet, and the first packet is sent to the target host of the corresponding target virtual switch domain; If the data packet hits the second address space, then all target virtual switch domains that need to receive the data packet are determined according to the multicast group identifier in the data packet. The data packet is copied into multiple copies, and address translation and identifier translation are performed on each copy before being sent to the target host of the corresponding target virtual switch domain. If the data packet hits the third address space, the corresponding target virtual switch domain is determined according to the doorbell interrupt offset in the data packet, the data packet is converted into a second packet, and the second packet is sent to the target host corresponding to the target switch domain. If the data packet hits the fourth address space, the data packet is sent to the system on-chip, and the system on-chip reads and writes the corresponding non-transparent endpoint.

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