Dual-path video signal zero-latency switching method based on EDID preloading

Abstract

The application discloses a dual-path video signal zero-delay switching method based on EDID preloading and particularly relates to the field of video signal switching, and is used for solving the problem of unknown connection state before dual-path video source switching. Display capability information of a target display link is checked and analyzed, a display capability response object is generated according to the source end identifier of the dual-path video source, the display capability response is provided and the display connection sensing state is maintained when the video source to be switched is not connected to the target display link, so that the output mode preparation is completed. The output stable state of the video source to be switched is detected, the connection state is identified in combination with the corresponding relationship among the actual output mode, the allowed output mode and the mode allowed range and the change relationship between the display connection sensing state and the response effective state, the switching permission result is generated, and the target display link connection, the current video source keeping, the safe picture output or the display capability response object degradation are executed according to the switching permission result.

Description

Technical Field

[0001] This invention relates to the field of video signal switching, and more specifically, to a method for zero-delay switching of dual-channel video signals based on EDID preloading. Background Technology

[0002] In scenarios where dual-channel computers, industrial control hosts, vehicle controllers, medical host systems, or conference signal sources share the same display link, video switching devices are typically located between multiple video sources and the same display. When a video source recognizes the display, it declares its acceptable resolution, refresh rate, pixel clock, color format, color depth, and audio capabilities to the video source via display capability information. The video source then selects its output mode based on this information. To reduce re-identification caused by plugging and unplugging or switching, existing video switching devices typically pre-read the display capability information of the target display link and provide display capability responses to video sources not currently connected through caching, simulation, or templates. This allows unselected video sources to also perceive the presence of the display and pre-configure some display output settings.

[0003] However, black screens, flickering, or resolution regression during dual-source video switching are not solely determined by whether the video source has read the display capability response. After reading the display capability response, the video source must complete resolution selection, refresh rate selection, pixel clock generation, color format configuration, color depth configuration, and synchronization signal output through the graphics output control path. Different video sources will not necessarily have the same selection result for the same display capability response. For example, one industrial control host may choose a more conservative refresh rate and color depth, while the other host may choose a higher pixel clock or a different color format due to driver strategy or interface negotiation results. In this case, although the display capability response is readable, the actual output mode of the video source to be switched to the interface side may have deviated from the range of modes that the target display link can stably handle.

[0004] Furthermore, before the video source to be switched is actually connected to the target display link, its perception of the display's status mainly relies on connection signals such as hot-plug detection, display data channel, auxiliary channel, and display capability response readability. If these statuses experience brief loss of response, jitter, or repeated activation before switching, the video source may re-enumerate the display and reselect the output mode. If the switching device performs the switch based solely on the provision of display capability response or solely on the detection of video signals on the video source side, the target display link may still receive an unstable pixel clock, asynchronous valid frames, or incompatible color formats at the moment of connection, thereby triggering the display to relock, experience a brief black screen, flicker, audio / video anomalies, resolution regression, or safety screen regression. Therefore, dual-channel video signal switching requires a unified judgment of the display capability response status, connection perception stability, and actual output mode acceptance status before the target display link connects to the video source to be switched.

[0005] To address the aforementioned problems, a technical solution is provided. Summary of the Invention

[0006] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a zero-delay switching method for dual-channel video signals based on EDID preloading. This method verifies and parses the display capability information of the target display link, generating a display capability response object according to the source end identifier of the dual video sources. When the video source to be switched is not connected to the target display link, a display capability response is provided and the display connection awareness state is maintained, enabling it to complete output mode preparation. Then, the output stability state of the video source to be switched is detected, and the acceptance state is identified by combining the correspondence between the actual output mode and the allowed output mode, the allowed mode range, and the change relationship between the display connection awareness state and the response effectiveness state. A switching permission result is generated, and accordingly, the target display link is connected, the current video source is maintained, a safe image is output, or the display capability response object is downgraded, thereby solving the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A zero-delay switching method for dual-channel video signals based on EDID preloading includes the following steps: Verify and parse the display capability information of the target display link, and generate a display capability response object containing the capability source, allowed output mode, allowed mode range and response status according to the source end identifier of the dual video source; Receive the display capability response object, provide display capability response when the video source to be switched is not connected to the target display link, maintain the display connection awareness state, and enable the video source to be switched to complete the output mode preparation based on the display capability response object; Receive the display connection awareness status and detect the output stability status of the video source to be switched. Based on the correspondence between the actual output mode and the allowed output mode and the allowed range of the mode, as well as the change relationship between the display connection awareness status and the response effective status, identify the acceptance status and generate the switching permission result. Upon receiving the switching permission result, if permitted, the target display link is connected to the video source to be switched; if not permitted, one of the following actions is taken: maintain the current video source, output a safe image, or downgrade the display capability response object.

[0008] Furthermore, verifying and parsing display capability information includes: selecting the reading path according to the interface type of the target display link; reading the EDID base block and extension block through the DDC channel in the HDMI link; and reading one type of data from the DisplayID block, CTA extension block, and equivalent display capability data output by the display interface controller through the AUX channel in the DisplayPort and USB-CAlt Mode links, and sequentially verifying the data length, checksum, version identifier, number of extension blocks, and timing field.

[0009] Furthermore, parsing the display capability information includes: extracting resolution, refresh rate, pixel clock, color format, and color depth from the verified display capability information to form allowed output modes; generating a mode allowable range for each allowed output mode; and writing only the candidate output modes that can form a correspondence between resolution, refresh rate, and pixel clock into the display capability response object.

[0010] Furthermore, generating a display capability response object includes: using the source identifier as an index, writing the capability source, allowed output mode, and allowed mode range into the response path corresponding to the source identifier; after writing, confirming the response effectiveness status based on the write address, data block length, and read response, and ensuring that the response effectiveness status corresponding to different video sources does not overwrite each other.

[0011] Furthermore, providing display capability response includes: the control processing unit finds the corresponding display capability response object according to the source identifier of the video source to be switched; when the response is effective, it sets the response path corresponding to the source identifier to an accessible state; when the response is ineffective, it writes the display capability response object in place to the response path corresponding to the source identifier and then reconfirms it; and outputs the preloaded HPD effective state in the HDMI link, while keeping the AUX proxy response readable in the DisplayPort link and USB-C AltMode link.

[0012] Furthermore, maintaining the display connectivity awareness state includes: using a finite state machine to process the connectivity awareness input vector, the finite state machine including an unaware state, a readable state, and a valid awareness state; when the read channel in the response path is unavailable, it transitions to the unaware state; when the read channel is available but the response validity state is invalid, it transitions to the readable state; when the read channel is available, the display capability response is readable and the response validity state is valid, it transitions to the valid awareness state.

[0013] Furthermore, the output mode preparation includes: when the video source to be switched is in a valid display connection awareness state, it reads the display capability response object, selects the resolution, refresh rate, pixel clock, color format and color depth combination corresponding to its own output capability from the allowed output modes, and forms the output mode preparation result when the synchronization signal, pixel clock and the detection quantity corresponding to the interface detection conditions in the continuous valid frame candidate output are detected.

[0014] Furthermore, the detection of stable output status includes: after the output mode preparation result has been formed, sampling the video reception detection path on the side of the video source to be switched, extracting the actual output mode based on the line synchronization status, field synchronization status, continuous valid frame status, pixel clock stability status, color format status and receiver chip lock status, and aligning the actual output mode with the allowed output modes of the same type of components.

[0015] Furthermore, identifying the acceptance state includes: comparing the actual output mode with the same category component of each allowed output mode according to the allowed range of the mode to obtain the normalized deviation, and obtaining the mode deviation value; displaying the connection sensing state and the response effective state in a predetermined observation window to combine them into a connection effective state sequence, calculating the change frequency of adjacent sampling times to obtain the state flip rate, and inputting the mode deviation value and the state flip rate into the Bayesian state decision model to generate the handover permission result.

[0016] Furthermore, the degraded display capability response object includes: the control processing unit determines the degraded component based on the normalized deviation corresponding to the mode deviation value; when the normalized deviation corresponding to a single mode component is the maximum value, the corresponding component is degraded; when the normalized deviation corresponding to multiple mode components is the same and is the maximum value, the components are degraded in the order of maximum pixel clock, maximum refresh rate, color depth, color format, HDR capability, and audio format complexity, and the updated display capability response object is written in place.

[0017] The technical effects and advantages of the zero-delay switching method for dual-channel video signals based on EDID preloading in this invention are as follows: This invention refines the display capability response object into a comparable object that includes allowed output modes and their allowed ranges. This allows the actual output mode formed before the video source to be switched can be compared with the acceptable boundaries of the target display link. Compared to switching methods that only confirm the readability of the display capability response or only confirm the presence of a video signal, this process can identify access risks caused by mismatches in resolution, refresh rate, pixel clock, color format, and color depth, reducing the need for display re-locking and output mode rollback.

[0018] This invention incorporates the relationship between display connection awareness and response activation status into the acceptance status identification, reflecting status changes such as hot-plug detection jitter, short-term loss of response in the display data channel, abnormal response in the auxiliary channel, and repeated activation of display capability response. This processing makes the switching judgment cover both connection stability and output mode acceptance, reducing the probability of re-enumerating the display end after the video source to be switched is connected.

[0019] When the switching permission result does not meet the access conditions, this invention performs the following actions: maintaining the current video source, outputting a safe image, or downgrading the display capability response object. This process can maintain stable reception of the target display link when the video source to be switched has not yet reached a state where it can accept output, and constrains the video source to be switched to reselect the output mode through the downgraded display capability response object, thereby reducing black screens, flickering, and abnormal displays. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the zero-delay switching method for dual-channel video signals based on EDID preloading according to the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figure 1 This invention provides a method for zero-delay switching of dual-channel video signals based on EDID preloading, comprising: This invention uses the display capability information of the target display link and the source end identifiers of the dual video sources as the starting point for processing. First, it performs integrity verification and capability parsing on the display capability information, organizing the capability source, allowed output mode, allowed mode range, and response effectiveness status into display capability response objects corresponding to each source end identifier. When the video source to be switched has not yet connected to the target display link, the control processing unit provides the corresponding display capability response based on the source end identifier and maintains the display connection awareness state, enabling the video source to be switched to complete output mode preparation under the condition that the display capability response can be read. Subsequently, the control processing unit detects the stable output state of the video source to be switched, extracts the actual output mode, performs corresponding processing with the allowed output mode and allowed mode range, and identifies the acceptance state based on the change relationship between the display connection awareness state and the response effectiveness state, forming a switching permission result. Finally, based on the switching permission result, it executes target display link access, or executes corresponding actions among maintaining the current video source, outputting a safe image, and downgrading the display capability response object.

[0023] With the target display link selected, the source identifiers of the dual video sources registered, and subsequent steps requiring the invocation of the display capability response object based on the source identifiers, S1 begins acquiring, verifying, and parsing the display capability information of the target display link. At this point, no display capability response has been provided to the video source to be switched. The processing result of S1 is used to form a display capability response object that can be read by S2, compared by S3, and configured for downgrade in S4.

[0024] S101: Display capability information acquisition and integrity verification.

[0025] S1 takes the selected result of the target display link as the starting point for processing and uses the source end identifier set of the dual video sources as the basis for object generation. The source end identifier set is a set formed by the source end identifiers of the two video sources in the order of the video input ports, and is used to determine the display capability response object corresponding to each video source in subsequent processing. The following steps are all executed by the control processing unit in the dual video switching device. The DDC proxy, AUX proxy, EDID cache, DisplayID cache, MCU register or FPGA mapping table complete the configuration of the corresponding response path according to the write instructions of the control processing unit.

[0026] The control processing unit first selects the reading path based on the interface type of the target display link. In an HDMI display link, it reads the EDID base block and its extension blocks through the DDC channel. In a DisplayPort or USB-C Alt Mode display link, it reads the DisplayID block, CTA extension block, or equivalent display capability data output by the display interface controller that can be parsed to obtain resolution, refresh rate, pixel clock, color format, or color depth through the AUX channel. After reading, the control processing unit assembles the data blocks into display capability information according to the block number, the number of extension blocks declared, and the reading order, and records the candidate status of the capability source corresponding to this display capability information.

[0027] Before the display capability information enters capability parsing, the control processing unit performs integrity verification. Integrity verification is performed in the order of basic blocks first, then extended blocks, checking data length, checksum, version identifier, number of extended blocks, and timing fields in sequence. If the basic block verification fails, its extended blocks are no longer used as the actual source of display capability; if the extended block verification fails, only the failed extended blocks are removed, and the basic block and the verified extended blocks are retained to continue into capability parsing. When the EDID basic block length meets the parsing requirements and the checksum is correct, the number of extended blocks is checked against the actual number of blocks read; when extended blocks exist but some of them fail verification, the basic block and the verified extended blocks are retained, and the capability source is determined to be the trimmed display capability information; when the basic block is readable and the extended block is missing but the basic timing fields meet the parsing requirements, the basic block is used as the subsequent parsing object; when the basic block is unreadable, fails verification, or the version identifier cannot be identified, a pre-stored conservative template is called as the display capability information; when the read path has no response and the pre-stored conservative template is unavailable, an exception fallback template is called as the display capability information.

[0028] The pre-stored conservative template is written by the dual-channel video switching device during the factory configuration phase. Its allowed output modes are limited to low-complexity display modes that the target display link can typically handle, and the allowed mode range uses narrowed boundaries. Both the pre-stored conservative template and the abnormal fallback template are pre-stored according to the field structure of the display capability response object. The pre-stored conservative template includes at least one set of allowed output modes whose resolution, refresh rate, pixel clock, color format, and color depth are all within the target display link's typical range, and records the corresponding narrowed allowed mode range. The abnormal fallback template only retains the maximum pixel clock, maximum refresh rate, and color depth configurations lower than those of the pre-stored conservative template. When the control processing unit calls the pre-stored conservative template or the abnormal fallback template, it does not change the correspondence between the source identifier and the display capability response object; it only updates the capability source, allowed output modes, and allowed mode range to the corresponding template content. The abnormal fallback template is used to provide the minimum display capability response when the read path has no response. Its allowed output modes are fewer than those of the pre-stored conservative template, and it prioritizes limiting the maximum pixel clock, maximum refresh rate, and color depth. When a pre-stored conservative template or an abnormal fallback template is invoked, its capability source is written into the display capability response object, allowing S4 to identify that the object is already based on a conservative response during downgrade configuration. This forms display capability information that has completed path selection verification, and identifies the capability source as one of the following: the actual display end, the trimmed display capability information, the pre-stored conservative template, or the abnormal fallback template.

[0029] For example, in an implementation where one HDMI monitor serves as the target display link and two industrial control hosts serve as dual video sources, the control processing unit first reads the EDID base block and CTA extension block from the monitor's DDC channel. If the base block verification passes but the CTA extension block verification fails, the failed extension block is not written to the response path. Instead, only the parsable timing information in the base block is retained, and the capability source is recorded as the trimmed display capability information. This result is not the final response object but rather the parsing input entering S102.

[0030] S102: Allow output mode and mode allowed range generation.

[0031] After the display capability information for the selected verification path is generated in S101, the control processing unit performs capability parsing on this information. The parsing process first reads the mode components that can participate in subsequent acceptance state identification, including resolution, refresh rate, pixel clock, color format, and color depth. If the display capability information includes audio or HDR capabilities, these are only included in the parsing results when they affect the selection of the video source output mode or subsequent downgrade configuration. The control processing unit extracts candidate output modes according to the entries related to the display's acceptable capabilities in the timing description, short video description, DisplayID timing block, or CTA extension block within the display capability information. These candidate modes are then merged according to the correspondence of the same resolution, refresh rate, pixel clock interval, and compatible color format to obtain the allowed output modes.

[0032] The control processing unit only writes candidate output modes that can form a correspondence between resolution, refresh rate, and pixel clock into the allowed output modes; candidate output modes that cannot form the above correspondence are only recorded as non-acceptable capability objects of the display capability response object and do not participate in the mode deviation value calculation of S3. For each allowed output mode, the control processing unit further generates a mode allowable range. Numerical mode components form a closed range according to the nominal value, upper and lower limit fields, or the acceptable boundary of the display interface controller given by the display capability information; enumerated mode components form an acceptable set according to the compatibility relationship declared in the display capability information. The mode allowable range corresponds one-to-one with the allowed output modes, so that after S3 detects the actual output mode, it can directly perform difference normalization or compatibility determination according to the mode components of the same category.

[0033] When the display capability information only provides nominal timing without upper and lower limit fields, the control processing unit retrieves the locally stored standard timing table according to the resolution, refresh rate, and nominal pixel clock value in the display capability information. The standard timing table is pre-stored in the non-volatile memory of the dual-channel video switching device. Each standard timing record includes resolution, refresh rate, nominal pixel clock value, pixel clock allowable range, and refresh rate allowable range. If the resolution and refresh rate in the display capability information match a certain standard timing record, the pixel clock allowable range and refresh rate allowable range in that standard timing record are used as the mode allowable range for the corresponding allowable output mode; if no matching record is found, the pixel clock and refresh rate corresponding to that nominal timing are used as the single-point allowable range, and the maximum refresh rate is preferentially reduced or the maximum pixel clock is limited in subsequent degradation configurations.

[0034] When the standard timing table records the pixel clock nominal value and allowable deviation At that time, the allowable range of the pixel clock is: ; in, This is the nominal pixel clock value corresponding to the current resolution and refresh rate in the standard timing table, used to represent the center pixel clock under this standard timing. This refers to the allowable deviation of the pixel clock within the same standard timing record, used to indicate the boundary of pixel clock variations that the display link can tolerate; both are read from the standard timing table. This allowable pixel clock range is used by S3 to perform normalized deviation calculations on the pixel clock in the actual output mode.

[0035] During the generation process, the control processing unit determines the acceptability of candidate output modes. If a candidate output mode lacks a resolution, refresh rate, or pixel clock component that can be compared with the actual output mode, then the candidate output mode will not be included in the allowed output modes. If the color format is incompatible with the receiving capability declared in the display capability information, then the color format will not be included in the allowed range of the allowed output mode. If there are multiple color depths or color format combinations for the same resolution and refresh rate, then corresponding allowed output modes are formed according to the acceptable combinations in the display capability information, or an acceptable set of enumerated mode components is formed under the same allowed output mode. After generation, the allowed output modes and the allowed range of modes together constitute the input basis for S3 to calculate the mode deviation value.

[0036] For example, in an implementation where the industrial control host outputs to the same display link via HDMI, if the display capability information retained in S101 can resolve 1920×1080, 60Hz, and the corresponding pixel clock range, the control processing unit combines this resolution and refresh rate to form an allowed output mode, and writes the acceptable range of the pixel clock, color format compatibility, and color depth tolerance boundaries into the mode allowable range corresponding to this allowed output mode. Subsequently, when another industrial control host to be switched is detected in S3 with its actual output mode, S3 can directly reference this allowed output mode and mode allowable range to calculate the degree of deviation.

[0037] S103: Generate and activate the display capability response object based on the source identifier.

[0038] After obtaining the allowed output modes and allowed mode ranges in S102, the control processing unit generates a display capability response object for each video source, using the source identifier set as an index. The generation process does not change the target display link's acceptable boundaries obtained in S102; instead, it writes the capability source, allowed output modes, and allowed mode ranges into the corresponding video source reading path according to the source identifier. When two video sources use the same display interface, the two display capability response objects reference the same set of allowed output modes and allowed mode ranges.

[0039] When two video sources use different display interfaces, the control processing unit only maintains consistency between the mode components in the display capability information that can be expressed by both types of interfaces, including resolution, refresh rate, pixel clock, color format, and color depth. Capabilities specific to the interface and not expressible by both interfaces are not used as input for calculating the mode deviation value in S3. Thus, the display capability response object in cross-interface scenarios remains consistent with the boundary that the target display link can accept, but interface-specific capabilities are not forcibly included in the mode deviation value calculation.

[0040] After the display capability response object is generated, the control processing unit writes it to the corresponding response carrier. For HDMI video sources, the display capability response object is written to the DDC proxy or EDID cache; for DisplayPort or USB-C Alt Mode video sources, the display capability response object is written to the AUX proxy or DisplayID cache; for implementations where read requests are handled by programmable logic, the display capability response object is written to the MCU register or FPGA mapping table. After writing, the control processing unit performs a status check on the read path of the corresponding source identifier: when the write address, data block length, and read response are all consistent with the display capability response object, the response status is set to valid; when writing is complete but the read path has not yet responded, the response status is kept invalid, and the correspondence between the source identifier and the display capability response object is retained, so that S2 can continue to identify that the corresponding video source has not yet obtained a readable response. The response status is recorded separately according to the source identifier, and the response status of different video sources does not overwrite each other; when calculating the state toggle rate, S3 only calls the response status corresponding to the video source to be switched.

[0041] In a dual-channel conference signal source switching implementation, the first video source is the conference host, the second video source is a backup laptop, and the target display link is the conference screen. After completing S102, the control processing unit establishes two display capability response objects based on the source end identifiers of the two video sources, and writes the same allowed output mode and mode allowed range into the two DDC proxy buffers. When the first DDC proxy can be read by the conference host and the second DDC proxy can be read by the backup laptop, the response status of the corresponding two display capability response objects is set to valid. If the second DDC proxy is successfully written but the read response is not returned, the second display capability response object is still retained, but its response status is invalid. In S2, when providing display capability response to the second video source, this status is directly referenced, and in S3, when calculating the status inversion rate, the response status is sampled again.

[0042] At this point, S1 has completed the acquisition, integrity verification, capability parsing, and generation of display capability response objects based on the source end identifiers of the dual video sources for the target display link. The output includes the display capability response object corresponding to each source end identifier, the capability source, the allowed output mode, the allowed mode range, and the response activation status. The display capability response object is used by S2 to provide display capability responses to the video source to be switched; the allowed output mode and the allowed mode range are used by S3 to calculate the mode deviation value; and the response activation status is used by S3 to calculate the state inversion rate. It can also be used as the object to be adjusted when S4 performs degradation configuration.

[0043] S1 has generated a display capability response object according to the source identifiers of the dual video sources and completed the writing confirmation of the allowed output mode, the allowed mode range, and the response activation status. S2 starts based on this result. The video source to be switched has not yet been connected to the target display link, but it still needs to obtain a display capability response consistent with the target display link and form a display connection awareness state that can be sampled by S3. Therefore, S2 undertakes the processing tasks of providing the corresponding response, maintaining connection awareness, and preparing to trigger the output mode.

[0044] S201: Display capability response object matching and response path access.

[0045] S2 takes the display capability response object output by S1, the source end identifiers of the dual video sources, and the distinction between the current video source and the video source to be switched as the starting point for processing. The control processing unit first reads the source end identifier of the video source to be switched pointed to in the switching request, and then searches for an object that matches the source end identifier in the display capability response object formed by S1 to obtain the display capability response object corresponding to the video source to be switched.

[0046] After the control processing unit completes object matching, it first reads the response status of the display capability response object. When the response status is valid, it sets the reading path corresponding to the display capability response object to an accessible state and keeps the physical video path of the target display link connected to the current video source. When the response status is invalid, the control processing unit rewrites the display capability response object into the DDC proxy, AUX proxy, EDID cache, DisplayID cache, MCU register, or FPGA mapping table corresponding to the video source to be switched. After confirming that the write address, data block length, and read response are consistent, the response status is updated to valid. This update result still belongs to the display capability response object generated by S1, and no new display capability object is generated.

[0047] For HDMI video sources, the control processing unit enables the DDC agent on the side of the video source to respond to the EDID read request and outputs the preloaded HPD valid state corresponding to the DDC agent or EDID cache to the video source to be switched during the preloading phase. The preloaded HPD valid state indicates that the video source to be switched can read the display capability response object, but does not indicate that the video path of the target display link has been connected to the video source to be switched. After the target display link is connected in S4, the control processing unit synchronizes the preloaded HPD valid state to the target display link HPD valid state after connection. For DisplayPort or USB-C Alt Mode video sources, the control processing unit enables the AUX agent on the side of the video source to respond to the display capability read request and keeps the bit in the link status register corresponding to the available state of the virtual display end as readable. Thus, even when the video source to be switched is not connected to the video transmission path of the target display link, it can still read the display capability response corresponding to the target display link according to its own interface protocol.

[0048] In one implementation of dual-host switching in a vehicle cockpit, the first vehicle controller is outputting images to the central control screen, while the second vehicle controller is designated as the video source to be switched. The control processing unit locates the display capability response object generated by S1 based on the source identifier of the second vehicle controller and provides the object to the AUX proxy on the second vehicle controller side. At this time, the video path of the central control screen remains connected to the first vehicle controller, and the second vehicle controller can only read the display capability response and cannot directly output video streams to the central control screen.

[0049] S202: Display connection sensing state maintenance and state sequence formation.

[0050] After enabling the video source to be switched to read the display capability response in S201, the control processing unit begins to maintain the display connection awareness state of the video source to be switched. This processing takes the response activation status in the display capability response object, the HPD valid status on the side of the video source to be switched, the DDC response available status, the AUX response available status, the display capability response readable status, or the virtual display terminal available status as input, and selects the corresponding input item according to the interface type.

[0051] The control processing unit uses a finite state machine to form the display connection awareness state. The finite state machine includes at least an unaware state, a readable state, and an awareness-valid state. An unaware state indicates that the connection condition for a readable display capability response has not yet been formed on the side of the video source to be switched; a readable state indicates that the DDC response or AUX response on the side of the video source to be switched is valid, but the readable display capability response state has not yet synchronized with the effective response state; an awareness-valid state indicates that both the readable display capability response state and the effective response state are valid at the same sampling time. At each sampling time, the control processing unit reads the connection awareness input vector. If the read channel is unavailable, the state remains or transitions to the unaware state; if the read channel is available and the display capability response is readable, but the effective response state is invalid, the state transitions to the readable state; if the read channel is available, the display capability response is readable, and the effective response state is valid, the state transitions to the awareness-valid state, and the display connection awareness state at that sampling time is recorded as valid. If, after being in the awareness-valid state, the read channel becomes unavailable or the display capability response becomes unreadable, the state transitions to the unaware state, and the display connection awareness state at that sampling time is recorded as invalid.

[0052] The input to the finite state machine is a connectivity-aware input vector arranged according to sampling times. The sampling times are generated by the control processing unit according to a fixed control cycle, which is determined during factory calibration or on-site debugging and is consistent with the sampling interval of the predetermined observation window in S3. Only one connectivity-aware input vector is generated for each sampling time and stored synchronously with the response activation state at the same sampling time. In HDMI scenarios, the connectivity-aware input vector consists of the pre-loaded HPD valid state, DDC response available state, and display capability response readable state in sequence; in DisplayPort or USB-C AltMode scenarios, the connectivity-aware input vector consists of the AUX response available state, display capability response readable state, and virtual display terminal available state in sequence. The control processing unit reads the connectivity-aware input vector at each sampling time and synchronously confirms it with the response activation state in the display capability response object to obtain the display connectivity-aware state at that sampling time.

[0053] After the displayed connection sensing state is formed, the control processing unit writes it into the displayed connection sensing state sequence according to the sampling order. The displayed connection sensing state sequence refers to a state record composed of the displayed connection sensing state sequence at multiple sampling times, used by S3 to continuously sample and calculate the state inversion rate within the observation window. Each item in the displayed connection sensing state sequence is bound and saved with the response effective state at the corresponding sampling time. When S3 captures the predetermined observation window, it captures both the displayed connection sensing state and the response effective state according to the sampling time.

[0054] In one implementation of a conference matrix switching mechanism, a backup laptop is the video source to be switched, and the conference screen is the target display link. After the control processing unit provides the display capability response object generated in S1 to the DDC agent on the backup laptop side, it continuously reads the pre-loaded HPD valid status, DDC response, and display capability response readable results. When the backup laptop can read the EDID cache and the response status is valid, a valid display connection awareness status is written at the corresponding sampling time. When the DDC response is briefly lost, an invalid display connection awareness status is written at the corresponding sampling time. This state change does not trigger a physical switch but forms the input basis for S3 to calculate the state inversion rate.

[0055] S203: Prepare output mode based on display capability response object trigger.

[0056] After the display connection awareness state sequence is formed in S202, the control processing unit triggers the video source to be switched to complete the output mode preparation based on the display connection awareness state and the display capability response object. This process takes the display capability response object corresponding to the video source to be switched, the display connection awareness state sequence, and the response activation status as input. It first confirms that the video source to be switched is in a connection awareness condition where the display capability response can be read, and then allows the video source to be switched to read the allowed output modes and the allowed range of modes according to its graphics output control logic.

[0057] After reading the display capability response object, the video source to be switched selects the combination of resolution, refresh rate, pixel clock, color format, and color depth that it can output from the allowed output modes, and writes this combination into its own display output control path to form a pending output state. The control processing unit does not change the allowed output modes and mode allowable range generated by S1, but only provides consistent read content to the video source to be switched through DDC proxy, AUX proxy, EDID cache, DisplayID cache, MCU register, or FPGA mapping table, so that the mode selection of the video source to be switched is restricted to the boundary that the target display link can bear.

[0058] When the video source to be switched completes the display capability reading and begins generating synchronization signals, pixel clocks, or continuous valid frame candidate outputs, the control processing unit records the output mode preparation result as formed. The output mode preparation result refers to the result of the video source to be switched completing mode selection and entering the output state based on the display capability response object. It is used to indicate that S3 can detect the stable output state. The output mode preparation result and the display connection perception state sequence are output to S3 together. The output mode preparation result indicates that the video source to be switched has the basis for detecting the actual output mode, while the display connection perception state sequence indicates the source of changes in the connection validity state within the observation window.

[0059] For example, in an implementation where two industrial control hosts share a single monitor, after the backup industrial control host reads the display capability response object provided by S1, it selects a 1920×1080, 60Hz output combination consistent with the allowed output mode and begins generating the corresponding pixel clock and synchronization signal. Even before the backup industrial control host connects to the monitor's video path, the control processing unit records its output mode preparation result as complete, while simultaneously retaining the display connection perception state sequence on the backup industrial control host side. Subsequently, S3 can detect the actual output mode of the backup industrial control host based on this, and perform acceptance state identification by combining the allowed output mode, mode allowable range, and response effectiveness status of S1.

[0060] At this point, S2 has completed the matching of the display capability response object corresponding to the video source to be switched, the provision of display capability response before access, the maintenance of display connection awareness status, and the output mode preparation triggering process. The output results include the display connection awareness status, the display connection awareness status sequence, and the output mode preparation result corresponding to the video source to be switched; among them, the display connection awareness status and the response effective status are used by S3 to calculate the state inversion rate, the output mode preparation result is used by S3 to start the output stability state detection, and the display capability response object can still serve as the basis for S2 to provide display capability response again after S4 performs downgrade configuration.

[0061] S1 has output the display capability response object, allowed output mode, allowed mode range, and response activation status corresponding to the video source to be switched. S2 has generated the display connection awareness status, display connection awareness status sequence, and output mode preparation result. Although the display capability of the video source to be switched has been read before access, it is still necessary to determine whether its actual output mode can be accepted by the target display link. S3 detects the output stability status based on the result and generates a switching permission result through acceptance status identification.

[0062] S301: Output stability detection and actual output mode extraction.

[0063] S3 uses the output mode preparation result from S2 as the detection start condition and the display capability response object corresponding to the video source to be switched as the mode comparison basis. The control processing unit first reads the output mode preparation result. If the output mode preparation result indicates that the video source to be switched has completed mode selection and entered the output state, then the video reception detection path on the side of the video source to be switched is sampled. The sampling objects include the state quantities that can be detected by the interface, such as the pixel clock stabilization state, line synchronization state, field synchronization state, continuous valid frame state, color format state, and receiver chip lock state. The video reception detection path is a detection path set on the side of the video source to be switched and isolated from the main video path of the target display link. It can be formed by the bypass detection port of the video receiver chip, the synchronization detection unit in the programmable logic, or the pre-stage detection unit of the high-speed channel selector. This video reception detection path is only used to read the pixel clock, synchronization signal, valid frame state, and color format state that the video source to be switched has generated before access, and does not change the physical connection state of the target display link currently connected to the current video source.

[0064] The detection period is the same as the predetermined observation window in S3, or a continuous sampling period shorter than the predetermined observation window as calibrated by the equipment at the factory, and is used to confirm that the actual output mode is resolvable before the mode deviation value is calculated. During the detection process, the control processing unit first confirms that the video source to be switched has generated a resolvable video output signal, and then extracts the actual output mode from the video output signal. The extraction order of the actual output mode is as follows: the resolution is determined by the horizontal synchronization state and the vertical synchronization state, the refresh rate is determined by the continuous effective frame interval, the pixel clock is read from the pixel clock stabilization state, and the color format and color depth are determined by the color format state and the receiver chip lock state. The extracted actual output mode retains only the mode components that can be compared with the allowed output modes in S1, and is used as the input for S302 to calculate the mode deviation value.

[0065] When the sampled video output signal continuously possesses pixel clock, horizontal sync, and vertical sync within the detection period, the control processing unit records the stable output state as detectable and outputs the actual output mode. When only the display connection sensing state can be read within the detection period but no resolvable video output signal can be obtained, the control processing unit retains the display connection sensing state sequence formed in S2, but records the actual output mode as empty and causes subsequent mode deviation values ​​to enter the maximum deviation path. This path belongs to the receiving state recognition input processing of S3 and does not change the display capability response object generated by S1.

[0066] In a dual-host switching implementation for medical displays, the current host continuously outputs images to the diagnostic display, while the backup host serves as the video source to be switched. After reading the display capability response object via S2, the backup host begins outputting candidate video signals. The control processing unit reads the pixel clock and synchronization signal from the chip on the backup host side and parses the resolution, refresh rate, and color format. If the synchronization signal is continuously valid, an actual output mode is formed and the process proceeds to S302; if the synchronization signal is missing, the actual output mode is recorded as empty and the process enters the maximum deviation path.

[0067] S302: Calculate the mode deviation value based on the allowed output modes and the allowed mode range.

[0068] After obtaining the actual output mode in S301, the control processing unit reads the display capability response object corresponding to the source identifier of the video source to be switched in S1, and obtains the allowed output modes and the allowed range of modes from it. The control processing unit aligns the mode component of the actual output mode with the same category component of each allowed output mode item by item, forming a mode component comparison sequence; the mode component comparison sequence refers to the comparison input composed of the components involved in the comparison from resolution, refresh rate, pixel clock, color format, and color depth in a fixed order, used to calculate the degree of deviation of the actual output mode from the allowed output modes.

[0069] For numerical model components, the normalized deviation The value is obtained by dividing the absolute value of the difference between the actual output mode component and the allowed output mode component by the width of the corresponding mode's allowed range; if the actual output mode component falls within the allowed range of the corresponding mode, then... Record it as 0; if it exceeds the allowed range of the corresponding mode, then divide the difference exceeding the boundary by the width of the allowed range of the corresponding mode to obtain the result. The allowable range width for a given mode is the difference between the upper and lower allowable limits of that mode component; when the allowable range of a mode is a single-point range, if the actual output mode component equals that single-point value, then... Record it as 0, otherwise It is denoted as 1. Wherein, For the first The first allowed output mode The normalized deviation of the first mode component; The first allowed output mode originates from the allowed output mode of S1; the second... Each mode component is derived from the comparable components in the actual output mode and the allowed output modes; the allowed mode range width is derived from the allowed mode range of the corresponding allowed output mode in S1.

[0070] For resolution matching, if the actual output mode resolution matches the allowed output mode resolution, the normalized deviation is recorded as 0. If they do not match, the deviation is calculated separately in the width and height directions, and the larger value is taken. When the resolutions do not match, the width deviation is the absolute value of the difference between the horizontal pixel count of the actual output mode and the horizontal pixel count of the allowed output mode divided by the corresponding horizontal pixel count of the allowed output mode. The height deviation is the absolute value of the difference between the vertical pixel count of the actual output mode and the vertical pixel count of the allowed output mode divided by the corresponding vertical pixel count of the allowed output mode. The larger of the two values ​​is used as the normalized deviation of the resolution component. For enumerated mode components such as color format, the normalized deviation is recorded as 0 when compatible and as 1 when incompatible. For color depth components, if the color depth is recorded in the acceptable set in the display capability response object, it is treated as an enumerated mode component. If the color depth level boundary is recorded in the mode's allowed range, it is treated as a numerical mode component, and the normalized deviation is formed by the difference between the actual color depth and the allowed color depth boundary. If the actual output mode of S301 is missing, then all mode components participating in the comparison are treated as having the maximum deviation.

[0071] Regarding the first One allowed output mode, the intermediate calculation of the mode deviation value is: ; in, For the first The deviation value corresponding to each allowed output mode is used to represent the overall degree of deviation of the actual output mode from the allowed output mode. For the first The number of mode components participating in the comparison under each allowed output mode is derived from the set of components that can be compared with the actual output mode and the allowed output mode. For the first The first allowed output mode The normalized deviation of each mode component. The control processing unit calculates the normalized deviation for each allowed output mode. And take the minimum value among them as the pattern deviation value: ; in, This is the pattern deviation value, used as input to the Bayesian state decision model; The number of allowed output modes in the display capability response object is derived from the allowed output modes of the display capability response object in S1. The control processing unit takes multiple... The minimum value is chosen because the target display link only needs to handle the closest match between the actual output mode and any allowed output mode. After the calculation is completed, the control processing unit establishes a correspondence between the mode deviation value and the allowed output mode that generated the minimum deviation value, serving as a traceable mode matching basis when S4 generates the degraded configuration.

[0072] In the conference matrix switching implementation, the laptop to be switched outputs a 1920×1080, 60Hz video signal. The allowed output mode formed in S1 includes this resolution and refresh rate combination. The control processing unit compares the pixel clock, color format, and color depth with the allowed range of the mode. If the color format is compatible and the pixel clock is within an acceptable range, the corresponding normalization deviation is small, and the mode deviation value is output from the allowed output mode. If the laptop to be switched is changed to output a resolution that the target display link has not declared to support, the resolution component is included in the deviation calculation, and the mode deviation value increases accordingly.

[0073] S303: Calculate the state inversion rate based on the displayed connection sensing state and the response effective state.

[0074] After obtaining the mode deviation value in S302, the control processing unit extracts sampling records within a predetermined observation window from the display connectivity sensing state sequence output by S2, and simultaneously reads the response activation status of the display capability response object in S1 at the same sampling time. The predetermined observation window refers to a continuous sampling period used to evaluate the frequency of changes in the effective connectivity state before switching. Its length and sampling interval are determined during equipment factory calibration or on-site debugging, and are consistent with the calibration sample acquisition conditions of the Bayesian state decision model. Within this predetermined observation window, the control processing unit continuously acquires display connectivity sensing states and response activation states, ensuring that the state flip rate has the same time scale as the state change frequency used during model training.

[0075] The control processing unit constructs a sequence of valid connection states according to the sampling time sequence. The valid connection state sequence is a binary sequence composed of the valid connection states at each sampling time, used to calculate the state inversion rate. When the displayed connection sensing state and the response activation state are both valid at a certain sampling time, the valid connection state at that sampling time is recorded as 1; when the displayed connection sensing state or the response activation state is invalid, the valid connection state at that sampling time is recorded as 0. After the valid connection state sequence is formed, the control processing unit compares the valid connection states at adjacent sampling times one by one, counting the number of times a state changes from 1 to 0 or from 0 to 1.

[0076] The state transition rate is calculated using the following formula: ; in, The state flip rate is used as input to the Bayesian state decision model. The number of sampling times within a predetermined observation window is determined by the sampling interval and the length of the observation window. For the first The connection validity status at each sampling time is obtained by combining the display connection sensing status and response validity status at the same sampling time; This indicates the valid connection state at the previous sampling time. The state inversion indicator is set to 1 when adjacent sampling times have different valid states and 0 when they are the same. If the number of sampling times within the predetermined observation window is less than 2, the control processing unit will output the state inversion rate as 1 and restrict the switching permission result to not allowing the switching to be performed.

[0077] In the dual-controller switching implementation for the vehicle cockpit, the vehicle controller to be switched reads the display capability response object through the AUX proxy. The control processing unit continuously reads the AUX response availability status, display capability response readability status, and response activation status within the observation window; if these states repeatedly switch between valid and invalid states between multiple sampling times, the sequence of valid states generates multiple flips, increasing the state flip rate; if they remain valid at all sampling times, the state flip rate approaches 0. This result, along with the mode deviation value output in S302, enters S304.

[0078] S304: Bayesian state determination and generation of license switching results.

[0079] After S302 outputs the mode deviation value and S303 outputs the state flip rate, the control processing unit combines these two values ​​in a fixed order to form a state determination input vector. This state determination input vector is a two-dimensional input consisting of the mode deviation value and the state flip rate, used to input the Bayesian state determination model. The state categories of the Bayesian state determination model include acceptable states, stabilizing states, and abnormal states. The model parameters are established using calibration samples, which include different video sources, response objects with different display capabilities, mode deviation values, state flip rates, and actual switching results.

[0080] When establishing the Bayesian state determination model, the control processing unit treats each calibration switch record as a calibration sample. The calibration sample includes the mode deviation value, state inversion rate, and actual switch result. The actual switch result is marked according to whether continuous valid frames are formed after access, whether display resynchronization occurs, and whether resolution fallback occurs. Samples that form continuous valid frames after access and do not experience display resynchronization or resolution fallback are marked as acceptable states. Samples that form valid images after access but experience short-term resynchronization or short-term invalid frames are marked as pending stabilization states. Samples that do not form valid images after access, experience safe image fallback, or experience output mode fallback are marked as abnormal states.

[0081] In one implementation, the Bayesian state decision model employs a Naive Gaussian Bayes model. For state categories... The mean mode deviation value is obtained by statistically analyzing the pattern deviation value sample sequence and the state flip rate sample sequence in the calibration samples belonging to this state category. Model deviation variance Mean state flip rate and state flip rate variance For the input pattern deviation value and state flip rate , No. The likelihood distribution for each state category is calculated using the following formula: ; in, This is the mode deviation value output by S302; The state transition rate output by S303; For the first One state category; For the first The mean of the pattern deviation values ​​under each state category; For the first Variance of pattern deviation values ​​under each state category; For the first The mean state flip rate under each state category; For the first The variance of the state flip rate under each state category. The mean and variance above are obtained from the statistics of the labeled samples for the corresponding state categories. Prior probabilities of each state category The variance is determined by the ratio of the number of calibrated samples belonging to that state category to the total number of calibrated samples. If the variance of the mode deviation or the variance of the state reversal rate under a certain state category is 0, the control processing unit uses the preset minimum variance instead of that variance in the calculation. The preset minimum variance is one-tenth of the minimum non-zero variance of the corresponding feature in all calibrated samples. If there is no non-zero variance, it is 0.0001.

[0082] The Bayesian state decision model calculates the posterior probability of the video source to be switched belonging to each state category based on the state decision input vector. The calculation relationship is as follows: ; in, For the mode deviation value and state flip rate When it is known, the video source to be switched belongs to the first... The posterior probability of each state category; For the first Joint likelihood of pattern deviation and state inversion rate for each state category; For the first The prior probabilities of each state category are calculated; the denominator is a normalization term for the probabilities of all state categories, used to ensure that the sum of the posterior probabilities of each state category is 1. The order of summation for state categories is fixed as: acceptable state, stabilizing state, and abnormal state. The control processing unit reads the prior probabilities and likelihood distributions of each state category in this order. The control processing unit outputs the posterior probability corresponding to the acceptable state as the acceptability probability.

[0083] In another embodiment, the Bayesian state decision model is implemented using a Bayesian neural network. The input to this Bayesian neural network is a state decision input vector, and the output is the posterior probability corresponding to the acceptable state, the stabilizing state, and the abnormal state. The posterior probability corresponding to the acceptable state is used as the acceptance probability. The Bayesian neural network includes one input layer, two hidden layers, and one output layer. The input layer includes two input nodes, the first hidden layer includes eight neurons, the second hidden layer includes six neurons, and the output layer includes three output nodes. Both the first and second hidden layers use a linear transformation followed by a modified linear activation function, and the output layer uses a normalized exponential function to output the probability distribution of the three state categories.

[0084] In the Bayesian neural network, the weights and biases are represented using Gaussian distributions. At the start of training, the mean and standard deviation of each weight distribution are initialized to 0, and the mean and standard deviation of each bias distribution are initialized to 0.02. The training dataset consists of samples collected from different video sources, display capability response objects, and different actual switching results. Each sample includes a mode deviation value, state flip rate, and an actual switching result label. The actual switching result label includes a usable state, a stabilizing state, and an abnormal state. Samples that form continuous valid frames after connection without display resynchronization or output mode rollback are labeled as usable states. Samples that form valid frames after connection but experience short-term resynchronization or short-term invalid frames are labeled as stabilizing states. Samples that do not form valid frames after connection, experience safe frame rollback, or experience output mode rollback are labeled as abnormal states.

[0085] The training dataset contains at least 3000 samples, with at least 500 samples for each state category. Before training, the pattern deviation and state flip rate are normalized to the interval between 0 and 1 using the minimum and maximum values ​​in the training dataset, respectively. When new calibration samples are added in the field, the same normalization boundary is used for processing. The model is trained using mini-batch gradient descent with a batch size of 64, 100 training epochs, and an initial learning rate of 0.001. The loss function consists of the state category cross-entropy loss and a divergence constraint term for the weight distribution relative to the prior distribution. The prior distribution is a Gaussian distribution with a mean of 0 and a standard deviation of 1; the coefficient of the divergence constraint term is the reciprocal of the total number of training samples. After training, the control processing unit saves the mean and standard deviation of the weight distribution and bias distribution of each layer, and performs multiple forward inferences on the same state decision input vector when needed, using the average of the multiple output probabilities as the posterior probability of each state category. During forward inference, the control processing unit samples a set of weight and bias values ​​from each layer's weight and bias distributions according to their corresponding means and standard deviations, and completes one forward inference cycle using these weight and bias values. The number of forward inference cycles for the same state decision input vector is 30. Each of the 30 forward inference cycles yields a probability distribution for one of the three state categories. The control processing unit averages the 30 probability values ​​for the same state category as the posterior probability of that state category. When the maximum value of the pattern deviation or state flip rate in the training dataset equals the minimum value, the normalization result of the corresponding feature is set to 0, and the normalization boundary of that feature is recorded as a single-value boundary.

[0086] The control processing unit then compares the acceptance probability with the switching level range. The switching level range is determined by factory calibration or on-site debugging and is stored in relation to the actual switching success rate, black screen occurrences, resynchronization occurrences, and output mode rollback occurrences. In one implementation, the control processing unit sorts the calibration samples according to the acceptance probability from smallest to largest and records the actual switching result for each sample. The lower quartile of the acceptance probability in samples where no black screen, no resynchronization, and no output mode rollback occurred is taken as the lower boundary of the allowed switching level; the upper quartile of the acceptance probability in samples where a black screen, safety screen rollback, or output mode rollback occurred is taken as the upper boundary of the prohibited switching level; the range between the upper boundary of the prohibited switching level and the lower boundary of the allowed switching level is taken as the waiting-to-stabilize level. If the two boundaries overlap, the higher boundary confirmed by on-site debugging is taken as the lower boundary of the allowed switching level. The lower boundary of the allow switching level is used to determine whether the acceptance probability is sufficient to perform a switching; the upper boundary of the prohibit switching level is used to determine whether the acceptance probability is low enough to prohibit switching; the wait for stability level is used to indicate that the acceptance probability is between the two, and it is necessary to continue to maintain the current video source or re-prepare the output mode.

[0087] When the acceptance probability falls into the allowed switching level, the control processing unit generates a switching permission result that allows the switching to proceed; when the acceptance probability falls into the waiting for stability level or the prohibited switching level, the control processing unit generates a switching permission result that disallows the switching to proceed. The switching permission result carries the mode deviation value, state inversion rate, and acceptance probability, enabling S4 to reference the decision source of S3 when maintaining the current video source, outputting a safe picture, or degrading the display capability response object.

[0088] In the dual-host switching implementation of industrial control, when the actual output mode of the standby industrial control host is close to the allowed output mode and the displayed connection perception status remains stable within the observation window, the Bayesian state determination model outputs a high acceptance probability, and the control processing unit generates a switching permission result that allows the switching to be performed; if the standby industrial control host outputs a video signal, but the DDC response is repeatedly lost within the observation window, the state inversion rate increases, and the acceptance probability falls into the waiting stability level or the prohibited switching level, the control processing unit generates a switching permission result that does not allow the switching to be performed, and outputs the result to S4.

[0089] At this point, S3 has completed the detection of the stable output state of the video source to be switched, extraction of the actual output mode, calculation of the mode deviation value, calculation of the state inversion rate, and Bayesian state determination. The switching permission result output by S3 includes whether the switching is allowed or not, and carries the mode deviation value, state inversion rate, and acceptance probability; these results directly inform S4's decision on whether to connect the video source to be switched, maintain the current video source, output a safe image, or downgrade the display capability response object.

[0090] S3 has already output the handover permission result, along with the mode deviation value, state inversion rate, and acceptance probability. Based on this determination result, S4 performs the final access control of the target display link. Although the video source to be switched has completed display capability reading and output mode preparation, the target display link will only connect to the video source to be switched if the handover permission result indicates that the handover is allowed. If the handover permission result indicates that the handover is not allowed, S4 will choose to maintain the current video source, output a safe image, or downgrade the display capability response object based on the determination source of S3.

[0091] S401: Parsing of license switching results and determination of processing path.

[0092] S4 takes the switching permission result output by S3 as the starting point for processing and reads the mode deviation value, state inversion rate, and acceptance probability carried by the switching permission result. The control processing unit first confirms the source end identifier of the video source to be switched corresponding to the switching permission result, and then associates the source end identifier with the display capability response object generated by S1, the display connection perception state formed by S2, and the connection state of the current video source to form the basis for handling before the target display link is accessed.

[0093] The control processing unit determines the handling path based on the category of the handover permission result. When the handover permission result indicates that the handover is allowed, the handling path is determined to be to connect the target display link to the video source to be switched. When the handover permission result indicates that the handover is not allowed and its refined result is "waiting for stability", the control processing unit prioritizes maintaining the current video source and continues to retain the display capability response object and display connection awareness status corresponding to the video source to be switched. When the handover permission result indicates that the handover is not allowed and its refined result is "handover prohibited", the control processing unit further reads the mode deviation value and state inversion rate, and performs a cause attribution determination.

[0094] When the switching permission result indicates that switching is not allowed, the control processing unit first reads the mode deviation value and state toggle rate, and compares them with the mode deviation boundary and toggle rate boundary, respectively. The mode deviation boundary is obtained by taking the quartile of the mode deviation values ​​in the calibration samples that cause display resynchronization or output mode rollback in ascending order. The toggle rate boundary is obtained by taking the quartile of the state toggle rates in the calibration samples that cause HPD jitter, DDC short-term unresponsiveness, or AUX response abnormality in ascending order. When the number of calibration samples used to form the mode deviation boundary is less than 10, the control processing unit reads the mode deviation boundary calibrated by the device at the factory; when the number of calibration samples used to form the toggle rate boundary is less than 10, the control processing unit reads the toggle rate boundary calibrated by the device at the factory. After new calibration samples are formed during field debugging, the control processing unit recalculates the corresponding boundaries using the field debugging samples and replaces the factory calibration boundaries. If the state flip rate is not less than the flip rate boundary and the mode deviation value is less than the mode deviation boundary, the reason for disallowing switching is attributed to repeated changes in the connection valid state. If the mode deviation value is not less than the mode deviation boundary, the reason for disallowing switching is attributed to the actual output mode deviating from the allowed output mode. If both the mode deviation value and the state flip rate reach their respective boundaries, the current video source or output safe image is maintained first, and then a downgrade configuration is performed on the display capability response object. The mode deviation boundary is used to determine whether the mode deviation value has reached the risk level that would cause the display to resynchronize or the output mode to revert. Its source is the mode deviation value sequence in the calibration sample. The flip rate boundary is used to determine whether the frequency of changes in the connection valid state has reached the risk level of HPD jitter, DDC short-term loss of response, or AUX response anomaly. Its source is the state flip rate sequence in the calibration sample.

[0095] In one implementation of an industrial control dual-host shared monitor, the current video source is outputting production line monitoring footage, and the video source to be switched to is the backup industrial control host. If the S3 output allows switching, the control processing unit determines the handling path as switching access; if the S3 output does not allow switching and the state inversion rate corresponds to the waiting stability level, the control processing unit does not change the video input source of the monitor and maintains the current video source image; if the S3 output does not allow switching and the mode deviation value indicates that the backup industrial control host output mode exceeds the allowed mode range, the control processing unit determines the handling path as degrading configuration.

[0096] S402: Allow target display link access during handover.

[0097] After S401 determines that the target display link is connected to the video source to be switched, the control processing unit uses the source identifier of the video source to be switched, the output mode preparation result formed in S2, and the switching permission result generated in S3 as the basis for execution. The control processing unit first keeps the display capability response object on the side of the video source to be switched readable and keeps its display connection awareness state valid, so that the video source to be switched continues to use the output mode formed based on the display capability response object at the moment of connection.

[0098] The control processing unit then performs video path switching according to the signal direction of the target display link. For HDMI links, the control processing unit controls the video switching device to switch the TMDS or FRL data channel from the current video source to the video source to be switched, and synchronizes the preloaded HPD valid state on the video source side to the valid state of the target display link after access. For DisplayPort or USB-C Alt Mode links, the control processing unit controls the high-speed channel selector to connect the main link to the video source to be switched, and maintains the configuration in the AUX proxy or link status register corresponding to the readable state of the display capability response. During the switching process, the allowed output mode and mode allowed range generated in S1 are not changed, and the video source to be switched continues to output the video stream according to the output mode preparation result completed in S2.

[0099] After the target display link is connected, the control processing unit reads the synchronization lock status and valid frame status after the connection to form a handover execution result. The handover execution result refers to the execution record after the target display link has connected to the video source to be switched, indicating whether the connection has been completed. When the target display link receives a valid video stream from the video source to be switched, the handover execution result is recorded as connection complete, and the video source to be switched is updated to the current video source. When no valid video stream is formed after connection, the control processing unit records the handover execution result as an connection anomaly and switches to the safe screen output path in S403. The connection anomaly is only used as an abnormal protection path after S3 has determined that handover is allowed. Its trigger record, along with the corresponding mode deviation value, state inversion rate, and acceptance probability, is saved as a subsequent calibration sample and is not used as the normal processing result for allowed handover paths.

[0100] In the conference matrix switching implementation, the backup laptop reads the display capability response object corresponding to the conference screen via S2, and obtains a switching permission result allowing the switching to be performed via S3. While the conference screen is still displaying the current conference host screen, the control processing unit switches the output of the video switching device to the backup laptop, and the backup laptop continues to output the screen according to the selected resolution and refresh rate; when the conference screen input detects consecutive valid frames, the switching execution result is recorded as access complete.

[0101] S403: Do not allow current video source preservation and safe screen output during switching.

[0102] If S401 determines that the handover permission result indicates that handover is not allowed, and the handling path does not enter the downgrade configuration or the downgrade configuration has not yet been completed, the control processing unit uses the connection status of the current video source, the current reception status of the target display link, and the state inversion rate output by S3 as the execution basis. The control processing unit first maintains the video path connection between the target display link and the current video source, and keeps the display output status of the current video source unaffected by the connection perception change of the video source to be switched.

[0103] When the current video source can still provide a valid video stream to the target display link, the control processing unit determines the outcome as maintaining the current video source and continues to provide the display capability response object generated in S1 to the video source to be switched, keeping the video source to be switched in the pre-access preparation state. At this time, the video source to be switched is not connected to the target display link, and the display connection perception state formed in S2 can still be sampled. S3 can reuse this state source in the next access state identification.

[0104] When the current video source can no longer provide a valid video stream, or when the reason for not allowing switching is accompanied by the target display link potentially receiving invalid timing, abnormal video streams, or unstable signals, the control processing unit initiates a safety screen output path. The safety screen is output from the video generation unit within the dual-channel video switching device to the target display link, and its content is one of the following: a solid color screen, a prompt screen, a current source freeze screen, or a preset maintenance screen. During the safety screen output, the display capability response object corresponding to the video source to be switched remains in the DDC proxy, AUX proxy, EDID cache, DisplayID cache, MCU register, or FPGA mapping table, for the video source to be switched to continue reading.

[0105] In the dual-controller switching implementation for the vehicle cockpit, if the AUX response of the vehicle controller to be switched repeatedly fails within the observation window, the S3 output will not allow switching to proceed. The control processing unit maintains the connection between the central control screen and the current vehicle controller, while the vehicle controller to be switched continues to read the display capability response object and remains in a ready-to-output state. If the current vehicle controller simultaneously loses a valid screen, the control processing unit outputs a preset maintenance screen to the central control screen via the internal video generation unit, without connecting the central control screen to the vehicle controller to be switched.

[0106] S404: Display capability response object downgrade configuration and redeployment.

[0107] When S401 determines that the disallowed switching is mainly due to the actual output mode deviating from the allowed output mode, the control processing unit uses the display capability response object generated by S1, the mode deviation value output by S3, and the allowed output mode that produces the minimum deviation value as the basis for degradation configuration. Degradation configuration does not change the physical access object of the target display link, but rather conservatively processes the allowed output mode or mode allowable range in the display capability response object corresponding to the video source to be switched.

[0108] The control processing unit first locates the allowed output modes corresponding to the mode deviation values ​​from the display capability response objects, and then performs degradation configuration according to the deviation components. The control processing unit determines the degradation order according to the normalized deviation corresponding to the mode deviation value. If only one mode component has a normalized deviation of the maximum value, the degradation configuration is performed on that mode component first; if multiple mode components have the same normalized deviation and are all the maximum value, the degradation configuration is performed in the order of maximum pixel clock, maximum refresh rate, color depth, color format, HDR capability, and audio format complexity. After each degradation configuration is performed, the control processing unit regenerates the allowed output modes and the allowed mode range, and writes the updated display capability response object in place into the response path corresponding to the video source to be switched.

[0109] Specifically, when the refresh rate component deviation leads to an increase in the mode deviation value, the maximum refresh rate in the allowed output modes is reduced; when the pixel clock component deviation leads to an increase in the mode deviation value, the maximum pixel clock is limited; when the color depth or color format components are incompatible, the color depth is reduced or the color format compatibility is limited; when HDR capability, variable refresh rate capability, or audio format complexity causes the video source to be switched to select an unacceptable output mode, the corresponding capability is turned off or the audio format complexity is reduced; when multiple components deviate simultaneously and cannot form an acceptable boundary through local component conservative processing, the capability source is updated to a pre-stored conservative template or an abnormal fallback template, and the allowed output modes and mode allowable ranges in the display capability response object are replaced accordingly.

[0110] Degradation configuration is not a fixed template replacement of the display capability response object. Instead, it determines the degradation component based on the mode deviation value output by S3 and the corresponding normalized deviation, and writes the updated display capability response object in situ into the response path corresponding to the same source identifier. This allows the video source to be switched to re-prepare its output mode based on the updated allowed output modes and mode allowable ranges. "Writing in situ" means replacing the readable content of the display capability response object in the response path corresponding to the same source identifier without changing the correspondence between the source identifier and the video source to be switched.

[0111] After the downgrade configuration is completed, the control processing unit writes the updated display capability response object in place to the DDC proxy, AUX proxy, EDID cache, DisplayID cache, MCU register, or FPGA mapping table corresponding to the video source to be switched, and reconfirms the response effectiveness status. Once the response effectiveness status is updated to valid, the updated display capability response object serves as the basis for S2 to re-provide the display capability response, enabling the video source to be switched to prepare for the output mode again. After the updated display capability response object is written, the control processing unit rereads the write address, data block length, and read response, and updates the response effectiveness status corresponding to the source identifier accordingly. When the response effectiveness status is valid, the control processing unit performs a re-providal processing on the display capability response read path of the video source to be switched, enabling the video source to be switched to reread the updated allowed output mode and mode allowable range. If the response effectiveness status is not restored to valid, the control processing unit maintains the current video source or outputs a safe screen.

[0112] In the dual-host switching implementation of medical displays, after the standby host reads the display capability response object, it selects a high color depth output mode that the target display link cannot handle. S3, due to a high mode deviation value, is not allowed to perform the switching. The control processing unit locates the allowed output mode corresponding to this color depth component, adjusts the color depth handling boundary in the display capability response object to a more conservative configuration, and disables HDR capability. Then, it writes the updated display capability response object back to the standby host's EDID cache. After the standby host reads the object again, it reselects the output mode, allowing S2 and S3 to continue forming a new basis for pre-access preparation and acceptance status identification.

[0113] At this point, S4 has completed the parsing of the S3 handover permission result, the access of the target display link when handover is permitted, the preservation of the current video source or safe screen output when handover is not permitted, and the downgrade configuration processing of the display capability response object. S4 outputs the handover execution result, the safe screen output result, or the updated display capability response object; the updated display capability response object continues to provide display capability response to S2 and enables the video source to be switched to prepare for output mode again.

[0114] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for zero-delay switching of dual-channel video signals based on EDID preloading, characterized in that, The following steps are all executed by the control processing unit in the dual-channel video switching equipment, including the following steps: Verify and parse the display capability information of the target display link, and generate a display capability response object containing the capability source, allowed output mode, allowed mode range and response status according to the source end identifier of the dual video source; Receive the display capability response object, provide display capability response when the video source to be switched is not connected to the target display link, maintain the display connection awareness state, and enable the video source to be switched to complete the output mode preparation based on the display capability response object; Receive the display connection awareness status and detect the output stability status of the video source to be switched. Based on the correspondence between the actual output mode and the allowed output mode and the allowed range of the mode, as well as the change relationship between the display connection awareness status and the response effective status, identify the acceptance status and generate the switching permission result. Upon receiving the switching permission result, if permitted, the target display link is connected to the video source to be switched; if not permitted, one of the following actions is taken: maintain the current video source, output a safe image, or downgrade the display capability response object. Verifying and parsing display capability information includes: selecting the reading path according to the interface type of the target display link; reading the EDID base block and extension block through the DDC channel in the HDMI link; and reading one type of data from the DisplayID block, CTA extension block, and equivalent display capability data output by the display interface controller through the AUX channel in the DisplayPort and USB-CAltMode links, and sequentially verifying the data length, checksum, version identifier, number of extension blocks, and timing field. Parsing display capability information includes: extracting resolution, refresh rate, pixel clock, color format, and color depth from the verified display capability information to form allowed output modes; generating a mode allowable range for each allowed output mode; and writing only candidate output modes that can form a correspondence between resolution, refresh rate, and pixel clock into the display capability response object. The process of generating a display capability response object includes: using the source identifier as an index, writing the capability source, allowed output mode, and allowed mode range into the response path corresponding to the source identifier; after writing, confirming the response effectiveness status based on the write address, data block length, and read response, and ensuring that the response effectiveness status of different video sources does not overwrite each other; Providing display capability response includes: the control processing unit finds the corresponding display capability response object according to the source end identifier of the video source to be switched; when the response is effective, the response path corresponding to the source end identifier is set to an accessible state; when the response is ineffective, the display capability response object is written to the response path corresponding to the source end identifier in its original position and then reconfirmed; and the preloaded HPD effective state is output in the HDMI link, while the AUX proxy response is kept readable in the DisplayPort link and USB-CAltMode link. The preloaded HPD valid status is used to indicate that the video source to be switched can read the display capability response object, but does not indicate that the video path of the target display link has been connected to the video source to be switched. Maintaining the display connectivity awareness state includes: using a finite state machine to process the connectivity awareness input vector, the finite state machine includes an unaware state, a readable state, and a valid awareness state; when the readable channel in the response path is unavailable, it transitions to the unaware state; when the readable channel is available but the response effective state is invalid, it transitions to the readable state; when the readable channel is available, the display capability response is readable and the response effective state is valid, it transitions to the valid awareness state. The output mode preparation process includes: when the video source to be switched is in a valid display connection awareness state, it reads the display capability response object, selects the resolution, refresh rate, pixel clock, color format and color depth combination corresponding to its own output capability from the allowed output modes, and forms the output mode preparation result when the synchronization signal, pixel clock and the detection quantity corresponding to the interface detection conditions in the continuous valid frame candidate output are detected. The detection of stable output status includes: after the output mode preparation result has been formed, sampling the video reception detection path on the side of the video source to be switched, extracting the actual output mode based on the line synchronization status, field synchronization status, continuous valid frame status, pixel clock stability status, color format status and receiver chip lock status, and aligning the actual output mode with the allowed output mode for the same type of components. The video reception detection path is a detection path set on the side of the video source to be switched and isolated from the main video path of the target display link; The video reception detection path is only used to read the pixel clock, synchronization signal, valid frame status and color format status that the video source to be switched has generated before access, and does not change the physical connection status of the target display link currently accessing the current video source; Identifying the acceptance state includes: comparing the actual output mode with the same category component of each allowed output mode according to the allowed range of the mode to obtain the normalized deviation, and obtaining the mode deviation value; displaying the connection sensing state and the response effective state in a predetermined observation window to combine them into a connection effective state sequence, calculating the change frequency of adjacent sampling times to obtain the state flip rate, and inputting the mode deviation value and the state flip rate into the Bayesian state decision model to generate the handover permission result.

2. The method for zero-delay switching of dual-channel video signals based on EDID preloading according to claim 1, characterized in that, The degraded display capability response object includes: the control processing unit determines the degraded component based on the normalized deviation corresponding to the mode deviation value; when the normalized deviation corresponding to a single mode component is the maximum value, the corresponding component is degraded; when the normalized deviation corresponding to multiple mode components is the same and all are the maximum value, the components are degraded in the order of maximum pixel clock, maximum refresh rate, color depth, color format, HDR capability, and audio format complexity, and the updated display capability response object is written in place.

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