High bandwidth memory device, system, and method of manufacturing the same

Abstract

The present disclosure relates to methods, apparatuses, systems, and techniques for high bandwidth memory (HBM). A semiconductor device includes a first semiconductor structure having first ground conductive layers and first signal conductive layers, and a second semiconductor structure having second ground conductive layers and second signal conductive layers. The semiconductor device further includes a first set of at least one signal contact structure contacting the first signal conductive layers and at least one ground contact structure contacting the first ground conductive layers, and a second set of at least one signal contact structure contacting the second signal conductive layers and at least one ground contact structure contacting the second ground conductive layers, and wherein at least one of the first set or the second set includes signal contact structures and ground contact structures arranged in an array.

Description

Technical Field

[0001] This disclosure relates to high-bandwidth memory (HBM) systems and devices, and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array.

[0003] High-bandwidth memory (HBM) uses stacked memory devices to achieve efficient data movement and access. While using less power with a smaller form factor, HBM devices can achieve high bandwidth. HBM devices are already used in high-performance graphics accelerators, networking equipment, high-performance data centers, artificial intelligence (AI) and machine learning (ML) training, and various supercomputers. Summary of the Invention

[0004] This disclosure describes methods, apparatus, systems, and techniques for high-bandwidth memory (HBM).

[0005] One aspect of this disclosure is a semiconductor device. The semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked along a first direction, wherein the first semiconductor structure includes a first ground conductive layer and a first signal conductive layer, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer. The semiconductor device further includes: a first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and a second group of signal contact structures and ground contact structures, wherein the second group extends along the first direction from the first semiconductor structure into the second semiconductor structure, at least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer, and wherein the first group or at least one of the second groups includes signal contact structures and ground contact structures arranged in an array; the array includes first signal contact structures and first ground contact structures arranged along a first line extending in a second direction perpendicular to the first direction; and the first ground contact structures are uniformly spaced apart from the first signal contact structures.

[0006] In some implementations, each signal contact structure in the array is adjacent to a corresponding ground contact structure in the array, wherein the distance between the signal contact structure and the corresponding ground contact structure in the array is equal to the spacing dimension of the array.

[0007] In some embodiments, the spacing dimension is in the range of 0.5 micrometers (μm) to 10 μm, and the dimension of each signal contact structure or each ground contact structure in the array along the second direction is between 0.5 μm and 10 μm.

[0008] In some implementations, the same number of first signal contact structures are located between any two adjacent first ground contact structures along the second direction.

[0009] In some implementations, the quantity is an integer between 1 and 5.

[0010] In some embodiments, the array further includes a second signal contact structure and a second ground contact structure arranged along a second line extending in the second direction, the second ground contact structures being uniformly spaced between the second signal contact structures, and the second line being adjacent to the first line along a third direction perpendicular to the first direction and the second direction.

[0011] In some embodiments, each of the first signal contact structures or each of the first ground contact structures is aligned with one of the second signal contact structures or one of the second ground contact structures along the third direction.

[0012] In some embodiments, each of the first signal contact structure and the first ground contact structure is located along the second direction between two adjacent second signal contact structures or between one of the second signal contact structures and one of the second ground contact structures.

[0013] In some embodiments, the semiconductor device further includes: a third semiconductor structure including a third ground conductive layer and a third signal conductive layer, wherein the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure along the first direction; and a third group of signal contact structures and ground contact structures, wherein the third group extends from the first semiconductor structure into the third semiconductor structure along the first direction, at least one signal contact structure in the third group contacts the third signal conductive layer, at least one ground contact structure in the third group contacts the third ground conductive layer, the third group including third signal contact structures and third ground contact structures arranged along a third line extending in the second direction, and the third ground contact structures are uniformly spaced apart from the third signal contact structures.

[0014] In some embodiments, the semiconductor device further includes: a first bonding structure located between the first semiconductor structure and the second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded through the first bonding structure; and a second bonding structure located between the second semiconductor structure and the third semiconductor structure, wherein the second semiconductor structure and the third semiconductor structure are bonded through the second bonding structure.

[0015] Another aspect of this disclosure is a semiconductor device. The semiconductor device includes: a first semiconductor structure and a second semiconductor structure stacked along a first direction, wherein the first semiconductor structure includes a first substrate, a first ground conductive layer, and a first signal conductive layer, the first substrate including a first dielectric structure and a semiconductor material surrounding the first dielectric structure, and the second semiconductor structure including a second ground conductive layer and a second signal conductive layer; a first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, the ground contact structures in the first group are uniformly spaced between the signal contact structures in the first group, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and a second group of signal contact structures and ground contact structures, wherein the second group extends along the first direction from the first semiconductor structure through the first dielectric structure and into the second semiconductor structure, the ground contact structures in the second group are uniformly spaced between the signal contact structures in the second group, at least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer.

[0016] In some embodiments, the second semiconductor structure includes a second substrate, the second substrate including a second dielectric structure and a semiconductor material surrounding the second dielectric structure, and the semiconductor device further includes: a third semiconductor structure including a third ground conductive layer and a third signal conductive layer, wherein the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure along the first direction; and a third group of signal contact structures and ground contact structures, wherein the third group extends along the first direction from the first semiconductor structure through the first dielectric structure and the second dielectric structure and extends into the third semiconductor structure, the signal contact structures in the third group are uniformly spaced apart, at least one signal contact structure in the third group contacts the third signal conductive layer, and at least one ground contact structure in the third group contacts the third ground conductive layer.

[0017] In some embodiments, the first dielectric structure and the second dielectric structure have the same dimensions along a second direction perpendicular to the first direction and are aligned along the first direction.

[0018] In some embodiments, the first semiconductor structure and the second semiconductor structure are bonded by a dielectric bonding structure.

[0019] In some embodiments, at least one of the first semiconductor structure or the second semiconductor structure is a dynamic random access memory (DRAM) device.

[0020] In some embodiments, the DRAM device includes an array structure and a peripheral structure, the array structure including an array of DRAM cells, at least one DRAM cell of the array structure including a transistor and a capacitor, and the peripheral structure including peripheral circuitry configured to control the array of DRAM cells.

[0021] In some embodiments, the array structure and the peripheral structure are bonded by a bonding structure, and the bonding structure includes conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts.

[0022] In some embodiments, the signal contact structure and the ground contact structure in at least one of the first group or the second group are arranged in an array, each signal contact structure in the signal contact structure is adjacent to a corresponding ground contact structure in the ground contact structure, wherein the distance between the signal contact structure and the corresponding ground contact structure is equal to the spacing dimension of the array.

[0023] Another aspect of this disclosure is a semiconductor device. The semiconductor device includes: a first semiconductor structure and a second semiconductor structure stacked along a first direction, wherein the first semiconductor structure includes a first substrate, a first ground conductive layer, and a first signal conductive layer, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer; a first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, the ground contact structures in the first group are uniformly spaced between the signal contact structures in the first group, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and a second group of signal contact structures and ground contact structures, wherein the second group extends along the first direction from the first semiconductor structure through the first substrate and into the second semiconductor structure, the ground contact structures in the second group are uniformly spaced between the signal contact structures in the second group, at least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer.

[0024] In some embodiments, the signal contact structure and the ground contact structure in at least one of the first group or the second group are arranged in an array, each signal contact structure in the signal contact structure is adjacent to a corresponding ground contact structure in the ground contact structure, wherein the distance between the signal contact structure and the corresponding ground contact structure is equal to the spacing dimension of the array.

[0025] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0027] Figure 1A-1B A cross-sectional view of an example semiconductor device is shown in accordance with some aspects of this disclosure.

[0028] Figure 1C A top view of an example semiconductor device according to some aspects of this disclosure is shown.

[0029] Figure 2AA top view of an example semiconductor device according to some aspects of this disclosure is shown.

[0030] Figure 2B A cross-sectional view of an example semiconductor device is shown in accordance with some aspects of this disclosure.

[0031] Figures 3A-3C A top view of an example semiconductor device according to some aspects of this disclosure is shown.

[0032] Figures 4A-4C A top view of an example semiconductor device according to some aspects of this disclosure is shown.

[0033] Figure 5 A block diagram of an example system having one or more semiconductor devices is shown.

[0034] The same reference numerals and names in the various figures denote the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and are not necessarily drawn to scale. Detailed Implementation

[0035] Due to the increasing demand for cheaper memory devices with higher density, memory devices (e.g., high-bandwidth memory (HBM)) can be designed with increased array density by stacking multiple layers of the memory device on top of each other. The high array density and layer-stacked structure of HBM memories require more signal contact structures to connect to each layer. A large number of signal contact structures can pose challenges to signal integrity. Current implementations that reduce signal noise while maintaining signal integrity involve increasing the number of shielding structures (e.g., ground contact structures) at certain fixed locations within the memory chip. This approach can present several challenges in integrating the ground contact structures. First, a large number of ground contact structures are needed around the signal contact structures to maintain signal integrity and ensure low loss between memory communications. However, a large number of ground contact structures will occupy a significant chip area, increasing manufacturing costs and reducing active area. Second, the fixed locations of the ground contact structures can lead to varying distances between the ground contact structures and the signal contact structures, which can reduce signal integrity when transmitting signals between different signal contact structures on the chip. Therefore, new techniques for forming and arranging ground contact structures for contact structures are desired, which can reduce manufacturing costs and occupy less area in the memory device.

[0036] In one or more embodiments of this disclosure, an example semiconductor device is provided. The semiconductor device may include a first semiconductor structure and a second semiconductor structure stacked along a first direction. The first semiconductor structure includes a first ground conductive layer and a first signal conductive layer, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer. The semiconductor device also includes a first group of signal contact structures and ground contact structures, wherein the first group extends into the first semiconductor structure along the first direction. At least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer. The semiconductor device also includes a second group of signal contact structures and ground contact structures, wherein the second group extends from the first semiconductor structure into the second semiconductor structure along the first direction. At least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer. At least one of the first or second groups includes signal contact structures and ground contact structures arranged in an array. The array includes first signal contact structures and first ground contact structures arranged along a first line extending in a second direction perpendicular to the first direction, and the first ground contact structures are uniformly spaced apart from the first signal contact structures.

[0037] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits: First, different groups of signal contact structures and ground contact structures ensure that at least one ground contact structure is connected to the ground conductive layer of each semiconductor structure. In other words, ground contact structures connected to the ground conductive layer of each semiconductor structure can help reduce noise in signal contact structures during a single transfer process. Second, the signal contact structures and ground contact structures in each group are uniformly spaced, which can help create an optimized layout to maintain signal integrity. Third, placing the same number of signal contact structures between any two adjacent ground contact structures in each group can help optimize the arrangement of ground contact structures between signal contact structures, reduce the number of ground contact structures required to maintain signal integrity, and reduce the chip size required for ground contact structures. Fourth, dielectric walls can be formed in the substrate of each of the semiconductor structures. Dielectric walls can help simplify the etching process used to form the signal contact structures and ground contact structures, which can reduce manufacturing costs.

[0038] Figure 1A A cross-sectional view of an exemplary semiconductor device 100a according to some aspects of this disclosure is shown. Semiconductor device 100a may be a memory device, such as HBM. It should be noted that in Figure 1AThe X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of the semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer on which components of the semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the wafer. The Z direction is perpendicular to the X and Y directions. As used herein, when the substrate is positioned in the Z direction in the lowest plane of the semiconductor device, whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0039] like Figure 1A As shown, semiconductor device 100a includes a stack 102 of semiconductor structures 104a-104d. Each of the semiconductor structures 104a-104d may be a dynamic random access memory (DRAM) device. The semiconductor structures 104a-104d are stacked (e.g., sequentially) along a vertical direction (e.g., the Z direction).

[0040] Semiconductor device 100a includes bonding structures 106a-106c (also known as dielectric bonding structures). For example... Figure 1A As shown, each of the bonding structures 106a-106c is located between two of the semiconductor structures 104a-104d. For example, as Figure 1A As shown, semiconductor structures 104a and 104b are bonded via bonding structure 106a. Semiconductor structures 104b and 104c are bonded via bonding structure 106b. Semiconductor structures 104c and 104d are bonded via bonding structure 106c. Each of bonding structures 106a-106c may include a top bonding layer and a bottom bonding layer bonded at the bonding interface. Each of the top bonding layer and the bottom bonding layer may include a dielectric material (including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof) and may not include conductive bonding contacts.

[0041] Semiconductor structure 104a can be bonded to the top of semiconductor structure 104b in a face-to-face manner via bonding structure 106a. The bonding interface is disposed between the top and bottom bonding layers, which is a result of direct bonding (e.g., dielectric-dielectric bonding), which forms a bond between surfaces without the use of intermediate layers such as solder or adhesive. In some embodiments ( Figure 1A(Not shown in the diagram), for example, when the dielectric material of the top bonding layer and the dielectric material of the bottom bonding layer are different materials, the bonding interface can be a visible layer of a certain thickness, which includes the top surface of the bottom bonding layer and the bottom surface of the top bonding layer. In some embodiments, such as Figure 1A As shown in the example, when the dielectric material of the top bonding layer and the dielectric material of the bottom bonding layer are the same material, the bonding interface may not be visible, and the top bonding layer and the bottom bonding layer can form a continuous bonding structure 106a.

[0042] In some implementations, such as Figure 1A As shown, a stack 102 of semiconductor structures 104a-104d is stacked on a substrate die 108 (also referred to as a logic die or buffer die). The substrate die 108 may include buffer circuitry and test logic for the semiconductor device 100a. The substrate die 108 may be configured to provide a physical layer communication protocol (e.g., IEEE-1500) between the semiconductor device 100a and the computing die. The substrate die 108 may be configured to transfer data between the semiconductor device 100a and the computing die based on control commands and addresses from the computing die. In some embodiments, the substrate die 108 is bonded to the stack 102 via a bonding structure 106d.

[0043] like Figure 1A As shown, each of the semiconducting structures 104a-104d in the stack 102 may include a memory array structure 110 and a peripheral structure 112. The memory array structure 110 may include a DRAM cell array. At least one DRAM cell in the DRAM cell array may include a transistor and a capacitor. In some embodiments, the peripheral structure 112 includes peripheral circuitry configured to control the DRAM cell array. In some embodiments, such as Figure 1A As shown, the memory array structure 110 and the peripheral structure 112 are bonded together by a bonding structure 111. The bonding structure 111 may include conductive bonding contacts and a dielectric material isolating the conductive bonding contacts. Each of the semiconductor structures 104a-104d may include a substrate 114, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The peripheral structure 112 may be formed on or in the substrate 114, such as... Figure 1A As shown. In some embodiments, the substrate can be thinned or removed in a later manufacturing process. For example, as Figure 1A As shown, the substrate 114 of the semiconductor structure 104a is thinned. In some embodiments, a semiconductor structure (e.g., as shown) Figure 1AThe substrate 114 of the semiconductor structure 104d shown may be thicker than the substrate of other semiconductor structures to provide support for the stack 102.

[0044] like Figure 1A As shown, each of the semiconductor structures 104a-104d may further include a signal conductive layer 116. For example, semiconductor structure 104a may include a first signal conductive layer 116a, semiconductor structure 104b may include a second signal conductive layer 116b, and semiconductor structure 104c may include a third signal conductive layer 116c. In some embodiments, the number of semiconductor structures 104 stacked on top of each other is greater than 3, and each of the semiconductor structures 104 may include a corresponding signal conductive layer 116. For example, as Figure 1A As shown, the semiconductor structure 104d may include a fourth signal conductive layer 116d.

[0045] like Figure 1A As shown, the signal conductive layers 116a-116d of the semiconductor structures 104a-104d in the semiconductor device 100b are arranged in a stepped structure. For example, as Figure 1A As shown, the first end 116a-1 of the first signal conductive layer 116a, the first end 116b-1 of the second signal conductive layer 116b, the first end 116c-1 of the third signal conductive layer 116c, and the first end 116d-1 of the fourth signal conductive layer 116d are offset along the Y direction; the second ends 116a-2 of the first signal conductive layer 116a, the second end 116b-2 of the second signal conductive layer 116b, the second end 116c-2 of the third signal conductive layer 116c, and the second end 116d-2 of the fourth signal conductive layer 116d are aligned along the Z direction. In some embodiments, such as Figure 1AAs shown, along the Y direction, the length of the first signal conductive layer 116a is less than the length of the second signal conductive layer 116b, the length of the second signal conductive layer 116b is less than the length of the third signal conductive layer 116c, and the length of the third signal conductive layer 116c is less than the length of the fourth signal conductive layer 116d. In some embodiments, the first signal conductive layer 116a is included in the interconnect layer of the semiconductor structure 104a. The second signal conductive layer 116b is included in the interconnect layer of the semiconductor structure 104b. The third signal conductive layer 116c is included in the interconnect layer of the semiconductor structure 104c. The fourth signal conductive layer 116d is included in the interconnect layer of the semiconductor structure 104d. The interconnect layer may include interconnects (also referred to herein as “contacts”), which include lateral interconnects and vertical interconnect access (VIA) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as middle-end process (MEOL) interconnects and back-end process (BEOL) interconnects. For example, each of the signal conductive layers 116 may be or may include one or more interconnects in the corresponding interconnect layer. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers") in which interconnects and VIA contacts may be formed. That is, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0046] Each of the semiconductor structures 104a-104d may further include a ground conductive layer 117. In each of the semiconductor structures 104a-104d, the ground conductive layer 117 is spaced apart from the signal conductive layer 116. For example, as Figure 1A As shown, semiconductor structure 104a may include a first ground conductive layer 117a extending along the Y direction and spaced apart from the first signal conductive layer 116a; semiconductor structure 104b may include a second ground conductive layer 117b extending along the Y direction and spaced apart from the second signal conductive layer 116b; and semiconductor structure 104c may include a third ground conductive layer 117c extending along the Y direction and spaced apart from the third signal conductive layer 116c. In some embodiments, the number of semiconductor structures 104 stacked on top of each other is greater than 3, and each of the semiconductor structures 104 may include a corresponding ground conductive layer 117. For example, as Figure 1A As shown, the semiconductor structure 104d may include a fourth ground conductive layer 117d extending along the Y direction and spaced apart from the fourth signal conductive layer 116d.

[0047] like Figure 1A As shown, the ground conductive layers 117a-117d of the semiconductor structures 104a-104d in the semiconductor device 100b are arranged in a stepped structure. For example, as Figure 1A As shown, the first end 117a-1 of the first ground conductive layer 117a, the first end 117b-1 of the second ground conductive layer 117b, the first end 117c-1 of the third ground conductive layer 117c, and the first end 117d-1 of the fourth ground conductive layer 117d are offset along the Y direction; the second ends 117a-2 of the first ground conductive layer 117a, the second end 117b-2 of the second ground conductive layer 117b, the second end 117c-2 of the third ground conductive layer 117c, and the second end 117d-2 of the fourth ground conductive layer 117d are aligned along the Z direction. In some embodiments, such as Figure 1A As shown, along the Y direction, the length of the first ground conductive layer 117a is less than the length of the second ground conductive layer 117b, the length of the second ground conductive layer 117b is less than the length of the third ground conductive layer 117c, and the length of the third ground conductive layer 117c is less than the length of the fourth ground conductive layer 117d.

[0048] The semiconductor device 100a may further include a plurality of signal contact structures 118 and ground contact structures 119 extending along the Z direction. The plurality of signal contact structures 118 and ground contact structures 119 are separated from each other along the Y direction. For example, as... Figure 1A As shown, the plurality of signal contact structures 118 may include a first signal contact structure 118a, a second signal contact structure 118b, and a third signal contact structure 118c. The plurality of ground contact structures 119 may include a first ground contact structure 119a, a second ground contact structure 119b, and a third ground contact structure 119c. In some embodiments, the plurality of signal contact structures 118 and the plurality of ground contact structures 119 are arranged in multiple groups 122, wherein each of the groups 122 of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 is connected to the signal conductive layer 116 and the ground conductive layer 117 of the corresponding semiconductor structures 104a-104c. For example, as... Figure 1AAs shown, the first group 122a of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 may include at least one first signal contact structure 118a and at least one first ground contact structure 119a extending into the semiconductor structure 104a, wherein at least one first signal contact structure 118a is connected to the first signal conductive layer 116a, and at least one first ground contact structure 119a is connected to the first ground conductive layer 117a. The second group 122b of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 may include at least one second signal contact structure 118b and at least one second ground contact structure 119b extending into the semiconductor structure 104b, wherein at least one second signal contact structure 118b is connected to the second signal conductive layer 116b, and at least one second ground contact structure 119b is connected to the second ground conductive layer 117b. The third group 122c of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 may include at least one third signal contact structure 118c and at least one third ground contact structure 119c extending into the semiconductor structure 104c, wherein at least one third signal contact structure 118c is connected to the third signal conductive layer 116c, and at least one third ground contact structure 119c is connected to the third ground conductive layer 117c. In some embodiments, the number of semiconductor structures 104 stacked on top of each other is greater than 3, and the group 122 of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 further includes a fourth group 122d, the fourth group 122d including at least one fourth signal contact structure 118d and at least one fourth ground contact structure 119d extending into the semiconductor structure 104d, wherein at least one fourth signal contact structure 118d is connected to the fourth signal conductive layer 116d, and at least one fourth ground contact structure 119d is connected to the fourth ground conductive layer 117d.

[0049] In some embodiments, a group 122 of multiple signal contact structures 118 and multiple ground contact structures 119 may be arranged in an array. In some embodiments, each of the signal contact structures 118 in the array is adjacent to a corresponding ground contact structure 119 in the array, wherein the distance between the signal contact structure 118 and the corresponding ground contact structure 119 in the array is equal to the array's spacing dimension. In some embodiments, the array spacing dimension is in the range of 0.5 micrometers (μm) to 10 μm, and the dimension of each of the signal contact structures 118 or each of the ground contact structures 119 in the array along the Y direction is between 0.5 μm and 10 μm. For example, a first group 122a of at least one first signal contact structure 118a and at least one first ground contact structure 119a may be arranged along a first line of the array extending in a horizontal direction (e.g., the Y direction) perpendicular to the Z direction. In some embodiments, the first ground contact structures 119a in the first group 122a are uniformly spaced apart from the first signal contact structures 118a in the first group 122a. For example, the same number of first signal contact structures 118a are located along the Y direction between any two adjacent first ground contact structures 119a. A second group 122b of at least one second signal contact structure 118b and at least one second ground contact structure 119b can be arranged along a second line of the array extending along the Y direction, wherein the second ground contact structures 119b are uniformly spaced between the second signal contact structures 118b, and the second line of the array is adjacent to the first line of the array along a second horizontal direction perpendicular to the first direction (e.g., the X direction). A third group 122c of at least one third signal contact structure 118c and at least one third ground contact structure 119c can be arranged along a third line of the array extending along the Y direction, wherein the third ground contact structures 119c are uniformly spaced between the third signal contact structures 118c, and the second line of the array is located along the X direction between the third line and the first line of the array. In some embodiments, the number of semiconductor structures 104 stacked on top of each other is greater than 3, and the group 122 of the plurality of signal contact structures 118 and the plurality of ground contact structures 119 further includes a fourth group 122d, the fourth group 122d including at least one fourth signal contact structure 118d and at least one fourth ground contact structure 119d extending into the semiconductor structure 104d. The fourth group 122d of at least one fourth signal contact structure 118d and at least one fourth ground contact structure 119d may be arranged along a fourth line of the array extending in the Y direction, wherein the fourth ground contact structures 119d are uniformly spaced between the fourth signal contact structures 118d, and a third line of the array lies in the X direction between the second and fourth lines of the array.

[0050] like Figure 1AAs shown, each of the signal contact structures 118 may include a first dielectric outer layer 120 surrounding the signal contact structure 118 along the Y direction. Each of the ground contact structures 119 may include a second dielectric outer layer 121 surrounding the ground contact structure 119 along the Y direction. The first dielectric outer layer 120 and the second dielectric outer layer 121 can be used to insulate the signal contact structures 118 and the ground contact structures 119 from other components of the semiconductor structures 104a-104b along the Y direction.

[0051] In some embodiments, signal contact structure 118 can be used as a signal transmission channel between memory devices in each of the semiconductor structures 104. Ground contact structure 119 can be used as a ground contact portion of signal contact structure 118, which reduces noise and interference generated by signal contact structure 118 during signal transmission and improves signal integrity during device operation. Ground contact structure 119 is placed adjacent to signal contact structure 118 to reduce chip area and increase the effective active area ratio of the memory device.

[0052] It should be understood that, such as Figure 1A The example semiconductor device 100a shown is for illustrative purposes and is not intended to be interpreted in a limiting sense. For example, the number of semiconductor structures 104 stacked on top of each other is not limited to four structures, and any number of semiconductor structures 104 can be stacked on top of each other in semiconductor device 100a. For each of the semiconductor structures 104, semiconductor device 100a includes a signal contact structure 118 that contacts a corresponding signal conductive layer 116 of each of the semiconductor structures 104 and a ground contact structure 119 that contacts a corresponding ground conductive layer 117 of each of the semiconductor structures 104.

[0053] In some embodiments, semiconductor device 100a may include device region 126 and connection region 128. For example... Figure 1A As shown, the device region 126 of the semiconductor device 100a may include the memory array structure 110 and the peripheral structure 112 of the semiconductor structures 104a-104b. The connection region 128 of the semiconductor device 100a may include the signal conductive layer 116, the ground conductive layer 117, the signal contact structure 118 connected to the corresponding signal conductive layer 116, and the ground contact structure 119 connected to the corresponding ground conductive layer 117 of the semiconductor structures 104a-104b.

[0054] In some embodiments, signal contact structure 118 and ground contact structure 119 can be formed by etching a first portion of semiconductor structures 104a-104d to form a first contact hole and etching a second portion of semiconductor structures 104a-104d to form a second contact hole. The first contact hole and the second contact hole are spaced apart from each other along the Y direction. The first contact hole contacts the signal conductive layer 116 of the corresponding semiconductor structure 104a-104d. The second contact hole contacts the ground conductive layer 117 of the corresponding semiconductor structure 104a-104d.

[0055] In some embodiments, the formation of the first and second contact holes may employ several etching processes. In some embodiments, the substrate 114 may include a semiconductor material (e.g., Si), and the semiconductor structures 104a-104d may include a dielectric filler having a dielectric material (e.g., SiO2) different from the semiconductor material of the substrate 114. The etchants used to etch the semiconductor material in the substrate 114 and the dielectric material in the dielectric filler of the semiconductor structures 104a-104d are different. For example, a first etching process with a first etchant is used to etch the dielectric filler in the semiconductor structure 104a, a second etching process with a second etchant is used to etch the substrate 114 through the semiconductor structure 104a, and a third etching process with a first etchant is used to etch a portion of the dielectric filler in the semiconductor structure 104b to form a first contact hole that contacts the second signal conductive layer 116b of the semiconductor structure 104b.

[0056] The signal structure 118 is formed by filling a first conductive material surrounded by a dielectric material in the first contact hole. The ground contact structure 119 is formed by filling a second conductive material surrounded by a dielectric material in the second contact hole. In some embodiments, the first conductive material can be any conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The second conductive material can be any conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The dielectric material can be any dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the first conductive material can be the same as the second conductive material. For example, both the first and second conductive materials can be W.

[0057] Figure 1B A cross-sectional view of an exemplary semiconductor device 100b is shown. In addition to the substrate 114, signal contact structure 118, and ground contact structure 119 of the semiconductor device 100b having... Figure 1AApart from having a different structure than semiconductor device 100a, semiconductor device 100b can be similar to... Figure 1A Semiconductor device 100a.

[0058] like Figure 1B As shown, the substrate 114 of each of the semiconductor structures 104a-104c may include a dielectric structure 124. The dielectric structure 124 is sometimes referred to as a well structure within the substrate 114. For example, as... Figure 1B As shown, the substrate 114 of semiconductor structure 104a includes a first dielectric structure 124a. The substrate 114 of semiconductor structure 104b includes a second dielectric structure 124b. The substrate 114 of semiconductor structure 104c includes a third dielectric structure 124c. The substrates 114 of semiconductor structures 104a-104c may include semiconductor materials, such as polysilicon. The first dielectric structure 124a, the second dielectric structure 124b, and the third dielectric structure 124c may include dielectric materials, such as SiO2. The first dielectric structure 124a may be surrounded by the semiconductor material of the substrate 114 of semiconductor structure 104a (e.g., along a direction perpendicular to the Z direction). Similarly, the second dielectric structure 124b may be surrounded by the semiconductor material of the substrate 114 of semiconductor structure 104b (e.g., along a direction perpendicular to the Z direction), and the third dielectric structure 124c may be surrounded by the semiconductor material of the substrate 114 of semiconductor structure 104c (e.g., along a direction perpendicular to the Z direction). In some embodiments, each of the dielectric structures 124a, 124b, and 124c may not be entirely surrounded by the semiconductor material of the substrate 114 of the corresponding semiconductor structure (e.g., 104a, 104b, or 104c). For example, dielectric structures 124a, 124b, and 124c may be adjacent to the semiconductor material of the substrate 114 of the semiconductor structures 104a, 104b, and 104c, respectively (e.g., along the Y direction). The first dielectric structure 124a, the second dielectric structure 124b, and the third dielectric structure 124c may be used to isolate the signal contact structure 118 and the ground contact structure 119 from the substrate 114 of the semiconductor structures 104a-104c. In some embodiments, the first dielectric structure 124a, the second dielectric structure 124b, and the third dielectric structure 124c have the same dimensions along the Y direction.

[0059] Semiconductor device 100b includes a first group 122a of first signal contact structures 118a and first ground contact structures 119a. The first group 122a extends along the Z direction into semiconductor structure 104a. The first ground contact structures 119a in the first group 122a are uniformly spaced apart from the first signal contact structures 118a in the first group 122a. At least one first signal contact structure 118a in the first group 122a contacts a first signal conductive layer 116a, and at least one first ground contact structure 119a in the first group 122a contacts a first ground conductive layer 117a. Semiconductor device 100b also includes a second group 122b of second signal contact structures 118b and second ground contact structures 119b. The second group 122b extends along the Z direction from semiconductor structure 104a through a first dielectric structure 124a and into semiconductor structure 104b. The second ground contact structures 119b in the second group 122b are uniformly spaced apart from the second signal contact structures 118b in the second group 122b. At least one second signal contact structure 118b in the second group 122b contacts the second signal conductive layer 116b, and at least one second ground contact structure 119b in the second group 122b contacts the second ground conductive layer 117b. In some embodiments, such as Figure 1BAs shown, the semiconductor device 100b may further include a third group 122c of third signal contact structures 118c and third ground contact structures 119c. The third group 112c extends along the Z direction from the semiconductor structure 104a through the first dielectric structure 124a and the second dielectric structure 124b and into the semiconductor structure 104c. The third ground contact structures 119c in the third group 122c are uniformly spaced between the third signal contact structures 118c in the third group 122c. At least one third signal contact structure 118c in the third group 122c contacts the third signal conductive layer 116c, and at least one third ground contact structure 119c in the third group 122c contacts the third ground conductive layer 117c. In some embodiments, the number of semiconductor structures 104 stacked on top of each other is greater than 3, and the group 122 of multiple signal contact structures 118 and multiple ground contact structures 119 further includes a fourth group 122d of fourth signal contact structures 118d and fourth ground contact structures 119d. The fourth group 112d extends along the Z direction from the semiconductor structure 104d through the first dielectric structure 124a, the second dielectric structure 124b, and the third dielectric structure 124c and into the semiconductor structure 104d. The fourth ground contact structure 119d in the fourth group 122d is uniformly spaced between the fourth signal contact structures 118d in the fourth group 122d. At least one fourth signal contact structure 118d in the fourth group 122d contacts the fourth signal conductive layer 116d, and at least one fourth ground contact structure 119d in the fourth group 122d contacts the fourth ground conductive layer 117d.

[0060] In some embodiments, a second group 122b of the second signal contact structure 118b and the second ground contact structure 119b extends along the Z direction from the semiconductor structure 104a through the substrate 114 of the semiconductor structure 104a and into the semiconductor structure 104b. The second ground contact structures 119b in the second group 122b are uniformly spaced apart from the second signal contact structures 118b in the second group 122b. At least one second signal contact structure 118b in the second group 122b contacts the second signal conductive layer 116b, and at least one second ground contact structure 119b in the second group 122b contacts the second ground conductive layer 117b.

[0061] Signal contact structures 118 and ground contact structures 119 in group 122 of semiconductor device 100b are arranged in an array. In this array, each signal contact structure 118 is adjacent to a corresponding ground contact structure 119, wherein the distance between the signal contact structure 118 and the corresponding ground contact structure 119 is equal to the spacing dimension of the array. In some embodiments, the spacing dimension of the array is in the range of 0.5 micrometers (μm) to 10 μm, and the dimension of each of the signal contact structures 118 or each of the ground contact structures 119 in the array along the Y direction is between 0.5 μm and 10 μm.

[0062] It should be understood that, such as Figure 1B The example semiconductor device 100b shown is for illustrative purposes and is not intended to be interpreted in a limiting sense. For example, the number of stacked semiconductor structures 104 is not limited to four, and any number of stacked semiconductor structures 104 may exist in the semiconductor device 100b. For each of the semiconductor structures 104, the semiconductor device 100b includes a signal contact structure 118 and a ground contact structure 119, which contact the corresponding signal conductive layer 116 and ground conductive layer 117 of each of the semiconductor structures 104.

[0063] In some implementations, such as Figure 1B As shown, the substrate 114 of semiconductor structures 104a-104c may include a dielectric structure 124 formed prior to the formation of the first and second contact holes. The dielectric structure 124 of semiconductor structures 104a-104c can be formed by etching a portion of the substrate 114 and filling the etched portion with a dielectric material (e.g., SiO2). Then, semiconductor structures 104a-104d are bonded to each other via bonding structure 106. In some embodiments, signal contact structure 118 and ground contact structure 119 can be formed by etching a first portion of semiconductor structures 104a-104d to form a first contact hole and etching a second portion of semiconductor structures 104a-104d to form a second contact hole, wherein a portion of the first and second contact holes extends through the dielectric structure 124. For example, the substrate 114 of semiconductor structure 104a may include a first dielectric structure 124a, and a portion of the first and second contact holes extends through the first dielectric structure 124a along the Z-direction.

[0064] In some embodiments, the dielectric structure 124 in the substrate 114 of the semiconductor structures 104a-104d may include the same dielectric material (e.g., SiO2) as the dielectric filler of the semiconductor structures 104a-104d. Figure 1A Compared to the formation of the first and second contact holes in semiconductor device 100a, the same dielectric material can help simplify the etching process when forming the first and second contact holes in semiconductor device 100b. For example, an etching process with a first etching can be used to etch through the dielectric filler of the first semiconductor structure 104a, the first dielectric structure 124a of the substrate 114 of the first semiconductor structure 104a, and into the dielectric filler of the second semiconductor structure 104b to form a first contact hole that contacts the second signal conductive layer 116b of the semiconductor structure 104b.

[0065] The first contact hole and the second contact hole are spaced apart from each other along the Y direction. The first contact hole contacts the signal conductive layer 116 of the corresponding semiconductor structures 104a-104d. The second contact hole contacts the ground conductive layer 117 of the corresponding semiconductor structures 104a-104d. A signal structure 118 is formed by filling the first contact hole with a first conductive material. A ground contact structure 119 is formed by filling the second contact hole with a second conductive material. In some embodiments, the first conductive material can be any conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The second conductive material can be any conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, the first conductive material can be the same as the second conductive material. For example, both the first and second conductive materials can be W.

[0066] Figure 1C A top view of an example semiconductor device 100c according to some aspects of this disclosure is shown. In some embodiments, device region 126 and connection region 128 may be arranged in an array. Device region 126 may be Figure 1A-1B The device region 126 of the semiconductor devices 100a-100b, and the connection region 128 may be Figure 1A-1B The connection region 128 of the semiconductor devices 100a-100b. For example, as... Figure 1C As shown, the first line of the array may include two device regions 126 along the Y direction and a connecting region 128 between the two device regions 126 along the Y direction. In some embodiments, such as Figure 1C As shown, the first lines of the array of device region 126 and connection region 128 can be stacked along the X direction to form columns of the array. Although Figure 1CAn example arrangement of a line of an array of (multiple) device regions 126 and (multiple) connection regions 128 is shown, but any other suitable arrangement is possible. In some embodiments, the semiconductor device 100c may include a device region 126 and a connection region 128 adjacent to each other along the Y direction. In some embodiments, the semiconductor device 100c may include two connection regions 128 arranged along the Y direction and a device region 126 located between the two connection regions 128 along the Y direction. In some embodiments, the semiconductor device 100c may include a first connection region 128, a second connection region 128, and a device region 126 arranged along the Y direction. The first connection region 128 may be at the center of the semiconductor device 100c, and the second connection region 128 may be on one side of the first connection region 128 (e.g., on the left). The device region 126 may be on the other side of the first connection region 128 (e.g., on the right). In some embodiments, the semiconductor device 100c may include a device region 126 and a connection region 128 adjacent to each other along the X direction.

[0067] Figure 2A A top view of an exemplary semiconductor device 200 according to some aspects of this disclosure is shown. The semiconductor device 200 may be... Figure 1A-1B A top view of the connection area 128 of the semiconductor devices 100a-100b.

[0068] like Figure 2A As shown, the semiconductor device 200 may include a signal contact structure 202 and a ground contact structure 204 arranged in an array 201. In some embodiments, the signal contact structure 202 of the semiconductor device 200 may be connected to... Figure 1A-1B The signal contact structure 118 of the semiconductor devices 100a-100b is similar to or the same as that of the semiconductor device 200. The ground contact structure 204 of the semiconductor device 200 can be similar to... Figure 1A-1B The grounding contact structure 119 of the semiconductor devices 100a-100b is similar or identical. Although Figure 1A-1B The examples show only one signal contact structure and one ground contact structure in each group (e.g., signal contact structure 118a and ground contact structure 119a in group 122a), but it should be understood that each group may include multiple signal contact structures and multiple ground contact structures. Figure 2A-4C The arrangement of the signal contact structure and ground contact structure shown can be applied to Figure 1A-1B Each group in the group (e.g., group 122a, 122b, 122c, or 122d). Alternatively, in some implementations, such as Figure 2A-4C The arrangement of the signal contact structure and ground contact structure shown can be applied to Figure 1A-1BA combination of multiple groups (e.g., a combination of groups 122a, 122b, 122c, and 122d). For example... Figure 2A As shown, the array 201 of signal contact structures 202 and ground contact structures 204 may have rows extending along the Y direction and columns extending along the X direction. In some embodiments, for each group, each signal contact structure in the group is adjacent to at least one ground contact structure. In this disclosure, the adjacency of a signal contact structure and a ground contact structure can be interpreted as the distance between the signal contact structure and the ground contact structure being the minimum distance between two contact structures in the array. For example, as... Figure 2A As shown, signal contact structure 202a is adjacent to ground contact structure 204a, but not adjacent to ground contact structure 204b, because the distance between signal contact structure 202a and ground contact structure 204a is the minimum distance between two contact structures in array 201, but the distance between signal contact structure 202a and ground contact structure 204b is greater than the minimum distance between two contact structures in array 201. In some embodiments, the minimum distance between two contact structures in array 201 is equal to the spacing dimension of array 201. In some embodiments, each signal contact structure in a combination of multiple groups in array 201 is adjacent to at least one ground contact structure. In some embodiments, each of the signal contact structures 202 in array 201 is adjacent to a corresponding ground contact structure 204 in array 201. The distance between the signal contact structure 202 in array 201 and the corresponding ground contact structure 204 in array 201 is equal to the spacing dimension of the array. In some embodiments, the spacing dimension of the array is in the range of 0.5 micrometers (μm) and 10 μm. In some implementations, each signal contact structure in the array is adjacent to the same number of ground contacts in the array. For example, as... Figure 2A As shown, each signal contact structure in array 201 is adjacent to two ground contact structures.

[0069] Figure 2B A cross-sectional view of a semiconductor device 200 along a cut line AA' is shown, according to some aspects of this disclosure. The cut line AA' may be along... Figure 2A The rows of array 201. In some implementations, such as Figure 2B As shown, the ground contact structures 204 are evenly spaced between the signal contact structures 202 along the rows of array 201. In some embodiments, the same number of signal contact structures 202 are spaced between any two adjacent ground contact structures 204 along the Y direction. In some embodiments, the number of signal contact structures 202 between any two adjacent ground contact structures 204 along the Y direction is an integer between 1 and 5 (e.g., ...). Figures 3A-3C array or Figures 4A-4C(as shown in the array). In some embodiments, the first end 202-1 of each of the signal contact structures 202 in array 201 or the first end 204-1 of each of the ground contact structures 204 has a dimension along the Y direction between 0.5 μm and 10 μm.

[0070] Figures 3A-3C A top view of an example semiconductor device 300 according to some aspects of this disclosure is shown. The semiconductor device 300 may be... Figure 1A-1B An example of an array of signal contact structures 118 and ground contact structures 119 in the connection regions 128 of semiconductor devices 100a-100b.

[0071] like Figures 3A-3C As shown, the semiconductor device 300 may include a signal contact structure 302 and a ground contact structure 304. In some embodiments, the signal contact structure 302 of the semiconductor device 300 may be connected to... Figure 1A-1B The signal contact structure 118 of the semiconductor device 100a-100b or Figure 2A The signal contact structure 202 of the semiconductor device 200 is similar to or the same as that of the semiconductor device 200. The ground contact structure 304 of the semiconductor device 200 can be similar to... Figure 1A-1B The grounding contact structure 119 of the semiconductor device 100a-100b or Figure 2A The grounding contact structure 204 of the semiconductor device 200 is similar to or the same.

[0072] In some embodiments, the signal contact structure 302 and the ground contact structure 304 can be arranged in an array 301, the array 301 having rows extending along the Y direction and columns extending along the X direction. In some embodiments, the array 301 of semiconductor devices can be... Figure 1A A portion of the connection region 128 of the semiconductor device 100a, wherein the array 301 of the signal contact structure 302 and the ground contact structure 304 can be separated into multiple groups 306 of corresponding signal conductive layers 116 and ground conductive layers 117 connected to each of the semiconductor structures 104a-104d of the semiconductor device 100a. For example, as Figure 3AAs shown, the first group 306a of signal contact structure 302 and ground contact structure 304 may include the first row 301-1 of array 301, wherein the signal contact structure 302 in the first group 306a is connected to the first signal conductive layer 116a of semiconductor structure 104a, and the ground contact structure 304 in the first group 306a is connected to the first ground conductive layer 117a of semiconductor structure 104a. The second group 306b of signal contact structure 302 and ground contact structure 304 may include the second row 301-2 of array 301, wherein the signal contact structure 302 in the second group 306b is connected to the second signal conductive layer 116b of semiconductor structure 104b, and the ground contact structure 304 in the second group 306b is connected to the first ground conductive layer 117a of semiconductor structure 104b.

[0073] In some embodiments, the array 301 of the signal contact structure 302 and the ground contact structure 304 of the semiconductor device 300 may belong to the same group 306 as one of the semiconductor structures 104a-104d connected to the semiconductor device 100a. For example, as Figure 3A As shown, all signal contact structures 302 in array 301 can be connected to the first signal conductive layer 116a of semiconductor structure 104a, and all ground contact structures 304 in array 301 can be connected to the first ground conductive layer 117a of semiconductor structure 104a.

[0074] In some implementations, such as Figures 3A-3C As shown, the rows of array 301 are offset along the X direction. For example, each of the signal contact structures 302 and ground contact structures 304 in the first group 306a is located along the Y direction between two adjacent signal contact structures in the signal contact structures 302 of the second group 306b, or between one of the signal contact structures 302 and one of the ground contact structures 304.

[0075] In some implementations, the same number of signal contact structures 302 are between any two adjacent ground contact structures 304 in each row of array 301. In some implementations, this number is an integer between 1 and 5. For example, as... Figure 3A As shown, the number of signal contact structures 302 between any two adjacent ground contact structures 304 in each row of array 301 is 5. Figure 3B As shown, the number of signal contact structures 302 between any two adjacent ground contact structures 304 in each row of array 301 is 2. Figure 3C As shown, the number of signal contact structures 302 between any two adjacent ground contact structures 304 in each row of array 301 is 1.

[0076] Figures 4A-4C A top view of an example semiconductor device 400 according to some aspects of this disclosure is shown. The semiconductor device 400 may be... Figure 1A-1B An example of an array of signal contact structures 118 and ground contact structures 119 in the connection regions 128 of semiconductor devices 100a-100b.

[0077] like Figures 4A-4C As shown, the semiconductor device 400 may include a signal contact structure 402 and a ground contact structure 404. In some embodiments, the signal contact structure 402 of the semiconductor device 400 may be connected to... Figure 1A-1B The signal contact structure 118 of the semiconductor device 100a-100b or Figure 2A The signal contact structure 202 of the semiconductor device 200 is similar to or the same as that of the semiconductor device 400. The ground contact structure 404 of the semiconductor device 400 can be similar to... Figure 1A-1B The grounding contact structure 119 of the semiconductor device 100a-100b or Figure 2A The grounding contact structure 204 of the semiconductor device 200 is similar to or the same.

[0078] In some embodiments, the signal contact structure 402 and the ground contact structure 404 can be arranged as an array 401, the array 401 having rows extending along the Y direction and columns extending along the X direction. In some embodiments, the array 401 of semiconductor devices can be... Figure 1A A portion of the connection region 128 of the semiconductor device 100a, wherein the array 401 of the signal contact structure 402 and the ground contact structure 404 can be separated into multiple groups 406 of corresponding signal conductive layers 116 and ground conductive layers 117 connected to each of the semiconductor structures 104a-104d of the semiconductor device 100a. For example, as Figure 4A As shown, the first group 406a of signal contact structure 402 and ground contact structure 404 may include the first row 401-1 of array 401, wherein the signal contact structure 402 in the first group 406a is connected to the first signal conductive layer 116a of semiconductor structure 104a, and the ground contact structure 404 in the first group 406a is connected to the first ground conductive layer 117a of semiconductor structure 104a. The second group 406b of signal contact structure 402 and ground contact structure 404 may include the second row 401-2 of array 401, wherein the signal contact structure 402 in the second group 406b is connected to the second signal conductive layer 116b of semiconductor structure 104b, and the ground contact structure 404 in the second group 406b is connected to the first ground conductive layer 117a of semiconductor structure 104b.

[0079] In some embodiments, the array 401 of signal contact structures 402 and ground contact structures 404 of the semiconductor device 400 may belong to the same group 406 connected to one of the semiconductor structures 104a-104d of the semiconductor device 100a. For example, all signal contact structures 402 in the array 401 may be connected to the first signal conductive layer 116a of the semiconductor structure 104a, and all ground contact structures 404 in the array 401 may be connected to the first ground conductive layer 117a of the semiconductor structure 104a.

[0080] In some implementations, such as Figures 4A-4C As shown, the rows of array 401 are aligned in the X direction. For example, as Figure 4A As shown, each of the signal contact structures 402 or each of the ground contact structures 404 in the first group 406a is aligned with one of the signal contact structures 402 or one of the ground contact structures 404 in the second group 406b (e.g., along the X direction).

[0081] In some implementations, the same number of signal contact structures 402 are between any two adjacent ground contact structures 404 in each row of array 401. In some implementations, this number is an integer between 1 and 5. For example, as... Figure 4A As shown, the number of signal contact structures 402 between any two adjacent ground contact structures 404 in each row of array 401 is 5. Figure 4B As shown, the number of signal contact structures 402 between any two adjacent ground contact structures 404 in each row of array 401 is 2. Figure 4C As shown, the number of signal contact structures 402 between any two adjacent ground contact structures 404 in each row of array 401 is 1.

[0082] Figure 5 A block diagram of a system 500 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure is shown. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 5As shown, system 500 may include a host device 508 and a memory system 502 having one or more 3D memory devices 504 and a memory controller 506. The host device 508 may include a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host device 508 may be configured to send data to or receive data from one or more 3D memory devices 504.

[0083] 3D memory device 504 can be any 3D memory device disclosed herein, such as Figure 1A-1B The 3D memory device 504 is depicted in the present disclosure. In some embodiments, the 3D memory device 504 includes at least one DRAM memory. A memory controller 506 (also referred to as controller circuitry) is coupled to the 3D memory device 504 and the host device 508. According to embodiments of the present disclosure, the 3D memory device 504 may include a plurality of conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller 506 may be coupled to the 3D memory device 504 through at least one of the plurality of conductive interconnects. The memory controller 506 is configured to control the 3D memory device 504. For example, the memory controller 506 may be configured to operate a plurality of channel structures via word lines. The memory controller 506 may manage data stored in the 3D memory device 504 and communicate with the host device 508.

[0084] In some implementations, the memory controller 506 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 506 is designed / configured to operate in high duty cycle environments, such as in SSDs, or in embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 506 can be configured to control the operation of the 3D memory device 504, such as read, erase, and program (or write) operations. The memory controller 506 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 506 is also configured to handle error correction codes (ECC) regarding data read from or written to the 3D memory device 504. The memory controller 506 may also perform any other suitable function, such as formatting the 3D memory device 504.

[0085] The memory controller 506 can communicate with external devices (e.g., host device 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0086] The memory controller 506 and one or more 3D memory devices 504 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 502 can be implemented and packaged into different types of end electronic products. Figure 5 In one example shown, the memory controller 506 and a single 3D memory device 504 can be integrated into the memory card 502. The memory card 502 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0087] The embodiments of the subject matter and actions described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random access memory device, or a combination of one or more of these, or as part thereof. The computer storage medium is not the propagated signal.

[0088] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some implementations," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include those specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will be able to influence such features, structures, or characteristics in conjunction with other implementations (whether explicitly described or not).

[0089] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0090] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” when there is an intermediate feature or layer between the two. Furthermore, “above” or “above” means not only “on” or “above” but can also include “on” or “above” when there is no intermediate feature or layer between the two (i.e., directly on).

[0091] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for descriptive purposes to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the equipment in use or process steps. The equipment may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0092] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top surface of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the bottom side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0093] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0094] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step, which is set during the design phase of the product or process along with a range of values ​​that are higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10%–30% of the value (e.g., ±0.10%, ±0.20%, or ±0.30% of the value).

[0095] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0096] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) that are vertically oriented on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0097] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can directly contact each other, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features do not directly contact each other. Furthermore, in various examples, reference numerals and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0098] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance given herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0099] While this disclosure includes numerous details of specific embodiments, these should not be construed as limiting the scope of the claims (which are defined by the claims themselves), but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in this disclosure in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed, in some cases, one or more features from the claimed combination may be derived from the combination, and the claims may be directed to sub-combinations or variations thereof.

[0100] Similarly, although operations are shown in the accompanying drawings and described in the claims in a specific order, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or to perform all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0101] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the drawings do not necessarily require a specific order or sequence to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0102] The scope and extent of this disclosure should not be limited by any of the embodiments described in the foregoing exemplary implementations, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first semiconductor structure and a second semiconductor structure are stacked along a first direction, wherein the first semiconductor structure includes a first ground conductive layer and a first signal conductive layer, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer; A first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and A second set of signal contact structures and ground contact structures, wherein the second set extends along the first direction into the second semiconductor structure, at least one signal contact structure in the second set contacts the second signal conductive layer, and at least one ground contact structure in the second set contacts the second ground conductive layer, wherein: At least one of the first group or the second group includes signal contact structures and ground contact structures arranged in an array; The array includes a first signal contact structure and a first ground contact structure arranged along a first line extending in a second direction perpendicular to the first direction; and Each of the first signal contact structures is adjacent to a corresponding ground contact structure in the array.

2. The semiconductor device according to claim 1, wherein, Each signal contact structure in the array is adjacent to a corresponding ground contact structure in the array, wherein the distance between the signal contact structure and the corresponding ground contact structure in the array is equal to the spacing dimension of the array.

3. The semiconductor device according to claim 2, wherein, Each signal contact structure in the array is adjacent to the same number of ground contact structures in the array.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The first grounding contact structure is evenly spaced between the first signal contact structures.

5. The semiconductor device according to any one of claims 1 to 4, wherein, At least one of the first semiconductor structure or the second semiconductor structure is a dynamic random access memory (DRAM) device.

6. The semiconductor device according to claim 5, wherein, The DRAM device includes an array structure and a peripheral structure. The array structure includes an array of DRAM cells, at least one DRAM cell of the array structure includes a transistor and a capacitor, and the peripheral structure includes peripheral circuitry configured to control the array of DRAM cells.

7. The semiconductor device according to claim 2, wherein, The spacing dimension is in the range of 0.5 micrometers (μm) to 10 μm, and the dimension of each signal contact structure or each ground contact structure in the array along the second direction is between 0.5 μm and 10 μm.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The same number of first signal contact structures are located between any two adjacent first ground contact structures along the second direction.

9. The semiconductor device according to claim 8, wherein, The quantity is an integer between 1 and 5.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The array further includes a second signal contact structure and a second ground contact structure arranged along a second line extending in the second direction, the second ground contact structures being uniformly spaced between the second signal contact structures, and the second line being adjacent to the first line along a third direction perpendicular to the first direction and the second direction.

11. The semiconductor device according to claim 10, wherein, Each of the first signal contact structures or each of the first ground contact structures is aligned with one of the second signal contact structures or one of the second ground contact structures along the third direction.

12. The semiconductor device according to claim 10, wherein, Each of the first signal contact structure and the first ground contact structure is located along the second direction between two adjacent second signal contact structures or between one of the second signal contact structures and one of the second ground contact structures.

13. The semiconductor device according to any one of claims 1 to 10, further comprising: A third semiconductor structure, comprising a third ground conductive layer and a third signal conductive layer, wherein the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure along the first direction; and A third group of signal contact structures and ground contact structures, wherein the third group extends along the first direction into the third semiconductor structure, at least one signal contact structure in the third group contacts the third signal conductive layer, at least one ground contact structure in the third group contacts the third ground conductive layer, the third group comprising third signal contact structures and third ground contact structures arranged along a third line extending in the second direction, and each of the third signal contact structures is adjacent to at least one ground contact structure in the third group.

14. The semiconductor device of claim 13, further comprising: A first bonding structure located between the first semiconductor structure and the second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded together by the first bonding structure; and A second bonding structure is located between the second semiconductor structure and the third semiconductor structure, wherein the second semiconductor structure and the third semiconductor structure are bonded together by the second bonding structure.

15. A semiconductor device, comprising: A first semiconductor structure and a second semiconductor structure stacked along a first direction, wherein the first semiconductor structure includes a first substrate, a first ground conductive layer and a first signal conductive layer, the first substrate includes a first dielectric structure and a semiconductor material adjacent to the first dielectric structure, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer; A first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, at least one signal contact structure in the first group is adjacent to a corresponding ground contact structure in the first group, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and A second group of signal contact structures and ground contact structures, wherein the second group extends along the first direction through the first dielectric structure and into the second semiconductor structure, at least one signal contact structure in the second group is adjacent to a corresponding ground contact structure in the second group, at least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer.

16. The semiconductor device according to claim 15, wherein, The second semiconductor structure includes a second substrate, the second substrate including a second dielectric structure and a semiconductor material adjacent to the second dielectric structure, and the semiconductor device further includes: A third semiconductor structure, comprising a third ground conductive layer and a third signal conductive layer, wherein the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure along the first direction; and A third group of signal contact structures and ground contact structures, wherein the third group extends along the first direction from the first semiconductor structure, through the first dielectric structure and the second dielectric structure and into the third semiconductor structure, at least one signal contact structure in the third group is adjacent to a corresponding ground contact structure in the third group, at least one signal contact structure in the third group contacts the third signal conductive layer, and at least one ground contact structure in the third group contacts the third ground conductive layer.

17. The semiconductor device according to claim 16, wherein, The first dielectric structure and the second dielectric structure have the same dimensions along a second direction perpendicular to the first direction and are aligned along the first direction. The semiconductor material in the first substrate is adjacent to the first dielectric structure along the second direction, and the semiconductor material in the second substrate is adjacent to the second dielectric structure along the second direction.

18. The semiconductor device according to any one of claims 15 to 17, wherein, The first semiconductor structure and the second semiconductor structure are bonded together by a dielectric bonding structure.

19. The semiconductor device according to any one of claims 15 to 18, wherein, At least one of the first semiconductor structure or the second semiconductor structure is a dynamic random access memory (DRAM) device.

20. The semiconductor device of claim 19, wherein, The DRAM device includes an array structure and a peripheral structure. The array structure includes an array of DRAM cells, at least one DRAM cell of the array structure includes a transistor and a capacitor, and the peripheral structure includes peripheral circuitry configured to control the array of DRAM cells.

21. The semiconductor device according to claim 20, wherein, The array structure and the peripheral structure are bonded together by a bonding structure, and the bonding structure includes conductive bonding contacts and a dielectric material that isolates the conductive bonding contacts.

22. The semiconductor device according to any one of claims 15 to 21, wherein, The signal contact structure and the ground contact structure in at least one of the first group or the second group are arranged in an array, each signal contact structure in the signal contact structure is adjacent to a corresponding ground contact structure in the ground contact structure, wherein the distance between the signal contact structure and the corresponding ground contact structure is equal to the spacing dimension of the array.

23. A semiconductor device, comprising: A first semiconductor structure and a second semiconductor structure stacked along a first direction, wherein the first semiconductor structure includes a first substrate, a first ground conductive layer and a first signal conductive layer, and the second semiconductor structure includes a second ground conductive layer and a second signal conductive layer; A first group of signal contact structures and ground contact structures, wherein the first group extends along the first direction into the first semiconductor structure, at least one signal contact structure in the first group is adjacent to a corresponding ground contact structure in the first group, at least one signal contact structure in the first group contacts the first signal conductive layer, and at least one ground contact structure in the first group contacts the first ground conductive layer; and A second group of signal contact structures and ground contact structures, wherein the second group extends along the first direction through the first substrate and into the second semiconductor structure, at least one signal contact structure in the second group is adjacent to a corresponding ground contact structure in the second group, at least one signal contact structure in the second group contacts the second signal conductive layer, and at least one ground contact structure in the second group contacts the second ground conductive layer.

24. The semiconductor device according to claim 23, wherein, The signal contact structure and the ground contact structure in at least one of the first group or the second group are arranged in an array, each signal contact structure in the signal contact structure is adjacent to a corresponding ground contact structure in the ground contact structure, wherein the distance between the signal contact structure and the corresponding ground contact structure is equal to the spacing dimension of the array.

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