A semiconductor device and a method of fabricating the same

Abstract

This application provides a semiconductor device and a method for fabricating the same, comprising: providing a substrate, forming a first interlayer dielectric layer on the substrate, forming a first metal interconnect layer in the first interlayer dielectric layer, and forming an opening in the first metal interconnect layer; forming a capacitor structure in the first interlayer dielectric layer, comprising: forming a first mask layer on the first interlayer dielectric layer, using the first mask layer and the first metal interconnect layer as masks, etching the first interlayer dielectric layer to form a trench, the trench communicating with the opening of the first metal interconnect layer; forming a capacitor material layer covering the first interlayer dielectric layer and the first metal interconnect layer and filling the trench; forming a second mask layer on the capacitor material layer, using the second mask layer as a mask, etching away a portion of the capacitor material layer, the remaining capacitor material layer constituting the capacitor structure, wherein the first mask layer and the second mask layer are formed using the same mask, one of the first mask layer and the second mask layer is a negative photoresist layer, and the other is a positive photoresist layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Capacitors are commonly used passive electronic devices in integrated circuits (ICs). They store electrical energy by accumulating charge on two parallel plates separated by a dielectric insulating material. In ICs, capacitors perform various functions, such as filtering stray noise, decoupling power supplies, and adjusting circuit resonant frequencies. Common capacitor types in ICs include metal-oxide-semiconductor (MOS) capacitors, metal-insulator-metal (MIM) capacitors, and thin-film capacitors. While MIM capacitors offer high capacitance density, their low breakdown voltage, limited by their structure and material properties, makes them unsuitable for high-voltage applications. Trench capacitors, by housing functional layers within trenches, significantly increase capacitance density per unit area and are widely used in high-performance integrated circuits.

[0003] In related technologies, trench capacitor fabrication typically involves multiple photolithographic masks used in a step-by-step process. This includes: first, etching trenches using a Via Trench Capacitor (VTC) mask to form a trench structure within the interlayer dielectric layer and expose the lower electrode; then, trench filling is performed, sequentially depositing a first conductive layer, a dielectric layer, and a second conductive layer to form a stacked trench capacitor structure; next, etching capacitors using a Metal Dielectric Capacitor Mask (MDC); and finally, etching vias using a Top Via (TV) mask to bring out the electrodes of the trench capacitor. However, this process requires at least three photolithographic masks, resulting in high costs, complex operation, and significant implementation difficulties. Furthermore, due to process limitations, trench capacitors can only be located below the top metal layer, leading to poor design flexibility and difficulty in meeting the application requirements of highly integrated integrated circuits.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating a semiconductor device, comprising: providing a substrate, forming a first interlayer dielectric layer on the substrate, forming a first metal interconnect layer in the first interlayer dielectric layer, forming an opening penetrating the first metal interconnect layer in the first metal interconnect layer, and exposing the top surface of the first metal interconnect layer in the first interlayer dielectric layer; forming a capacitor structure in the first interlayer dielectric layer, comprising: forming a patterned first mask layer on the first interlayer dielectric layer, and using the patterned first mask layer and the first metal interconnect layer as masks, etching the first interlayer dielectric layer to form an opening penetrating the first interlayer dielectric layer. A trench is formed in the dielectric layer, the trench being connected to the opening of the first metal interconnect layer; a capacitor material layer is formed covering the first interlayer dielectric layer and the first metal interconnect layer and filling the trench; a patterned second mask layer is formed on the capacitor material layer, and a portion of the capacitor material layer on the first interlayer dielectric layer and the first metal interconnect layer is etched away using the patterned second mask layer as a mask, the remaining capacitor material layer constituting the capacitor structure, wherein the patterned first mask layer and the patterned second mask layer are formed using the same mask, one of the first mask layer and the second mask layer is a negative photoresist layer, and the other is a positive photoresist layer.

[0007] For example, the method further includes: forming a second interlayer dielectric layer covering the capacitor structure, the first interlayer dielectric layer and the first metal interconnect layer, and forming a first interconnect structure and a second interconnect structure in the second interlayer dielectric layer, wherein the first interconnect structure is electrically connected to the capacitor structure and the second interconnect structure is electrically connected to the first metal interconnect layer.

[0008] For example, the first metal interconnect layer is formed using a first mask, and the patterned first mask layer and the patterned second mask layer are formed using a second mask. The first metal interconnect layer includes an interconnect region and an opening region adjacent to the interconnect region. The opening region has an array of opening patterns, which are used to define the openings in the first metal interconnect layer.

[0009] For example, multiple first interlayer dielectric layers are formed on the substrate, and the multiple first interlayer dielectric layers are stacked sequentially along a direction perpendicular to the surface of the substrate. Each first interlayer dielectric layer has a first metal interconnect layer and the capacitor structure formed therein. Each first interlayer dielectric layer has an opening through the first metal interconnect layer. Each first interlayer dielectric layer exposes the top surface of the corresponding first metal interconnect layer.

[0010] For example, a second metal interconnect layer is formed in the substrate, the substrate exposes the top surface of the second metal interconnect layer, and the trench exposes a portion of the second metal interconnect layer.

[0011] For example, the first interlayer dielectric layer includes a first barrier layer and a first dielectric layer located on the first barrier layer; and / or the second interlayer dielectric layer includes a second barrier layer and a second dielectric layer located on the second barrier layer.

[0012] For example, the capacitor material layer includes a first conductive material layer, an insulating material layer and a second conductive material layer stacked sequentially. The first conductive material layer covers the bottom and sidewalls of the trench and the surface of the first interlayer dielectric layer. The insulating material layer covers the first conductive material layer and the second conductive material layer covers the insulating material layer.

[0013] Another aspect of this application provides a semiconductor device, comprising: a substrate; a first interlayer dielectric layer located on the substrate, wherein a first metal interconnect layer is formed in the first interlayer dielectric layer, an opening is formed in the first metal interconnect layer, the first interlayer dielectric layer exposes a top surface of the first metal interconnect layer, a trench is formed in the first interlayer dielectric layer that penetrates the first interlayer dielectric layer, the trench communicating with the opening of the first metal interconnect layer; and a capacitor structure located in the trench and covering a portion of the surface of the first metal interconnect layer.

[0014] For example, it further includes: a second interlayer dielectric layer covering the capacitor structure, the first interlayer dielectric layer, and the first metal interconnect layer; a first interconnect structure located in the second interlayer dielectric layer, wherein the first interconnect structure is electrically connected to the capacitor structure; and a second interconnect structure located in the second interlayer dielectric layer, wherein the second interconnect structure is electrically connected to the first metal interconnect layer.

[0015] For example, multiple first interlayer dielectric layers are formed on the substrate, and the multiple first interlayer dielectric layers are stacked sequentially along a direction perpendicular to the surface of the substrate. Each first interlayer dielectric layer has a first metal interconnect layer and the capacitor structure formed therein. Each first interlayer dielectric layer has an opening through the first metal interconnect layer. Each first interlayer dielectric layer exposes the top surface of the corresponding first metal interconnect layer.

[0016] The semiconductor device and its fabrication method provided in this application utilize a single mask to fabricate a patterned first mask layer and a patterned second mask layer. Using the patterned first mask layer and a first metal interconnect layer as masks, a first interlayer dielectric layer is etched to form trenches, ensuring communication between the trenches and the openings of the first metal interconnect layer. This facilitates the subsequent formation of a capacitor structure. This design effectively reduces the number of masks and process steps, significantly lowering manufacturing costs and process complexity. Simultaneously, by fabricating the capacitor structure between interlayer dielectric layers, it improves the flexibility of capacitor layout, adapts to the design requirements of highly integrated semiconductor devices, and balances process convenience with device performance stability. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0018] In the attached image: Figures 1A-1D A schematic diagram of the semiconductor device obtained by sequentially implementing the semiconductor device fabrication method of the related technology of this application is shown; Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3F This illustration shows a schematic diagram of the semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application; Figure 4 A top view of the first metal interconnect layer of this application is shown; Figure 5 A planar schematic diagram of the second mask of this application is shown. Detailed Implementation

[0019] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In related technologies, such as Figures 1A-1D As shown, the fabrication of trench capacitors is typically achieved in steps using multiple photomasks, including: first, providing a substrate 10, in which a lower electrode 11 is formed, and a first dielectric layer 12 is formed on the substrate 10; using a VTC mask, trenches 13 are etched to form trenches 13 in the first dielectric layer 12, exposing the lower electrode 11; then, trenches 13 are filled, and a first conductive layer 14, a dielectric layer 15, and a second conductive layer 16 are deposited sequentially to form a stacked structure of trench capacitor 17; next, trench capacitor 17 is etched using an MDC mask; finally, a protective layer 18 and a second dielectric layer 19 are formed on trench capacitor 17, wherein the first dielectric layer 12, the protective layer 18, and the second dielectric layer 19 constitute an intermetallic dielectric layer (IMD); then, vias 191 are etched using a TV mask to complete the electrode lead-out of the capacitor.

[0025] However, the trench structure of trench capacitors is usually fabricated using dry etching processes. Excessive etching depth can easily lead to instability in the critical dimension (CD) and process problems such as interruption of etching. At the same time, due to the influence of the trench capacitor structure layout, the IMD layer needs to be thickened accordingly, which requires the etching of the top via to cross a large topographic step difference. This makes the process difficult to implement and can easily cause open circuits in the via interconnects, leading to trench capacitor failure. In addition, the trench capacitor can only be placed below the top metal layer, and the capacitor placement position is fixed, resulting in poor design flexibility. Furthermore, the trench capacitor fabrication process requires at least three photomasks and cannot achieve multi-layer stacking integration applications. The process cost is high, and the capacitor density and capacitance improvement effect are limited, making it difficult to meet the application requirements of highly integrated integrated circuits.

[0026] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 2As shown, it mainly includes the following steps: Step S1: Provide a substrate, form a first interlayer dielectric layer on the substrate, form a first metal interconnect layer in the first interlayer dielectric layer, form an opening through the first metal interconnect layer in the first metal interconnect layer, and expose the top surface of the first metal interconnect layer in the first interlayer dielectric layer. Step S2, forming a capacitor structure in the first interlayer dielectric layer, includes: forming a patterned first mask layer on the first interlayer dielectric layer; using the patterned first mask layer and the first metal interconnect layer as masks, etching the first interlayer dielectric layer to form a trench penetrating the first interlayer dielectric layer, the trench being connected to the opening of the first metal interconnect layer; forming a capacitor material layer covering the first interlayer dielectric layer and the first metal interconnect layer and filling the trench; forming a patterned second mask layer on the capacitor material layer; using the patterned second mask layer as a mask, etching away a portion of the capacitor material layer on the first interlayer dielectric layer and the first metal interconnect layer, the remaining capacitor material layer constituting the capacitor structure, wherein the patterned first mask layer and the patterned second mask layer are formed using the same mask, one of the first mask layer and the second mask layer is a negative photoresist layer, and the other is a positive photoresist layer.

[0027] The semiconductor device and its fabrication method according to the embodiments of this application use the same mask to prepare a patterned first mask layer and a patterned second mask layer. The patterned first mask layer and the first metal interconnect layer are used as masks to etch the first interlayer dielectric layer to form trenches, ensuring that the trenches are connected to the openings of the first metal interconnect layer, thereby forming a capacitor structure. This design effectively reduces the number of mask layers and process steps, significantly reducing manufacturing costs and process complexity. At the same time, the capacitor structure is fabricated between the interlayer dielectric layers, which improves the layout flexibility of the capacitor, adapts to the design requirements of highly integrated semiconductor devices, and balances process convenience and device performance stability.

[0028] Example 1 Below, for reference Figure 2 as well as Figures 3A-3F The method for fabricating the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 3A-3F The diagram illustrates a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0029] For example, the method for fabricating the semiconductor device of this application includes the following steps: First, step S1 is performed, a substrate is provided, a first interlayer dielectric layer is formed on the substrate, a first metal interconnect layer is formed in the first interlayer dielectric layer, an opening is formed in the first metal interconnect layer, and the top surface of the first metal interconnect layer is exposed by the first interlayer dielectric layer.

[0030] In one example, such as Figure 3A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0031] In one example, such as Figure 3A As shown, a second metal interconnect layer 201 is formed in the substrate 20, and the top surface of the second metal interconnect layer 201 is exposed in the substrate 20. Specifically, a damascus trench can be formed in the substrate using a process including but not limited to photolithography etching, followed by deposition of metal material into the prepared trench, and then the surface is smoothed by a chemical mechanical polishing (CMP) process to form the second metal interconnect layer 201. For example, the material of the second metal interconnect layer 201 includes, but is not limited to, conductive materials such as copper (Cu), and the thickness of the first metal interconnect layer 201 is reasonably set according to process requirements and is not specifically limited thereto. The second metal interconnect layer of this application is formed using the above-mentioned damascus process. In addition, other conventional and suitable metal layer preparation methods in the art can also be used to process and form the second metal interconnect layer. After the second metal interconnect layer is formed, its top surface is exposed, which can provide an alignment reference for subsequent trench etching, and at the same time serve as the bottom conductive connection terminal of the subsequent capacitor, realizing a stable electrical interconnection between the capacitor and the underlying circuit.

[0032] In one example, a first interlayer dielectric layer 22 is formed on a substrate 20, a first metal interconnect layer 23 is formed in the first interlayer dielectric layer 22, an opening 231 is formed in the first metal interconnect layer 23, and the first interlayer dielectric layer 22 exposes the top surface of the first metal interconnect layer 23. Specifically, firstly, a first interlayer dielectric layer 22 can be formed on the substrate 20 using processes including but not limited to chemical vapor deposition (CVD). The material of the first interlayer dielectric layer 22 includes, but is not limited to, silicon oxide, silicon nitride, or low-k dielectric materials. Its function is to achieve interlayer electrical insulation, flatten the substrate surface morphology, and provide a flat process substrate for trench capacitor fabrication. Secondly, a first metal interconnect layer 23 is formed in the first interlayer dielectric layer 22 using photolithography etching and damascus etching. The metal interconnect layer can also be called an interconnect metal layer. The material of the first metal interconnect layer 23 includes, but is not limited to, conductive materials such as copper. While patterning the first metal interconnect layer 23, an opening 231 is formed through the first metal interconnect layer 23. During the subsequent trench etching of the first interlayer dielectric layer, the characteristic that the first metal interconnect layer 23 is not etched is used to make it a hard mask to position and block the trench etching, ensuring that the trench and the opening 231 are aligned and connected. The size, number, and distribution of the openings 231 can be adjusted according to the subsequent trench capacitor layout requirements, ensuring process alignment accuracy and electrical performance while improving the flexibility of circuit layout. After the first interlayer dielectric layer 22 is fabricated, it can be treated with processes including but not limited to chemical mechanical polishing to expose the top surface of the first metal interconnect layer 23, facilitating subsequent etching and capacitor material layer deposition and interconnection.

[0033] In one example, the first interlayer dielectric layer 22 includes a first barrier layer 221 and a first dielectric layer 222 located on the first barrier layer 221. The first metal interconnect layer 23 and the opening 231 penetrating it are both formed in the first dielectric layer 22. Exemplarily, the material of the first barrier layer 221 includes, but is not limited to, silicon nitride, silicon carbide, or silicon oxynitride. The first barrier layer 221 effectively blocks the upward diffusion of metal ions, preventing metal atoms in the metal interconnect layer from drifting into the dielectric layer, thus avoiding leakage and reliability degradation. It also serves as interlayer insulation, stress buffering, and improves interface adhesion. Furthermore, it can act as an etching stop layer in subsequent photolithography etching processes, improving process controllability. Exemplarily, the material of the first dielectric layer 222 includes, but is not limited to, silicon oxide or low-k dielectric materials, primarily used to achieve electrical insulation between adjacent metal interconnect layers, providing a stable and flat process substrate for subsequent trench etching and capacitor material layer deposition.

[0034] In one example, such as Figure 4As shown, the first metal interconnect layer 23 is formed by a first mask. The first metal interconnect layer includes an interconnect region 233 and an opening region 234 adjacent to the interconnect region 233. The opening pattern 235 of the opening region 234 is arranged in an array and is used to define the opening 231 in the first metal interconnect layer 23. Specifically, in the photolithography process for fabricating the first metal interconnect layer 23, a first mask is used to complete the photolithographic patterning. The first metal interconnect layer 23 is divided into an interconnect region 233 and an opening region 234 adjacent to the interconnect region 233. An array of opening patterns 235 are arranged in the opening region 234. In the photolithography process for fabricating the first metal interconnect layer 23, after exposure and development using the pattern of the first mask, the first metal interconnect layer is patterned and defined by an etching process. An opening 231 of a preset size is defined in the first metal interconnect layer 23 by the opening pattern 235. The opening region corresponds to the preset position of the trench 25 formed by the subsequent etching of the first interlayer dielectric layer 22. The opening 231 defined by the opening pattern in the opening region is connected to the trench 25 formed subsequently, realizing the positioning, alignment and connection structure. That is, the opening 231 is the alignment window for the subsequent trench etching, and the interconnect region 233 defines the circuit interconnection trace of the first metal interconnect layer 23. The same first photomask can simultaneously define the metal interconnect pattern and the opening pattern, providing positional constraints and pattern references for subsequent trench etching and capacitor structure forming, eliminating the need for additional photomasks, simplifying the process and saving manufacturing costs.

[0035] Next, step S2 is performed to form a capacitor structure in the first interlayer dielectric layer, including: forming a patterned first mask layer on the first interlayer dielectric layer; using the patterned first mask layer and the first metal interconnect layer as masks, etching the first interlayer dielectric layer to form a trench penetrating the first interlayer dielectric layer, the trench being connected to the opening of the first metal interconnect layer; forming a capacitor material layer covering the first interlayer dielectric layer and the first metal interconnect layer and filling the trench; forming a patterned second mask layer on the capacitor material layer; using the patterned second mask layer as a mask, etching away part of the capacitor material layer on the first interlayer dielectric layer and the first metal interconnect layer, the remaining capacitor material layer constituting the capacitor structure, wherein the patterned first mask layer and the patterned second mask layer are formed using the same mask, one of the first mask layer and the second mask layer is a negative photoresist layer, and the other is a positive photoresist layer.

[0036] In one example, the specific steps for forming the capacitor structure 26 in the first interlayer dielectric layer 22 include: First, such as Figure 3BAs shown, a patterned first mask layer 24 is formed on the first interlayer dielectric layer 22. The patterned first mask layer defines the region of the trench. Using the patterned first mask layer 24 and the first metal interconnect layer 23 as masks, the first interlayer dielectric layer 22 is etched to form a trench 25 penetrating the first interlayer dielectric layer. That is, the trench 25 exposes a portion of the second metal interconnect layer 201, and the trench 25 and the opening 231 of the first metal interconnect layer 23 are connected. Then, the patterned first mask layer 24 is removed. The etching of the first interlayer dielectric layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching. The number of trenches 25 can be one, two, three, four, five, or more, and there is no specific limitation.

[0037] Secondly, such as Figure 3C As shown, a capacitor material layer 261 is formed covering the first interlayer dielectric layer 22, the first metal interconnect layer 23, and filling the trench 25. Exemplarily, the method for forming the capacitor material layer 261 includes, but is not limited to, processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the capacitor material layer 261 includes a first conductive material layer 262, an insulating material layer 263, and a second conductive material layer 264 sequentially stacked. The first conductive material layer 262 covers the bottom and sidewalls of the trench 25, the surface of the first interlayer dielectric layer 22, and the surface of the first metal interconnect layer 23. The insulating material layer 263 covers the first conductive material layer 262, and the second conductive material layer 264 covers the insulating material layer 263. The first conductive material layer 262 can be made of one or more of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), or other conductive materials. The insulating material layer 263 can be made of materials including, but not limited to, aluminum oxide, hafnium oxide, silicon oxide, or silicon oxide. The second conductive material layer 264 can be made of one or more of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), or other conductive materials. The materials of the first conductive material layer 262 and the second conductive material layer 264 can be the same conductive material or different conductive materials; no specific limitation is made in this regard.

[0038] Next, as Figure 3C and Figure 3DAs shown, a patterned second mask layer 27 is formed on the capacitor material layer 261. Using the patterned second mask layer 27 as a mask, a portion of the capacitor material layer 261 on the first interlayer dielectric layer 22 and the first metal interconnect layer 23 is etched away. The remaining capacitor material layer 261 constitutes the capacitor structure 26. The patterned first mask layer 24 and the patterned second mask layer 27 are formed using the same mask. Specifically, after forming the capacitor material layer 261, a patterned second mask layer 27 is formed on the capacitor material layer 261, covering a portion of the capacitor material layer 261. Subsequently, using the patterned second mask layer 27 as a mask, a portion of the capacitor material layer 261 is etched away, that is, a portion of the capacitor material layer 261 on the first interlayer dielectric layer 22 and the first metal interconnect layer 23 is removed. The remaining capacitor material layer 261 serves as the capacitor structure 26. Finally, the patterned second mask layer 27 is removed. Among them, the etching of the capacitor material layer can be carried out by conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0039] For example, such as Figure 5 As shown, the patterned first mask layer 24 and the patterned second mask layer 27 are fabricated using the second mask 241. One of the first mask layer and the second mask layer is set as a negative photoresist layer and the other is set as a positive photoresist layer. By utilizing the different photolithography and development characteristics of the positive and negative photoresists, the trench etching pattern and the capacitor structure definition pattern are formed respectively under the premise of sharing the same mask (i.e., sharing the second mask). No additional mask is required, which greatly simplifies the process flow and saves manufacturing costs. At the same time, it ensures that the trench position and the capacitor position are aligned, with high structural matching and good process consistency, effectively improving the device performance and mass production yield of the integrated capacitor.

[0040] In another example, such as Figure 3FAs shown, multiple first interlayer dielectric layers 22 are formed on the substrate 20. These multiple first interlayer dielectric layers 22 are stacked sequentially along a direction perpendicular to the surface of the substrate 20. Each first interlayer dielectric layer 22 contains a first metal interconnect layer 23 and a capacitor structure 26. Each first metal interconnect layer 23 in each first interlayer dielectric layer 22 has an opening 231 penetrating through it, and each first interlayer dielectric layer 22 exposes the top surface of its corresponding first metal interconnect layer 23. Multiple first interlayer dielectric layers can be configured according to integration density and capacitor stacking requirements. Each first interlayer dielectric layer 22 is formed sequentially according to the same fabrication process as in the aforementioned embodiments. Each first interlayer dielectric layer 22 contains a corresponding first metal interconnect layer 23, and each first metal interconnect layer 23 has an opening 231 penetrating its own thickness. Each first interlayer dielectric layer 22 exposes the top surface of its corresponding first metal interconnect layer 23. Each first interlayer dielectric layer 22 follows the same process steps as described above: a patterned first mask layer is formed sequentially; trenches connected to the openings are etched using the first mask layer and its corresponding first metal interconnect layer as masks; a capacitor material layer is deposited to cover and fill the trenches; and excess capacitor material layers are removed by etching using a patterned second mask layer as a mask. Finally, capacitor structures 26 are formed in each first interlayer dielectric layer 22. This application places the capacitor structure within the interlayer dielectric layer, which not only effectively improves design flexibility but also avoids the high step difference problem caused by increasing the thickness of the dielectric layer, thereby reducing the difficulty of subsequent via etching. By using the same mask and combining it with the metal interconnect layer as a hard mask to fabricate the trench and capacitor structures, the number of masks is reduced, saving manufacturing costs. In addition, this process is highly reusable; only one additional mask is needed to complete the fabrication of each trench capacitor. By repeating this process layer by layer, multiple capacitor structures can be stacked vertically (i.e., in the direction perpendicular to the surface of the substrate), thereby significantly increasing the capacitance density per unit area while maintaining the simplicity and high compatibility of the overall process.

[0041] In one example, such as Figure 3EAs shown, a second interlayer dielectric layer 28 is formed covering the capacitor structure 26, the first interlayer dielectric layer 22, and the first metal interconnect layer 23. Exemplarily, the second interlayer dielectric layer 28 can be formed using processes including, but not limited to, chemical vapor deposition (CVD). Exemplarily, the second interlayer dielectric layer 28 includes a second barrier layer 281 and a second dielectric layer 282 located on the second barrier layer 281. The material of the second barrier layer 281 includes, but is not limited to, silicon nitride, silicon carbide, or silicon oxynitride, and the material of the second dielectric layer 282 includes, but is not limited to, silicon oxide or a low-k dielectric material. The function of the second barrier layer 281 is to effectively prevent metal ions from penetrating into the capacitor structure or metal interconnect layer, causing problems such as leakage, capacitor failure, and decreased device reliability. It can also serve as an etching stop layer in the subsequent interconnect structure etching process. The function of the second dielectric layer 282 is to achieve electrical insulation isolation, avoiding problems such as short circuits and signal crosstalk between different structures.

[0042] In one example, a first interconnect structure 291 and a second interconnect structure 292 are formed in the second interlayer dielectric layer 28. Specifically, after forming the second interlayer dielectric layer 28, photolithography and etching processes are performed to define a first via and a second via in the second interlayer dielectric layer 28. Subsequently, metal material is filled into the first and second vias by chemical vapor deposition (CVD), electroplating, or other processes to form the first interconnect structure 291 and the second interconnect structure 292. The first interconnect structure 291 is electrically connected to the capacitor structure 26, and the second interconnect structure 292 is electrically connected to the first metal interconnect layer 23. Other conventional processes in the art can also be used to form the interconnect structures; specific details are not described here.

[0043] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0044] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included in the scope of the fabrication method of this embodiment.

[0045] In summary, the semiconductor device fabrication method of this application uses the same mask to fabricate a patterned first mask layer and a patterned second mask layer. Using the patterned first mask layer and the first metal interconnect layer as masks, a first interlayer dielectric layer is etched to form trenches, ensuring that the trenches are connected to the openings of the first metal interconnect layer, thereby subsequently forming a capacitor structure. This design effectively reduces the number of masks used and process steps, significantly reducing manufacturing costs and process complexity. Simultaneously, by fabricating the capacitor structure between the interlayer dielectric layers, it improves the flexibility of capacitor layout, adapts to the design requirements of highly integrated semiconductor devices, and balances process convenience with device performance stability.

[0046] Example 2 This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or by other suitable preparation methods.

[0047] The following reference Figures 3A-3F The semiconductor devices in the embodiments of this application will be explained and described, wherein structures that are the same as those in the aforementioned Embodiment 1 will not be described in detail here.

[0048] Specifically, such as Figures 3A-3F As shown, the semiconductor device of this application includes: a substrate 20; a first interlayer dielectric layer 22 located on the substrate 20; a first metal interconnect layer 23 formed in the first interlayer dielectric layer 22; an opening 231 penetrating the first metal interconnect layer 23 formed in the first metal interconnect layer 23; the first interlayer dielectric layer 22 exposing the top surface of the first metal interconnect layer 23; a trench 25 penetrating the first interlayer dielectric layer 22 formed in the first interlayer dielectric layer 22; the trench 25 communicating with the opening 231 of the first metal interconnect layer 23; and a capacitor structure 26 located in the trench 25 and covering a portion of the surface of the first metal interconnect layer 23.

[0049] In one example, the material of substrate 20 includes, but is not limited to, at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-side polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0050] In one example, such as Figure 3A As shown, a second metal interconnect layer 201 is formed in the substrate 20, and the top surface of the second metal interconnect layer 201 is exposed in the substrate 20. Exemplarily, the material of the second metal interconnect layer 201 includes, but is not limited to, conductive materials such as copper (Cu), and the thickness of the second metal interconnect layer 201 is reasonably set according to process requirements and is not specifically limited thereto.

[0051] In one example, a first interlayer dielectric layer 22 is formed on the substrate 20, a first metal interconnect layer 23 is formed in the first interlayer dielectric layer 22, and an opening 231 is formed in the first metal interconnect layer 23, exposing the top surface of the corresponding first metal interconnect layer 23. Exemplarily, the material of the first interlayer dielectric layer 22 includes, but is not limited to, silicon oxide, silicon nitride, or low-k dielectric materials, and its function is to achieve interlayer electrical insulation, smooth the substrate surface morphology, and provide a smooth process substrate for the fabrication of the upper trench capacitor. The opening 231 is formed in the first metal interconnect layer 23, and the subsequently formed trench 25 communicates with the opening 231.

[0052] In one example, the first interlayer dielectric layer 22 includes a first barrier layer 221 and a first dielectric layer 222 located on the first barrier layer 221. Exemplarily, the material of the first barrier layer 221 includes, but is not limited to, silicon nitride, silicon carbide, or silicon oxynitride. Exemplarily, the material of the first dielectric layer 222 includes, but is not limited to, silicon oxide or a low-k dielectric material.

[0053] In one example, a capacitor structure 26 is formed in the first interlayer dielectric layer 22. Exemplarily, a trench 25 is formed in the first interlayer dielectric layer 22, penetrating the first interlayer dielectric layer 22, the trench 25 communicating with an opening 231 of the first metal interconnect layer 23, and the capacitor structure 26 is located in the trench 25 and covers a portion of the surface of the first metal interconnect layer 23.

[0054] In another example, multiple first interlayer dielectric layers 22 are formed on the substrate 20. The multiple first interlayer dielectric layers 22 are stacked sequentially along a direction perpendicular to the surface of the substrate 20. Each first interlayer dielectric layer 22 has a first metal interconnect layer 23 and a capacitor structure 26 formed therein. Each first interlayer dielectric layer 22 has an opening 231 that penetrates the first metal interconnect layer 23. Each first interlayer dielectric layer 22 exposes the top surface of the corresponding first metal interconnect layer 23. For example, when a first interlayer dielectric layer 22 is provided, the trench 25 in the first interlayer dielectric layer 22 near the substrate exposes the second metal interconnect layer 201. The purpose of this arrangement is to enable the capacitor structure 26 of this layer to achieve stable electrical interconnection with the bottom circuit of the substrate through the second metal interconnect layer 201 at the bottom of the trench 25; the trench 25 in the remaining first interlayer dielectric layer 22 exposes the first metal interconnect layer 23 in the adjacent first interlayer dielectric layer 22 below it, realizing the docking of the capacitors of the upper and lower adjacent layers with the metal interconnect layer.

[0055] In one example, a second interlayer dielectric layer 28 is also included, which covers the capacitor structure 26, the first interlayer dielectric layer 22, and the first metal interconnect layer 23. Exemplarily, the second interlayer dielectric layer 28 includes a second barrier layer 281 and a second dielectric layer 282 located on the second barrier layer 281. The material of the second barrier layer 281 includes, but is not limited to, silicon nitride, silicon carbide, or silicon oxynitride, and the material of the second dielectric layer 282 includes, but is not limited to, silicon oxide or a low-k dielectric material.

[0056] In one example, a first interconnect structure 291 and a second interconnect structure 292 are also included. The first interconnect structure 291 is located in the second interlayer dielectric layer 28, and the second interconnect structure 292 is located in the second interlayer dielectric layer 28. The first interconnect structure 291 is electrically connected to the capacitor structure 26, and the second interconnect structure 292 is electrically connected to the first metal interconnect layer 23.

[0057] In summary, the semiconductor device of this application uses the same mask to prepare a patterned first mask layer and a patterned second mask layer. The patterned first mask layer and the first metal interconnect layer are used as masks to etch the first interlayer dielectric layer to form trenches, ensuring that the trenches are connected to the openings of the first metal interconnect layer, thereby forming a capacitor structure. This design effectively reduces the number of masks used and process steps, significantly reducing manufacturing costs and process complexity. At the same time, by preparing the capacitor structure between the interlayer dielectric layers, the layout flexibility of the capacitor is improved, adapting to the design requirements of highly integrated semiconductor devices, and balancing process convenience and device performance stability.

[0058] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, on which a first interlayer dielectric layer is formed, a first metal interconnect layer is formed in the first interlayer dielectric layer, an opening is formed in the first metal interconnect layer, and the first interlayer dielectric layer exposes the top surface of the first metal interconnect layer. Forming a capacitor structure in the first interlayer dielectric layer includes: A patterned first mask layer is formed on the first interlayer dielectric layer. Using the patterned first mask layer and the first metal interconnect layer as masks, the first interlayer dielectric layer is etched to form a trench penetrating the first interlayer dielectric layer. The trench is connected to the opening of the first metal interconnect layer. A capacitor material layer is formed that covers the first interlayer dielectric layer and the first metal interconnect layer and fills the trench; A patterned second mask layer is formed on the capacitor material layer. Using the patterned second mask layer as a mask, a portion of the capacitor material layer on the first interlayer dielectric layer and the first metal interconnect layer is etched away. The remaining capacitor material layer constitutes the capacitor structure. The patterned first mask layer and the patterned second mask layer are formed using the same mask. One of the first mask layer and the second mask layer is a negative photoresist layer, and the other is a positive photoresist layer.

2. The preparation method according to claim 1, characterized in that, The method further includes: A second interlayer dielectric layer is formed to cover the capacitor structure, the first interlayer dielectric layer, and the first metal interconnect layer. A first interconnect structure and a second interconnect structure are formed in the second interlayer dielectric layer, wherein the first interconnect structure is electrically connected to the capacitor structure, and the second interconnect structure is electrically connected to the first metal interconnect layer.

3. The preparation method according to claim 1, characterized in that, The first metal interconnect layer is formed using a first mask, and the patterned first mask layer and the patterned second mask layer are formed using a second mask. The first metal interconnect layer includes an interconnect region and an opening region adjacent to the interconnect region. The opening region has an array of opening patterns, which are used to define the openings in the first metal interconnect layer.

4. The preparation method according to claim 1, characterized in that, Multiple first interlayer dielectric layers are formed on the substrate. The multiple first interlayer dielectric layers are stacked sequentially along a direction perpendicular to the surface of the substrate. Each first interlayer dielectric layer has a first metal interconnect layer and a capacitor structure. Each first interlayer dielectric layer has an opening that penetrates the first metal interconnect layer. Each first interlayer dielectric layer exposes the top surface of the corresponding first metal interconnect layer.

5. The preparation method according to claim 1, characterized in that, A second metal interconnect layer is formed in the substrate, the substrate exposes the top surface of the second metal interconnect layer, and the trench exposes a portion of the second metal interconnect layer.

6. The preparation method according to claim 2, characterized in that, The first interlayer dielectric layer includes a first barrier layer and a first dielectric layer located on the first barrier layer; and / or The second interlayer dielectric layer includes a second barrier layer and a second dielectric layer located on the second barrier layer.

7. The preparation method according to claim 1, characterized in that, The capacitor material layer includes a first conductive material layer, an insulating material layer, and a second conductive material layer stacked sequentially. The first conductive material layer covers the bottom and sidewalls of the trench and the surface of the first interlayer dielectric layer. The insulating material layer covers the first conductive material layer, and the second conductive material layer covers the insulating material layer.

8. A semiconductor device, characterized in that, include: Substrate; A first interlayer dielectric layer is located on the substrate. A first metal interconnect layer is formed in the first interlayer dielectric layer. An opening is formed in the first metal interconnect layer that penetrates the first metal interconnect layer. The first interlayer dielectric layer exposes the top surface of the first metal interconnect layer. A trench is formed in the first interlayer dielectric layer that penetrates the first interlayer dielectric layer. The trench communicates with the opening of the first metal interconnect layer. A capacitor structure located in the trench and covering a portion of the surface of the first metal interconnect layer.

9. The semiconductor device as claimed in claim 8, characterized in that, Also includes: A second interlayer dielectric layer covers the capacitor structure, the first interlayer dielectric layer, and the first metal interconnect layer. A first interconnect structure is located in the second interlayer dielectric layer, wherein the first interconnect structure is electrically connected to the capacitor structure; A second interconnect structure is located in the second interlayer dielectric layer, wherein the second interconnect structure is electrically connected to the first metal interconnect layer.

10. The semiconductor device as claimed in claim 8, characterized in that, Multiple first interlayer dielectric layers are formed on the substrate. The multiple first interlayer dielectric layers are stacked sequentially along a direction perpendicular to the surface of the substrate. Each first interlayer dielectric layer has a first metal interconnect layer and a capacitor structure. Each first interlayer dielectric layer has an opening that penetrates the first metal interconnect layer. Each first interlayer dielectric layer exposes the top surface of the corresponding first metal interconnect layer.

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