A method for fabricating superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation

Abstract

The application provides a super-junction planar gate silicon carbide VDMOS for inhibiting bipolar degradation and a preparation method. The method comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the upper side of the silicon carbide substrate to form a defect inhibition zone; epitaxially growing on the defect inhibition zone to form a drift layer; forming a barrier layer above the drift layer, etching, ion implanting to form a p region, a p+ region, an n region, a p-type well region and an n+ source region; removing the barrier layer, re-forming the barrier layer, etching and depositing through a via to form a gate insulating medium layer; removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a via and depositing through the via to form a gate metal layer; re-forming the barrier layer, forming the barrier layer above the drift layer, etching the barrier layer to form a via, depositing through the via to form a source metal layer, removing the barrier layer and completing the preparation, so that the compromise relationship between the withstand voltage and the on-resistance is optimized and the body diode freewheeling capability is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for fabricating a superjunction planar gate silicon carbide VDMOS that suppresses bipolar degradation. Background Technology

[0002] Silicon carbide (Silicon carbide), as a third-generation wide-bandgap semiconductor material, possesses excellent characteristics such as high critical breakdown electric field, high thermal conductivity, and fast saturated electron drift velocity, giving it significant advantages in high-voltage, high-frequency, and high-temperature power devices. Silicon carbide VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) devices fully utilize the high critical breakdown electric field characteristics of silicon carbide, significantly reducing drift layer thickness and on-resistance at the same voltage rating. Compared to silicon-based VDMOS devices, they exhibit superior power loss and switching performance, thus showing broad application prospects in high-voltage power conversion fields such as new energy vehicles, smart grids, and rail transportation.

[0003] However, silicon carbide VDMOS devices still face several technical challenges in practical applications. First, stacking faults are inevitably generated during the crystal growth and epitaxy of silicon carbide materials. These faults mainly originate from the silicon carbide substrate and extend into the epitaxial layer. When the device is bipolar-conducting in body diode freewheeling mode, the recombination energy of electron-hole pairs excites the growth and expansion of stacking faults, leading to a reduction in the active area and a decrease in minority carrier lifetime. This, in turn, causes a significant increase in the device's on-resistance and output characteristic drift; this phenomenon is known as "bipolar degradation." Bipolar degradation severely affects the long-term reliability and lifespan of silicon carbide VDMOS devices and is one of the key reliability issues currently restricting their large-scale industrialization.

[0004] Secondly, the on-resistance of silicon carbide VDMOS devices is closely related to the cell size. As the breakdown voltage increases, the drift layer thickness increases, and the on-resistance increases accordingly. To reduce on-resistance, existing technologies often employ superjunction structures, introducing alternating p-type and n-type pillar regions in the drift region to reduce on-resistance while maintaining breakdown voltage. However, the fabrication process of superjunction structures is complex, especially achieving deep trench etching and filling in silicon carbide materials, which is quite difficult. Furthermore, in planar gate silicon carbide VDMOS devices, the p-type well region undergoes lateral diffusion during high-temperature processing, leading to a reduction in the width of the JFET (Junction Field-Effect Transistor) region, increasing the resistance of the current path, and limiting further reduction in cell size and on-resistance.

[0005] To address the bipolar degradation problem, existing technologies attempt to suppress the propagation of stacking defects by optimizing substrate quality, improving epitaxial processes, and employing buffer layers. However, these methods are either costly or have limited effectiveness, making it difficult to completely eliminate defect propagation under bipolar conduction conditions. Regarding the JFET region shrinkage problem, some solutions mitigate it by adjusting the doping distribution of the p-type well region or increasing the JFET region width, but this often comes at the cost of sacrificing cell density or increasing on-resistance.

[0006] Therefore, how to effectively reduce the on-resistance and shrink the cell size while suppressing the bipolar degradation effect of silicon carbide VDMOS devices has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a method for fabricating a superjunction planar gate silicon carbide VDMOS that suppresses bipolar degradation, which can significantly suppress the bipolar degradation effect of SiC VDMOS devices, optimize the trade-off between breakdown voltage and on-resistance, and improve the freewheeling capability of the body diode.

[0008] In a first aspect, the present invention provides a method for fabricating a superjunction planar gate silicon carbide VDMOS that suppresses bipolar degradation, comprising the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow metal on the upper side of the silicon carbide substrate to form a defect suppression region. Step 2: Epitaxial growth is performed on the defect suppression region to form a drift layer; a barrier layer is formed above the drift layer, the barrier layer is etched to form a via, and ion implantation is performed to form a p-region; Step 3: Ion implantation to form the p+ region; Step 4: Remove the barrier layer from Step 3, form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form the n-region; Step 5: Remove the barrier layer from Step 4, form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form a p-type well region. Step 6: Remove the barrier layer from Step 5, form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form an n+ source region. Step 7: Remove the barrier layer from Step 6, form a barrier layer above the drift layer, etch the barrier layer to form vias, and deposit a gate insulating dielectric layer through the vias; Step 8: Remove the barrier layer from Step 7, form a barrier layer above the drift layer, etch the barrier layer to form a via, and deposit the gate metal layer through the via. Step 9: Remove the barrier layer from Step 8, form a barrier layer above the drift layer, etch the barrier layer to form a via, deposit the source metal layer through the via, remove the barrier layer, and complete the fabrication.

[0009] Secondly, the present invention provides a superjunction planar gate silicon carbide VDMOS that suppresses bipolar degradation, wherein the silicon carbide VDMOS is prepared by the superjunction planar gate silicon carbide VDMOS preparation method for suppressing bipolar degradation described in the first aspect.

[0010] The advantages of this invention are: 1. This invention establishes a defect suppression region using n-type diamond material between an n+ silicon carbide substrate and an n-type drift layer. Due to the difference in lattice constants between diamond and silicon carbide, a high defect density can be formed at this heterogeneous interface, effectively capturing and recombinizing stacking defects extending from the substrate and preventing their diffusion into the active region of the device. Simultaneously, the n-type doped diamond material, while ensuring good conductivity, avoids increasing on-resistance due to the introduction of a high-resistance layer. When the device is bipolar conducting in bulk diode freewheeling mode, the defect suppression region releases the growth energy of stacking defects in advance, thereby significantly suppressing the bipolar degradation effect and ensuring the long-term stability and reliability of the device.

[0011] 2. This invention forms p-regions on both sides of the n-type drift layer through layered epitaxy and ion implantation, constructing a superjunction structure extending from near the defect suppression region to near the gate structure. In the off-state, this superjunction structure exhibits lateral depletion between the p-regions and the n-type drift layer, increasing the effective doping concentration of the drift layer and significantly reducing the drift layer resistance under the same breakdown voltage conditions (3kV~5kV). In the on-state, majority carriers conduct laterally through the low-resistance n-type drift layer, avoiding the process complexity issues associated with deep trench etching and filling in traditional superjunction structures. Therefore, this invention effectively reduces on-resistance while ensuring high breakdown voltage capability, improving the figure of merit of power devices.

[0012] 3. The invention incorporates a p+ region and an adjacent n-region in the gate structure of the device, with the n-region distributed between the two p+ regions of the cell. The doping concentration of this n-region is higher than that of the n-type drift layer, maintaining a high n-type doping level in the middle of the p-type well region. This effectively compensates for the reduction in JFET width caused by lateral diffusion of the p-type well region during high-temperature processing. By rationally setting the minimum and maximum widths of the n-region, the invention reduces the cell size while avoiding a significant increase in on-resistance, achieving low on-resistance characteristics in small-sized cells, which is beneficial for improving cell integration density.

[0013] 4. This invention constructs a low-resistivity body diode structure within the gate structure, formed by the p+ region and the adjacent n-region. The high doping concentration of the p+ region effectively reduces the forward voltage drop of the body diode and improves its freewheeling current capability. When the device operates in applications requiring body diode freewheeling, such as bridge circuits, this low-resistivity body diode can significantly reduce reverse recovery charge and reverse recovery loss, thereby reducing system switching losses and improving overall conversion efficiency. Simultaneously, the width and thickness parameters of the p+ region ensure sufficient contact area with the n-region, further optimizing the current uniformity of the body diode.

[0014] 5. The device cell structure proposed in this invention is mainly based on conventional silicon carbide processes such as layered epitaxy, ion implantation, and barrier layer etching, without the need for complex processes such as deep trench etching and difficult filling. The n-type diamond material in the defect suppression region can be epitaxially grown using chemical vapor deposition (CVD), and the process conditions are highly compatible with silicon carbide epitaxy. Therefore, this invention achieves performance improvement while maintaining high process feasibility and yield, making it suitable for industrial-scale application. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0016] Figure 1 This is a cell cross-sectional view of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention.

[0017] Figure 2 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 1 .

[0018] Figure 3 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 2 .

[0019] Figure 4 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 3 .

[0020] Figure 5 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 4 .

[0021] Figure 6 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 5 .

[0022] Figure 7 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 6 .

[0023] Figure 8 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 7 .

[0024] Figure 9 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 8 .

[0025] Figure 10 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 9 .

[0026] Figure 11 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 10 .

[0027] Figure 12 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 10 one.

[0028] Figure 13 This is a cross-sectional view of the process of a superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention. Figure 10 two. Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0034] like Figures 1 to 13 As shown, this application provides a method for fabricating a superjunction planar gate silicon carbide VDMOS that suppresses bipolar degradation, comprising the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9, and epitaxially grow on the upper side of silicon carbide substrate 1 to form defect suppression region 2; Step 2: Epitaxial growth is performed on the defect suppression region 2 to form a drift layer 3; a barrier layer a is formed above the drift layer 3; the barrier layer a is etched to form a via; and ion implantation is performed to form the p region 31. Step 3: Ion implantation to form p+ region 4; Step 4: Remove the barrier layer a from step 3, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, and implant ions to form region n 5; Step 5: Remove the barrier layer a from step 4, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, and implant ions to form a p-type well region 51; Step 6: Remove the barrier layer a from step 5, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, and implant ions to form the n+ source region 511. Step 7: Remove the barrier layer a from step 6, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, and deposit the gate insulating dielectric layer 6 through the via. Step 8: Remove the barrier layer a from step 7, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, and deposit the gate metal layer 7 through the via. Step 9: Remove the barrier layer a from step 8, form a barrier layer a above the drift layer 3, etch the barrier layer a to form a via, deposit the source metal layer 8 through the via, remove the barrier layer a, and complete the fabrication.

[0035] In this embodiment, preferably, step 2 specifically comprises: Step 21: Epitaxial growth is performed on the defect suppression region 2 to form the first drift region 32; Step 22: Form a barrier layer a above the first drift region 32, etch the barrier layer a to form a via, and implant ions to form the first region 311; Step 23: Remove the blocking layer a from step 23, and epitaxially grow on the first drift region 32 to form the second drift region 33; Step 24: Form a barrier layer a above the second drift region 33, etch the barrier layer a to form a via, and implant ions to form the second region 312. The p region 31 includes the first region 311 and the second region 312. The drift layer 3 includes the first drift region 32 and the second drift region 33.

[0036] In this embodiment, preferably, the width of the p+ region 4 is equal to the width of the p region 31.

[0037] In this embodiment, preferably, the thickness of the drift layer 3 is greater than the thickness of the p region 31, and the p region 31 is located on both sides of the drift layer 3.

[0038] In this embodiment, preferably, the doping concentration of the p-region 31 is less than or equal to the doping concentration of the drift layer 3.

[0039] In this embodiment, preferably, the doping concentration of the p+ region 4 is greater than the doping concentration of the p-type well region 51.

[0040] In this embodiment, preferably, the thickness of the defect suppression region 2 is less than the thickness of the drift layer 3.

[0041] In this embodiment, preferably, the silicon carbide substrate 1, the defect suppression region 2, and the drift layer 3 are all N-type.

[0042] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1, Defect suppression region 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; Drift layer 3, the lower side of which is connected to the upper side of the defect suppression region 2, and a p region 31 is provided in the drift layer 3; p+ region 4, the lower side of p+ region 4 is connected to the upper side of p region 31; n region 5, the lower side of n region 5 is connected to the drift layer 3, the outer side of n region 5 is connected to the inner side of p+ region 4, and a p-type well region 51 is provided in n region 5, and an n+ source region 511 is provided in p-type well region 51. A gate insulating dielectric layer 6, the lower side of which is connected to the n+ source region 511, the p-type well region 51 and the n-region 5 respectively; Gate metal layer 7, the lower side of which is connected to the upper side of gate insulating dielectric layer 6; Source metal layer 8, which is connected to p+ region 4, p-type well region 51 and n+ source region 511 respectively; And a drain metal layer 9, the upper side of which is connected to the lower side of the silicon carbide substrate 1.

[0043] In another embodiment of the present invention, the doping concentration of the n-type silicon carbide substrate 1 is 2-8e18cm. -3 Defect suppression region 2 uses n-type diamond material with a doping concentration of 1-5e18cm. -3 The doping concentration of the n-type drift layer 3 is 1-5e17cm.-3 The doping concentration of p-region 31 is 6-10e16cm. -3 The doping concentration of n-region 5 is 6-10e17cm. -3 The doping concentration of p+ region 4 is 6-10e18cm. -3 The doping concentration of the p-type well region 51 is 6-10e17cm. -3 The doping concentration of the n+ source region 511 is 2-8e18cm. -3 The gate insulating dielectric layer 6 is a high-k dielectric such as silicon dioxide or hafnium dioxide, and the gate metal layer 7 and the source metal layer 8 are one or more alloys of copper, nickel, and aluminum. The doping concentration of the n-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, reducing the overall on-resistance of the device. The defect suppression region 2 uses n-type doped diamond material. Due to the difference in lattice between diamond and silicon carbide, lattice defects are captured and recombinated in this region to suppress the growth and diffusion of stacking defects. N-type doping can reduce the increase in device cell on-resistance caused by defect suppression region 2 (because the activation rate of n-type doping in diamond material is low, its doping concentration is high). This concentration is a trade-off between suppressing bipolar degradation and on-resistance. The doping concentration of the n-type drift layer 3 mainly considers the device's breakdown voltage and on-resistance. A high doping concentration results in low on-resistance but low breakdown voltage. Due to the use of a superjunction structure, its higher doping concentration can reduce the on-resistance of the device cell. The doping concentration of the p-region 31 is to ensure the device's superjunction structure. A high doping concentration will affect the effective freewheeling area of ​​the device, while a low doping concentration will reduce the on-resistance. This results in a lower breakdown voltage of the lateral pn junction in the superjunction structure. The doping concentration of the n-region 5 is higher than that of the n-type drift layer 3, but not too high. This is to ensure the width of the JFET region of the device without affecting the switching characteristics of the device, so as to ensure that the on-resistance of the device does not increase while reducing the device size. The doping concentration of the p-type well region 51 is to comprehensively ensure the low gate charge of the device, reduce the switching loss of the device, improve the switching speed of the device and reduce the leakage current. A high doping concentration of the p-type well region 51 results in a low leakage current but a large gate charge, and vice versa. The doping concentration of the p+ region 4 is to form a parasitic pn junction body diode of the device. Under the condition of suppressing bipolar degradation, the current carrying capacity of the pn junction body diode is greater, which can ensure the freewheeling capability of the device body diode. It is also to form a lateral pn junction breakdown voltage structure near the top of the gate, so as to avoid the electric field concentration at the gate structure. The doping concentration of the n+ source region 511 is to reduce the source resistance of the device. The thickness of the n-type silicon carbide substrate 1 is 1 μm, which is to ensure support during the device fabrication process. The thickness of the n-type drift layer 3 is 30-50 μm, because this structure can be applied to different withstand voltage ranges of 3KV-5KV. The withstand voltage range is mainly affected by the thickness of the n-type drift layer 3. The width of p+ region 4 is 1μm and the thickness is 2μm. This width, combined with the doping concentration, ensures the contact area between p+ region 4 and n region 5, thereby enabling the large current freewheeling of the parasitic diode of the device. Its thickness is to ensure the lateral diffusion of the space charge region during reverse breakdown, thereby improving the breakdown voltage of the device and ensuring the gate reliability of the device. The p-type well region 51 has a width of 2μm and a thickness of 1μm. This is to ensure the switching and breakdown voltage characteristics of the device while reducing the width of the JFET region. The thickness and width affect the breakdown voltage and off-state current. Sufficient thickness and width are necessary to ensure the off-state characteristics of the device. Too thick and too wide will affect the conduction characteristics of the device. The source metal layer 8 has a width of 2.5 μm and a thickness of 500 nm. This is to ensure the contact area between the source metal layer 8 and the p+ region 4 and the n+ source region 511, and to reduce the source contact resistance. The n+ source region 511 has a width of 1μm and a thickness of 500nm, and is distributed on the side of the p-type well region 51 near the gate. The minimum distance between the n+ source region 511 and the p-type well region 51 near the gate is 300nm. This is to ensure low ohmic contact resistance with the source metal and to ensure current capability. The n-region 5 has a maximum width of 5μm, a maximum thickness of 2μm, and a minimum width of 1μm. The minimum width is the minimum distance between the two p-type well regions 51. This distance is used to achieve low on-resistance while ensuring small device cell size. The maximum width spans between the p+ regions, which can ensure the body diode characteristics of the device. The gate insulating dielectric layer 6 has a width of 2μm, which is to ensure that the conductive channels of the device are distributed directly below the gate metal layer 7. The thickness is 50nm, which is determined by the characteristics of silicon carbide material and is a comprehensive consideration of the device's gate control capability and gate reliability. The gate metal layer 7 has a thickness of 500 nm and a width of 1.8 μm. The width of the overlap of the gate metal layer 7 with the longitudinal n+ source region 511 on the edge side is 100 nm. This overlap can avoid the gate metal not being distributed directly above the p-type well region 51 of the conductive channel due to process errors, thus ensuring the gate control capability of the device and ensuring the low resistance of the conductive channel. The thickness of defect suppression region 2 is 1 μm, which is to form effective defect suppression and reduce the impact on the on-resistance of the device; The width of p-region 31 is 1 μm, and the thickness of n-type drift layer 3 between its bottom and the defect suppression region is 5 μm. This is to ensure that the defects of the device diffuse into p-region 31 and affect the superjunction structure of the device. The device adopts an n-type silicon carbide substrate 1 and a defect suppression region 2 structure, which releases the stacking defects of the substrate in the defect suppression region 2, avoiding the bipolar degradation effect caused by the bipolar conduction of the device in the later stage. p-region 31 was formed by layered epitaxy and ion implantation on both sides of the n-type drift layer 3, constructing a superjunction structure from the device cell near the defect suppression region to the vicinity of the gate structure, which reduces the device on-resistance while ensuring the device withstand voltage. A p+ region 4 and an adjacent n region 5 are constructed in the gate structure. This structure can form a low-resistance body diode structure and improve the freewheeling capability of the body diode. The n-region 5 of the device is distributed between the two p+ regions 4 of the cell. It can ensure high n-type doping in the middle of the p-type well region 51, suppress the shrinkage of the JFET region caused by the lateral diffusion of doping, and affect the on-resistance of the cell, thus achieving low on-resistance of small-sized cells.

[0044] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation, characterized in that: Includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow metal on the upper side of the silicon carbide substrate to form a defect suppression region. Step 2: Epitaxial growth is performed on the defect suppression region to form a drift layer; a barrier layer is formed above the drift layer, the barrier layer is etched to form a via, and ion implantation is performed to form a p-region; Step 3: Ion implantation to form the p+ region; Step 4: Remove the barrier layer from Step 3, form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form the n-region; Step 5: Remove the barrier layer from Step 4, form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form a p-type well region. Step 6: Remove the barrier layer from Step 5, form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form an n+ source region. Step 7: Remove the barrier layer from Step 6, form a barrier layer above the drift layer, etch the barrier layer to form vias, and deposit a gate insulating dielectric layer through the vias; Step 8: Remove the barrier layer from Step 7, form a barrier layer above the drift layer, etch the barrier layer to form a via, and deposit the gate metal layer through the via. Step 9: Remove the barrier layer from Step 8, form a barrier layer above the drift layer, etch the barrier layer to form a via, deposit the source metal layer through the via, remove the barrier layer, and complete the fabrication.

2. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: Step 2 specifically involves: Step 21: Epitaxial growth is performed on the defect suppression region to form the first drift region; Step 22: Form a barrier layer above the first drift region, etch the barrier layer to form a via, and implant ions to form the first region; Step 23: Remove the blocking layer from step 23, and epitaxially grow on the first drift region to form the second drift region; Step 24: Form a barrier layer above the second drift region, etch the barrier layer to form a via, and implant ions to form the second region. The p-region includes the first region and the second region, and the drift layer includes the first drift region and the second drift region.

3. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The width of the p+ region is equal to the width of the p region.

4. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The thickness of the drift layer is greater than the thickness of the p region, and the p region is located on both sides of the drift layer.

5. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The doping concentration of the p-region is less than or equal to the doping concentration of the drift layer.

6. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The doping concentration of the p+ region is greater than that of the p-type well region.

7. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The thickness of the defect suppression region is less than the thickness of the drift layer.

8. The method for fabricating a superjunction planar gate silicon carbide VDMOS to suppress bipolar degradation as described in claim 1, characterized in that: The silicon carbide substrate, defect suppression region, and drift layer are all N-type.

9. A superjunction planar gate silicon carbide VDMOS for suppressing bipolar degradation, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

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