Semiconductor devices and their fabrication methods, power modules

Abstract

This application provides a semiconductor device and its fabrication method, as well as a power module. The method includes forming a trench within a semiconductor layer, forming a first dielectric layer in the corner region of the trench, and forming a second dielectric layer on the first dielectric layer. The second dielectric layer extends and covers the bottom and sidewall surfaces of the trench, and the dielectric constant of the second dielectric layer is lower than that of the first dielectric layer. The device includes a semiconductor layer with trenches, and a first dielectric layer and a second dielectric layer disposed within the trenches. The first dielectric layer is located in the corner region covering the trench, and the second dielectric layer is located on the first dielectric region covering the corner region. This application is advantageous for optimizing the electric field distribution of the semiconductor device in the trench corner region without introducing interface defects and lattice damage, thus meeting the stability and reliability requirements for applications operating under ultra-high electric field conditions.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and more specifically, to a semiconductor device and its preparation method, and a power module. Background Technology

[0002] In trench semiconductor devices, the gate dielectric layer is typically distributed continuously along the trench sidewalls and the trench bottom. Due to the geometric discontinuities at the trench corners, electric field accumulation is easily generated in this region during operation, resulting in a significant increase in the local electric field intensity at both ends of the gate dielectric layer.

[0003] The electric field concentration at both ends of the gate dielectric layer directly reduces the reliability of the gate dielectric layer, thereby inducing increased gate leakage current, threshold voltage drift, and shortening the long-term lifespan of the device. This makes trench corners a key factor affecting the withstand voltage and reliability of trench power devices. To alleviate the electric field concentration problem at trench corners, various structural modification schemes have been proposed to disperse the electric field distribution to a certain extent, thereby reducing the local peak electric field intensity. However, with the continuous miniaturization of device dimensions and the increasing integration density, existing structural modification methods also face shortcomings such as increased process complexity and limited suppression effect.

[0004] Therefore, how to effectively suppress the electric field concentration at the corner of the trench while also ensuring the simplicity of the process remains a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned problems, the first aspect of this application aims to provide a semiconductor device comprising: A semiconductor layer having trenches therein, the trenches having a bottom wall, side walls, and a corner area connecting the bottom wall and the side walls; A first dielectric layer is located within the trench and covers the corner area; A second dielectric layer is located on the first dielectric layer and extends to cover the bottom wall and the side wall; The dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.

[0006] The aforementioned semiconductor device includes a semiconductor layer with trenches, and a first dielectric layer and a second dielectric layer stacked within the trenches. The first dielectric layer is located in the corner region covering the trench, and the second dielectric layer is located on the first dielectric region covering the corner region, extending to cover the bottom and sidewall surfaces of the trench. This application, by covering the corner region of the trench with a first dielectric layer having a higher dielectric constant and using the first dielectric layer to separate the corner region from the second dielectric layer, optimizes the electric field distribution in the trench corner region without introducing interface defects or lattice damage. This effectively suppresses the phenomenon of electric field concentration at the corner tip, thereby contributing to a reduction in subsequent gate leakage current and an improvement in gate dielectric reliability, enabling the semiconductor device to meet the stability and reliability requirements under ultra-high electric field operating conditions.

[0007] A second aspect of this application provides a method for fabricating a semiconductor device, comprising: Provides a semiconductor layer; A trench is formed within the semiconductor layer, the trench having a bottom wall, sidewalls, and a corner area connecting the bottom wall and the sidewalls; A first dielectric layer is formed within the trench, and the first dielectric layer covers the corner area; A second dielectric layer is formed within the trench, the second dielectric layer covering the first dielectric layer and extending to cover the bottom wall and the side wall, and the dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.

[0008] The aforementioned semiconductor device fabrication method includes forming a trench within a semiconductor layer, forming a first dielectric layer in the corner region of the trench, and forming a second dielectric layer on the first dielectric layer, extending the second dielectric layer to cover the bottom and sidewalls of the trench, and setting the dielectric constant of the second dielectric layer to be smaller than that of the first dielectric layer. Therefore, without introducing interface defects or lattice damage, the electric field distribution in the corner region of the trench can be optimized using a first dielectric layer with a larger dielectric constant that covers the corner region. This effectively suppresses the electric field concentration phenomenon at the trench corner, and achieves subsequent reductions in gate leakage current and improvements in gate dielectric reliability, thereby enabling the semiconductor device to meet the stability and reliability requirements for applications operating under ultra-high electric field conditions.

[0009] A third aspect of this application provides a power module, the power module comprising: Substrate: A semiconductor device, wherein the semiconductor device is located on the substrate; wherein... The power module includes a semiconductor device as described in the first aspect above; or, a semiconductor device prepared using the semiconductor device preparation method described in the second aspect above.

[0010] The power module of the third aspect described above has the semiconductor device described in the first aspect, and therefore has all the beneficial effects of the semiconductor device described in the first aspect, which will not be repeated here. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0012] Figure 2 This is a schematic diagram of the structure of another semiconductor device according to an embodiment of this application.

[0013] Figure 3 for Figure 2 A magnified schematic diagram of the first and second dielectric layers.

[0014] Figure 4 This is a schematic flowchart illustrating a semiconductor device fabrication method according to an embodiment of this application.

[0015] Figures 5-12 This is a schematic diagram of the structure corresponding to each step in a semiconductor device fabrication method according to an embodiment of this application.

[0016] Figure 13 This is a schematic diagram of the structure of a power module according to an embodiment of this application.

[0017] Explanation of key component symbols: 10 Semiconductor device; 110 Semiconductor layer; 111 Substrate; 112 Drift region; 113 Well region; 114 Source region; 120 Trench; 130 Mask layer; 131 Window region; 140 First dielectric material layer; 141 First dielectric layer; 150 Passivation layer; 160 Second dielectric layer; 161 First dielectric region; 162 Second dielectric region; 162a First sub-dielectric region; 162b Second sub-dielectric region; 170 Gate electrode; 180 Insulating layer; 190 Source contact; 191 Ohmic contact metal layer; 200 Drain contact; A Corner region; 20 Power module; 210 Substrate.

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments of this application will be described below in conjunction with specific implementation methods. Obviously, the drawings and embodiments described below only involve some embodiments of this application and are not intended to limit this disclosure. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0020] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0022] In the description of the embodiments of this application, the term "layer" refers to a thin or thick film structure that is arranged layer by layer along the thickness direction of the device, has a continuous overall distribution, and possesses a unified molding process and overall function. Its molding process is mostly a one-time continuous process. The continuity referred to here means the complete form after deposition or growth but before patterning. Even if subsequent processes such as etching form openings, trenches, or discrete patterns (such as metal interconnects), these residual portions still belong to the same layer. The term "region" refers to a local semiconductor region within the same layer. These regions have different doping types, doping concentrations, or electrical functions. Their structures rely on the same semiconductor layer, but they have differentiated designs in local performance, thereby achieving functional partitioning and performance synergy among different regions within the same layer. Furthermore, the doping boundaries of "regions" are usually determined by ion implantation masks or diffusion windows. Even if a gradual junction exists at the boundary between different regions, they are still considered different partitions. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0023] In the description of the embodiments of this application, unless otherwise stated, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections, electrical connections, or connections that can communicate with each other; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two components or interactive relationships between two components.

[0024] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] As described in the background art, due to the geometric discontinuity at the corner of the trench, the gate in this region is prone to electric field accumulation during operation, which leads to a significant increase in the local electric field intensity at both ends of the gate dielectric layer.

[0026] To address the aforementioned technical problems, this application provides a semiconductor device structure and its fabrication method, including forming a trench within a semiconductor layer, and forming a first dielectric layer and a second dielectric layer with different dielectric constants within the trench. The first dielectric layer is formed in the corner region, and the second dielectric layer is formed on top of the first dielectric layer, covering the bottom and sidewalls of the trench outside the corner region. Therefore, without introducing interface defects or lattice damage, the electric field distribution in the trench corner region can be optimized by utilizing the first dielectric layer, which directly covers the corner region and has a higher dielectric constant. This effectively suppresses the sharp electric field concentration phenomenon at the trench corner, achieving reduced gate leakage current and improved gate dielectric reliability, thus enabling the semiconductor device to meet the application requirements under ultra-high electric field operating conditions. Furthermore, this application can achieve self-aligned forming of the first dielectric layer in the trench corner region while effectively suppressing the electric field concentration at the trench corner, without requiring additional photolithography or patterning alignment processes. This balances process simplicity and compatibility, effectively suppressing the electric field concentration at the trench corner while maintaining process simplicity, improving production yield and efficiency, and reducing manufacturing costs.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] According to a first aspect of this application, a semiconductor device is provided.

[0029] Please see Figure 1 and Figure 2The semiconductor device 10 of this application embodiment includes: a semiconductor layer 110, a trench 120 therein, and a first dielectric layer 141 and a second dielectric layer 160 stacked within the trench 120. Specifically, the trench wall of the trench 120 may include a bottom wall S1 located at the bottom of the trench 120, and a side wall S2 located above the bottom wall S1. The area where the bottom wall S1 and the side wall S2 connect constitutes a corner region A. The first dielectric layer 141 is located in the corner region A of the trench 120, and the second dielectric layer 160 is located on top of the second dielectric layer 160 covering the corner region A, extending to cover the surface of the trench wall 120 outside the corner region A. Furthermore, the dielectric constant of the first dielectric layer 141 is greater than that of the second dielectric layer 160.

[0030] This application forms a first dielectric layer 141 in the corner region of the trench 120, and forms a second dielectric layer 160 on the second dielectric layer 160 covering the corner region A, extending to cover the trench wall surface of the trench 120 outside the corner region A. This allows the second dielectric layer 160 to not only form a stable, low-defect semiconductor-dielectric interface with the inner wall of the trench 120, suppressing interface state charge and leakage current, but also to synergize with the high dielectric constant first dielectric layer 141. Thus, without introducing interface defects and lattice damage, the first dielectric layer 141 with a higher dielectric constant optimizes the electric field distribution of the trench 120 in the corner region A, effectively suppressing the peak electric field concentration phenomenon in the corner region A of the trench 120, and achieving the effects of reducing subsequent gate leakage current and improving gate dielectric reliability. This allows the semiconductor device 10 to meet the stability and reliability requirements under ultra-high electric field operating conditions.

[0031] Among them, semiconductor layer 110 refers to a combination of multiple functional layers or doped regions of a device formed in advance through processes such as epitaxy, ion implantation, high-temperature activation and annealing.

[0032] For example, the semiconductor layer 110 consists of a substrate 111 of a first conductivity type and a first epitaxial layer formed on the substrate 111.

[0033] Here, the first conductivity type refers to the impurity ion doping type that is opposite to the second conductivity type, including N-type impurity ion doping or P-type impurity ion doping, which can be flexibly set according to the specific semiconductor device 10 type. For example, when the first conductivity type is N-type doping, the second conductivity type is P-type doping, or vice versa. P-type impurity ions include impurity ions such as aluminum ions, boron ions, or indium ions, while N-type impurity ions include impurity ions such as nitrogen ions, phosphorus ions, or arsenic ions.

[0034] It should be noted that the specific structure and materials of the semiconductor layer 110 described above are merely illustrative examples and should not be construed as limiting the scope of protection of this application. In other words, the semiconductor layer 110 in this application includes, but is not limited to, semiconductor materials suitable for power semiconductor devices such as single-crystal silicon, silicon-on-insulator (SOI), germanium (Ge), silicon-germanium (GeSi), or gallium arsenide (GaAs).

[0035] Among them, trench 120 refers to one or more mutually spaced groove structures that extend into the semiconductor layer 110 to a predetermined depth by etching a predetermined area on the surface of the semiconductor layer 110 using a dry or wet etching method.

[0036] For example, the corner region A of the trench 120 is a curved surface, and the center of curvature of the corner region A is located within the trench 120. Setting the corner region A so that the center of curvature is located within the trench 120 helps to alleviate the electric field concentration phenomenon in the corner region A of the trench 120, improves the withstand voltage reliability of the semiconductor device 10, and can also repair the lattice damage remaining in the trench 120 during the etching process.

[0037] In some embodiments, the first dielectric layer 141 is composed of a high-k dielectric material.

[0038] The high-k dielectric material can be one or more of the following materials, including but not limited to zirconium dioxide (ZrO2), hafnium oxide (HfO2), titanium dioxide (TiO2), or zirconium hafnium oxide (HfZrO).

[0039] For example, the contact surface between the first dielectric layer 141 and the second dielectric layer 160 is a curved surface, and the center of curvature of the contact surface is located within the groove 120. Furthermore, the radius of curvature of the corner region A is smaller than the radius of curvature of the contact surface.

[0040] Since the contact surface between the first dielectric layer 141 and the second dielectric layer 160 is curved and its radius of curvature is greater than that of the corner area A, the contact surface and the corner area are connected at one end near the side wall S2 and the other end near the bottom wall S1, respectively, forming the first end and the second end of the first dielectric layer 141. The first end is the end of the first dielectric layer 141 near the side wall S2, and the second end is the end of the first dielectric layer 141 near the bottom wall S1.

[0041] Furthermore, since both the corner area A and the curvature center of the contact surface are located within the groove 120, the central region of the first dielectric layer 141 between the first end and the second end has a thickness greater than that of the edge regions near the first end and the edge regions near the second end.

[0042] For example, such as Figure 1 and Figure 2As shown, the first dielectric layer 141 has a continuously varying thickness, and the thickness of the first dielectric layer 141 continuously decreases from the central region between the first end and the second end toward the edge region near the first end and the edge region near the second end.

[0043] In some embodiments, such as Figure 1 As shown, the second dielectric layer 160 is composed of a uniform insulating dielectric material.

[0044] For example, the insulating dielectric material constituting the second dielectric layer 160 may include, but is not limited to, a silicon oxide dielectric layer. For instance, the second dielectric layer 160 is composed of a silicon oxide dielectric material with a dielectric constant k of approximately 3.9.

[0045] In other embodiments, such as Figure 2 and Figure 3 As shown, the second dielectric layer 160 is composed of a combination of different insulating dielectric materials.

[0046] The second dielectric layer 160 includes a first dielectric region 161 and a second dielectric region 162 stacked on top of each other; the first dielectric region 161 is formed on the first dielectric layer 141 and extends to cover the bottom wall S1 and the side wall S2, and the second dielectric region 162 is formed on the first dielectric region 161; and the dielectric constant of the second dielectric region 162 is greater than that of the first dielectric region 161, and the dielectric constant of the first dielectric layer 141 is greater than that of the second dielectric region 162.

[0047] Since the dielectric constant of the first dielectric layer 141 is greater than that of the second dielectric region 162, and the dielectric constant of the second dielectric region 162 is greater than that of the first dielectric region 161, the high dielectric constant of the first dielectric layer 141 can effectively share the electric field load, buffer the electric field stress of the trench 120 in the corner region A, and weaken the local electric field peak. At the same time, the second dielectric region 162, which has a lower dielectric constant than the first dielectric layer 141, can further share the electric field load in the corner region and further buffer the electric field stress of the trench 120 in the corner region A. Together with the inner first dielectric layer 141, they can form synergistic protection, which is conducive to weakening the local electric field peak, thereby improving the overall insulation withstand voltage level of the gate dielectric.

[0048] For example, the insulating dielectric material constituting the first dielectric region 161 may be silicon oxide, and the insulating dielectric material constituting the second dielectric region 162 may be one or more combinations of silicon nitride, silicon oxynitride, or other high-k dielectric materials.

[0049] By forming a second dielectric region 162 on the first dielectric region 161 covering the first dielectric layer 141, and using the first dielectric region 161 and the first dielectric layer 141 to separate the second dielectric region 162 from the inner wall surface of the trench 120, the average dielectric constant of the second dielectric layer 160 can be increased directly by utilizing the second dielectric region 162 with a larger dielectric constant without introducing interface defects and lattice damage. This optimizes the electric field distribution in the corner region A of the trench 120 and significantly reduces the local electric field intensity in the corner region A of the trench 120, which helps to alleviate the electric field concentration effect. As a result, the semiconductor device 10 can still meet the stringent requirements for electric field uniformity in high voltage and high frequency applications under ultra-high electric field operating conditions, thereby improving the breakdown voltage and long-term reliability of the semiconductor device 10.

[0050] For example, the first dielectric region 161 is composed of silicon oxide material, and the second dielectric region 162 is a nitrogen-rich region. The insulating dielectric material constituting the second dielectric region 162 may include, but is not limited to, silicon nitride and silicon oxynitride dielectric layers. For example, the second dielectric region 162 is composed of silicon oxynitride dielectric material with a dielectric constant k ranging from 4.5 to 6, and the higher the nitrogen enrichment concentration, the greater the dielectric constant of the second dielectric region 162.

[0051] For example, the second medium region 162 includes a first sub-medium region 162a and a second sub-medium region 162b that are interconnected. The first sub-medium region 162a is formed on the first medium region 161 covering the corner region A, and the second sub-medium region 162b is formed on the first medium region 161 covering the bottom wall S1 and the side wall S2.

[0052] Specifically, the nitrogen enrichment concentration in the first sub-dielectric region 162a can be set to be greater than that in the second sub-dielectric region 162b. For example, the ratio of the nitrogen enrichment concentration in the first sub-dielectric region 162a to that in the second sub-dielectric region 162b is not less than 1.2. This allows the first sub-dielectric region 162a to have a higher dielectric constant than the second sub-dielectric region 162b. This, in turn, helps to increase the local dielectric constant of the gate dielectric in the corner region A of the covering trench 120 and reduces the electric field concentration in this region, thereby reducing the peak electric field.

[0053] Meanwhile, the thickness of the first sub-dielectric region 162a can be set to be greater than that of the second sub-dielectric region 162b. For example, the ratio of the thickness of the first sub-dielectric region 162a to that of the second sub-dielectric region 162b can be set to 2 to 3. This is beneficial to improve the local dielectric constant of the gate dielectric in the corner region A of the covering trench 120 and reduce the electric field concentration in this region, thereby reducing the peak electric field.

[0054] The first sub-dielectric region 162a further includes a first surface S3 that contacts the first dielectric region 161, and a second surface S4 that is disposed opposite to the first surface S3 and contacts the gate electrode 170.

[0055] The first surface S3 and the second surface S4 are both curved surfaces with their curvature centers located within the trench 120. The first surface S3 is also configured to have a curvature radius smaller than that of the second surface S4, so that the first sub-dielectric region 162a can have a thickness greater than that of the second sub-dielectric region 162b. This is beneficial to improving the local dielectric constant of the gate dielectric covering the corner region A of the trench 120 and reducing the electric field concentration in this region, thereby reducing the peak electric field.

[0056] Furthermore, the overall dielectric constant of the second dielectric region 162, composed of the first sub-dielectric region 162a and the second sub-dielectric region 162b, can be set to have a continuously gradually changing distribution, thereby avoiding new electric field spikes and distortions caused by drastic changes in dielectric constant. Based on this, the gate dielectric formed by the second dielectric region 162 and the first dielectric region 161 can achieve good compactness, uniformity, and interface stability, thereby reducing gate leakage current and improving the device's withstand voltage reliability and long-term operating life.

[0057] For example, the thickness of the gate dielectric composed of the first dielectric layer and the second dielectric layer ranges from 30 nm to 80 nm. Examples include 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, and 80 nm. When the thickness of the gate dielectric is less than 30 nm, it is difficult for the gate dielectric to provide sufficient insulation strength and withstand voltage margin for the semiconductor device 10, which can easily lead to a reduction in the breakdown field strength of the semiconductor device 10, resulting in a significant decrease in its reliability under high-voltage operating conditions. Conversely, when the thickness of the gate dielectric exceeds 80 nm, it increases the equivalent gate dielectric thickness of the semiconductor device 10, causing a significant increase in on-resistance. This weakens the switching characteristics and gate voltage regulation capability of the semiconductor device 10, thereby reducing the overall controllability and operating efficiency of the semiconductor device 10.

[0058] The thickness of the second medium region 162 covering the bottom wall S1 and / or side wall S2 is greater than the thickness of the first medium region 161.

[0059] In some embodiments, the semiconductor device 10 provided in this application further includes a gate electrode 170 filled in the trench 120, an ohmic contact metal layer 191 and an insulating layer 180 located on the semiconductor layer 110, a source contact 190 located on the ohmic contact metal layer 191 and the insulating layer 180, and a drain contact 200 located on the side of the semiconductor layer 110 away from the gate electrode 170.

[0060] The gate electrode 170 completely fills the interior of the trench 120 and is isolated from the inner wall of the trench 120 by the gate dielectric composed of the first dielectric layer 141 and the second dielectric layer 160.

[0061] The source contact 190 is disposed on the side of the semiconductor layer 110 near the gate electrode 170 and directly contacts the source region 114, ensuring good conductivity between the source contact 190 and the source region 114. An insulating layer 180 is located between the gate electrode 170 and the source contact 190, effectively isolating the source contact 190 from the gate electrode 170 and avoiding parasitic capacitance between them, thereby further optimizing the switching performance of the device. A drain contact 200 is also provided on the side of the semiconductor layer 110 away from the gate electrode 170, ensuring continuity between the drain contact 200 and the semiconductor layer 110 and providing a stable current path for the device.

[0062] It should be noted that the semiconductor device 10 in this application embodiment is preferably a trench MOSFET, but it can also be applied to a trench insulated gate bipolar transistor (IGBT). The fabrication method and device structure of this application can also be extended to other gate-controlled power semiconductor devices 10 with trench gate structures, such as trench field-effect transistors (FETs), trench metal-semiconductor field-effect transistors (MESFETs), and trench insulated gate field-effect transistors (IGFETs), etc., and this application embodiment does not limit them in this regard. Those skilled in the art can adaptively adjust the conductivity type, doping concentration, and structural size of each functional region in the semiconductor layer 110 according to actual application requirements, thereby adapting the semiconductor device 10 structure of this application to the above-mentioned different types of semiconductor devices 10, and all of them can achieve the core technical effects of trench corner electric field control and channel interface characteristic maintenance.

[0063] According to a second aspect of this application, a method for fabricating a semiconductor device is provided.

[0064] Please see Figure 4 The semiconductor device fabrication method of this application includes the following steps: For step S100, please refer to the relevant documentation. Figure 5 , providing semiconductor layer 110.

[0065] Here, semiconductor layer 110 refers to a combination of multiple functional layers or doped regions of a device formed in advance through processes such as epitaxy, ion implantation, high-temperature activation, and annealing.

[0066] For example, the semiconductor layer 110 consists of a substrate 111 of a first conductivity type and a first epitaxial layer 112 formed on the substrate 111.

[0067] Here, the first conductivity type refers to the impurity ion doping type that is opposite to the second conductivity type, including N-type impurity ion doping or P-type impurity ion doping, which can be flexibly set according to the specific semiconductor device 10 type. For example, when the first conductivity type is N-type doping, the second conductivity type is P-type doping, or vice versa. P-type impurity ions include impurity ions such as aluminum ions, boron ions, or indium ions, while N-type impurity ions include impurity ions such as nitrogen ions, phosphorus ions, or arsenic ions.

[0068] It should be noted that the specific structure and materials of the semiconductor layer 110 described above are merely illustrative examples and should not be construed as limiting the scope of protection of this application. In other words, the semiconductor layer 110 in this application includes semiconductor materials suitable for power semiconductor devices, such as single-crystal silicon, silicon-on-insulator (SOI), germanium (Ge), silicon-germanium (GeSi), or gallium arsenide (GaAs).

[0069] Please refer to step S200. Figures 6-9 A trench 120 is formed in the semiconductor layer 110. The trench 120 has a bottom wall S1, a side wall S2, and a corner region A connecting the bottom wall S1 and the side wall S2.

[0070] Here, trench 120 refers to one or more spaced groove structures that extend into the semiconductor layer 110 to a predetermined depth along the thickness direction by etching a predetermined area on the surface of the semiconductor layer 110 using a dry, wet, or dry-wet combined etching method. Specifically, the trench wall of trench 120 may include a bottom wall S1 located at the bottom of trench 120, a side wall S2 located above the bottom wall S1, and a corner area A connecting the bottom wall S1 and the side wall S2.

[0071] In some embodiments, the step of forming a trench 120 within the semiconductor layer 110 includes: Step S201: A mask layer 130 is formed on the semiconductor layer 120.

[0072] Please see Figure 6 The mask layer 130 has a patterned window area 131, which exposes part of the surface of the semiconductor layer 120, thereby defining the formation location and size of the trench 120 in the semiconductor layer 120. The surface of the semiconductor layer 110 not exposed by the window area 131 is covered and protected by the mask layer 130 to prevent subsequent etching processes from damaging non-target areas of the semiconductor layer 110.

[0073] In step S202, an etching process is used to directionally etch the surface of the semiconductor layer 120 exposed in the window area 131 until the preset depth is reached, so as to form a trench 120 that conforms to the design size in the semiconductor layer 110.

[0074] For example, please refer to Figure 7 Inductively Coupled Plasma (ICP) dry etching can be used, which features high etching rate and strong directionality, and can precisely control the depth, width, and sidewall S2 perpendicularity of trench 120, thereby reducing semiconductor layer lattice damage during etching and ensuring that the morphology of trench 120 meets device design requirements. In other examples, the etching process can also be reactive ion etching (RIE).

[0075] Step S203: The bottom wall S1 and corner area A of the trench 120 are rounded.

[0076] For example, please refer to Figure 8 and Figure 9 Plasma etching or sacrificial oxidation can be used to selectively etch the bottom wall S1 and corner area A of trench 120, removing the sharp corner between the bottom wall S1 and the side wall S2, so that the corner area A of trench 120 forms a smooth transition curved surface structure with a preset radius of curvature and the center of curvature located inside trench 120, thereby alleviating the electric field concentration phenomenon in corner area A, improving the withstand voltage reliability of the device, and further repairing the lattice damage remaining during the etching process.

[0077] Among them, the plasma etching process used for the rounding of the bottom wall S1 and the corner area A is a low-damage, weakly isotropic modification etching process. Compared with the aforementioned highly anisotropic ICP plasma etching process used for the main body forming of the trench 120, it has lower radio frequency power, shorter etching time, and higher etching selectivity. It only performs micro-etching on the sharp corner between the bottom wall S1 and the side wall S2 without changing the overall size of the trench 120 and the morphology of the side wall S2. At the same time, it can simultaneously remove residual etching damage without adding additional repair steps, thus improving process efficiency.

[0078] The sacrificial oxidation process used for rounding the bottom wall S1 and corner area A involves performing high-temperature oxidation on the semiconductor layer 110 after the initial etching of the trench 120. This process uniformly generates a thin oxide layer on the surface of the trench wall of the trench 120. Since the surface activity of the corner area A is stronger, the oxide layer in this area grows to a relatively larger thickness. When the entire sacrificial oxide layer is subsequently removed by wet etching, the etching allowance brought about by the thickness difference of the oxide layer at the corner area A is used to simultaneously remove the sharp edges of the corner area A. This achieves a smooth transition and curvature optimization of the corner area A of the trench 120 without destroying the overall outline of the trench 120, while also mitigating the surface defects introduced by etching.

[0079] It should be noted that, in order to reduce the actual process flow, the step of rounding the bottom wall S1 and corner area A of the trench 120 can be performed after the subsequent step of forming a passivation film 150 on the side wall S2, so as to achieve selective etching and rounding of the bottom wall S1 and corner area A.

[0080] For step S300, please refer to... Figures 8-12 A first dielectric layer 141 is formed in the trench 120, and the first dielectric layer 141 covers the corner area A.

[0081] Here, the first dielectric layer 141 is composed of a high-K dielectric material. The high-K dielectric material may be one or more of the following materials, including but not limited to zirconium dioxide (ZrO2), hafnium oxide (HfO2), titanium dioxide (TiO2), or zirconium hafnium oxide (HfZrO).

[0082] Those skilled in the art will know that the electric field strength and the dielectric constant satisfy the following constitutive relation: E=D / ε r .

[0083] in, E For electric field strength, ε r The relative permittivity, D It is the electric displacement vector, and also the electric flux density.

[0084] It can be seen that, under the conditions of a fixed structure of semiconductor device 10 and an applied bias voltage, the electric displacement vector... D The electric potential distribution of semiconductor device 10 is uniquely determined and is independent of the properties of the dielectric material. Therefore, the electric displacement vector... D It can be considered a constant value.

[0085] Under this premise, by setting the first dielectric layer 141 covering the corner region A to be composed of a high-k dielectric material with a higher dielectric constant, and by making the first dielectric layer 141 cover only the corner region A of the trench 120, the relative dielectric constant of the corner region A can be significantly improved. ε corner This achieves the goal of optimizing the electric field distribution of the trench 120 in the corner region A, significantly reducing the local electric field intensity of the trench 120 in the corner region A, and effectively mitigating the electric field concentration effect.

[0086] In some embodiments, the step of forming a first dielectric layer 141 within the trench 120 includes: For step S301, please refer to... Figure 8 and Figure 9 A passivation layer 150 is formed on the sidewall S2 of the trench 120.

[0087] Here, the passivation layer 150 tightly covers the entire sidewall S2 surface of the trench 120, and also extends to cover the surface of the mask layer 130 exposed in the window area 131, which serves to protect the sidewall S2 of the trench 120 and prevent subsequent processes from damaging the sidewall S2 of the trench 120. At the same time, it also provides a sacrificial substrate for the subsequent deposition and selective removal of the first dielectric material layer 140.

[0088] The passivation layer 150 may be composed of materials that are easy to selectively remove, such as silicon oxide or fluoropolymer materials, so that it can be completely removed by subsequent dry or wet selective removal processes, while ensuring that the first dielectric material layer 140 covering the corner area A can be accurately retained, so as to avoid affecting the morphology and performance of the first dielectric layer 141.

[0089] For example, the passivation layer 150 can be prepared using a passivation-rich plasma process and a fluorocarbon-based gas as the reactant. During plasma discharge, the fluorocarbon-based gas dissociates to generate fluorocarbon groups such as CF2 and CF3. These fluorocarbon groups adsorb and deposit on the sidewall S2 of the trench 120 and the exposed surface of the window region 131 of the mask layer 130, forming a fluorocarbon polymer (C). x F y The fluoropolymer film is the passivation layer 150 on the surface of the sidewall S2 above the corner region A and part of the surface of the mask layer 130. Its material properties can not only effectively protect the sidewall S2 and the mask layer, but also meet the process requirements of subsequent selective removal.

[0090] The fluorocarbon-based gas may include, but is not limited to, octafluorocyclobutane (C4F8), or a mixture of CHF3 and C3F8.

[0091] For step S302, please refer to... Figure 10A first dielectric material layer 140 is formed in the trench 120. The first dielectric material layer 140 covers the bottom wall S1 and the corner area A, and extends to cover the passivation layer 150.

[0092] Here, the first dielectric material layer 140 is composed of a high-k dielectric material, which may include, but is not limited to, one or more combinations of zirconium dioxide (ZrO2), hafnium oxide (HfO2), titanium dioxide (TiO2), or zirconium hafnium oxide (HfZrO). Since the first dielectric layer 141 is formed by selectively etching the first dielectric material layer 140 in a subsequent process, the first dielectric layer 141 and the first dielectric material layer 140 are composed of the same material.

[0093] The first dielectric material layer 140 is formed by conformal deposition, which can uniformly cover the bottom wall S1 and corner area A of the trench 120, ensuring that the corner area A is fully covered without any omissions. At the same time, the first dielectric material layer 140 can continuously extend to cover the surface of the passivation layer 150, thereby providing a stable structural basis for the subsequent selective removal process of the first dielectric material layer 140 and ensuring the accurate formation of the subsequent first dielectric layer 141.

[0094] For step S303, please refer to... Figure 11 The passivation layer 150 and part of the first dielectric material layer 140 are removed, while the part of the first dielectric material layer 140 covering the corner area A is retained to form the first dielectric layer 141.

[0095] The first dielectric layer 141 can be formed by a selective removal process. While completely removing the passivation layer 150, the selective removal process can also simultaneously remove a portion of the first dielectric material layer 140 covering the surface of the passivation layer 150 and a portion of the first dielectric material layer 140 covering the bottom wall S1 of the trench 120, leaving only a portion of the first dielectric material layer 140 covering the corner area A. This retained portion is the first dielectric layer 141.

[0096] The portion of the first dielectric material layer 140 covering the bottom wall S1 of the trench 120 can be selectively removed using an anisotropic dry etching process (etch-back process). This etching process will preferentially remove the portion of the first dielectric material layer 140 covering the plane of the bottom wall S1 of the trench 120, while retaining the portion of the first dielectric material layer 140 covering the corner area A.

[0097] The portion of the first dielectric material layer 140 covering the surface of the passivation layer 150 can be selectively removed using an isotropic wet etching process or a plasma ashing process.

[0098] For example, hydrofluoric acid (HF) can be used to selectively remove the passivation layer 150. The portion of the first dielectric material layer 140 above the passivation layer 150 has weak interfacial adhesion because it does not directly contact the trench 120. As a result, the portion of the first dielectric material layer 140 covering the passivation layer 150 will also be selectively peeled off and removed simultaneously, or removed in a subsequent cleaning process.

[0099] Furthermore, while selectively removing the passivation layer 150 using hydrofluoric acid (HF), the hard mask layer 130 covering the surface of the semiconductor layer 110 is also removed, thereby exposing the surface of the semiconductor layer 110 again.

[0100] In addition, after the step of selectively peeling off a portion of the first dielectric material layer 140 covering the passivation layer 150, the process further includes using a cleaning process to remove the particles of the first dielectric material layer 140 remaining in the trench 120, or selectively removing the portion of the first dielectric material layer 140 that is not in direct contact with the sidewall S2 of the trench 120, thereby laying the foundation for the subsequent contact between the second dielectric layer 160 and the exposed sidewall S2 and bottom wall S1 surfaces of the trench 120 to form a stable channel interface.

[0101] The cleaning process can use SC-1 cleaning solution (NH4OH / H2O2 / H2O) to selectively remove the residual first medium material layer 140 outside the corner area A within the trench 120. SC-1 cleaning solution is also known as APM (Ammonia Peroxide Mixture), and the volume ratio of NH4OH:H2O2:H2O in SC-1 cleaning solution is between 1:1:5 and 1:2:7.

[0102] The formation process of the first dielectric layer 141 does not require additional photolithography mask and precision overlay alignment process. Relying on the inherent morphology of the trench 120, the deposition and distribution characteristics of the passivation layer 150 and the first dielectric material layer 140, as well as the selectivity of the etching reaction, the first dielectric layer 141 is spontaneously formed in the corner area A (i.e., self-aligned process formation). This effectively avoids the alignment deviation and process complexity caused by the traditional patterned alignment process, while simplifying the preparation process and ensuring the film placement accuracy and structural consistency of the first dielectric layer 141 in the corner area A.

[0103] Step S400, please refer to Figure 12 A second dielectric layer 160 is formed in the trench 120. The second dielectric layer 160 covers the first dielectric layer 141 and extends to cover the bottom wall S1 and side wall S2 of the trench 120. The dielectric constant of the first dielectric layer 141 is greater than that of the second dielectric layer 160.

[0104] Here, the second dielectric layer 160 is composed of a dielectric material with a dielectric constant lower than that of the first dielectric layer 141. For example, the constituent materials of the second dielectric layer 160 may be one or more combinations of materials such as silicon oxide and silicon oxynitride.

[0105] Therefore, this application is based on the electric field strength E With dielectric constant ε r By forming a first dielectric layer 141 composed of a high-k dielectric material in corner region A, directly covering corner region A, and covering the first dielectric layer 141 with a second dielectric layer 160 having a lower dielectric constant, and extending to cover the bottom wall S1 and sidewall S2 of the trench 120 exposed outside corner region A, the dielectric constant of the dielectric material covering the entire corner region A can be increased directly by utilizing the first dielectric layer 141 formed in corner region A without introducing or with minimal introduction of interface defects and lattice damage. ε corner This is to optimize the electric field distribution in the corner region A of trench 120, significantly reduce the local electric field intensity in the corner region A of trench 120, and effectively alleviate the electric field concentration effect, so that the semiconductor device 10 can still meet the stringent requirements of electric field uniformity for high voltage and high frequency applications under ultra-high electric field operating conditions, and improve the breakdown voltage and long-term reliability of the semiconductor device 10.

[0106] In this application, silicon oxide or silicon oxynitride is formed as a second dielectric layer 160 within the trench 120, and the surface of the trench wall 120 outside the corner region A is covered. This not only helps to form a stable, low-defect semiconductor-dielectric interface with the trench wall 120, suppressing interface state charge and leakage current, but also, with its moderate dielectric constant, further regulates the electric field distribution inside the trench 120 to a certain extent, thereby alleviating the electric field concentration in the corner region A and improving the insulation reliability and stability of the semiconductor device 10 under high voltage operation.

[0107] For example, the total thickness of the first dielectric layer 141 and the second dielectric layer 160 ranges from 30 nm to 80 nm. Examples include 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, and 80 nm. When the total thickness is less than 30 nm, using the first dielectric layer 141 and the second dielectric layer 160 together as the equivalent gate dielectric of the semiconductor device 10 will be insufficient to provide adequate insulation strength and withstand voltage margin, easily leading to a decrease in the breakdown field strength of the semiconductor device 10, and consequently a significant decrease in its reliability under high-voltage operating conditions. Conversely, when the total thickness exceeds 80 nm, the equivalent gate dielectric thickness of the semiconductor device 10 will increase, significantly raising the on-resistance, weakening the switching characteristics and gate voltage regulation capability of the semiconductor device 10, and thus reducing the overall controllability and operating efficiency of the semiconductor device 10.

[0108] In some embodiments, please refer to Figure 2 After the step of forming the second medium layer 160 in the trench 120, the method further includes: selectively nitriding a portion of the second medium layer 160 on the side away from the trench wall using a selective nitriding process.

[0109] Here, selective nitriding refers to nitriding a portion of the second medium layer 160 on the side facing away from the tank wall to form a second medium region 162.

[0110] Correspondingly, the portion of the second dielectric layer 160 outside the second dielectric region 162 is not nitrided and is formed in the first dielectric region 161, so that the first dielectric region 161 can retain the same material as the second dielectric layer 160.

[0111] Under this premise, the second dielectric layer 160 covering part of the corner region A will be made of SiO2 material with a relatively low dielectric constant (dielectric constant). ε r Approximately 3.9) is converted into SiON material with a relatively higher permittivity (dielectric constant). ε r (Approximately 4.5~6), which can directly increase the dielectric constant of the second dielectric layer 160 covering the first dielectric layer 141, thereby further increasing the dielectric constant of the gate dielectric covering the corner region A. ε corner .

[0112] Therefore, this application is based on the electric field strength E With dielectric constant ε rBy forming a first dielectric layer 141, a first dielectric region 161, and a second dielectric region 162 with different dielectric constants within the gate dielectric covering the corner region A, the electric field distribution of the corner region A of the trench 120 can be optimized without introducing interface defects and lattice damage. This significantly reduces the local electric field intensity of the corner region A of the trench 120 and effectively alleviates the electric field concentration effect. This is beneficial for semiconductor devices to meet the stringent requirements for electric field uniformity in high-voltage and high-frequency applications under ultra-high electric field operating conditions, thereby improving the breakdown voltage and long-term reliability of semiconductor devices.

[0113] For example, the second dielectric region 162 is a nitrogen-rich region. The step of forming the second dielectric region 162 in the second dielectric layer 160 includes providing a nitrogen-containing atmosphere, applying a negative bias voltage to the substrate 110, and using a plasma nitriding process to nitrid a local area of ​​the second dielectric layer 160 to form a nitrogen-rich second dielectric region 162 on the side of the second dielectric layer 160 away from the trench wall.

[0114] Specifically, the semiconductor layer 110 on which the second dielectric layer 160 is formed can be placed on a support base in the nitriding reaction chamber, and at least one nitrogen-containing gas selected from nitrogen, nitric oxide, or nitrous oxide can be introduced into the nitriding reaction chamber to form a nitrogen-containing atmosphere. Then, the radio frequency plasma power supply is turned on to excite the nitrogen-containing gas in the nitriding reaction chamber to generate nitrogen plasma on the surface of the second dielectric layer 160. Next, a negative bias voltage is applied to the support base to make the semiconductor layer 110 negative potential, so as to drive the nitrogen active particles in the nitrogen plasma to bombard the exposed surface area of ​​the second dielectric layer 160 in a directional manner, thereby achieving selective nitriding treatment of a local area of ​​the second dielectric layer 160.

[0115] Here, the nitriding reaction chamber refers to a vacuum reaction chamber that can provide a controllable atmosphere, apply a bias voltage to excite radio frequency plasmas, and locally nitrid the second dielectric layer 160 on the side away from the tank wall. It can usually be implemented by a plasma-enhanced chemical vapor deposition chamber, an inductively coupled plasma treatment chamber, or a capacitively coupled plasma treatment chamber.

[0116] Because a sheath electric field with a potential gradient is formed between the surface of the second dielectric layer 160 on the side facing away from the trench wall 120 and the plasma, and under the control of the negative bias voltage, the positive ions (N) in the plasma... 3+The positive ions will move towards the surface of the second dielectric layer 160 under the acceleration effect of the sheath electric field. At the same time, due to the geometric focusing effect of the corner region A of the trench 120, the positive ion flux will be locally concentrated in the corner region A of the trench 120, thereby targeting and nitriding the second dielectric layer 160 near the corner region A, thus forming a second dielectric region 162 on the side of the second dielectric layer 160 away from the trench 120. Since the second dielectric layer 160 is composed of silicon oxide, the plasma nitriding process will convert the silicon oxide into silicon oxynitride, thus making the second dielectric region 162 also a nitrogen-rich region.

[0117] In this process, the process parameters of the reaction chamber can be coordinated and set. For example, the nitrogen gas flow rate can be set to 10 sccm~200 sccm, or 20 sccm~100 sccm; the reaction chamber pressure can be set to 1 mTorr~200 mTorr; the bias voltage applied to the bottom of the substrate 110 can be set to -50V~-300V, or -100V~-200V; and the process temperature of the reaction chamber can be set to 200℃~400℃. By using one or more of the above process parameters to jointly regulate the mean free path, acceleration energy and incident angle of the ions, the concentration effect of positive ion flux in the corner region A of trench 120 can be further enhanced, so that nitrogen element is precisely enriched in the second dielectric layer 160 near the corner region A, and a nitrogen enrichment region is formed, so as to maximize the dielectric constant of the gate dielectric covering the corner region A. ε corner This effectively alleviates electric field concentration and improves the breakdown voltage and long-term reliability of semiconductor devices.

[0118] For example, the second dielectric region 162 includes a first sub-dielectric region 162a and a second sub-dielectric region 162b that are interconnected. The step of nitriding a portion of the second dielectric layer 160 facing away from the tank wall further includes nitriding a portion of the second dielectric layer 160 covering the first dielectric layer 141 to form the first sub-dielectric region 162a, and nitriding a portion of the second dielectric layer 160 covering the bottom wall S1 and the side wall S2 to form the second sub-dielectric region 162b. Furthermore, the first sub-dielectric region 162a and the second sub-dielectric region 162b are simultaneously formed within the second dielectric layer 160 facing away from the tank wall, and are interconnected and continuously distributed, together constituting a nitrogen-enriched region within the second dielectric layer 160.

[0119] Specifically, by utilizing the sheath electric field between the surface of the second dielectric layer 160 and the plasma, as well as the focusing effect of the geometry of the corner region A of the trench 120, the positive ion flux is locally concentrated in the corner region A of the trench 120. This enhances the nitriding of the second dielectric layer 160 near the corner region A, forming a first sub-dielectric region 162a with a higher nitrogen enrichment concentration. Simultaneously, because nitrogen ions and active nitrogen groups in the plasma irradiate the entire exposed surface of the second dielectric layer 160, even the portion of the second dielectric layer 160 covering the bottom wall S1 and side wall S2, which lacks ion focusing effect, still undergoes nitriding and forms a second sub-dielectric region 162b with a relatively lower nitrogen enrichment concentration. This also results in the second sub-dielectric region 162b having a smaller thickness within the second dielectric layer 160 than the first sub-dielectric region 162a.

[0120] The ratio of nitrogen enrichment concentration in the first sub-dielectric region 161a to that in the second sub-dielectric region 162b is preferably not less than 1.2, which is beneficial to further improve the local dielectric constant of the gate dielectric in the corner region A of the covering trench 120, reduce the electric field concentration in the region, and thus reduce the peak electric field.

[0121] Meanwhile, the interconnected and continuously distributed second sub-dielectric regions 162a also ensure that the overall dielectric constant of the second dielectric region 162 exhibits a gradual distribution, preventing new electric field spikes and distortions caused by drastic changes in dielectric constant. Based on this, the second dielectric layer 160, composed of the first dielectric region 161 and the second dielectric region 162, achieves a good balance of density, uniformity, and interface stability, which is beneficial for further reducing gate leakage current and improving the device's withstand voltage reliability and long-term operating life.

[0122] In addition, the sheath electric field can fully utilize the ion focusing effect, so that the positive ion flux is effectively concentrated in the corner region A of the trench 120, while ensuring that the ions can be smoothly transported to the bottom wall S1 and side wall S2 of the trench 120. This also takes into account the enhanced nitriding of the local second dielectric layer 160 above the corner region A of the trench 120, as well as the uniform nitriding of the local second dielectric layer 160 above the bottom wall S1 and side wall S2 of the trench 120.

[0123] In addition, please refer to Figure 1 or Figure 2 After the step of forming a second dielectric layer 160 in the trench 120, the method further includes filling the trench 120 with polysilicon to form a gate electrode 170 of a gate structure.

[0124] Here, the gate electrode 170 completely fills the interior of the trench 120 and is isolated from the trench wall of the trench 120 by the first dielectric layer 141 and the second dielectric layer 160.

[0125] In addition, after the step of forming the gate electrode 170, the method further includes forming an ohmic contact metal layer 191 and an insulating layer 170 on the semiconductor layer 110, forming a source contact 190 on the ohmic contact metal layer 191 and the insulating layer 180, and forming a drain contact 200 on the side of the semiconductor layer 110 away from the gate electrode 170.

[0126] The source contact 190 is disposed on the side of the semiconductor layer 110 near the gate electrode 170 and directly contacts the source region 114, ensuring good conductivity between the source contact 190 and the source region 114. An insulating layer 180 is located between the gate electrode 170 and the source contact 190, effectively isolating the source contact 190 from the gate electrode 170 and avoiding parasitic capacitance between them, thereby further optimizing the switching performance of the device. A drain contact 200 is also provided on the side of the semiconductor layer 110 away from the gate electrode 170, ensuring continuity between the drain contact 200 and the semiconductor layer 110 and providing a stable current path for the device.

[0127] It should be noted that the process steps and sequence in the semiconductor device 10 fabrication methods described in the embodiments of the second aspect above are not fixed and can be adjusted according to the actual process. The semiconductor processes such as masking, photolithography, etching, and cleaning that are carried out once or multiple times in the formation of each layer structure will not be described in detail in the embodiments of this application.

[0128] According to a third aspect of this application, a power module is also provided.

[0129] Please see Figure 13 The power module 20 of this application embodiment includes a substrate 210 and a semiconductor device 10 disposed on the substrate 210. The semiconductor device 10 includes, but is not limited to, the semiconductor device 10 described in any embodiment of the first aspect above, or a semiconductor device 10 prepared by the semiconductor device preparation method described in any embodiment of the second aspect above.

[0130] Here, substrate 210 refers to the basic support component in power module 20 used to support and fix semiconductor device 10 and realize electrical connection and heat conduction. It can form a physical bonding, welding or encapsulation integration connection with semiconductor device 10, providing mechanical support, circuit conduction path or heat dissipation channel for semiconductor device 10.

[0131] The specific type of substrate 210 can be flexibly selected according to the application scenario and power requirements of the power module 20, including but not limited to direct bonding copper substrate (DBC), active metal brazed ceramic substrate (AMB), low temperature co-fired ceramic substrate (LTCC), ceramic substrate, metal core printed circuit board (MCPCB), printed circuit board (PCB), insulated metal substrate (IMS), aluminum nitride ceramic substrate (AlN substrate), composite material substrate (such as AlSiC substrate, glass ceramic substrate), etc. This application does not limit the specific type of substrate 210 selected in the power module 20.

[0132] Furthermore, the power module 20 in this application embodiment is an electronic power device equipped with the power semiconductor device 10, which can be applied to various fields such as new energy power generation, power transmission, rail transit, industrial control, new energy vehicles, consumer electronics, and aerospace. Specifically, it can include photovoltaic inverters, wind power converters, grid converter valves, locomotive traction converters, industrial frequency converters, vehicle power controllers, charging piles, power adapters, energy storage systems, etc., and this application embodiment does not limit this. Those skilled in the art can adapt the specifications of the semiconductor device 10 and the circuit topology of the power module 20 according to the power, voltage, integration and other requirements of the actual application scenario. Moreover, the power module 20 equipped with the semiconductor device 10 described in this application can achieve higher energy conversion efficiency, more stable operation and longer service life because the device has both excellent high-voltage reliability and switching performance.

[0133] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer having trenches therein, the trenches having a bottom wall, side walls, and a corner area connecting the bottom wall and the side walls; A first dielectric layer is located within the trench and covers the corner area; A second dielectric layer is located on the first dielectric layer and extends to cover the bottom wall and the side wall; The dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The corner area is a curved surface, and the center of curvature of the corner area is located within the groove.

3. The semiconductor device as described in claim 2, characterized in that, The contact surface between the first dielectric layer and the second dielectric layer is a curved surface, and the center of curvature of the contact surface is located within the groove.

4. The semiconductor device as described in claim 3, characterized in that, The radius of curvature of the corner area is smaller than that of the contact surface.

5. The semiconductor device as claimed in claim 1, characterized in that, The first dielectric layer includes a first end near the sidewall and a second end near the bottom wall, and the first dielectric layer has a thickness in the central region between the first end and the second end that is greater than the thickness of the edge regions near the first end and / or the second end.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The second dielectric layer includes a first dielectric region and a second dielectric region stacked together. The first dielectric region is formed on the first dielectric layer and extends to cover the bottom wall and the side wall. The second dielectric region is formed on the first dielectric region. Furthermore, the dielectric constant of the second dielectric region is greater than that of the first dielectric region, and the dielectric constant of the first dielectric layer is greater than that of the second dielectric region.

7. The semiconductor device as claimed in claim 6, characterized in that, The second medium region includes a first sub-medium region and a second sub-medium region that are interconnected; wherein, The first sub-medium region is located on the first medium region covering the corner region; The second sub-medium region is located on the first medium region covering the bottom wall and the side wall; Furthermore, the dielectric constant of the first sub-dielectric region is greater than that of the second sub-dielectric region.

8. The semiconductor device as claimed in claim 7, characterized in that, The thickness of the first sub-dielectric region is greater than that of the second sub-dielectric region.

9. The semiconductor device as claimed in claim 7, characterized in that, The first sub-medium region further includes a first surface in contact with the first medium region, and a second surface opposite to the first surface and not in contact with the first medium region; Wherein, both the first surface and the second surface are curved surfaces with their curvature centers located within the groove, and the radius of curvature of the second surface is greater than that of the first surface.

10. The semiconductor device as claimed in claim 7, characterized in that, The first medium region is a nitrogen-rich region, and the nitrogen enrichment concentration in the first sub-medium region is greater than that in the second sub-medium region.

11. The semiconductor device as claimed in claim 10, characterized in that, The ratio of nitrogen enrichment concentration in the first sub-medium region to that in the second sub-medium region is not less than 1.

2.

12. The semiconductor device as claimed in claim 7, characterized in that, The ratio of the thickness of the first sub-dielectric region to that of the second sub-dielectric region is in the range of 2 to 3.

13. The semiconductor device according to any one of claims 6 to 12, characterized in that, The first dielectric layer is composed of a high-k dielectric material, the first dielectric region is composed of silicon oxide, and the second dielectric region is composed of silicon oxynitride.

14. A method for fabricating a semiconductor device, characterized in that, include: Provides a semiconductor layer; A trench is formed within the semiconductor layer, the trench having a bottom wall, sidewalls, and a corner area connecting the bottom wall and the sidewalls; A first dielectric layer is formed within the trench, and the first dielectric layer covers the corner area; A second dielectric layer is formed within the trench, the second dielectric layer covering the first dielectric layer and extending to cover the bottom wall and the side wall, and the dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.

15. The semiconductor device fabrication method according to claim 14, characterized in that, The step of forming a first dielectric layer in the trench includes: A passivation layer is formed on the sidewall; A first dielectric material layer is formed in the trench, the first dielectric material layer covers the bottom wall and the corner area, and extends to cover the passivation layer; The passivation layer and a portion of the first dielectric material layer are removed, while a portion of the first dielectric material layer covering the corner area is retained to form the first dielectric layer.

16. The semiconductor device fabrication method according to claim 15, characterized in that, The step of removing the passivation layer and a portion of the first dielectric material layer includes: Remove a portion of the first dielectric material layer covering the bottom wall; and, Remove the passivation layer and a portion of the first dielectric material layer covering the passivation layer.

17. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The step of forming trenches within the semiconductor layer includes: A mask layer is formed on the semiconductor layer, the mask layer having patterned window areas that expose a portion of the surface of the semiconductor layer; The surface of the semiconductor layer exposed in the window area is etched to form the trench within the semiconductor layer.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The step of removing the passivation layer and part of the first dielectric material layer further includes: Remove the mask layer to expose the surface of the semiconductor layer.

19. The method for fabricating a semiconductor device according to any one of claims 14 to 18, characterized in that, The step of forming trenches within the semiconductor layer further includes: The corner area is selectively etched to form a curved surface, wherein the center of curvature of the corner area is located within the trench.

20. The method for fabricating a semiconductor device according to any one of claims 14 to 18, characterized in that, After the step of forming the second dielectric layer in the trench, the method further includes: The second dielectric layer is selectively nitrided to form a first dielectric region and a second dielectric region stacked within the second dielectric layer; Wherein, the first medium region is the portion of the second medium layer that is close to the trench and has not undergone nitriding treatment; the second medium region is the portion of the second medium layer that is away from the trench and has undergone nitriding treatment.

21. A power module, characterized in that, include: Substrate: A semiconductor device, wherein the semiconductor device is located on the substrate; wherein... The semiconductor device includes the semiconductor device as described in any one of claims 1 to 13.

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