Dual mos integrated package structure

Abstract

This application provides a dual MOS integrated package structure, including: a lead frame, which includes a base island and pins located around the base island; a first MOS chip and a second MOS chip; a bonding wire assembly, including multiple bonding wires; multiple copper sheets covered and soldered to one or more bonding wires; and a molding compound covering the copper sheets, the first MOS chip, the second MOS chip, the base island, and part of the pins. This application integrates two MOS chips side-by-side on the same lead frame base island, connects them to corresponding pins using a bonding wire assembly, and simultaneously strengthens the low impedance by covering and soldering copper sheets to the source bonding wires, before completely encapsulating them with a molding compound, thus achieving a high-density monolithic integrated package for dual MOS devices. This structure shortens the electrical connection paths between chips and between chips and pins, effectively reduces package parasitic inductance and resistance, improves current carrying capacity and heat dissipation efficiency, and enhances power density, switching speed, and long-term reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device packaging technology, and in particular to a dual MOS integrated packaging structure. Background Technology

[0002] With the increasing demands for power density in applications such as new energy vehicles, industrial power supplies, and high-density energy storage modules, power MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices must simultaneously meet stringent requirements for high current carrying capacity, efficient heat dissipation, low parasitic parameters, and high integration. Traditional single-transistor MOS packages typically require multiple devices connected in parallel under high current conditions, resulting in problems such as large PCB (Printed Circuit Board) footprint, high system parasitic parameters, and uneven heat dissipation paths.

[0003] Therefore, how to simultaneously achieve low parasitic parameters, efficient heat dissipation, high current carrying capacity, and high integration in the packaging structure under high current and high frequency operating conditions has become a technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0004] This application provides a dual MOS integrated package structure to solve or alleviate one or more technical problems in the prior art.

[0005] This application provides a dual MOS integrated package structure, including: The lead frame includes a base island region and a pin region located around the base island region; the pin region includes multiple source pins and multiple gate pins. The first MOS chip and the second MOS chip are arranged side by side on the base island area; A bonding wire assembly includes multiple bonding wires, which are respectively electrically connected to the source pin and gate pin of a first MOS chip and the corresponding source pin and gate pin of a second MOS chip. Multiple copper sheets are soldered onto one or more bonding wires. A molding compound encapsulates the copper sheet, the first MOS chip, the second MOS chip, the base island region, and part of the pin region.

[0006] In one embodiment, the base island region includes two opposing first sides and two opposing second sides; a plurality of source pins and a plurality of gate pins are distributed on the two opposing first sides; and a plurality of drain pins are distributed on the two opposing second sides.

[0007] In one embodiment, the first MOS chip and the second MOS chip are N-channel power MOS chips with the same electrical parameters, arranged in a direction parallel to the second side, and the first MOS chip and the second MOS chip form a half-bridge topology circuit inside the package.

[0008] In one embodiment, the pin area and the base island area are separated by a gap of 1-3 mm. The pin area includes a connecting part that is close to the base island area and connects to one or more pins. The cross-section of the connecting part is an L-shaped stepped structure, with the side closer to the base island area being higher than the side away from the base island area. The step height of the L-shaped step is 0.3±0.05 mm.

[0009] In one embodiment, the bonding wire assembly includes source bonding wires and gate bonding wires; the source bonding wires are multiple parallel thick aluminum wires used to connect the source region of the first MOS chip or the second MOS chip to the corresponding source pin; the gate bonding wire is a single aluminum wire used to independently connect the gate region of the first MOS chip or the second MOS chip to the corresponding gate pin.

[0010] In one implementation, multiple drain pins are soldered to the base island region.

[0011] In one embodiment, multiple irregularly shaped locking grooves are intermittently distributed along the edge of the base island area.

[0012] In one embodiment, the back side of the base island region is formed with a textured structure by precision stamping, and the surface roughness Ra of the textured structure is ≤1.6μm.

[0013] In one embodiment, the copper sheet is made of oxygen-free copper through precision stamping, and the thickness of the copper sheet is 0.1mm-0.3mm.

[0014] In one embodiment, the distance between the first MOS chip and the second MOS chip is 0.5-0.6 mm; both the first MOS chip and the second MOS chip adopt a back metal drain and a front partitioned electrode structure, with their back sides bonded to the surface of the base island region.

[0015] This embodiment integrates two MOS chips side-by-side on the same leadframe base island area and connects them to their corresponding pins using bonding wire assemblies. A copper sheet is then used to cover and solder the source bonding wires for low impedance enhancement, followed by overall encapsulation with a molding compound. This achieves a high-density monolithic integrated package for dual MOS devices. This structure shortens the electrical connection paths between chips and between chips and pins, effectively reducing package parasitic inductance and resistance, improving current carrying capacity and heat dissipation efficiency. The copper sheet coverage further reduces ohmic losses in the source path and suppresses bonding wire flow displacement, thereby improving power density, switching speed, and long-term reliability.

[0016] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0018] Figure 1 A schematic diagram of the lead frame structure in a dual MOS integrated package structure according to an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of the bonding wire connection structure in a dual MOS integrated package structure according to an embodiment of this application is shown.

[0020] Figure 3 A schematic diagram of the copper sheet covering structure in a dual MOS integrated package structure according to an embodiment of this application is shown.

[0021] Figure 4 This diagram illustrates a molding layer encapsulation structure in a dual MOS integrated package structure according to an embodiment of the present application.

[0022] Figure 5 This diagram illustrates the side structure of the molding layer package in a dual MOS integrated package structure according to an embodiment of the present application. Detailed Implementation

[0023] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0024] This application provides a dual MOS integrated package structure, such as... Figures 1 to 5 As shown, the dual MOS integrated package structure includes: a lead frame, a first MOS chip 210 and a second MOS chip 220, a bonding wire assembly, multiple copper sheets 410 and 420, and a molding compound 500.

[0025] The leadframe, serving as the mechanical support framework and electrical connection carrier of the entire package structure, is made of copper alloy (such as C19400 or C7025) through precision stamping and selective electroplating processes. The leadframe includes a base island area 110 and pin areas 120 surrounding the base island area 110. The base island area 110 is a rectangular flat structure, its dimensions determined by the total area of ​​the two MOS chips and heat dissipation requirements; its length can be, for example, 8-15 mm, its width can be, for example, 6-12 mm, and its thickness can be, for example, 0.2-0.4 mm. The upper surface of the base island area 110 serves as the chip mounting area and can undergo surface roughening treatment to enhance the soldering bond with the metal on the back of the chip. The back portion of the base island area 110 is exposed outside the molding compound 500 and serves as a heat dissipation pad for direct soldering to the external circuit board, forming a low thermal resistance heat dissipation channel.

[0026] The pin area 120 includes a plurality of source pins 122 and a plurality of gate pins 123. Exemplarily, the number of source pins 122 can be 4-18, and the number of gate pins 123 can be 2-4. Each pin extends outward from the periphery of the base island area 110 in a radial distribution. The outer end of each pin has a bent structure for surface mount soldering to an external printed circuit board (PCB). The pin area 120 and the base island area 110 are mechanically fixed and electrically insulated from each other by an injection-molded encapsulation layer 500.

[0027] The first MOS chip 210 and the second MOS chip 220 are arranged side-by-side on the base island region 110. The two chips are arranged with their long sides facing each other or their short sides facing each other, and the specific arrangement direction is determined based on the pin distribution and electrical connection path optimization. The chips are mounted on the surface of the base island region 110 using conductive adhesive (such as silver paste) or solder (such as SnAgCu-based lead-free solder). The front side (active side) of each MOS chip has a source region and a gate region. The source region typically occupies most of the front side area of ​​the chip (approximately 80%-90%), while the gate region is located at the edge of the front side of the chip (approximately 5%-10%). The back side of the chip is a full-surface drain metal layer, which is directly electrically and thermally connected to the base island region 110.

[0028] The bonding wire assembly includes multiple bonding wires that are electrically connected to the source pin 122 and gate pin 123 of the first MOS chip 210, respectively, and electrically connected to the source pin 122 and gate pin 123 of the second MOS chip 220.

[0029] For example, for the first MOS chip 210, one end of the source bonding wire 320 is bonded to the source pad on the front side of the chip, and the other end is bonded to the inner end of the lead frame corresponding to the source pin 122 of the first MOS chip 210; one end of the gate bonding wire 310 is bonded to the gate pad on the front side of the chip, and the other end is bonded to the inner end of the lead frame corresponding to the gate pin 123 of the first MOS chip 210. The bonding connection of the second MOS chip 220 is arranged centrally symmetrically with that of the first MOS chip 210. The bonding wire material can be high-purity aluminum wire (99.99% Al) or copper wire, and the wire diameter is selected according to the current carrying capacity.

[0030] Multiple copper sheets 410 and 420 are soldered onto one or more bonding wires. The copper sheets 410 and 420 are thin sheet-like metal components made of oxygen-free copper, and their planar dimensions are at least larger than the diameter of a single bonding wire. The copper sheets 410 and 420 are soldered onto multiple points of the bonding wire using solder or conductive silver paste.

[0031] The copper strips 410 and 420 increase the effective conductive cross-sectional area of ​​the bonding wires, reducing the resistance and inductance of the source path, thereby reducing conduction and switching losses. Simultaneously, the copper strips 410 and 420, covering the bonding wires, protect them during the molding process and prevent the bonding wires from shifting or collapsing due to the impact of the molding compound flow.

[0032] The molding compound 500 covers copper sheets 410 and 420, the first MOS chip 210, the second MOS chip 220, the base island region 110, and part of the pin region 120.

[0033] For example, the molding compound 500 is made of epoxy resin composite material with high thermal conductivity, high insulation, high temperature resistance, and high weather resistance. The material has a thermal conductivity ≥1.5W / (m·K), which has excellent thermal conductivity and insulation protection performance. The molding compound 500 is used to completely wrap the upper part of the lead frame, the two MOS chips, all bonding circuits, and copper sheets 410 and 420 through injection molding, isolating external moisture, dust, oil, and mechanical forces, and playing a role in insulation protection, moisture-proof and corrosion-proof, and impact and deformation resistance. At the same time, the high thermal conductivity molding compound 500 can assist in the lateral heat dissipation of the chip. Together with the exposed base island on the back, it forms an all-round heat dissipation system. After molding, the back of the base island is exposed, which can fit tightly with the external heat sink, minimizing contact thermal resistance and ensuring stable heat dissipation under long-term high-power operation.

[0034] This embodiment integrates two MOS chips side-by-side on the same leadframe base island region 110, and connects them to their corresponding pins with bonding wire assemblies. Copper sheets 410 and 420 are then soldered over the source bonding wire 320 for low impedance enhancement, and the entire assembly is encapsulated with a molding compound 500, achieving a high-density monolithic integrated package for dual MOS devices. This structure shortens the electrical connection paths between chips and between chips and pins, effectively reducing package parasitic inductance and resistance, and improving current carrying capacity and heat dissipation efficiency. The soldering of copper sheets 410 and 420 further reduces ohmic losses in the source path and suppresses bonding wire flow displacement, thereby improving power density, switching speed, and long-term reliability.

[0035] In one embodiment, the base island region 110 includes two opposing first sides and two opposing second sides; a plurality of source pins 122 and a plurality of gate pins 123 are distributed on the two opposing first sides; and a plurality of drain pins are distributed on the two opposing second sides.

[0036] For example, on one first side (such as the left side) of the base island region 110, 2-4 source pins 122 and 1 gate pin 123 are arranged; on the other opposite first side (such as the right side), 2-4 source pins 122 and 1 gate pin 123 are arranged; wherein the two gate pins 123 on the left and right sides are arranged diagonally.

[0037] The distribution method provided in this application embodiment allows the source and gate pins 123 of the first MOS chip 210 and the second MOS chip 220 to be located on opposite sides of the package, which facilitates the separation of the drive circuit and power circuit during PCB layout, reduces the parasitic inductance of the gate drive circuit, and improves the controllability of the switching speed. At the same time, the symmetrically distributed source pins 122 on both sides can be used in parallel to increase the current carrying capacity.

[0038] The drain pin is electrically connected to the drain on the back of the chip through the base island region 110. Therefore, the drain pin can extend directly from the second side of the base island region 110 or be led out through the edge transition region of the base island region 110.

[0039] The drain pins are distributed on both sides perpendicular to the source / gate pins 123, forming a "cross" pin layout. This layout maximizes spatial separation between the high-potential (drain) and low-potential (source / gate) pins, reducing parasitic capacitance between pins and potential creepage risks, thus improving the electrical safety of the package. Simultaneously, the distribution of the drain pins on both sides of the chip alignment direction facilitates drain connections between the upper and lower bridge arms in a half-bridge topology (e.g., to DC bus voltage).

[0040] In one embodiment, the first MOS chip 210 and the second MOS chip 220 are N-channel power MOS chips with the same electrical parameters, arranged in a direction parallel to the second side, and the first MOS chip 210 and the second MOS chip 220 form a half-bridge topology circuit inside the package.

[0041] The electrical parameters are the same, including but not limited to: rated drain-source breakdown voltage V (e.g., 30V, 60V or 100V), rated continuous drain current I (e.g., 50A, 100A or 200A), on-resistance R (e.g., 1mΩ, 2mΩ or 5mΩ), gate threshold voltage V (e.g., 1.5-2.5V), gate charge Q (e.g., 20-50nC), etc.

[0042] Using chips with identical electrical parameters ensures consistent switching characteristics between the upper and lower arms in a half-bridge topology, avoiding uneven current distribution, differences in switching losses, or electromagnetic interference (EMI) issues caused by parameter mismatch. The two chips can be from the same wafer batch and package batch to maximize parameter consistency.

[0043] The drains of the two chips are electrically connected together through the base island region 110 (common drain structure) to serve as the midpoint or DC input terminal of the half-bridge; the source of the first MOS chip 210 is led out through its source pin 122 to serve as one output terminal of the half-bridge (such as low-side output), and the source of the second MOS chip 220 is led out through its source pin 122 to serve as the other output terminal of the half-bridge (such as high-side output); the gates of the two chips are led out through independent gate pins 123 to receive their respective gate drive signals.

[0044] In half-bridge mode, the two chips alternately turn on and off to achieve DC-to-AC power conversion. Since the two chips are integrated into the same package, the connection path between the drains is extremely short (directly connected through the base island 110), which significantly reduces the parasitic inductance at the midpoint of the half-bridge and reduces voltage overshoot during switching. This allows for the use of higher switching frequencies or lower on-resistance chips, improving system efficiency and power density.

[0045] By integrating two N-channel MOS chips with identical electrical parameters into the same package and forming a half-bridge topology, combined with the optimized layout of the lead frame, a high degree of integration of the half-bridge power module is achieved.

[0046] In one embodiment, the pin area 120 and the base island area 110 are intermittently arranged with an intermittent distance of 1-3 mm.

[0047] During the lead frame stamping stage, the lead area 120 and the base island area 110 are temporarily connected by a tie bar. After molding, the tie bar is cut off or punched out, forming a 1-3mm intermittent gap. This intermittent distance ensures that the molding compound can fully fill the area between the lead area 120 and the base island area 110, forming a reliable electrical insulation barrier.

[0048] The intermittent spacing ensures that the base island region 110 (drain potential) and the pin region 120 (source / gate potential) are insulated only by the molding layer 500, avoiding the risk of short circuits caused by metal connections. The 1-3mm intermittent distance ensures insulation reliability while avoiding an increase in package size due to excessive spacing.

[0049] The pin area 120 includes a connection portion 121, which is close to the base island area 110. The connection portion 121 connects to one or more pins. The cross-section of the connection portion 121 is an L-shaped stepped structure, with the side closer to the base island area being higher than the side away from the base island area. The step height of the L-shaped step is 0.3±0.05mm.

[0050] The step height is 0.3±0.05mm, for example, 0.25mm, 0.28mm, 0.3mm, 0.32mm or 0.35mm; the raised height can ensure convenient and stable contact between the pin and the copper sheet 410, 420, so as to make the soldering stable and also ensure the mechanical strength of the pin itself.

[0051] The L-shaped stepped structure of pin area 120 provides a stable support platform for the bonding wire assembly. The inner height of the stepped structure matches the height of the front side of the chip, allowing the source bonding wire 320 and the gate bonding wire 310 to be bonded with optimal arc height, reducing stress concentration and the risk of wire collapse.

[0052] In one embodiment, the bonding wire assembly includes source bonding wires 320 and gate bonding wires 310. The source bonding wires 320 are multiple parallel thick aluminum wires used to connect the source regions of the first MOS chip 210 or the second MOS chip 220 to the corresponding source pins 122. A first copper sheet 420 is soldered over and onto the multiple source bonding wires 320. The gate bonding wire 310 is a single aluminum wire used to independently connect the gate region of the first MOS chip 210 or the second MOS chip 220 to the corresponding gate pin 123. A first copper sheet 410 is soldered over and onto the single gate bonding wire 310.

[0053] Multiple parallel connections allow the source regions of a single chip to be connected in parallel to the corresponding source pin 122 via 3-8 bonding wires, thereby increasing current carrying capacity and reducing on-resistance and parasitic inductance.

[0054] Coarse aluminum wire refers to high-purity aluminum wire (Al-1%Si or Al-0.5%Cu alloy) with a diameter of 300-500μm. Using coarse aluminum wire allows the source path to carry large currents (e.g., 50-200A), requiring low ohmic losses (P = I²R). Aluminum wire also has good ductility and bonding processability, making it suitable for wedge bonding or ball bonding of large wire diameters.

[0055] Copper sheets 410 and 420 cover multiple parallel thick aluminum wires. After the thick aluminum wires are completely covered and welded by copper sheets 410 and 420, a "aluminum wire-copper sheet 410 and 420" composite conductor structure is formed, which further reduces resistance and inductance.

[0056] A single wire means that the gate of each chip is connected by only one bonding wire, which can reduce the parasitic capacitance of the gate circuit and improve the rise / fall rate of the gate drive signal.

[0057] Independent connection means that the gates of the first MOS chip 210 and the second MOS chip 220 are respectively connected to independent gate pins 123 through their respective gate bonding lines 310, and there are no shared bonding lines or pins between the gates of the two chips. This independent design allows each chip to accept independent gate drive signals, which facilitates the implementation of advanced drive functions such as dead time control, current balancing, or fault protection.

[0058] In one implementation, multiple drain pins are soldered to the base island region 110.

[0059] During the lead frame manufacturing stage, the drain pin is not intermittently connected to the base island region 110 like the source / gate pin 123, but is permanently electrically and mechanically connected to the base island region 110 through a soldering process. For example, the inner end of the drain pin overlaps with and is soldered to the edge of the base island region 110, with an overlap width of 0.5-1.5 mm.

[0060] The soldered connection between the drain pin and the base island region 110 creates a low-impedance path between the drain on the back of the chip (through the base island region 110) and the drain pin. In the half-bridge topology, the drains of both chips are led out through the base island region 110 and the soldered drain pin, achieving a common-drain connection. Compared to connecting the drains via bonding wires or jumpers, the soldered connection offers higher mechanical reliability, lower parasitic inductance, and stronger current carrying capacity.

[0061] The number of drain pins is typically 2-6, evenly distributed along the second side of the base island region 110 to balance current distribution and heat dissipation path.

[0062] In one embodiment, the edge of the base island region 110 is intermittently distributed with a plurality of irregularly shaped locking grooves 112.

[0063] Intermittent distribution refers to the discontinuous arrangement of multiple irregularly shaped locking grooves 112 along the four edges of the base island area 110, with a spacing of 2-5 mm between adjacent grooves 112, in order to avoid excessively weakening the mechanical strength of the base island area 110.

[0064] The irregularly shaped locking groove 112 refers to a groove structure with a complex contour, rather than a simple rectangle or semicircle in cross-section. Specific shapes can include: dovetail groove (narrower at the top and wider at the bottom), inverted T-shape, serrated shape, or corrugated shape. Taking the dovetail groove as an example, the opening width of the groove 112 is 0.3-0.6mm, the bottom width is 0.5-1.0mm, the depth is 0.1-0.2mm, and the opening angle is 60-90°.

[0065] During the molding process, molten epoxy molding compound flows into the groove 112 and, after curing, forms a molding compound protrusion 111 structure that complements the shape of the groove 112. Due to the irregular (non-straight-walled) design of the groove 112, a mechanical interlock is formed between the molding compound protrusion 111 and the groove 112, significantly increasing the bonding area and shear resistance between the base island region 110 and the molding layer 500. The irregularly shaped locking groove 112 effectively resists this shear stress through mechanical interlocking, preventing interface delamination or cracking of the molding layer 500, and improving the long-term reliability of the encapsulation.

[0066] In one embodiment, the back side of the base island region 110 is formed with a textured structure by precision stamping, and the surface roughness Ra of the textured structure is ≤1.6μm.

[0067] The textured structure on the back can increase the heat dissipation capacity of the base island area 110 and improve the heat dissipation effect of the MOD device.

[0068] In this embodiment, after the molding layer 500 is molded, the back side of the base island area 110 remains exposed, which can be attached to the heat dissipation device. The textured structure can increase the flow space during the heat dissipation process and further improve the heat dissipation effect.

[0069] In one embodiment, the copper sheets 410 and 420 are precision stamped from oxygen-free copper, and the thickness of the copper sheets 410 and 420 is 0.1mm-0.3mm.

[0070] Oxygen-free copper refers to high-purity copper with a purity of not less than 99.95% and an oxygen content of not more than 0.001%. Oxygen-free copper has extremely low impurity content, thus exhibiting excellent electrical conductivity (≥100% IACS, i.e., ≥58 MS / m) and thermal conductivity (≥390 W / (m·K)). Compared to ordinary pure copper, oxygen-free copper is less prone to oxidation at high temperatures (such as welding temperatures of 250-300℃ or molding curing temperatures of 175-185℃), maintaining stable electrical and welding properties.

[0071] Precision stamping refers to stamping accuracy controlled within ±0.05mm, ensuring the flatness of copper sheets 410 and 420 is less than 0.05mm, and free of burrs (less than 0.02mm) and cracks. The shape of copper sheets 410 and 420 is designed according to the layout of the bonding wires they cover, and is usually rectangular, L-shaped, or irregularly shaped to accommodate the spatial positions of different chips and bonding wires.

[0072] After precision stamping, copper sheets 410 and 420 can undergo selective plating treatment, such as nickel plating (1-3μm) + gold plating (0.05-0.1μm) or tin plating (5-10μm), to improve oxidation resistance and solder wettability.

[0073] In one embodiment, the spacing between the first MOS chip 210 and the second MOS chip 220 is 0.5-0.6 mm; this spacing refers to the minimum distance between adjacent edges of the two chips, which is precisely controlled by a high-precision placement machine (Placement Accuracy ±25μm) and a vision positioning system.

[0074] When the pitch is less than 0.5mm, it is difficult to fill the molding compound between the two chips, which can easily lead to voids. In addition, the bonding wire space is limited, which can easily cause short circuits between the wires. When the pitch is greater than 0.6mm, the package size increases, the utilization rate of the base island 110 decreases, and the thermal coupling between the two chips weakens (which is not conducive to thermal equilibrium). At the same time, the span of the source bonding wire 320 increases, and the parasitic inductance increases.

[0075] Both the first MOS chip 210 and the second MOS chip 220 adopt a back metal drain and a front partitioned electrode structure, with their back sides bonded to the surface of the base island region 110.

[0076] After bonding, a low-resistance and low-thermal-resistance connection is formed between the metal drain on the back of the chip and the base island region 110. The full-surface metallization on the back of the chip and the flat surface of the base island region 110 form a large-area close contact, which is beneficial for rapid heat conduction and uniform current distribution. At the same time, the mechanical strength of the bonding ensures the positional stability of the chip during subsequent bonding, molding, and use.

[0077] The metal drain on the back of the chip is bonded to the base island region 110, and then the base island region 110 is bonded to the drain pin, forming a low-impedance path from the chip drain to the external PCB. Copper sheets 410 and 420 cover the source bonding line 320, and are optimized in conjunction with the drain path to make the on-resistance (R) of the entire package close to the intrinsic on-resistance of the chip.

[0078] Other configurations of the dual MOS integrated package structure in the above embodiments can be adopted from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0079] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0081] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0082] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0083] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dual MOS integrated package structure, characterized in that, include: A lead frame, the lead frame including a base island portion and a pin portion located around the base island portion; the pin portion includes a plurality of source pins and a plurality of gate pins; The first MOS chip and the second MOS chip are arranged side by side on the base island portion; A bonding wire assembly includes multiple bonding wires, which are respectively electrically connected to the first MOS chip and the source pin and the gate pin of the corresponding first MOS chip, and electrically connected to the second MOS chip and the source pin and the gate pin of the corresponding second MOS chip; Multiple copper sheets are soldered onto one or more bonding wires. A molding compound covering the copper sheet, the first MOS chip, the second MOS chip, the base island portion, and a portion of the pin portion.

2. The dual MOS integrated package structure according to claim 1, characterized in that, The base island portion includes two opposing first sides and two opposing second sides; a plurality of source pins and a plurality of gate pins are distributed on the two opposing first sides; a plurality of drain pins are distributed on the two opposing second sides.

3. The dual MOS integrated package structure according to claim 2, characterized in that, The first MOS chip and the second MOS chip are N-channel power MOS chips with the same electrical parameters, arranged in a direction parallel to the second side, and the first MOS chip and the second MOS chip form a half-bridge topology circuit inside the package.

4. The dual MOS integrated package structure according to claim 1, characterized in that, The pin portion and the base island portion are intermittently arranged with an intermittent distance of 1-3mm. The pin portion includes a connecting portion, which is close to the base island portion and connects to one or more pins. The cross-section of the connecting portion is an L-shaped stepped structure, with the side closer to the base island portion being higher than the side away from the base island portion. The step height of the L-shaped step is 0.3±0.05mm.

5. The dual MOS integrated package structure according to claim 4, characterized in that, The bonding wire assembly includes source bonding wires and gate bonding wires; the source bonding wires are multiple parallel thick aluminum wires used to connect the source region of the first MOS chip or the second MOS chip to the corresponding source pin; the gate bonding wire is a single aluminum wire used to independently connect the gate region of the first MOS chip or the second MOS chip to the corresponding gate pin.

6. The dual MOS integrated package structure according to claim 1, characterized in that, Multiple drain pins are soldered to the base island region.

7. The dual MOS integrated package structure according to claim 1, characterized in that, The edge of the base island area has multiple irregularly shaped locking grooves distributed intermittently.

8. The dual MOS integrated package structure according to claim 1, characterized in that, The back side of the base island area is formed by precision stamping to create a textured structure, and the surface roughness Ra of the textured structure is ≤1.6μm.

9. The dual MOS integrated package structure according to claim 1, characterized in that, The copper sheet is made of oxygen-free copper through precision stamping, and the thickness of the copper sheet is 0.1mm-0.3mm.

10. The dual MOS integrated package structure according to claim 1, characterized in that, The spacing between the first MOS chip and the second MOS chip is 0.5-0.6 mm; both the first MOS chip and the second MOS chip adopt a back metal drain and a front partitioned electrode structure, and their back sides are bonded to the surface of the base island region.

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