A piezoelectric ultrasonic transducer
Patent Information
- Application Number
- CN202610641108.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-11
- Publication Date
- 2026-09-01
AI Technical Summary
[0006]针对现有技术的缺陷,本申请的目的在于提供一种压电超声换能器,旨在解决现有压电超声换能器结构设计无法实现残余应力的有效释放与均匀调控,从而导致压电微机械超声换能器的频率一致性、振幅性能无法满足预期的问题
本申请提供一种压电超声换能器,通过在压电驱动叠层中设置环形沟槽和中心贯穿通孔,而实现阶梯式应力调控的分级应力释放结构。其中,环形沟槽自顶部电极层向下贯穿压电层和底部电极层,将原本连续的压电驱动叠层在径向上分割为中心驱动区域和边缘驱动区域,从而形成质量与刚度的阶梯状分布;中心贯穿通孔则进一步移除振动薄膜中心的最大应力集中点,并与空腔形成贯通的气流通道。根据圆形薄板振动理论,PMUT的工作状态由无量纲参数所决定,当器件内部的有效残余张力较大时,器件工作于“薄膜主导区”,此时谐振频率对残余应力的微小变化极为敏感;而当有效残余张力被降低至一定程度时,器件回归“平板主导区”,其刚度主要由材料本身的抗弯刚度决定,谐振频率对残余应力的波动呈现出显著的低敏感性,此时的谐振位移得到有效提高。
Smart Images

Figure CN122679818A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of ultrasonic transducers, and more specifically, relates to a piezoelectric ultrasonic transducer. Background Technology
[0002] Piezoelectric micromachined ultrasonic transducers (PMUTs) have shown broad application prospects in distance sensing, medical imaging, non-destructive testing, and underwater communication due to their advantages such as small size, low power consumption, and ease of arraying. These devices typically consist of a multilayer thin-film structure suspended above a substrate cavity, comprising, from top to bottom, a top electrode, a piezoelectric functional layer, a bottom electrode, and a support layer. When an alternating voltage is applied between the top and bottom electrodes, the piezoelectric layer undergoes lateral stretching strain due to the inverse piezoelectric effect, which, under boundary constraints, is converted into out-of-plane bending vibration of the thin film, thereby radiating ultrasonic waves into the surrounding medium. However, in actual manufacturing and operation, residual and accumulated stresses inevitably arise within the thin film due to factors such as material deposition, thermal mismatch, and process gradients. This leads to non-uniform deformation of the thin film, resonant frequency drift, and amplitude attenuation, severely restricting the consistency of the array device and the overall acoustic performance of the system.
[0003] To address the aforementioned stress issues, various structural engineering strategies have been developed in the prior art. One such strategy is a quasi-closed diaphragm design, which transforms a continuous thin film into a segmented cantilever beam structure through a central cross slit to release residual stress and reduce the quality factor, thereby improving frequency uniformity and extending the linear operating range (Wang Y, Chen P, Zhang J, et al. Quasi-closed diaphragm based piezoelectric micromachined ultrasonic transducer with reduced Q and stress sensitivity for in-air rangefinding. Sensors and Actuators A: Physical, 2024, 379: 115938.). Secondly, the use of a cantilever beam PMUT combined with post-processing of polydimethylsiloxane (PDMS) soft interconnection can suppress asynchronous vibration and shorten ringing tail, thereby achieving a longer detection distance (Wang Y, Chen P, Zhang J, et al. Cantilever beam-based piezoelectric micromachined ultrasonic transducer with post-processing soft interconnecting strategy for in-air range finding. Microsystems & Nanoengineering, 2025, 11(1): 97.). In addition, local stiffness modification to redistribute stress concentration or the use of island-shaped monocrystalline lead zirconate titanate thin film (Thao PN, Yoshida S, Tanaka S. Development of mechanically-robust piezoelectric micromachined ultrasonic transducer (PMUT) with island-shaped PZT monocrystalline thin film. IEEE, 2019: 833-836.) also shows potential in mitigating fracture risk.
[0004] While the aforementioned studies have achieved varying degrees of performance improvement at the single-device level, they still face several significant limitations in practical large-scale applications. In terms of geometry, the central micrometer-level slit required for quasi-closed diaphragms demands extremely high precision control over deep reactive ion etching (DRIE). Even minute process fluctuations can lead to significant changes in slit geometry, resulting in uneven distribution of wafer-level thermoviscous damping and quality factor. Similarly, while designs relying on fine suspension beams or island-like discontinuous structures theoretically help guide stress distribution, such complex topologies often introduce mechanical weak points into the device, posing a risk of fracture under high-voltage driving conditions. Regarding heterogeneous integration solutions, PDMS soft interconnect strategies rely on manual dispensing. The uncontrollable differences in droplet volume, position, and curing conditions directly translate into discreteness in the boundary conditions and damping characteristics of each unit in the array, ultimately leading to decreased wafer-level frequency consistency and insufficient repeatability. Furthermore, most current stress control solutions still require additional post-processing steps or non-standard process modules, further limiting their compatibility with standard photolithography processes and the feasibility of large-scale manufacturing.
[0005] Therefore, how to effectively release and uniformly control residual stress through structural design while maintaining high compatibility with standard semiconductor processes, thereby simultaneously improving the frequency consistency, amplitude performance and mechanical robustness of piezoelectric micromechanical ultrasonic transducers, remains a key technical problem that urgently needs to be solved in this field. Summary of the Invention
[0006] In view of the shortcomings of the prior art, the purpose of this application is to provide a piezoelectric ultrasonic transducer, which aims to solve the problem that the existing piezoelectric ultrasonic transducer structural design cannot achieve effective release and uniform control of residual stress, resulting in the frequency consistency and amplitude performance of the piezoelectric micromechanical ultrasonic transducer failing to meet expectations.
[0007] To achieve the above objectives, in a first aspect, this application provides a piezoelectric ultrasonic transducer, the piezoelectric ultrasonic transducer comprising a first base layer, a second base layer, a first electrode layer, a piezoelectric layer and a second electrode layer stacked sequentially; the first base layer has a cavity coaxial with the piezoelectric layer; the piezoelectric layer has a first through hole and a first annular groove respectively penetrating through it; The first electrode layer is provided with a second through hole and a second annular groove that penetrate through it respectively; A third through hole is provided in the second base layer; The first through hole is located at the center of the piezoelectric layer, and the first annular groove is coaxially arranged with the piezoelectric layer; The second through hole and the third through hole are connected to the first through hole in sequence, and the third through hole is connected to the cavity; the second annular groove is connected to the first annular groove, and the outer diameter of the first annular groove is not greater than the diameter of the cavity.
[0008] As a further preferred embodiment, the second electrode layer covers the area on the upper surface of the piezoelectric layer surrounded by the first annular groove.
[0009] As a further preferred embodiment, the ratio of the radius of the first through hole to the radius of the second electrode layer is in the range of 7.14%-9%.
[0010] As a further preferred embodiment, the ratio of the radius of the second electrode layer to the radius of the cavity is in the range of 68%-72%.
[0011] As a further preferred embodiment, the ratio of the annular width of the first annular groove to the cavity radius is in the range of 28%-32%.
[0012] As a further preferred embodiment, the first through hole, the second through hole, and the third through hole have the same radius and are smoothly connected.
[0013] As a further preferred embodiment, the first substrate comprises, from bottom to top, a bottom silicon layer and a buried oxide layer; the second substrate comprises a top silicon layer.
[0014] As a further preferred embodiment, the aforementioned buried oxide layer is a silicon dioxide layer.
[0015] As a further preferred option, the piezoelectric layer material is lead zirconate titanate (PZT).
[0016] As a further preferred embodiment, the thickness of the first electrode layer is 200 nm; the thickness of the piezoelectric layer is 2 μm; and the thickness of the second electrode layer is 200 nm.
[0017] As a further preferred embodiment, the thickness of the bottom silicon layer is 525 μm; the thickness of the buried oxide layer is 2 μm; and the thickness of the top silicon layer is 10 μm.
[0018] Secondly, this application provides a method for fabricating the piezoelectric ultrasonic transducer described in the first aspect above, comprising the following steps: Step S1, providing a silicon-on-insulator (SOI) substrate; the SOI substrate comprises, from bottom to top, a bottom silicon layer, a buried oxide layer, and a top silicon layer; Step S2: Sequentially deposit a first electrode layer and a piezoelectric layer on the upper surface of the SOI substrate; Step S3: Deposit a second electrode layer on the upper surface of the piezoelectric layer; Step S4: Pattern the piezoelectric layer and the first electrode layer, and etch the piezoelectric layer and the first electrode layer sequentially until the upper surface of the underlying top silicon layer is exposed to form an annular trench; the annular trench includes a first annular trench and a second annular trench. Step S5: Etch from the front side of the SOI substrate at the center of the area enclosed by the annular trench, with the etching depth penetrating the top silicon layer until the buried oxide layer underneath is exposed, forming a through-hole. Step S6: From the back side of the SOI substrate, etch the circular area corresponding to the cavity, and sequentially etch away the bottom silicon layer and the buried oxide layer until the lower surface of the device silicon layer is exposed.
[0019] In summary, compared with the prior art, the technical solutions conceived in this application have the following main technical advantages: This application provides a piezoelectric ultrasonic transducer (PMUT) that achieves a stepped stress-relieving structure with controlled stress by setting an annular groove and a central through-hole in the piezoelectric driving stack. The annular groove extends from the top electrode layer downwards through the piezoelectric and bottom electrode layers, radially dividing the originally continuous piezoelectric driving stack into a central driving region and an edge driving region, thus forming a stepped distribution of mass and stiffness. The central through-hole further removes the maximum stress concentration point at the center of the vibrating film and forms a through-flow channel with the cavity. According to the theory of circular thin-plate vibration, the operating state of the PMUT is determined by dimensionless parameters. When the effective residual tension inside the device is large, the device operates in the "thin-film dominant region," where the resonant frequency is extremely sensitive to small changes in residual stress. When the effective residual tension is reduced to a certain level, the device returns to the "plate dominant region," where its stiffness is mainly determined by the bending stiffness of the material itself, and the resonant frequency exhibits significantly low sensitivity to fluctuations in residual stress, effectively improving the resonant displacement.
[0020] This application provides a piezoelectric ultrasonic transducer that, through a stepped stress-regulating structure, interrupts the continuity of the piezoelectric layer in the radial plane. This allows the residual tensile stress generated during manufacturing to be released at the grooves, effectively reducing the equivalent residual tension of the vibrating film. This forces the device to return from the stress-sensitive "film-dominated region" to the frequency-stable "plate-dominated region," thereby significantly suppressing resonant frequency drift caused by process fluctuations or environmental changes and enhancing the frequency consistency of the unit device. Simultaneously, the central through-hole physically removes the material in the central region with the highest stress under the first-order bending mode, further weakening the stress concentration effect. Furthermore, by introducing controllable thermoviscous damping (i.e., air medium), the operating bandwidth is broadened while ringing attenuation is accelerated, improving the impedance and phase at the resonant frequency. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the cross-section of an existing piezoelectric ultrasonic transducer; Figure 2 This is a schematic diagram of the stress distribution on the upper surface of PZT in a piezoelectric ultrasonic transducer when a uniform load is applied. Figure 3This is a schematic diagram of the charge density on the upper surface of PZT in a piezoelectric ultrasonic transducer when a uniform load is applied. Figure 4 This is a schematic diagram of the displacement frequency curve of an existing piezoelectric ultrasonic transducer; Figure 5 This is a schematic diagram of the frequency impedance phase curve of an existing piezoelectric ultrasonic transducer; Figure 6 This is a schematic cross-sectional view of the piezoelectric ultrasonic transducer provided in the embodiments of this application; Figure 7 This is a schematic diagram of the displacement frequency curve of the piezoelectric ultrasonic transducer provided in Embodiment 1 of this application; Figure 8 This is a schematic diagram of the displacement frequency curve of the piezoelectric ultrasonic transducer provided in Embodiment 2 of this application; Figure 9 This is a schematic diagram of the displacement frequency curve of the piezoelectric ultrasonic transducer provided in Embodiment 3 of this application; Figure 10 This is a schematic diagram of the frequency impedance phase curve of the piezoelectric ultrasonic transducer provided in Embodiment 1 of this application; Figure 11 This is a schematic diagram of the frequency impedance phase curve of the piezoelectric ultrasonic transducer provided in Embodiment 2 of this application; Figure 12 This is a schematic diagram of the frequency impedance phase curve of the piezoelectric ultrasonic transducer provided in Embodiment 3 of this application. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0023] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0024] Furthermore, throughout this specification, references to "an embodiment"; "an embodiment," "an example," or similar language indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. Therefore, the appearance of the phrase "in one embodiment;" throughout this specification, and similar language, may, but not necessarily, refer to the same embodiment.
[0025] Figure 1 This is a schematic diagram of the cross-section of an existing piezoelectric ultrasonic transducer; such as Figure 1 As shown, an existing piezoelectric ultrasonic transducer comprises, from bottom to top, a bottom silicon layer, a buried oxide layer (usually silicon dioxide), a top silicon layer, a bottom electrode, a PZT piezoelectric layer, and a top electrode. Cavities are provided in the bottom silicon layer and the silicon dioxide layer; the top electrode only covers the middle region of the PZT piezoelectric layer, and the area of the top electrode is smaller than the area of the cavity.
[0026] When a uniform load is applied to the surface of the PMUT structure, the diaphragm will deform under the force. The stress distribution along the in-plane x-axis is as follows: Figure 2 As shown, the stress distribution in the central region is opposite to that at the edges. The black contour lines represent stress values of zero, due to the PMUT's bending vibration mode. The contour lines with zero stress are located at 68% of the surface radius.
[0027] like Figure 3 As shown, when the PMUT is in emission mode, the driving voltage generates an electric field through the electrodes, which in turn induces stress in the material through the piezoelectric effect. If the electrodes simultaneously cover both positive and negative stress regions, the generated driving forces will partially cancel each other out, reducing vibration efficiency. Simultaneously, the surface charge polarity is opposite in the central region to that at the edges, and its radius is approximately 72% of the piezoelectric film radius.
[0028] In summary, when the PMUT is in receiving mode, vibration induces strain in the piezoelectric layer, which in turn generates charge. If the electrodes simultaneously cover both positive and negative charge regions, the generated charges will cancel each other out inside the electrodes, resulting in a weakened output signal. Therefore, to achieve optimal electromechanical coupling efficiency, the radius of the top electrode should be approximately 68% to 72% of the cavity radius.
[0029] It should be noted that the aforementioned top electrode radius is generally only related to the cavity radius and is unrelated to the improved through-hole and annular groove in this embodiment. This is because the top electrode radius focuses on optimizing the electromechanical conversion efficiency of the effective vibration region, while the through-hole and annular groove optimize the mechanical boundary conditions and residual stress release. The two involve problems at different physical levels and are therefore not directly related in design. Therefore, in this embodiment, the top electrode radius is taken as 68%-72% of the cavity radius. This will not be specifically explained in the following embodiments.
[0030] Figure 4 This is a schematic diagram of the displacement-frequency curve of an existing piezoelectric ultrasonic transducer. The parameters of the ultrasonic transducer are: top electrode radius 50µm, cavity radius 70µm, PZT thickness 2µm, SOI substrate, and no through holes or trenches. At the resonant frequency, its displacement peak is small, only 1.2µm. At this time, the residual stress of the film is large, and the device itself has high stiffness.
[0031] Figure 5 This is a schematic diagram of the frequency impedance phase curve of an existing piezoelectric ultrasonic transducer; the phase value at the resonance point is 38° and the impedance is 78Ω, indicating that the energy encounters greater resistance during the electromechanical conversion process at this point, and the electromechanical coupling coefficient and quality factor of the device are poor.
[0032] Figure 6 This is a schematic cross-sectional view of the piezoelectric ultrasonic transducer provided in the embodiments of this application; as shown... Figure 6 As shown, it includes a first base layer (bottom silicon layer + buried oxide layer), a second base layer (top silicon layer), a first electrode layer (bottom electrode), a piezoelectric layer (PZT layer), and a second electrode layer (top electrode) stacked in sequence.
[0033] Among them, such as Figure 6 As shown, the first substrate, from bottom to top, includes a bottom silicon layer and a buried oxide layer; the second substrate includes a top silicon layer. The buried oxide layer is typically a silicon dioxide layer.
[0034] Specifically, a cavity coaxial with the piezoelectric layer is provided in the first base layer; the cavity is cylindrical.
[0035] like Figure 6 As shown, compared to Figure 1 In this embodiment, a piezoelectric layer has a first through-hole and a first annular groove that penetrate through it; a first electrode layer has a second through-hole and a second annular groove that penetrate through it; and a second base layer has a third through-hole that penetrates through it. The first through-hole is located at the center of the piezoelectric layer, and the first annular groove is coaxially arranged with the piezoelectric layer. The second and third through-holes are sequentially connected to the first through-hole, and the third through-hole is connected to a cavity. The second annular groove is connected to the first annular groove, and the outer diameter of the first annular groove is not greater than the diameter of the cavity. The second electrode layer covers the area on the upper surface of the piezoelectric layer surrounded by the first annular groove.
[0036] Furthermore, the first through hole, the second through hole, and the third through hole have the same radius and are smoothly connected, forming... Figure 6 The corresponding through holes are usually integrally formed.
[0037] Furthermore, the second annular groove is the same size as the first annular groove and is smoothly connected, forming... Figure 6 The corresponding annular groove is usually integrally formed.
[0038] As a further preferred embodiment, the ratio of the radius of the first through hole to the radius of the second electrode layer is in the range of 7.14%-9%.
[0039] As a further preferred embodiment, the ratio of the radius of the second electrode layer to the radius of the cavity is in the range of 68%-72%.
[0040] As a further preferred embodiment, the ratio of the annular width of the first annular groove to the cavity radius is in the range of 28%-32%.
[0041] It should be noted that, under normal circumstances, the sum of the radius of the second electrode layer and the width of the first annular groove is half the outer diameter of the first annular groove.
[0042] Understandably, the cavity radius defines the effective area for free vibration, the top electrode radius defines the energy input area for active driving, and the trench outer diameter defines a controllable and optimized boundary condition that can release film stress, allowing for a larger vibration area and more efficient vibration.
[0043] Inside the cavity, the groove can release membrane stress by reducing stiffness. However, outside the cavity, it directly induces severe stress concentration at the artificial cut at the fixed end of the diaphragm, becoming a potential mechanical failure point. Simultaneously, a cavity radius smaller than the groove's outer diameter alters the diaphragm's boundary conditions. The groove redefines the diaphragm's boundary as a "mechanical hinge," while the rigid anchor point outside the cavity may experience parasitic resonance due to stress concentration, consuming energy and causing signal crosstalk. In summary, the groove's performance-enhancing effect depends entirely on its location within the diaphragm's effective area. Once it extends beyond the cavity boundary, it transforms from a "performance amplifier" into a "parasitic structure," bringing negative consequences. Therefore, the aforementioned half-outer diameter should not exceed the cavity radius, i.e., the outer diameter should not exceed the cavity diameter; thus, the sum of the ratio of the second electrode layer radius to the cavity radius and the ratio of the ring width of the first annular groove to the cavity radius should not exceed 1.
[0044] As a further preferred embodiment, the thickness of the first electrode layer can be 200 nm; the thickness of the piezoelectric layer can be 2 μm; and the thickness of the second electrode layer can be 200 nm.
[0045] As a further preferred embodiment, the thickness of the bottom silicon layer can be 525 μm; the thickness of the buried oxide layer can be 2 μm; and the thickness of the top silicon layer can be 10 μm.
[0046] In summary, the piezoelectric ultrasonic transducer provided in this application achieves a graded stress relief structure by setting an annular groove and a central through-hole in the piezoelectric driving stack. The annular groove extends from the top electrode layer downwards through the piezoelectric layer and the bottom electrode layer, radially dividing the originally continuous piezoelectric driving stack into a central driving region and an edge driving region, thus forming a stepped distribution of mass and stiffness. The central through-hole further removes the maximum stress concentration point at the center of the vibrating film and forms a through-flow channel with the cavity.
[0047] According to the vibration theory of circular thin plates, the working state of PMUT is determined by dimensionless parameters. When the effective residual tension inside the device is large, the device operates in the "thin film dominant region". At this time, the resonant frequency is extremely sensitive to small changes in residual stress. When the effective residual tension is reduced to a certain extent, the device returns to the "plate dominant region". Its stiffness is mainly determined by the bending stiffness of the material itself. The resonant frequency shows a significantly low sensitivity to fluctuations in residual stress. At this time, the resonant displacement is effectively improved.
[0048] This application utilizes a stepped stress-regulating structure to disrupt the continuity of the piezoelectric layer in the radial plane. This allows the residual tensile stress generated during manufacturing to be released at the grooves, effectively reducing the equivalent residual tension of the vibrating thin film. This forces the device to return from the stress-sensitive "thin film-dominated region" to the frequency-stable "plate-dominated region," significantly suppressing resonant frequency drift caused by process fluctuations or environmental changes, and enhancing the frequency consistency of the unit device. Simultaneously, the central through-hole physically removes the material from the central region where stress is highest under the first-order bending mode, further weakening the stress concentration effect. Furthermore, by introducing controllable thermoviscous damping (i.e., air medium), it broadens the operating bandwidth while accelerating ringing attenuation, thus improving the impedance and phase at the resonant frequency.
[0049] Compared to existing stress control methods such as overall preload application, residual stress compensation, or complex suspension structures, the stepped stress control structure provided in this application offers the following advantages in piezoelectric ultrasonic transducers: firstly, improved frequency consistency; secondly, enhanced resonant displacement; and thirdly, improved impedance and phase at the resonant frequency. Therefore, this application proposes a piezoelectric ultrasonic transducer based on stepped stress control, aiming to significantly improve the frequency stability and amplitude output capability of the device while maintaining process compatibility through a structural design that releases stress in stages.
[0050] The piezoelectric ultrasonic transducer and its fabrication method provided in this application will be described in detail below through specific embodiments.
[0051] Example 1 The method for fabricating a piezoelectric ultrasonic transducer based on stepped stress regulation provided in this embodiment includes the following steps: S1. Patterning of piezoelectric layer deposition and stepped stress-controlled structure.
[0052] A silicon-on-insulator (SOI) substrate is used. A bottom electrode layer and a piezoelectric layer are sequentially deposited on the silicon layer of the device. A stepped stress-controlled structure is formed by photolithography and dry etching processes. The process includes the following sub-steps: S11. Provide a silicon-on-insulator substrate, wherein the SOI substrate comprises, from bottom to top, a bulk silicon layer, a buried oxide layer and a device silicon layer, wherein the thickness of the device silicon layer is 10 μm and the thickness of the buried oxide layer is 2 μm. S12. A bottom electrode layer and a piezoelectric layer are sequentially deposited on the upper surface of the silicon layer of the device using a magnetron sputtering process. The bottom electrode layer is made of Pt with a thickness of 200 nm, and the piezoelectric layer is made of PZT with a thickness of 2 μm. S13. The top electrode layer is patterned by a lift-off process to define the top electrode pattern, and then the top electrode is sputtered by magnetron sputtering with Pt material. S14. The piezoelectric layer and the bottom electrode layer are patterned using photolithography and inductively coupled plasma (ICP) etching processes, and an annular trench structure is formed simultaneously in this step. Specifically, an annular opening pattern corresponding to the annular trench is designed on the photolithographic mask, the piezoelectric layer in the corresponding area is removed by ICP etching, and the bottom electrode layer in the corresponding area is removed by RIE etching until the upper surface of the underlying device silicon layer is exposed, forming an annular trench. The annular trench includes a first annular trench and a second annular trench stacked in spatial position.
[0053] S2, Through-hole etching and vibration film release.
[0054] After patterning the piezoelectric layer and top and bottom electrodes, the central through-hole is etched and the cavity is released to complete the device fabrication. This process includes the following sub-steps: S21. Using photolithography and deep reactive ion etching (DRIE) processes, etching is performed from the front side of the device silicon layer at the center of the area enclosed by the annular trench, with the etching depth penetrating the device silicon layer until the buried oxide layer underneath is exposed, forming a through-hole; the through-hole includes a first through-hole, a second through-hole, and a third through-hole stacked in spatial position. S22. Photolithography and deep reactive ion etching are performed on the back side of the SOI substrate. The etching area is a circular area corresponding to the cavity with a radius of 50um. The bulk silicon layer and buried oxide layer are removed sequentially until the lower surface of the device silicon layer is exposed, thereby releasing the vibrating film composed of the device silicon layer and the piezoelectric layer above it, while forming a cavity, and making the through hole connected to the cavity. S23. The device is cleaned by removing the adhesive, and ultrasonic cleaning is performed in sequence with acetone, isopropanol and deionized water. Then it is dried with a nitrogen gun to complete the device fabrication.
[0055] Example 2 The cavity prepared in this embodiment has a radius of 70 μm, and other parameters and preparation process are the same as in Example 1.
[0056] Example 3 The cavity prepared in this embodiment has a radius of 90 μm, and other parameters and preparation process are the same as in Example 1.
[0057] In Examples 1-3 above, the radius of the top electrode is taken as 70% of the cavity radius.
[0058] Figures 7-9 These are schematic diagrams of the displacement-frequency curves of the piezoelectric ultrasonic transducers provided in Embodiments 1-3 of this application; the displacement-frequency curves were obtained using the finite element analysis simulation software COMSOL Multiphysics. Figures 7 to 9 It can be seen that the maximum displacement can be obtained at the circumference of the through hole when the through hole radius is 3um (the ratio of the through hole radius to the cavity radius is 6%, and the ratio to the top electrode radius is 8.58%), 4um (the ratio of the through hole radius to the cavity radius is 5.71%, and the ratio to the top electrode radius is 8%), and 5 / 6um (the ratio of the through hole radius to the cavity radius is 5.56% / 6.67%, and the ratio to the top electrode radius is 7.93% / 9.52%).
[0059] Based on the premise that the maximum displacement attenuation corresponding to each embodiment does not exceed 0.1%, such as Figures 7 to 9 The position of the red line indicates that the ratio of the through-hole radius to the top electrode radius ranges from (7.14%~10%), (6%~9%), and (7.14%~9.84%). Taking the intersection of these three ratio ranges, we find that the ratio of the through-hole radius to the top electrode radius should be between 7.14% and 9%. At this range, a piezoelectric ultrasonic transducer with better performance can be fabricated.
[0060] Figures 10-12 This is a schematic diagram of the frequency impedance phase curve of the piezoelectric ultrasonic transducer provided in Embodiments 1-3 of this application; the above frequency impedance phase curves were obtained using the finite element analysis simulation software COMSOL Multiphysics. Figures 10 to 12 The figures show the relationship between the outer diameter Rg of the isolation trench with back cavity radii of 50µm, 70µm, and 90µm and the displacement. The trends all indicate that as the trench outer diameter gradually increases to the back cavity radius, the maximum displacement gradually increases. Considering that the ratio of the top electrode radius to the cavity radius ranges from 68% to 72%, the displacement reaches its maximum when the ratio of the trench ring width to the cavity radius is between 28% and 32%.
[0061] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A piezoelectric ultrasonic transducer, comprising a first base layer, a second base layer, a first electrode layer, a piezoelectric layer, and a second electrode layer stacked sequentially; wherein a cavity coaxial with the piezoelectric layer is provided in the first base layer; characterized in that, The piezoelectric layer is provided with a first through hole and a first annular groove that respectively penetrate through it; The first electrode layer is provided with a second through hole and a second annular groove that penetrate through it respectively; A third through hole is provided in the second base layer; The first through hole is located at the center of the piezoelectric layer, and the first annular groove is coaxially arranged with the piezoelectric layer; The second through hole and the third through hole are connected to the first through hole in sequence, and the third through hole is connected to the cavity; the second annular groove is connected to the first annular groove, and the outer diameter of the first annular groove is not greater than the diameter of the cavity.
2. The piezoelectric ultrasonic transducer as described in claim 1, characterized in that, The second electrode layer covers the area on the upper surface of the piezoelectric layer that is surrounded by the first annular groove.
3. The piezoelectric ultrasonic transducer as described in claim 2, characterized in that, The ratio of the radius of the first through hole to the radius of the second electrode layer ranges from 7.14% to 9%.
4. The piezoelectric ultrasonic transducer as described in claim 2, characterized in that, The ratio of the radius of the second electrode layer to the radius of the cavity ranges from 68% to 72%.
5. The piezoelectric ultrasonic transducer as described in claim 2, characterized in that, The ratio of the annular width to the cavity radius of the first annular groove ranges from 28% to 32%.
6. The piezoelectric ultrasonic transducer as described in claim 2, characterized in that, The first through hole, the second through hole, and the third through hole have the same radius and are smoothly connected.
7. The piezoelectric ultrasonic transducer as described in claim 2, characterized in that, The first base layer, from bottom to top, includes a bottom silicon layer and a buried oxide layer; the second base layer includes a top silicon layer.
8. The piezoelectric ultrasonic transducer as described in claim 7, characterized in that, The buried oxide layer is a silicon dioxide layer.
9. The piezoelectric ultrasonic transducer according to any one of claims 1 to 8, characterized in that, The piezoelectric layer is made of lead zirconate titanate (PZT).
10. A method for preparing a piezoelectric ultrasonic transducer according to any one of claims 1 to 9, characterized in that, Includes the following steps: Step S1, providing a silicon-on-insulator (SOI) substrate; the SOI substrate comprises, from bottom to top, a bottom silicon layer, a buried oxide layer, and a top silicon layer; Step S2: Sequentially deposit a first electrode layer and a piezoelectric layer on the upper surface of the SOI substrate; Step S3: Deposit a second electrode layer on the upper surface of the piezoelectric layer; Step S4: Pattern the piezoelectric layer and the first electrode layer, and etch the piezoelectric layer and the first electrode layer sequentially until the upper surface of the underlying top silicon layer is exposed to form an annular trench; the annular trench includes a first annular trench and a second annular trench. Step S5: Etch from the front side of the SOI substrate at the center of the area enclosed by the annular trench, with the etching depth penetrating the top silicon layer until the buried oxide layer underneath is exposed, forming a through-hole. Step S6: From the back side of the SOI substrate, etch the circular area corresponding to the cavity, and sequentially etch away the bottom silicon layer and the buried oxide layer until the lower surface of the device silicon layer is exposed.