Silicon carbide epitaxial structures and their preparation methods, silicon carbide devices and electronic devices

Abstract

This application relates to the field of silicon carbide epitaxial wafer technology and provides silicon carbide epitaxial structures and their fabrication methods, silicon carbide devices, and electronic devices. The fabrication method of the silicon carbide epitaxial structure includes: implanting a silicon source, a carbon source, and a conductive dopant source into a reaction chamber to grow a silicon carbide buffer layer on a substrate; implanting the silicon source, carbon source, and conductive dopant source into the reaction chamber to grow a silicon carbide drift layer on the silicon carbide buffer layer; annealing the silicon carbide drift layer at a temperature of 1450~1550°C for 1~3 min; and forming a silicon layer with a thickness of 5~15 nm on the entire surface of the annealed silicon carbide drift layer. This application, by forming a uniform, flat, and continuous silicon layer on silicon carbide, can improve the adhesion of photoresist, reduce the risk of pattern transfer distortion, and improve the performance of silicon carbide devices during subsequent silicon carbide device fabrication.

Description

Technical Field

[0001] This application relates to the field of silicon carbide epitaxial wafer technology, specifically to silicon carbide epitaxial structures and their preparation methods, silicon carbide devices and electronic devices. Background Technology

[0002] Silicon carbide (SiC) devices generally refer to electronic devices fabricated using silicon carbide semiconductor materials. Silicon carbide epitaxial wafers, as the basic material for manufacturing silicon carbide devices, typically consist of a silicon carbide substrate and a silicon carbide epitaxial layer formed on the substrate through epitaxial processes (such as chemical vapor deposition).

[0003] However, existing silicon carbide epitaxial wafers have a number of defects. Among them, during the manufacturing process of silicon carbide devices, the photoresist on the surface of the silicon carbide epitaxial layer is prone to lifting or even falling off, resulting in pattern transfer distortion and affecting device performance. This defect of silicon carbide epitaxial wafers has become one of the technical problems that urgently need to be solved in the fields of silicon carbide epitaxial growth and silicon carbide device manufacturing. Summary of the Invention

[0004] Therefore, it is necessary to provide a silicon carbide epitaxial structure and its preparation method, as well as a silicon carbide device and electronic device, to improve the adhesion of the silicon carbide epitaxial structure to photoresist.

[0005] The first aspect of this application provides a method for preparing a silicon carbide epitaxial structure. The method includes: implanting a silicon source, a carbon source, and a conductive dopant source into a reaction chamber to grow a silicon carbide buffer layer on a substrate; implanting the silicon source, carbon source, and conductive dopant source into the reaction chamber to grow a silicon carbide drift layer on the silicon carbide buffer layer; annealing the silicon carbide drift layer at a temperature of 1450~1550°C for 1~3 min; and forming a silicon layer with a thickness of 5~15 nm on the entire surface of the annealed silicon carbide drift layer to obtain the silicon carbide epitaxial structure.

[0006] The aforementioned method for fabricating silicon carbide epitaxial structures involves forming a silicon layer with a thickness of 5-15 nm on the silicon carbide epitaxial layer. Since the exposed silicon layer is prone to oxidation, forming Si-OH groups, these Si-OH groups can form hydrogen bonds with the -OH groups in the photoresist during subsequent silicon carbide device fabrication. This improves photoresist adhesion, reduces the risk of pattern transfer distortion, and enhances the performance of the silicon carbide device. By controlling the silicon layer thickness within the 5-15 nm range, a complete and effective silicon layer can be formed on the silicon carbide epitaxial layer, reducing silicon layer defects and improving the uniformity of surface energy in different regions of the silicon carbide epitaxial structure. This further improves photoresist adhesion. Simultaneously, a thinner silicon layer facilitates the miniaturization of the silicon carbide epitaxial structure while having minimal impact on the overall performance of the silicon carbide epitaxial structure. Annealing the silicon carbide epitaxial layer can effectively eliminate defects such as steps and stacking misalignments generated during epitaxial growth, reduce stress concentration, provide a good growth plane for the formation of the silicon layer, and improve the bonding force between the silicon layer and the silicon carbide epitaxial layer, thereby improving the quality of the formed silicon layer.

[0007] In some possible implementations, the thickness of the silicon layer is 8-12 nm.

[0008] By further controlling the thickness of the silicon layer within the above range, the integrity and effectiveness of the silicon layer can be further ensured, while the impact on the performance of the silicon carbide epitaxial structure can be further reduced.

[0009] In some possible implementations, the silicon layer is a monocrystalline silicon layer.

[0010] Monocrystalline silicon layers can achieve atomic-level flatness, making it easier to form thinner and more uniform silicon layers.

[0011] In some possible implementations, the silicon layer formation process includes at least one of coating, physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, and ion implantation.

[0012] Silicon layers can be formed on silicon carbide drift layers in various ways, each with its own advantages. Coating, physical vapor deposition, chemical vapor deposition, atomic layer deposition, and molecular beam epitaxy all form silicon layers on the surface of the silicon carbide epitaxial layer, which is beneficial for forming complete, continuous silicon layers with fewer defects. Ion implantation modifies the surface layer of the silicon carbide epitaxial layer to form a silicon layer without adding extra thickness, thus helping to reduce the thickness of the silicon carbide epitaxial structure.

[0013] In some possible embodiments, the silicon layer is formed by chemical vapor deposition (CVD). The silicon layer is formed by a CVD process at a growth temperature of 1000–1100°C, a carrier gas flow rate of 2–8 slm, a silicon source gas flow rate of 200–400 sccm, an operating pressure of 40–60 mbar, and a growth time of 3–20 min. The silicon source gas used for silicon layer growth includes at least one of SiH4, SiHCl3, and SiH2Cl2. The carrier gas used for silicon layer growth includes hydrogen.

[0014] By using CVD and controlling the CVD process parameters, the growth quality and thickness of the silicon layer can be better controlled, which is conducive to forming a complete, continuous silicon layer with fewer defects.

[0015] In some possible implementations, the surface of the silicon carbide drift layer away from the silicon carbide buffer layer includes a central region and an edge region surrounding the outer side of the central region. The step of growing the silicon layer includes: introducing gas into the central region and the edge region respectively, and controlling the silicon source gas flow rate of the edge region to be 8-12% of the silicon source gas flow rate of the central region, so that the thickness difference of the silicon layer formed in the central region and the edge region is <2%.

[0016] By controlling the flow rate of silicon source gas in different regions during the epitaxial growth of the silicon layer through zoned gas intake, and supplementing the silicon source gas in the edge region, the thickness uniformity of the silicon layer at the edge and in the middle can be effectively improved, so that the thickness difference between the middle and the edge of the silicon layer is less than 2%.

[0017] In some possible implementations, the growth conditions of the silicon carbide buffer layer include: a silicon source flow rate of 300-400 sccm, a carbon source flow rate of 80-120 sccm, a conductive dopant source flow rate of 300-400 sccm, a growth temperature of 1550-1630℃, a growth pressure of 30-80 mbar, a growth time of 20-25 min, and a silicon carbide drift layer thickness of 8-12 μm.

[0018] By forming a silicon carbide buffer layer on the substrate using the above method, a good growth plane can be provided for the formation of the silicon carbide drift layer, improving the formation quality of the drift layer and reducing defects and stress concentration. Controlling the growth conditions of the buffer layer can further improve its growth quality and provide a good growth plane for the drift layer.

[0019] In some possible implementations, the growth conditions of the silicon carbide buffer layer include: a silicon source flow rate of 100-150 sccm, a carbon source flow rate of 15-30 sccm, a conductive dopant source flow rate of 100-150 sccm, a growth temperature of 1550-1620℃, a growth pressure of 30-80 mbar, a growth time of 2-5 min, and a thickness of 1-2 μm for the silicon carbide buffer layer.

[0020] By controlling the growth of the silicon carbide drift layer, a higher quality silicon carbide drift layer can be formed, the formation of defects can be reduced, a good growth plane can be provided for the formation of the silicon layer, and thus the quality of the silicon layer can be improved.

[0021] The second aspect of this application provides a silicon carbide epitaxial structure, which is prepared by the method for preparing the silicon carbide epitaxial structure of the first aspect of this application.

[0022] The surface of the silicon carbide epitaxial structure prepared by the above method is a silicon layer with high adhesion. During the fabrication of silicon carbide devices, the photoresist can be spread evenly, and the photoresist pattern is not prone to lifting, peeling or falling off, which is beneficial to improving the performance of silicon carbide devices.

[0023] A third aspect of this application provides a silicon carbide device. The silicon carbide device includes a silicon carbide epitaxial structure as described in the second aspect of this application and a semiconductor structure disposed on the silicon carbide epitaxial structure.

[0024] The silicon carbide device of the third aspect of this application has at least the same advantages as the silicon carbide epitaxial structure of the second aspect of this application, which will not be elaborated here.

[0025] A fourth aspect of this application provides an electronic device. The electronic device includes a circuit board and a silicon carbide device of the third aspect of this application disposed on the circuit board.

[0026] The electronic device of the fourth aspect of this application has at least the same advantages as the silicon carbide device of the third aspect of this application, which will not be elaborated here. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating a method for preparing a silicon carbide epitaxial structure according to an embodiment of this application.

[0028] Figure 2 This is a schematic diagram of a silicon carbide epitaxial structure according to an embodiment of this application.

[0029] Figure 3 and Figure 4 This is a schematic diagram illustrating the fabrication process of a silicon carbide device according to an embodiment of this application.

[0030] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0032] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0033] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0034] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0035] In the description of the embodiments of this application, unless otherwise stated, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections, electrical connections, or connections that can communicate with each other; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two components or interactive relationships between two components.

[0036] In the description of the embodiments in this application, the terms "exemplarily" or "for example," etc., are used to indicate examples, illustrations, or descriptions, and should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example," is intended to present the relevant concepts in a concrete manner.

[0037] Unless otherwise specified, the data range values ​​described in the embodiments of this application shall include the end values.

[0038] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0039] SiC (Silicon Carbide) material possesses a wide bandgap and is a typical material in third-generation semiconductors, showing great potential in applications such as high voltage, high frequency, and high temperature. A SiC epitaxial layer refers to a high-quality SiC single-crystal thin film grown and deposited on a wafer substrate during silicon carbide device manufacturing. Unlike traditional silicon power device fabrication processes, SiC power device fabrication requires the growth of a homogeneous epitaxial drift layer with a certain doping concentration and thickness on a conductive SiC single-crystal substrate using epitaxial technology. Various devices are then fabricated on this epitaxial layer.

[0040] In the process of developing this application, the inventors discovered that silicon carbide has a low surface energy, making it difficult to form effective chemical bonds or physical adsorption with organic photoresist molecules. Specifically, the critical surface tension of SiC was experimentally measured to be approximately 30 mN / m, while the critical surface tension of conventional photoresists is in the range of 40-50 mN / m. According to wetting theory, a liquid can only spontaneously spread on the substrate and form a small contact angle when the surface energy (or critical surface tension) of the substrate is higher than the surface tension of the liquid. However, the critical surface tension of SiC is significantly lower than that of photoresist, resulting in a larger contact angle of the photoresist on the surface of the SiC epitaxial layer and a significant decrease in wettability. The mismatch in surface tension between the SiC epitaxial layer and the photoresist directly causes a series of problems in the photolithography process: for example, the photoresist cannot spread evenly during coating, and the edges of the photoresist pattern are prone to lifting and peeling after exposure and development, or even falling off completely in subsequent wet etching or ion implantation processes, causing pattern transfer distortion or device failure.

[0041] Furthermore, the inventors of this application have discovered that the low surface energy of silicon carbide is precisely because silicon carbide has high chemical stability, resulting in its surface atoms being in a low-energy state and lacking active hydroxyl groups (-OH), thus failing to form hydrogen bonds with the polar groups in the photoresist. In contrast, the surface energy of single-crystal silicon (Si) is typically three times higher than that of SiC. This is because Si is easily oxidized in air to form Si-OH, and -OH can form hydrogen bonds with the polar groups in the photoresist.

[0042] Based on this, in order to fully utilize the excellent properties of SiC material, improve the surface adhesion of SiC epitaxial layer, and solve the problem that photoresist is prone to lifting, peeling, or even falling off on the surface of SiC epitaxial layer, the inventors of this application propose the following technical solution.

[0043] Please see Figure 1 and Figure 2As shown, this application provides a method for preparing a silicon carbide epitaxial structure 100, which specifically includes the following steps S10 to S40. Depending on different requirements, the order of some steps or sub-steps in the method for preparing the silicon carbide epitaxial structure 100 can be changed, and some steps or sub-steps can be omitted or combined.

[0044] Step S10: Form a silicon carbide epitaxial layer 120 on the substrate 110.

[0045] In some embodiments, step S10 includes steps S11 to S14.

[0046] Step S11: Place the substrate 110 into the reaction chamber, evacuate and introduce hydrogen (H2), and heat it to bake at high temperature to remove surface impurities and moisture.

[0047] Substrate 110 refers to a SiC substrate. Using a substrate made of the same material as the SiC drift layer 140 can improve the epitaxial formation quality of the SiC drift layer 140 on substrate 110 and reduce defects in the SiC drift layer 140. For example, the material of substrate 110 can be 4H-SiC.

[0048] Step S12: Etch the surface of substrate 110 to obtain a flat and clean growth surface.

[0049] Specifically, H2 is introduced at a flow rate of 90–110 slm (e.g., 100 slm) and etched at a pressure of 90–110 mbar (100 mbar) and a temperature of 1550–1600°C (e.g., 1590°C) for 4–7 min (e.g., 5 min).

[0050] In step S13, silicon source gas, carbon source gas, and conductive dopant source are injected into the reaction chamber to grow a silicon carbide buffer layer 130 on the substrate 110. Forming a silicon carbide buffer layer 130 on the substrate 110 first provides a good growth plane for the subsequent formation of the drift layer, improves the formation quality of the drift layer, and reduces defects and stress concentration.

[0051] Specifically, the silicon source flow rate is 100~150 sccm (e.g., 150 sccm), the carbon source flow rate is 15~30 sccm (e.g., 30 sccm), the conductive dopant source flow rate is 100~150 sccm (e.g., 150 sccm), the growth temperature is 1550~1620℃, the growth pressure is 30~80 mbar, the growth time is 2~5 min, and the thickness of the silicon carbide buffer layer is 1~2 μm.

[0052] The conductive dopant can be an N-type impurity ion doping source. N-type impurity ions include nitrogen ions.

[0053] In some embodiments, the silicon carbide buffer layer 130 may be a gradient-doped SiC buffer layer, wherein the gradient doping is configured such that the doping concentration is gradually adjusted from the side near the substrate 110 to the side away from the substrate 110 to match the doping concentration of the subsequent silicon carbide drift layer. Alternatively, a buffer layer with a single concentration may be used.

[0054] In step S14, a silicon source, a carbon source, and a conductive dopant source are injected into the reaction chamber to form a silicon carbide drift layer 140 on the silicon carbide buffer layer 130. The silicon carbide buffer layer 130 and the silicon carbide drift layer 140 constitute the silicon carbide epitaxial layer 120.

[0055] Specifically, the flow rate of the silicon source is 300~400 sccm (e.g., 350 sccm), the flow rate of the carbon source is 80~120 sccm (e.g., 100 sccm), the flow rate of the conductive dopant source is 300~400 sccm (e.g., 350 sccm), the growth temperature is 1550~1630℃, the growth pressure is 30~80 mbar, the growth time is 20~25 min, and the thickness of the silicon carbide drift layer 140 is 8~12 μm.

[0056] The conductive doping source forming the silicon carbide drift layer 140 and the conductive doping source forming the silicon carbide buffer layer 130 have the same conductivity type, and the types of impurity ions can be the same or different.

[0057] Step S20 involves annealing the silicon carbide drift layer 140. The annealing temperature is 1450~1550°C (e.g., 1500°C), and the annealing time is 1~3 min (e.g., 2 min). During annealing, the silicon carbide epitaxial layer 120, composed of the silicon carbide buffer layer 130 and the silicon carbide drift layer 140, is actually annealed.

[0058] By annealing the silicon carbide epitaxial layer 120 under the above annealing conditions, defects such as steps and stacking misalignments generated during the epitaxial growth process (especially in the silicon carbide drift layer 140) can be effectively eliminated, stress concentration can be reduced, and a flatter and higher quality growth plane can be provided for the subsequent formation of the silicon layer. This is beneficial to improving the quality of the formed silicon layer and also can improve the bonding force between the silicon layer and the silicon carbide drift layer 140.

[0059] In step S30, a silicon layer 150 is formed on the silicon carbide epitaxial layer 120 to obtain the silicon carbide epitaxial structure 100. That is, a silicon layer 150 is formed on the entire surface of the silicon carbide drift layer 150.

[0060] The silicon layer 150 can be formed through processes including, but not limited to, coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and ion implantation. A variety of methods can be used to form the silicon layer 150 on the silicon carbide drift layer 140, each offering different advantages, and the appropriate method can be selected based on specific needs. Processes such as coating, PVD, CVD, ALD, and MBE all grow the silicon layer 150 on the surface of the silicon carbide drift layer 140, which is beneficial for forming a complete, continuous silicon layer 150 with fewer defects. Ion implantation, on the other hand, modifies the surface layer of the silicon carbide drift layer 140 to form the silicon layer 150. This method does not add additional thickness, thus reducing the overall thickness of the silicon carbide epitaxial structure 100.

[0061] In some embodiments, the silicon layer 150 is formed by chemical vapor deposition. Specifically, a carrier gas (e.g., H2) is introduced at a flow rate of 2-8 slm (e.g., 5 slm), a growth silicon source is introduced at a flow rate of 200-400 sccm (e.g., 300 sccm), the growth temperature is 1000-1100 °C (e.g., 1050 °C), the growth pressure is 40-60 mbar (e.g., 50 mbar), and the growth time is 3-20 min to grow the silicon layer 150. Using CVD to grow the silicon layer 150 on the surface of the silicon carbide drift layer 140, and controlling the corresponding CVD process parameters, allows for better control of the growth quality and thickness uniformity of the silicon layer 150. This facilitates the formation of a complete, continuous silicon layer 150 with fewer defects, resulting in a more uniform surface energy of the silicon carbide epitaxial structure 100 and further improving adhesion.

[0062] In some embodiments, the silicon source gas used for growing the silicon layer 150 includes at least one of SiH4, SiHCl3, and SiH2Cl2.

[0063] In some embodiments, the surface of the silicon carbide drift layer 140 away from the silicon carbide buffer layer 130 includes a central region and an edge region surrounding the central region. During silicon layer growth, gas is introduced into both the central region and the edge region, and the silicon source gas flow rate in the edge region is controlled to be 8-12% of the silicon source gas flow rate in the central region, so that the thickness difference of the silicon layer 150 formed in the central region and the edge region is less than 2%. That is, by controlling the silicon source gas flow rate in sections and supplementing the silicon source in the edge region, the edge thickness of the silicon layer 150 can be made to be substantially consistent with the central thickness, improving the thickness uniformity of the silicon layer 150 and enabling the thickness difference between the edge thickness and the central region of the silicon layer 150 to reach within 2%.

[0064] In some embodiments, the thickness of the silicon layer 150 is 5-15 nm. By controlling the thickness of the silicon layer 150 within the above range, the thickness of the silicon layer 150 can be made more uniform, ensuring the formation of a complete and effective silicon layer 150 on the silicon carbide epitaxial layer 120, reducing the absence of silicon layer 150, thereby improving the surface energy uniformity of the silicon carbide epitaxial structure 100, and thus improving the adhesion of photoresist. At the same time, the thinner silicon layer 150 has less impact on the overall performance of the silicon carbide epitaxial layer 120, and is beneficial to the thinning of the silicon carbide epitaxial structure 100.

[0065] Furthermore, the thickness of the silicon layer 150 can be in the range of 5~8nm, 8~12nm, 12~15nm, etc., to suit the adhesion requirements of different devices. Furthermore, the thickness of the silicon layer is 8~12nm. By further controlling the thickness of the silicon layer 150 within this range, the integrity and effectiveness of the silicon layer 150 can be further ensured, while further reducing the impact on the performance of the silicon carbide epitaxial layer 120 and further reducing the thickness of the silicon carbide epitaxial structure 100.

[0066] In some embodiments, the silicon layer 150 is a monocrystalline silicon layer, that is, the silicon layer 150 is formed based on monocrystalline silicon. The flatness of the monocrystalline silicon layer is atomically flat, and the thickness uniformity is better, so that an extremely thin silicon layer 150 can be generated on the surface of the silicon carbide drift layer 140.

[0067] Step S40: Remove the silicon carbide epitaxial structure 100 from the reaction chamber.

[0068] The method for fabricating the silicon carbide epitaxial structure 100 provided in this application involves forming a thin silicon layer 150 on the silicon carbide epitaxial layer 120. Since the surface of the silicon layer 150 is easily oxidized to form Si-OH after exposure, the Si-OH on the surface of the silicon layer 150 can form hydrogen bonds with the -OH in the photoresist during the subsequent fabrication of the silicon carbide device. This improves the adhesion of the photoresist, reduces the problem of photoresist lifting, peeling, or even falling off, thereby reducing the risk of pattern transfer distortion and improving the performance of the silicon carbide device.

[0069] The contact angle of the silicon carbide epitaxial structure prepared in the embodiments of this application can be 50~70°, which can improve the adhesion of photoresist solution. At the same time, the carrier mobility of the silicon carbide epitaxial structure is 330~470 cm² / V·s, which can meet the performance requirements of the device.

[0070] In addition, combined Figure 3 and Figure 4 As shown, based on the method for fabricating silicon carbide epitaxial structures, this application also provides a method for fabricating silicon carbide devices, including: Step S50, as follows Figure 3As shown, a photoresist layer 160 is formed on the surface of the silicon carbide epitaxial structure 100, and the photoresist layer 160 is located on the surface of the silicon layer 150.

[0071] Step S60, as follows Figure 4 As shown, the photoresist layer 160 is patterned to form multiple openings 161, allowing a portion of the silicon layer 150 to be exposed through the openings 161.

[0072] In step S70, ion implantation is performed on the silicon carbide epitaxial structure 100 through opening 161.

[0073] After ion implantation, the photoresist 160 can be removed, and subsequent semiconductor device fabrication can be carried out to obtain silicon carbide devices.

[0074] In the fabrication of silicon carbide devices, the silicon layer 150 serves as the surface in contact with the photoresist 160. The strong interfacial bonding between the silicon layer 150 and the photoresist 160 improves the adhesion of the photoresist 160, reduces the risk of the photoresist 160 lifting, peeling, or even falling off during device formation, thereby reducing the risk of pattern transfer distortion and improving the performance of silicon carbide devices.

[0075] Please see Figure 2 As shown, this application embodiment also provides a silicon carbide epitaxial structure 100. The silicon carbide epitaxial structure 100 is fabricated using the aforementioned method for fabricating silicon carbide epitaxial structures. The silicon carbide epitaxial structure 100 includes a substrate 110, a silicon carbide epitaxial layer 120, and a silicon layer 150 sequentially stacked.

[0076] In some embodiments, the silicon carbide epitaxial layer 120 includes a silicon carbide buffer layer 130 and a silicon carbide drift layer 140 sequentially formed on the substrate 110.

[0077] This application provides a silicon carbide device. The silicon carbide device includes the aforementioned silicon carbide epitaxial structure and a semiconductor structure disposed on the silicon carbide epitaxial structure.

[0078] In some embodiments, the silicon carbide device can be, but is not limited to, a Schottky barrier diode, an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, a junction field-effect transistor, and a bipolar transistor. The semiconductor structure, depending on the type of the silicon carbide device, includes one or more of the following functional layers and electrode structures: In some embodiments, the silicon carbide device is a Schottky barrier diode, and the semiconductor structure includes a Schottky contact layer disposed on the front side of the silicon carbide epitaxial structure, a metal anode, and a cathode structure disposed on the back side of the silicon carbide epitaxial structure. The Schottky contact layer is formed by contacting a specific metal (such as titanium, nickel, platinum, etc.) with the silicon carbide epitaxial layer to create a Schottky barrier.

[0079] In some embodiments, the silicon carbide device is a metal-oxide-semiconductor field-effect transistor (MOSFET), and the semiconductor structure includes a gate structure, a source structure, and a drain structure. A base region and a source region located within the base region are formed within the silicon carbide epitaxial structure. A gate insulating dielectric layer (such as silicon dioxide) is covered on the surface of the silicon carbide epitaxial structure, and a gate electrode (such as a polysilicon or metal gate) is disposed above the gate insulating dielectric layer. The source structure includes, for example, a source metal forming an ohmic contact with the source region, and the drain structure includes, for example, a drain metal disposed on the back side of the substrate.

[0080] In some embodiments, the silicon carbide device is an insulated gate bipolar transistor, whose semiconductor structure is based on a front gate structure similar to that of a metal-oxide-semiconductor field-effect transistor, and further includes a hole injection layer on the back side of the silicon carbide epitaxial structure to achieve bipolar carrier transport.

[0081] In some embodiments, the silicon carbide device is a junction field-effect transistor, and the semiconductor structure includes a gate control region formed by a PN junction. A channel region is formed in the silicon carbide epitaxial layer by doping, and the conductivity of the channel region is adjusted by changing the depletion layer width of the gate PN junction.

[0082] In some embodiments, the silicon carbide device is a bipolar transistor, and the semiconductor structure includes emitter, base, and collector regions that are stacked or staggered sequentially. By injecting control current into the base region, the bipolar carrier transport mechanism is used to amplify and control the collector current.

[0083] In some embodiments, the semiconductor structure described above further includes an interlayer dielectric layer, a passivation layer, and a metal interconnect layer.

[0084] By forming a silicon layer on the epitaxial wafer, the surface energy of the epitaxial wafer is increased. During the fabrication of silicon carbide devices, the photoresist can spread better on the surface of the epitaxial wafer, improving the adhesion of the photoresist on the epitaxial wafer, reducing the risk of pattern transfer distortion, and thus improving the performance and yield of silicon carbide devices.

[0085] This application also provides an electronic device. The electronic device includes a circuit board and the aforementioned silicon carbide device. The silicon carbide device is disposed on the circuit board.

[0086] In some embodiments, the electronic device may be, but is not limited to, a power conversion device, such as a power adapter, an energy storage device, a switching power supply, a DC / DC converter, a photovoltaic power generation device, and an electric drive system.

[0087] In some embodiments, the electronic device can be other devices with power conversion mechanisms, such as consumer electronics, home electronics, automotive electronics, and financial terminal products. Examples of consumer electronics include mobile phones, tablets, laptops, e-readers, personal digital assistants, smart wearables (e.g., smartwatches, smart bracelets), virtual reality terminal devices, augmented reality terminal devices, and drones. Examples of home electronics include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). Examples of automotive electronics include car navigation systems. Examples of financial terminal products include self-service terminals.

[0088] The following specific examples further illustrate the aforementioned silicon carbide epitaxial structure and its preparation method.

[0089] Example 1 Step 1: Place the SiC substrate into the reaction chamber, evacuate and introduce hydrogen (H2), heat to 1590℃, and bake at high temperature for 5 minutes to remove surface impurities and moisture.

[0090] Step 2: SiHCl3, C2H4 and NH3 are introduced at flow rates of 150 sccm, 30 sccm and 150 sccm respectively, and grown at 1590℃ and 50 mbar for 2 min to form a 1 μm thick SiC buffer layer.

[0091] Step 3: SiHCl3, C2H4 and NH3 are introduced at flow rates of 350 sccm, 100 sccm and 300 sccm respectively, and grown at 1600℃ and 50 mbar for 22 min to form a 10 μm thick SiC drift layer.

[0092] Step 4: Cool down to 1500℃ and anneal the SiC epitaxial layer from Step 4 for about 2 minutes.

[0093] Step 5: H2 and SiH4 are introduced at flow rates of 5 slm and 300 sccm respectively, and the silicon layer is grown at 1100℃ and 50 mbar for 5 min to form a 5 nm thick silicon layer, thus obtaining a silicon carbide epitaxial structure.

[0094] Step 6: Remove the silicon carbide epitaxial structure from the reaction chamber.

[0095] Example 2 The difference from Example 1 is that in step 5, H2 and SiH4 are introduced at flow rates of 5 slm and 300 sccm respectively, and the silicon layer is grown at 1100 ℃ and 50 mbar for 10 min to form a 10 nm thick silicon layer, thus obtaining a silicon carbide epitaxial structure. The other steps are basically the same as in Example 1.

[0096] Example 3 The difference from Example 1 is that in step 5, H2 and SiH4 are introduced at flow rates of 5 slm and 300 sccm respectively, and the silicon layer is grown at 1100°C and 50 mbar for 15 min to form a 15 nm thick silicon layer, thus obtaining a silicon carbide epitaxial structure. The other steps are basically the same as in Example 1.

[0097] Comparative Example 1 The difference from Example 1 is that no silicon layer is formed on the surface of the silicon carbide drift layer, i.e., steps 4 and 5 are not performed. The other steps are basically the same as in Example 1.

[0098] Comparative Example 2 The difference from Example 1 is that in step 5, H2 and SiH4 are introduced at flow rates of 5 slm and 300 sccm respectively, and the silicon layer is grown at 1100°C and 50 mbar for 20 min to form a 20 nm thick silicon layer, thus obtaining a silicon carbide epitaxial structure. The other steps are basically the same as in Example 1.

[0099] Test method: Thickness testing: Silicon layer thickness testing: Ellipsometry is used for characterization. Elliptoscopic ellipsometry (SE) is a standard method for measuring nanoscale thin films. It models and calculates the thickness and refractive index of the film by measuring the change in polarization state of reflected light, with an accuracy of 0.1-0.01 nm.

[0100] Contact angle test: The contact angle of deionized water on the sample surface is usually measured.

[0101] Photoresist adhesion test: The spread of the photoresist solution on the silicon carbide epitaxial structure was tested by optical microscopy (OM) observation, and the presence of edge lifting, peeling, or detachment of the photoresist layer was checked. A high-temperature baking test was also conducted, followed by optical microscopy observation.

[0102] Carrier mobility testing of silicon carbide epitaxial structures: Hall effect tester for carrier mobility testing.

[0103] The theoretical test results of the silicon carbide epitaxial structures obtained in Examples 1-3 and Comparative Examples 1-2 are shown in Table 1 below.

[0104] The comparison between Examples 1-3 and Comparative Examples 1-2 shows that when a 5nm thick silicon layer is grown on a SiC drift layer, a completely continuous, pinhole-free covering layer may not yet be formed. Water droplets simultaneously contact the silicon island and the exposed SiC drift layer, resulting in a contact angle dominated by SiC (~52°) that is slightly higher than in Examples 2 and 3. However, compared to Comparative Example 1, which does not have a silicon layer, the contact angle is significantly reduced. In Example 2, the silicon layer after 10nm forms a complete and continuous film, and the contact angle drops to the intrinsic value of silicon. In Example 3, when the silicon layer reaches 15nm, the silicon film is continuous, but the grains grow and the roughness increases, so the contact angle may slightly increase.

[0105] In Comparative Example 1, no silicon layer was deposited on the surface of the SiC drift layer. As a hard material, SiC has a high surface energy polarity, easily adsorbing organic pollutants from the environment to form a low surface energy layer, which significantly reduces adhesion. When a 5 nm thick silicon film is formed on the surface of the SiC drift layer, the film is in an island-like growth or discontinuous stage. At this point, the photoresist is actually contacting a Si / SiC mixed surface, and the adhesion is significantly improved compared to Comparative Example 1. When the silicon layer thickness reaches 10 nm, a continuous film layer is formed, and the surface chemistry is entirely dominated by silicon (or the native oxide layer SiO2), providing high surface energy and abundant hydroxyl groups (-OH), which is a prerequisite for achieving stable chemical bonding (e.g., through adhesion promoters such as HMDS). Therefore, the surface adhesion in Examples 2 and 3 is significantly improved.

[0106] The fundamental reason for the differences in overall carrier mobility of the silicon carbide epitaxial structures at the three thicknesses in Examples 1-3 is as follows: In Example 1, the 5 nm silicon layer has a discontinuous island structure, resulting in a high Si / SiC interface state density, strong surface scattering, and high contact resistance, leading to the lowest mobility; in Example 2, the 10 nm silicon layer is continuously deposited, significantly reducing the interface state density and scattering, improving contact resistance, and achieving a mobility consistent with the comparative example; in Example 3, the excessive thickness of the 15 nm silicon layer leads to a decrease in mobility. In contrast, in Comparative Example 2, the excessive thickness of the 20 nm silicon layer results in a significant decrease in mobility.

[0107] In summary, this application effectively improves the surface energy of silicon carbide epitaxial structures, enhances the adhesion of photoresist, and improves the performance of silicon carbide devices by forming a silicon layer with a thickness of 5-15 nm on the silicon carbide drift layer.

[0108] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for preparing a silicon carbide epitaxial structure, characterized in that, include: Silicon source, carbon source and conductive dopant source are injected into the reaction chamber to grow a silicon carbide buffer layer on the substrate. A silicon source, a carbon source, and a conductive dopant source are injected into the reaction chamber, and a silicon carbide drift layer is grown on the silicon carbide buffer layer. The silicon carbide drift layer is annealed at a temperature of 1450~1550°C for 1~3 min. as well as A silicon layer with a thickness of 5-15 nm is formed on the entire surface of the annealed silicon carbide drift layer to obtain the silicon carbide epitaxial structure.

2. The method for preparing a silicon carbide epitaxial structure as described in claim 1, characterized in that, The thickness of the silicon layer is 8~12nm; and / or The silicon layer is a monocrystalline silicon layer.

3. The method for preparing a silicon carbide epitaxial structure as described in claim 1, characterized in that, The silicon layer formation process includes coating, physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, or ion implantation.

4. The method for preparing a silicon carbide epitaxial structure as described in claim 3, characterized in that, The silicon layer is formed by chemical vapor deposition. The growth temperature of the silicon layer is 1000~1100°C, the carrier gas flow rate is 2~8 slm, the silicon source gas flow rate is 200~400 sccm, the operating pressure is 40~60 mbar, and the growth time is 3~20 min. The silicon source gas used for silicon layer growth includes at least one of SiH4, SiHCl3 and SiH2Cl2. The carrier gas used for silicon layer growth includes hydrogen.

5. The method for preparing a silicon carbide epitaxial structure as described in claim 4, characterized in that, The surface of the silicon carbide drift layer away from the silicon carbide buffer layer includes a central region and an edge region surrounding the outer side of the central region, wherein the step of growing the silicon layer includes: Gas is introduced into the central region and the edge region respectively, and the silicon source gas flow rate in the edge region is controlled to be 8-12% of the silicon source gas flow rate in the central region, so that the thickness difference of the silicon layer formed in the central region and the edge region is less than 2%.

6. The method for preparing a silicon carbide epitaxial structure as described in claim 1, characterized in that, The growth conditions for the silicon carbide drift layer include: a silicon source flow rate of 300-400 sccm, a carbon source flow rate of 80-120 sccm, a conductive dopant source flow rate of 300-400 sccm, a growth temperature of 1550-1630℃, a growth pressure of 30-80 mbar, a growth time of 20-25 min, and a silicon carbide drift layer thickness of 8-12 μm.

7. The method for preparing a silicon carbide epitaxial structure as described in claim 1, characterized in that, The growth conditions of the silicon carbide buffer layer include: silicon source flow rate of 100~150 sccm, carbon source flow rate of 15~30 sccm, conductive dopant source flow rate of 100~150 sccm, growth temperature of 1550~1620℃, growth pressure of 30~80 mbar, growth time of 2~5 min, and the thickness of the silicon carbide buffer layer is 1~2 μm.

8. A silicon carbide epitaxial structure, characterized in that, It is prepared by the method for preparing silicon carbide epitaxial structures as described in any one of claims 1 to 7.

9. A silicon carbide device, characterized in that, include: The silicon carbide epitaxial structure as described in claim 8; as well as A semiconductor structure is disposed on the silicon carbide epitaxial structure.

10. An electronic device, characterized in that, include: The circuit board and the silicon carbide device as described in claim 9 disposed on the circuit board.

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